From nobody Mon Feb 9 07:23:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64757+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64757+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1598633568; cv=none; d=zohomail.com; s=zohoarc; b=i3mtkb1cS16o3Adr8slGHXmbEskbZBHjKSZHu+rzGHq9aSiUmrDidvAhvVawJrYPFjVl6rDIckaAfD9fGvZRpTU3ORDIJ3WhB5GDzStr68dSIsBXL3cjl3OhHDLPVRqzG13lmS/HuGz1TL77fEe1ZMOUHQZHf/wxmUWyPxUgayM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598633568; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=TLS9zsNzrtbjHlhk1A+BMKSpM36rNvQaHPmIb88BmrA=; b=WYb3imeOfu+D/cKvW42nAqATQ8M9i6ABStxZQc+gIHED2XBtya7B7Tgd20/pzlcb27Q5YQFvCNLAv1c8oo70eUd8BM0dQC23D5TJj+JR1kjyR0La3yKx5Ca7DmZvBmCTIn4DImzKHm/8NE9kXQ6mNJexefFESUD3ns2BLWh+HVs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64757+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598633568510625.5607873563353; Fri, 28 Aug 2020 09:52:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id nxJtYY1788612xQel0eP6bid; Fri, 28 Aug 2020 09:52:47 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.47160.1598633567314079571 for ; Fri, 28 Aug 2020 09:52:47 -0700 X-Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07SGpx0Z019348; Fri, 28 Aug 2020 16:52:46 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 336fajhd15-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Aug 2020 16:52:46 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id DE8A556; Fri, 28 Aug 2020 16:52:45 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (unknown [15.119.209.39]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id A835E48; Fri, 28 Aug 2020 16:52:44 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Leif Lindholm , Michael D Kinney Subject: [edk2-devel] [edk2-platforms][PATCH v3 3/3] Platform/U5SeriesPkg: Revise Readme.md Date: Sat, 29 Aug 2020 00:09:40 +0800 Message-Id: <20200828160940.5467-4-abner.chang@hpe.com> In-Reply-To: <20200828160940.5467-1-abner.chang@hpe.com> References: <20200828160940.5467-1-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 6ioMCHmB0e8HSyg5RX6usqJxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598633567; bh=88Vn4lslKMZksbia2t50q0jUqTblPs6KPviKZC5xPws=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=UAb05suoM/AeOBKqxGWL6HF6EsLV3vEwkeC/s0XQRynUYb4yB5iYz9WcVTqOgzk8wyJ 3p3FsAkJPgPcnID/ClSpwFBf8SLYa+7npdOgSfITt/lApFSRBe/M7zQrr+kj1jWnc6h7M nM/iw8QWwpYbchncm0Q/YkL6TpQXbEA90qg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update RISC-V U5SeriesPkg Readme.md to align with the latest implementation. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Reviewed-by: Daniel Schaefer Cc: Leif Lindholm Cc: Michael D Kinney Cc: Daniel Schaefer --- Platform/SiFive/U5SeriesPkg/Readme.md | 124 +++++++++++++++----------- 1 file changed, 72 insertions(+), 52 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/Readme.md b/Platform/SiFive/U5Seri= esPkg/Readme.md index 4d293e54f6..4b0f9ea966 100644 --- a/Platform/SiFive/U5SeriesPkg/Readme.md +++ b/Platform/SiFive/U5SeriesPkg/Readme.md @@ -1,92 +1,105 @@ -=EF=BB=BF# Introduction -U5SeriesPkg provides the common EFI library and driver modules for SiFive -U5 series core platforms. Currently the supported platforms are Freedom -U500 VC707 platform and Freedom U540 HiFive Unleashed platform. - -Both platforms are built with below common packages, -- **U5SeriesPkg**, edk2 platform branch - (Currently is in edk2-platforms/devel-riscvplatforms branch) -- **RiscVPlatformPkg**, edk2 master branch - (Currently is in edk2-staging/RISC-V-V2 branch) -- **RiscVPkg**, edk2 master branch - (Currently is in edk2-staging/RISC-V-V2 branch) +# Introduction of SiFive U5 Series Platforms +U5SeriesPkg provides the common EDK2 libraries and drivers for SiFive U5 s= eries +platforms. Currently the supported platforms are Freedom U500 VC707 platfo= rm and +Freedom U540 HiFive Unleashed platform. + +Both platforms are built with below common edk2 packages under edk2-platfo= rms +repository, +- [**U5SeriesPkg**](https://github.com/tianocore/edk2-platforms/tree/maste= r/Platform/SiFive/U5SeriesPkg) +- [**RiscVPlatformPkg**](https://github.com/tianocore/edk2-platforms/tree/= master/Platform/RISC-V/PlatformPkg) +- [**RiscVProcessorPkg**](https://github.com/tianocore/edk2-platforms/tree= /master/Silicon/RISC-V/ProcessorPkg) =20 ## U500 Platform -This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U= 500 +This is a sample platform package used against to SiFive Freedom U500 VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Getting Started Guide" on https://www.sifive.com/documentation. +The binary built from Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board ca= n run +on U500 VC707 FPGA board. +``` +build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU500VC707Bo= ard/U500.dsc +``` =20 ## U540 Platform -This is a sample RISC-V EDK2 platform package used against SiFive Freedom = U540 -HiFive Unleashed development board, please refer to "SiFive Freedom U540-C= 000 -Manual" on https://www.sifive.com. -The binary built from Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleash= edBoard/ -can run on main stream [QEMU](https://git.qemu.org/?p=3Dqemu.git;a=3Dsumma= ry) -using qemu-system-riscv64 under riscv64-softmmu. Launch the binary with +This is a sample platform package used for the SiFive Freedom U540 HiFive = Unleashed +development board, please refer to "SiFive Freedom U540-C000 Manual" on +https://www.sifive.com. The binary built from +Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/ can run on bo= th +hardware and [QEMU](https://git.qemu.org/?p=3Dqemu.git;a=3Dsummary). +It is confirmed that version 5.0 of QEMU can boot with this firmware to E= FI shell +and Linux user space. +``` +build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveU= nleashedBoard/U540.dsc +``` +For running U540 edk2 binary on QEMU, use qemu-system-riscv64 under riscv6= 4-softmmu +to launch the binary with below parameters, =20 ``` --cpu sifive-u54 -machine sifive_u +qemu-system-riscv64 -cpu sifive-u54 -machine sifive_u -bios U540.fd -m 204= 8 -nographic -smp cpus=3D5,maxcpus=3D5 ``` =20 -## Download the sources +## Download the Source Code ``` -git clone https://github.com/tianocore/edk2-staging.git -# Checkout RISC-V-V2 branch +git clone https://github.com/tianocore/edk2.git git clone https://github.com/tianocore/edk2-platforms.git -# Checkout devel-riscvplatforms branch -git clone https://github.com/tianocore/edk2-non-osi.git +# Below to clone opensbi submodule. +git submodule update --init ``` - -## Platform Owners -Chang, Abner -Chen, Gilbert +Refer to [Readme.md](https://github.com/tianocore/edk2-platforms/blob/mast= er/Platform/RISC-V/PlatformPkg/Readme.md) for building RISC-V platforms. =20 ## Platform Status -Currently the binary built from U500Pkg can boot SiFive Freedom U500 VC707 +**FreedomU500VC707Board** +Currently the binary built from U500 edk2 package can boot SiFive Freedom = U500 VC707 FPGA to EFI shell with console in/out enabled. =20 -## Linux Build Instructions -You can build the RISC-V platform using below script, -`build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU500VC707= Board/U500.dsc` +**FreedomU540HiFiveUnleashedBoard** +Currently the binary built from U540 edk2 package can boot SiFive Freedom = U540 HiFive +Unleashed to EFI shell with console in/out enabled and Linux kernel. Pleas= e refer to +https://github.com/riscv/riscv-uefi-edk2-docs for booting to Linux kernel. =20 ## Supported Operating Systems -Only support to boot to EFI Shell so far. +Please refer to https://github.com/riscv/riscv-uefi-edk2-docs. =20 ## Known Issues and Limitations Only RISC-V RV64 is verified on this platform. =20 ## Related Materials +- [RISC-V UEFI Documents](https://github.com/riscv/riscv-uefi-edk2-docs) - [RISC-V OpenSbi](https://github.com/riscv/opensbi) -- [SiFive U500 VC707 FPGA Getting Started Guide](https://sifive.cdn.prismi= c.io/sifive%2Fc248fabc-5e44-4412-b1c3-6bb6aac73a2c_sifive-u500-vc707-gettin= gstarted-v0.2.pdf) +- [SiFive U500 VC707 FPGA Getting Started Guide](https://sifive.cdn.prismi= c.io/ +sifive%2Fc248fabc-5e44-4412-b1c3-6bb6aac73a2c_sifive-u500-vc707-gettingsta= rted-v0.2.pdf) - [SiFive Freedom U540-C000 Manual](https://sifive.cdn.prismic.io/sifive%2= F834354f0-08e6-423c-bf1f-0cb58ef14061_fu540-c000-v1.0.pdf) - [SiFive RISC-V Core Document](https://www.sifive.com/documentation) =20 ## U5SeriesPkg Libraries and Drivers ### PeiCoreInfoHobLib -This is the library to create RISC-V core characteristics for building up -RISC-V related SMBIOS records to support the unified boot loader and OS im= age. -This library leverage the silicon libraries provided in Silicon/SiFive. +This is the library to create RISC-V core characteristics for building up = RISC-V +related SMBIOS records to support a single boot loader or OS image on all= RISC-V +platforms by discovering RISC-V hart configurations dynamically. This libr= ary leverage +the silicon libraries provided in Silicon/SiFive. =20 ### RiscVPlatformTimerLib -This is common U5 series platform timer library which has the -platform-specific timer implementation. +This is common U5 series platform timer library which has the platform-spe= cific +timer implementation. + +### SerialLib +This is common U5 series platform serial port library. =20 ### TimerDxe -This is U5 series platform timer DXE driver whcih has the platform-specific +This is common U5 series platform timer DXE driver which has the platform-= specific timer implementation. =20 ## U500 Platform Libraries and Drivers ### RiscVOpensbiPlatformLib In order to reduce the dependencies with RISC-V OpenSBI project -(https://github.com/riscv/opensbi) and fewer burdens to EDK2 build process= , the -implementation of RISC-V EDK2 platform is leveraging platform source code = from -OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from -RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build -environment. +(https://github.com/riscv/opensbi) and avoid duplicating code we use it, t= he +implementation of RISC-V EDK2 platform is leveraging platform source code = from OpenSBI +code tree. The "platform.c" under OpenSbiPlatformLib is cloned from +[RISC-V OpenSBI code tree](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensb= iLib/opensbi) +and built based on edk2 build environment. =20 ### PlatformPei -This is the platform-implementation specific library which is executed in = early -PEI phase for U500 platform initialization. +This is the platform-implementation specific library which is executed in = early PEI +phase for U500 platform initialization. =20 ## U540 Platform Libraries and Drivers ### RiscVOpensbiPlatformLib @@ -94,17 +107,24 @@ In order to reduce the dependencies with RISC-V OpenSB= I project (https://github.com/riscv/opensbi) and fewer burdens to EDK2 build process= , the implementation of RISC-V EDK2 platform is leveraging platform source code = from OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from -RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build -environment. +[RISC-V OpenSBI code tree](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensb= iLib/opensbi) +and built based on edk2build environment. =20 ### PlatformPei -This is the platform-implementation specific library which is executed in = early -PEI phase for U540 platform initialization. +This is the platform-implementation specific library which is executed in = early PEI +phase for U540 platform initialization. =20 ## U5SeriesPkg Platform PCD settings =20 | **PCD name** |**Usage**| |----------------|----------| +|PcdU5PlatformSystemClock| U5 series platform system clock| |PcdNumberofU5Cores| Number of U5 core enabled on U5 series platform| |PcdE5MCSupported| Indicates whether the Monitor Core (E5) is supported on= U5 series platform| |PcdU5UartBase|Platform serial port base address| + + +## Platform Owners +Chang, Abner +Chen, Gilbert +Schaefer, Daniel --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64757): https://edk2.groups.io/g/devel/message/64757 Mute This Topic: https://groups.io/mt/76478049/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-