From nobody Mon Feb 9 16:51:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64756+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64756+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1598633567; cv=none; d=zohomail.com; s=zohoarc; b=JxjIPAeRdELEdE4rlSsJH4GhLaiC7RGdOOwNXAp00VxveWz+csvsuy+mEyWRpu/w558n4W39MZMcT1CXE+Y3ApY869Ej5UMcmBAuDOUzZxeFpVJ3P2thT/VC+gUnWbqz6jU4YfQj/Kob3Qg52TgMr0XCIL7ijWOeY3g/QjhIROA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598633567; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KZCs5on0oW/DSSKcsBF8IWA3/Bea93p08MPnZ9Gk3zU=; b=Nga2RqsgzlbmJgAaN0XfxincRPeQCkRn6QMJxfnNeAiGmAiSYy3q2/q5VFo8bgjWpetSe7g8D1JKC8Ky/QjkmjkldE469CTNFBXDvKGJg/V1DeFVzY3TkMMIx2XjWInZoBHnYFKmK339wmdk1uWlihcmXdZd+QImGOfvx4i/Ixw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64756+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598633567116974.8034339682303; Fri, 28 Aug 2020 09:52:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id DAjaYY1788612x4eldN7UTzv; Fri, 28 Aug 2020 09:52:46 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.47159.1598633565729214738 for ; Fri, 28 Aug 2020 09:52:45 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07SGhikH001859; Fri, 28 Aug 2020 16:52:45 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 336faq9gk6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Aug 2020 16:52:44 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 56EC358; Fri, 28 Aug 2020 16:52:44 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (unknown [15.119.209.39]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 1DFD348; Fri, 28 Aug 2020 16:52:42 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Leif Lindholm , Michael D Kinney Subject: [edk2-devel] [edk2-platforms][PATCH v3 2/3] RISC-V/PlatformPkg: Revise Readme.md Date: Sat, 29 Aug 2020 00:09:39 +0800 Message-Id: <20200828160940.5467-3-abner.chang@hpe.com> In-Reply-To: <20200828160940.5467-1-abner.chang@hpe.com> References: <20200828160940.5467-1-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: sLuphsJBatE9RSd7H06YkHQhx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598633566; bh=a5nj4amI0kxQxbrc6o54PZO6GBszo+hOoIRzlJHpAa8=; h=Cc:Date:From:Reply-To:Subject:To; b=vyZhirUx5CMO3w+BrivWIREqM4IMO5y5T4WSTSv9fAQKH+ZKjQB7NIgPP13+Qmg4u4V D3FfuFgdH6kH8ithDGUyx9jo8oqArFWjgT4cMCOJO5v5x+RbdrS7BkX6nRaqGAz4MYrOy X3pZIVmOjjVPoANwoV70xuxnOxmlpsb7Sp8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update RISC-V PlatformPkg Readme.md to align with the latest implementation. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Reviewed-by: Daniel Schaefer Cc: Leif Lindholm Cc: Michael D Kinney Cc: Daniel Schaefer --- Platform/RISC-V/PlatformPkg/Readme.md | 88 ++++++++++++++++----------- 1 file changed, 52 insertions(+), 36 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/Platfo= rmPkg/Readme.md index 2632ebeb28..4b933a2e0f 100644 --- a/Platform/RISC-V/PlatformPkg/Readme.md +++ b/Platform/RISC-V/PlatformPkg/Readme.md @@ -1,49 +1,62 @@ # Introduction =20 -## EDK2 RISC-V Platform Packages -RISC-V platform package provides the generic and common modules for RISC-V -platforms. RISC-V platform package could include RiscPlatformPkg.dec to -use the common drivers, libraries, definitions, PCDs and etc. for the -platform development. +## EDK2 RISC-V Platform Project =20 -There are two packages to support RISC-V: -- `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec` -- `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec` +### EDK2 Build Architecture for RISC-V +The edk2 build architecture which is supported and verified on edk2 code b= ase for +RISC-V platforms is `RISCV64`. =20 -`RiscVPlatformPkg` provides SEC phase and NULL libs. -`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers. +### Toolchain for RISC-V +The toolchain is on RISC-V GitHub (https://github.com/riscv/riscv-gnu-tool= chain) +for building edk2 RISC-V binary. The corresponding edk2 Toolchain tag for = building +RISC-V platform is "GCC5" declared in `tools_def.txt`. =20 -### Download the sources ### +### Packages +There are two packages to support RISC-V edk2 platforms: +- `Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec` +- `Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec` + +`RiscVPlatformPkg` currently provides the generic SEC driver for all RISC-= V platforms, +and some platform level libraries. +`RiscVProcessorPkg` currently provides RISC-V processor related libraries,= PEI modules, +DXE drivers and industrial standard header files. + +## EDK2 RISC-V Platform Package +RISC-V platform package provides the common modules for RISC-V platforms. = RISC-V +platform vendors could include RiscPlatformPkg.dec to use the common drive= rs, libraries, +definitions, PCDs and etc. for the RISC-V platforms development. + +### Download the Source Code ### ``` git clone https://github.com/tianocore/edk2.git +git clone https://github.com/tianocore/edk2-platforms.git =20 -git clone https://github.com/changab/edk2-platforms.git -# Check out branch: riscv-smode-lib ``` =20 -To build it, you have to follow the regular steps for EDK2 and additionall= y set -an environmen variable to point to your RISC-V toolchain installation, -including the binary prefixes: - +You have to follow the build steps for +EDK2 (https://github.com/tianocore/tianocore.github.io/wiki/Getting-Starte= d-with-EDK-II) +and additionally set an environment variable to point to your RISC-V toolc= hain binaries +for building RISC-V platforms, ``` +# e.g. If the toolchain binaries are under /riscv-gnu-toolchain-binaries/b= in export GCC5_RISCV64_PREFIX=3D/riscv-gnu-toolchain-binaries/bin/riscv64-unk= nown-elf- ``` =20 -Then you can build the image for the SiFive HifiveUnleashed platform: +Then you can build the edk2 firmware image for RISC-V platforms. =20 ``` +# e.g. For building SiFive Hifive Unleashed platform: build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveU= nleashedBoard/U540.dsc ``` =20 -### EDK2 project -All changes in edk2 are upstream, however, most of the RISC-V code is in -edk2-platforms. Therefore you have to check out the branch `riscv-smode-li= b` on -`github.com/changab/edk2-platforms`. - -The build architecture which is supported and verified so far is `RISCV64`. -The latest master of the RISC-V toolchain https://github.com/riscv/riscv-g= nu-toolchain -should work but the latest verified commit is `b468107e701433e1caca3dbc8ae= f8d40`. -Toolchain tag is "GCC5" declared in `tools_def.txt` +## RISC-V OpenSBI Library +RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation of +[RISC-V SBI (Supervisor Binary Interface) specification](https://github.co= m/riscv/riscv-sbi-doc). +For EDK2 UEFI firmware solution, RISC-V OpenSBI is integrated as a library +[(submoudule)](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi= ) in EDK2 +RISC-V Processor Package. The RISC-V OpenSBI library is built in SEC drive= r without +any modifications and provides the interfaces for supervisor mode executio= n environment +to execute privileged operations. =20 ## RISC-V Platform PCD settings ### EDK2 Firmware Volume Settings @@ -54,9 +67,9 @@ EDK2 Firmware volume related PCDs which declared in platf= orm FDF file. |PcdRiscVSecFvBase| The base address of SEC Firmware Volume| |PcdRiscVSecFvSize| The size of SEC Firmware Volume| |PcdRiscVPeiFvBase| The base address of PEI Firmware Volume| -|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| +|PcdRiscVPeiFvSize| The size of PEI Firmware Volume| |PcdRiscVDxeFvBase| The base address of DXE Firmware Volume| -|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| +|PcdRiscVDxeFvSize| The size of DXE Firmware Volume| =20 ### EDK2 EFI Variable Region Settings The PCD settings regard to EFI Variable @@ -84,21 +97,24 @@ Below PCDs could be set in platform FDF file. |--------------|---------| |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific| |PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS| +|PcdBootableHartNumber|The bootable HART number, which is incorporate with= RISC-V OpenSBI platform hart_index2id value| =20 ### RISC-V OpenSBI Settings =20 | **PCD name** |**Usage**| |--------------|---------| -|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RIS= C-V HARTs| -|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-= V HARTs| -|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use OpenSBI| +|PcdScratchRamBase| The base address of RISC-V OpenSBI scratch buffer for = all RISC-V HARTs| +|PcdScratchRamSize| The total size of RISC-V OpenSBI scratch buffer for al= l RISC-V HARTs| +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use RISC-V OpenSBI| |PcdTemporaryRamBase| The base address of temporary memory for PEI phase| |PcdTemporaryRamSize| The temporary memory size for PEI phase| +|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI pha= se| =20 ## Supported Operating Systems -Only support to boot to EFI Shell so far. - -Porting GRUB2 and Linux EFISTUB is in progress. +Currently support boot to EFI Shell and Linux kernel. +Refer to below link for more information, +https://github.com/riscv/riscv-uefi-edk2-docs =20 ## Known Issues and Limitations -Only RISC-V RV64 is verified. +Only RISC-V RV64 is verified on edk2. + --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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