From nobody Wed May 1 20:08:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64696+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64696+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1598545577; cv=none; d=zohomail.com; s=zohoarc; b=L7DBjkDs9XyrXh35kXSoOxvr0MHHMeBZ0Jl1DrL7J4FxmV/hllEBYfgcImhxwFZWNAqlvaEAqmmuYtws5O8D7CX4RLLMH02+bd9avyrVMjIFc5v12WZ0rbvAgsQNq2AhBnqcnGggXelRFto+zxKj0S4h+Y5axTHKtQj1DDbbFSs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598545577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=XLvQ/Ll3bQq91SPe3mH5S6tllisxhGipH9c2iom8Zd4=; b=XENelkIRJqfohNCfhy+fP+Q1mID4BPe0k7hXbwnmeFCu54I9TAyK+IKOyDGJCBhNaERC8mBv5gtkZ4+pP9o9Cur1YyzxWJxhvaIQLL6H5ztwxYnoobUe5lW5qSiEZYh6FY6uTbXiGTGei8FJmIDQjHtNY2bhpyHPV49LbXJqhmw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64696+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15985455773641016.4918897100104; Thu, 27 Aug 2020 09:26:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jkCZYY1788612x4X2QscusGt; Thu, 27 Aug 2020 09:26:17 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web10.23011.1598545576246973180 for ; Thu, 27 Aug 2020 09:26:16 -0700 X-Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07RGNZ2T002292; Thu, 27 Aug 2020 16:26:14 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 336fan0hd1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 16:26:14 +0000 X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.39]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id E79E65F; Thu, 27 Aug 2020 16:26:12 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Leif Lindholm , Michael D Kinney Subject: [edk2-devel] [edk2-platforms][PATCH v2 1/3] edk2-platforms: Revise Readme.md Date: Thu, 27 Aug 2020 23:43:12 +0800 Message-Id: <20200827154314.31480-2-abner.chang@hpe.com> In-Reply-To: <20200827154314.31480-1-abner.chang@hpe.com> References: <20200827154314.31480-1-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: BMakDkVbWGHH7bPuiV2XuWnox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598545577; bh=vZMJNr5IGJOFdFqRiXJ2IERt+psWeAgzERX/f8Oc0Yk=; h=Cc:Date:From:Reply-To:Subject:To; b=xHkulnvvgBG62+bHLbYPATvn1vfP9uAj3cGYnw/hjBidMF3G4k1Pa4MmxTKHC16IFw3 Y26mPabjwuJq3Q5JNuU43GmgyxR4H0qp3HfoOUFi2eFcFlCzhHve7jP5kFQToUkl7424H iL+t7TrvcU5Hu8MxiE7q4KwPEj6IdSObgug= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Mention to update submodule under for edk2-platforms. It is for RISC-V Open= SBI library. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Reviewed-by: Leif Lindholm Cc: Leif Lindholm Cc: Michael D Kinney --- Readme.md | 1 + 1 file changed, 1 insertion(+) diff --git a/Readme.md b/Readme.md index 0675685fb7..d896b2c5fc 100644 --- a/Readme.md +++ b/Readme.md @@ -97,6 +97,7 @@ target-specific binutils. These are included with any pre= packaged GCC toolchain $ git submodule update --init ... $ git clone https://github.com/tianocore/edk2-platforms.git + $ git submodule update --init ... $ git clone https://github.com/tianocore/edk2-non-osi.git ``` --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64696): https://edk2.groups.io/g/devel/message/64696 Mute This Topic: https://groups.io/mt/76455358/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 20:08:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64697+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64697+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1598545577; cv=none; d=zohomail.com; s=zohoarc; b=jOOTjSI4/QkWsJGwYTpoA1DxLbNc4l4hn5qeBsEsH8umyNueYauyEfc6gAfmqMqz7ZDBPaNvsrbXNdduafvT1t38J2wSjrxu4vnPJYQnkpbYtRxeJDmoV28BmkUxs+nkJm4mmzbRQUhIuTNAW00wGGxQKx8efNcbb+uWf4fv7K0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598545577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Va5+jeOSQS27wGI+F/itaFgUu9vWufnHIIzWwnm57Ok=; b=JQDUOmAjeR2vMWRD3ySbu/ZcvW452UktBYSTRTDMuBsx26V6rpgwnHr0awT21IihT1a/FXmQn585qx9v9NT2uHqiFLrS1o6Cwgb1y1ujXyE76K+UO1g4YFmRBQasnkbhLK4KUWoK2jpcckeL2LznWISZI2GYy31BsQeog7s3Ko8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64697+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598545577956152.73225113226317; Thu, 27 Aug 2020 09:26:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id F9nUYY1788612xlFrZHEh7ex; Thu, 27 Aug 2020 09:26:17 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.22831.1598545576942120005 for ; Thu, 27 Aug 2020 09:26:16 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07RGNS56015384; Thu, 27 Aug 2020 16:26:16 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0a-002e3701.pphosted.com with ESMTP id 336fan0gsw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 16:26:16 +0000 X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.39]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 9942F61; Thu, 27 Aug 2020 16:26:14 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Leif Lindholm , Michael D Kinney Subject: [edk2-devel] [edk2-platforms][PATCH v2 2/3] RISC-V/PlatformPkg: Revise Readme.md Date: Thu, 27 Aug 2020 23:43:13 +0800 Message-Id: <20200827154314.31480-3-abner.chang@hpe.com> In-Reply-To: <20200827154314.31480-1-abner.chang@hpe.com> References: <20200827154314.31480-1-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: UZiFs8CvAWuDjWEenxQ9Z8qRx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598545577; bh=t49IaPl5unlUlGGYjyCOXLKdR3WaN2K57/lC5Aq8IaU=; h=Cc:Date:From:Reply-To:Subject:To; b=LAVRJ3JFRiJUtX1iEeE3CHdtjGkusBbhH6ddHKNjY39aaUS2d73iGVy0PdgP7AbhHvX cgWubTxFvL4AV/k4nLHeRK4MOc64RS74C5J1PtufmV1WEPRTWw2DQ3TUSFzkv4gq/GDbt htauzlUK7Yzy5cCTIKrgGUCSyiYf8Enhack= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update RISC-V PlatformPkg Readme.md to align with the latest implementation. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Leif Lindholm Cc: Michael D Kinney Cc: Daniel Schaefer Reviewed-By: Daniel Schaefer --- Platform/RISC-V/PlatformPkg/Readme.md | 74 ++++++++++++++------------- 1 file changed, 38 insertions(+), 36 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/Platfo= rmPkg/Readme.md index 2632ebeb28..1ff649eaf7 100644 --- a/Platform/RISC-V/PlatformPkg/Readme.md +++ b/Platform/RISC-V/PlatformPkg/Readme.md @@ -1,49 +1,48 @@ # Introduction =20 -## EDK2 RISC-V Platform Packages -RISC-V platform package provides the generic and common modules for RISC-V -platforms. RISC-V platform package could include RiscPlatformPkg.dec to -use the common drivers, libraries, definitions, PCDs and etc. for the -platform development. +## EDK2 RISC-V Platform Project +The edk2 build architecture which is supported and verified on edk2 code b= ase for RISC-V platforms is `RISCV64`. +The toolchain is on RISC-V GitHub (https://github.com/riscv/riscv-gnu-tool= chain) for building edk2 RISC-V binary. +The corresponding edk2 Toolchain tag for building RISC-V platform is "GCC5= " declared in `tools_def.txt`. =20 -There are two packages to support RISC-V: -- `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec` -- `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec` +There are two packages to support RISC-V edk2 platforms: +- `Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec` +- `Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec` =20 -`RiscVPlatformPkg` provides SEC phase and NULL libs. -`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers. +`RiscVPlatformPkg` currently provides the generic SEC driver for all RISC-= V platforms, and some platform level libraries. +`RiscVProcessorPkg` currently provides RISC-V processor related libraries,= PEI modules, DXE drivers and industrial +standard header files. =20 -### Download the sources ### +## EDK2 RISC-V Platform Package +RISC-V platform package provides the common modules for RISC-V platforms. = RISC-V platform vendors could include +RiscPlatformPkg.dec to use the common drivers, libraries, definitions, PCD= s and etc. for the +RISC-V platforms development. + +### Download the Source Code ### ``` git clone https://github.com/tianocore/edk2.git +git clone https://github.com/tianocore/edk2-platforms.git =20 -git clone https://github.com/changab/edk2-platforms.git -# Check out branch: riscv-smode-lib ``` =20 -To build it, you have to follow the regular steps for EDK2 and additionall= y set -an environmen variable to point to your RISC-V toolchain installation, -including the binary prefixes: - +You have to follow the build steps for EDK2 (https://github.com/tianocore/= tianocore.github.io/wiki/Getting-Started-with-EDK-II) +and additionally set an environment variable to point to your RISC-V toolc= hain binaries for building RISC-V +platforms, ``` +# e.g. If the toolchain binaries are under /riscv-gnu-toolchain-binaries/b= in export GCC5_RISCV64_PREFIX=3D/riscv-gnu-toolchain-binaries/bin/riscv64-unk= nown-elf- ``` =20 -Then you can build the image for the SiFive HifiveUnleashed platform: +Then you can build the edk2 firmware image for RISC-V platforms. =20 ``` +# e.g. For building SiFive Hifive Unleashed platform: build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveU= nleashedBoard/U540.dsc ``` =20 -### EDK2 project -All changes in edk2 are upstream, however, most of the RISC-V code is in -edk2-platforms. Therefore you have to check out the branch `riscv-smode-li= b` on -`github.com/changab/edk2-platforms`. - -The build architecture which is supported and verified so far is `RISCV64`. -The latest master of the RISC-V toolchain https://github.com/riscv/riscv-g= nu-toolchain -should work but the latest verified commit is `b468107e701433e1caca3dbc8ae= f8d40`. -Toolchain tag is "GCC5" declared in `tools_def.txt` +## RISC-V OpenSBI Library +RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation o= f [RISC-V SBI (Supervisor Binary Interface) specification](https://github.c= om/riscv/riscv-sbi-doc). For EDK2 UEFI firmware solution, RISC-V OpenSBI is= integrated as a library [(submoudule)](Silicon/RISC-V/ProcessorPkg/Library= /RiscVOpensbiLib/opensbi) in EDK2 RISC-V Processor Package. The RISC-V Open= SBI library is built in SEC driver +without any modifications and provides the interfaces for supervisor mode = execution environment to execute privileged operations. =20 ## RISC-V Platform PCD settings ### EDK2 Firmware Volume Settings @@ -54,9 +53,9 @@ EDK2 Firmware volume related PCDs which declared in platf= orm FDF file. |PcdRiscVSecFvBase| The base address of SEC Firmware Volume| |PcdRiscVSecFvSize| The size of SEC Firmware Volume| |PcdRiscVPeiFvBase| The base address of PEI Firmware Volume| -|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| +|PcdRiscVPeiFvSize| The size of PEI Firmware Volume| |PcdRiscVDxeFvBase| The base address of DXE Firmware Volume| -|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| +|PcdRiscVDxeFvSize| The size of DXE Firmware Volume| =20 ### EDK2 EFI Variable Region Settings The PCD settings regard to EFI Variable @@ -84,21 +83,24 @@ Below PCDs could be set in platform FDF file. |--------------|---------| |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific| |PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS| +|PcdBootableHartNumber|The bootable HART number, which is incorporate with= RISC-V OpenSBI platform hart_index2id value| =20 ### RISC-V OpenSBI Settings =20 | **PCD name** |**Usage**| |--------------|---------| -|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RIS= C-V HARTs| -|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-= V HARTs| -|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use OpenSBI| +|PcdScratchRamBase| The base address of RISC-V OpenSBI scratch buffer for = all RISC-V HARTs| +|PcdScratchRamSize| The total size of RISC-V OpenSBI scratch buffer for al= l RISC-V HARTs| +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use RISC-V OpenSBI| |PcdTemporaryRamBase| The base address of temporary memory for PEI phase| |PcdTemporaryRamSize| The temporary memory size for PEI phase| +|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI pha= se| =20 ## Supported Operating Systems -Only support to boot to EFI Shell so far. - -Porting GRUB2 and Linux EFISTUB is in progress. +Currently support boot to EFI Shell and Linux kernel. +Refer to below link for more information, +https://github.com/riscv/riscv-uefi-edk2-docs =20 ## Known Issues and Limitations -Only RISC-V RV64 is verified. +Only RISC-V RV64 is verified on edk2. + --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64697): https://edk2.groups.io/g/devel/message/64697 Mute This Topic: https://groups.io/mt/76455359/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 20:08:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64698+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64698+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1598545584; cv=none; d=zohomail.com; s=zohoarc; b=oC9CCG4iQHksFEz637fGsLipUesbyadc1aLY2PaphGyY6YBJxYkdLFSt1uC76aB1+mxf9PB5U/zefLCYAswWxasGvNJh17/gywuxJJyuqHRyCqZUQfPJQiGhlbTkd8997Vpy7Ket2pPv83lE3Rw+q94naJG7941iVIoVxtsOILA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598545584; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=MGwW/QHiL0FkveS4yxX3QdxR2/cCej3kMzDAMubvnyk=; b=QAW9szfculqJAwua6h3wHZINe4MMqv7ygdcN0NwBIL25ySvUHtJ3m6iDz0YdJllpJJ+5f7JGW+Cje6Za/9V2lcV06nx/wDy9E3YCdiKly0FFcrTDpAk4vR4PHxUljd8N16gNWMPPuMgMdmc7TF47OgbyovCJ3jHeNnj+vXMPen8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64698+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598545584187250.56411705752498; Thu, 27 Aug 2020 09:26:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7nm3YY1788612x0aKaCwAYMX; Thu, 27 Aug 2020 09:26:23 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.22993.1598545578355214786 for ; Thu, 27 Aug 2020 09:26:18 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 07RGNer2019884; Thu, 27 Aug 2020 16:26:18 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0a-002e3701.pphosted.com with ESMTP id 336fat0gjm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Aug 2020 16:26:18 +0000 X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.39]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 2ED8554; Thu, 27 Aug 2020 16:26:16 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Leif Lindholm , Michael D Kinney Subject: [edk2-devel] [edk2-platforms][PATCH v2 3/3] Platform/U5SeriesPkg: Revise Readme.md Date: Thu, 27 Aug 2020 23:43:14 +0800 Message-Id: <20200827154314.31480-4-abner.chang@hpe.com> In-Reply-To: <20200827154314.31480-1-abner.chang@hpe.com> References: <20200827154314.31480-1-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: HAaoZTkam2MaPjzVn25hlg5ax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598545583; bh=eOD6Je5KVrRV71DyUYn4UoG2zGaOv2iMZULxGKldj+Q=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=m7cG+TZx+PARx0GXs9FQadIKRHUdvPq9GenASG1PzF/ZmvfoANMFe+tdC9IbRQVUET0 OytZ2CUkK7Lbvtc0ftHZZp8XYc9xHCzlweED7Fdd8oRqzre0zB/D8LDyPJGXdidSuuTdk LpB4rnPyb8DFxlBcYvIS37S/hLkWOqbO3LE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update RISC-V U5SeriesPkg Readme.md to align with the latest implementation. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Leif Lindholm Cc: Michael D Kinney Cc: Daniel Schaefer Reviewed-By: Daniel Schaefer --- Platform/SiFive/U5SeriesPkg/Readme.md | 114 ++++++++++++++------------ 1 file changed, 60 insertions(+), 54 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/Readme.md b/Platform/SiFive/U5Seri= esPkg/Readme.md index 4d293e54f6..2ced71fa56 100644 --- a/Platform/SiFive/U5SeriesPkg/Readme.md +++ b/Platform/SiFive/U5SeriesPkg/Readme.md @@ -1,61 +1,61 @@ -=EF=BB=BF# Introduction -U5SeriesPkg provides the common EFI library and driver modules for SiFive -U5 series core platforms. Currently the supported platforms are Freedom -U500 VC707 platform and Freedom U540 HiFive Unleashed platform. - -Both platforms are built with below common packages, -- **U5SeriesPkg**, edk2 platform branch - (Currently is in edk2-platforms/devel-riscvplatforms branch) -- **RiscVPlatformPkg**, edk2 master branch - (Currently is in edk2-staging/RISC-V-V2 branch) -- **RiscVPkg**, edk2 master branch - (Currently is in edk2-staging/RISC-V-V2 branch) +# Introduction of SiFive U5 Series Platforms +U5SeriesPkg provides the common EDK2 libraries and drivers for SiFive U5 s= eries platforms. Currently the supported +platforms are Freedom U500 VC707 platform and Freedom U540 HiFive Unleashe= d platform. + +Both platforms are built with below common edk2 packages under edk2-platfo= rms repository, +- [**U5SeriesPkg**](https://github.com/tianocore/edk2-platforms/tree/maste= r/Platform/SiFive/U5SeriesPkg) +- [**RiscVPlatformPkg**](https://github.com/tianocore/edk2-platforms/tree/= master/Platform/RISC-V/PlatformPkg) +- [**RiscVProcessorPkg**](https://github.com/tianocore/edk2-platforms/tree= /master/Silicon/RISC-V/ProcessorPkg) =20 ## U500 Platform -This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U= 500 +This is a sample platform package used against to SiFive Freedom U500 VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Getting Started Guide" on https://www.sifive.com/documentation. +The binary built from Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board ca= n run on U500 VC707 FPGA board. +``` +build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU500VC707Bo= ard/U500.dsc +``` =20 ## U540 Platform -This is a sample RISC-V EDK2 platform package used against SiFive Freedom = U540 -HiFive Unleashed development board, please refer to "SiFive Freedom U540-C= 000 -Manual" on https://www.sifive.com. -The binary built from Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleash= edBoard/ -can run on main stream [QEMU](https://git.qemu.org/?p=3Dqemu.git;a=3Dsumma= ry) -using qemu-system-riscv64 under riscv64-softmmu. Launch the binary with +This is a sample platform package used for the SiFive Freedom U540 HiFive = Unleashed development board, please refer to "SiFive Freedom U540-C000 Manu= al" on https://www.sifive.com. +The binary built from Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleash= edBoard/ can run on both hardware and +[QEMU](https://git.qemu.org/?p=3Dqemu.git;a=3Dsummary). It is confirmed th= at version 5.0 of QEMU can boot with this firmware to EFI shell and Linux = userspace. +``` +build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveU= nleashedBoard/U540.dsc +``` +For running U540 edk2 binary on QEMU, use qemu-system-riscv64 under riscv6= 4-softmmu to launch the binary with +below parameters, =20 ``` --cpu sifive-u54 -machine sifive_u +qemu-system-riscv64 -cpu sifive-u54 -machine sifive_u -bios U540.fd -m 204= 8 -nographic -smp cpus=3D5,maxcpus=3D5 ``` =20 -## Download the sources +## Download the Source Code ``` -git clone https://github.com/tianocore/edk2-staging.git -# Checkout RISC-V-V2 branch +git clone https://github.com/tianocore/edk2.git git clone https://github.com/tianocore/edk2-platforms.git -# Checkout devel-riscvplatforms branch -git clone https://github.com/tianocore/edk2-non-osi.git +# Below to clone opensbi submodule. +git submodule update --init ``` - -## Platform Owners -Chang, Abner -Chen, Gilbert +Refer to [Readme.md](https://github.com/tianocore/edk2-platforms/blob/mast= er/Platform/RISC-V/PlatformPkg/Readme.md) for building RISC-V platforms. =20 ## Platform Status -Currently the binary built from U500Pkg can boot SiFive Freedom U500 VC707 +**FreedomU500VC707Board** +Currently the binary built from U500 edk2 package can boot SiFive Freedom = U500 VC707 FPGA to EFI shell with console in/out enabled. =20 -## Linux Build Instructions -You can build the RISC-V platform using below script, -`build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU500VC707= Board/U500.dsc` +**FreedomU540HiFiveUnleashedBoard** +Currently the binary built from U540 edk2 package can boot SiFive Freedom = U540 HiFive Unleashed +to EFI shell with console in/out enabled and Linux kernel. Please refer to= https://github.com/riscv/riscv-uefi-edk2-docs for booting to Linux kernel. =20 ## Supported Operating Systems -Only support to boot to EFI Shell so far. +Please refer to https://github.com/riscv/riscv-uefi-edk2-docs. =20 ## Known Issues and Limitations Only RISC-V RV64 is verified on this platform. =20 ## Related Materials +- [RISC-V UEFI Documents](https://github.com/riscv/riscv-uefi-edk2-docs) - [RISC-V OpenSbi](https://github.com/riscv/opensbi) - [SiFive U500 VC707 FPGA Getting Started Guide](https://sifive.cdn.prismi= c.io/sifive%2Fc248fabc-5e44-4412-b1c3-6bb6aac73a2c_sifive-u500-vc707-gettin= gstarted-v0.2.pdf) - [SiFive Freedom U540-C000 Manual](https://sifive.cdn.prismic.io/sifive%2= F834354f0-08e6-423c-bf1f-0cb58ef14061_fu540-c000-v1.0.pdf) @@ -63,48 +63,54 @@ Only RISC-V RV64 is verified on this platform. =20 ## U5SeriesPkg Libraries and Drivers ### PeiCoreInfoHobLib -This is the library to create RISC-V core characteristics for building up -RISC-V related SMBIOS records to support the unified boot loader and OS im= age. +This is the library to create RISC-V core characteristics for building up = RISC-V related SMBIOS records to support +a single boot loader or OS image on all RISC-V platforms by discovering R= ISC-V hart configurations dynamically. This library leverage the silicon libraries provided in Silicon/SiFive. =20 ### RiscVPlatformTimerLib -This is common U5 series platform timer library which has the -platform-specific timer implementation. +This is common U5 series platform timer library which has the platform-spe= cific timer implementation. + +### SerialLib +This is common U5 series platform serial port library. =20 ### TimerDxe -This is U5 series platform timer DXE driver whcih has the platform-specific -timer implementation. +This is common U5 series platform timer DXE driver which has the platform-= specific timer implementation. =20 ## U500 Platform Libraries and Drivers ### RiscVOpensbiPlatformLib -In order to reduce the dependencies with RISC-V OpenSBI project -(https://github.com/riscv/opensbi) and fewer burdens to EDK2 build process= , the -implementation of RISC-V EDK2 platform is leveraging platform source code = from +In order to reduce the dependencies with RISC-V OpenSBI project (https://g= ithub.com/riscv/opensbi) and avoid duplicating +code we use it, the implementation of RISC-V EDK2 platform is leveraging p= latform source code from OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from -RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build -environment. +[RISC-V OpenSBI code tree](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensb= iLib/opensbi) and built based on edk2 +build environment. =20 ### PlatformPei -This is the platform-implementation specific library which is executed in = early -PEI phase for U500 platform initialization. +This is the platform-implementation specific library which is executed in = early PEI phase for U500 platform +initialization. =20 ## U540 Platform Libraries and Drivers ### RiscVOpensbiPlatformLib -In order to reduce the dependencies with RISC-V OpenSBI project -(https://github.com/riscv/opensbi) and fewer burdens to EDK2 build process= , the -implementation of RISC-V EDK2 platform is leveraging platform source code = from +In order to reduce the dependencies with RISC-V OpenSBI project (https://g= ithub.com/riscv/opensbi) and fewer +burdens to EDK2 build process, the implementation of RISC-V EDK2 platform = is leveraging platform source code from OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from -RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build -environment. +[RISC-V OpenSBI code tree](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensb= iLib/opensbi) and built based on edk2 +build environment. =20 ### PlatformPei -This is the platform-implementation specific library which is executed in = early -PEI phase for U540 platform initialization. +This is the platform-implementation specific library which is executed in = early PEI phase for U540 platform +initialization. =20 ## U5SeriesPkg Platform PCD settings =20 | **PCD name** |**Usage**| |----------------|----------| +|PcdU5PlatformSystemClock| U5 series platform system clock| |PcdNumberofU5Cores| Number of U5 core enabled on U5 series platform| |PcdE5MCSupported| Indicates whether the Monitor Core (E5) is supported on= U5 series platform| |PcdU5UartBase|Platform serial port base address| + + +## Platform Owners +Chang, Abner +Chen, Gilbert +Schaefer, Daniel --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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