From nobody Sun May 5 12:57:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64612+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64612+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598362816; cv=none; d=zohomail.com; s=zohoarc; b=KrgHczCvrERMmoZWi28yHcFW3pH2BdCw24KRlaiccmx6c8egAy8qxS7xRFBceGbDNUdqVGElUpv00aujomj+AiTQn2w+R4LRgUFuuew8E/MVSDtWBVGAGXIB7me4Hd2NGZB4n0QhXDOmQI3iZd9t2u4CP4XB+rxVSxpYvVoqISI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598362816; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ALqTB8/xMB0ema3su2P1aJggDKj7GULC74uGaQXA/sE=; b=QvW2C7OYoZS830T6NGzPggQgP0BgRt3L4y4ZVjypv6zoaBeLproX8vbt3cbbQJt5Vnl6+hjmtG+7IavHMKInd68aTGd1L9a5Gmo5WYQhhz2oIW4IhAyk8GARWPjvzv+qyN2cy6MufuV0DnND8xAcMQKTcyDLluhz/gSOsQG1BTo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64612+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598362816426698.1089962668772; Tue, 25 Aug 2020 06:40:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id NipMYY1788612xzAQFt5k1o6; Tue, 25 Aug 2020 06:40:16 -0700 X-Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by mx.groups.io with SMTP id smtpd.web11.13788.1598362815590238456 for ; Tue, 25 Aug 2020 06:40:15 -0700 X-Received: by mail-pg1-f193.google.com with SMTP id g1so3054525pgm.9 for ; Tue, 25 Aug 2020 06:40:15 -0700 (PDT) X-Gm-Message-State: xpqaIAJHOhkOhcmMsG97XfUNx1787277AA= X-Google-Smtp-Source: ABdhPJw5jQD0Us2eMjnQIUgD07VAU+XFIfDHpGHst4tWEDDNlg2eDmeDGQKC6gODbdVxXTFU46U3jQ== X-Received: by 2002:a63:cf03:: with SMTP id j3mr6902982pgg.14.1598362815035; Tue, 25 Aug 2020 06:40:15 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id z186sm3913768pfb.199.2020.08.25.06.40.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 06:40:14 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale , Graeme Gregory , Jonathan Cameron Subject: [edk2-devel] [PATCH v3 edk2-platforms 1/8] SbsaQemu: Initial support for static ACPI tables Date: Tue, 25 Aug 2020 19:09:51 +0530 Message-Id: <20200825133958.17372-2-tanmay.jagdale@linaro.org> In-Reply-To: <20200825133958.17372-1-tanmay.jagdale@linaro.org> References: <20200825133958.17372-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598362816; bh=S1BWFc+NwSLL2+SJCHBfxxBQe/+nKkz5vGXUBf4VGHk=; h=Cc:Date:From:Reply-To:Subject:To; b=I8mcGucsmvmYYOGeyyqVbVx9WCvZS/0GIBnpImxAOP53N9DoLGqg2k5LVo8m8GrEopa 8MS22XtJSik9MDfbFHn3epOUpRLvhE2vSzjqPd5/MDrylrSx6G6WVMGdiuE0DNJWRUrfH BPFCtMoNTiquqPj/c8RGGAQfrFyk+RxJPFw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Add the following ACPI tables for SbsaQemu platform DSDT, FADT, GTDT, SPCR - Created an Include directory to hold common header files. - Also included the Acpiview shell utility. Co-authored-by: Graeme Gregory Co-authored-by: Jonathan Cameron Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 +- Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 35 ++++++ Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 + Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 8 ++ Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 45 +++++++ Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 31 +++++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 133 ++++++= ++++++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 80 ++++++= ++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 67 ++++++= ++++ Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 53 ++++++= ++ 10 files changed, 460 insertions(+), 2 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/Sbs= aQemu.dec index cd879f4dbd96..71ba55a082e2 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -21,8 +21,8 @@ [Defines] # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION # ##########################################################################= ###### -#[Includes.common] -# Include # Root include for the package +[Includes] + Include # Root include for the package =20 [Guids.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid =3D { 0xaab3bea9, 0xa8e8, 0x4e7= 6, { 0xb5, 0x3a, 0x35, 0x22, 0x11, 0xce, 0xf7, 0xf7 } } diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acp= i.dsc.inc new file mode 100644 index 000000000000..c4a8d7a27b78 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc @@ -0,0 +1,35 @@ +# +# Copyright (c) 2020, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LINARO" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x554D4551415342= 53 #SBSAQEMU + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20200810 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c #LNRO + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### + +[Components.common] + # + # ACPI support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 4db3ab465163..4739443cae93 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -516,6 +516,7 @@ [Components.common] ShellPkg/Application/Shell/Shell.inf { ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf @@ -675,3 +676,8 @@ [Components.common] MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # ACPI Support +!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/S= bsaQemu.fdf index be7c78acebfd..4526eaaa02c5 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf @@ -227,6 +227,14 @@ [FV.FvMain] INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf =20 + # + # ACPI support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF RuleOverride =3D ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTabl= es.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf + # # PCI support # diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu= /SbsaQemu/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000000..ee524895524e --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -0,0 +1,45 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2020, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SbsaAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dsdt.asl + Fadt.aslc + Gtdt.aslc + Spcr.aslc + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h new file mode 100644 index 000000000000..eac195b0585c --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -0,0 +1,31 @@ +/** @file +* +* Copyright (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SBSAQEMUACPI_H +#define SBSAQEMUACPI_H + +// A macro to initialise the common header part of EFI ACPI tables as defi= ned by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define SBSAQEMU_ACPI_HEADER(Signature, Type, Revision) { = \ + Signature, /* UINT32 Signature */ = \ + sizeof (Type), /* UINT32 Length */ = \ + Revision, /* UINT8 Revision */ = \ + 0, /* UINT8 Checksum */ = \ + { 'L', 'I', 'N', 'A', 'R', 'O' }, /* UINT8 OemId[6] */ = \ + FixedPcdGet64 (PcdAcpiDefaultOemTableId), /* UINT64 OemTableId */ = \ + FixedPcdGet32 (PcdAcpiDefaultOemRevision), /* UINT32 OemRevision */= \ + FixedPcdGet32 (PcdAcpiDefaultCreatorId), /* UINT32 CreatorId */ = \ + FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevisio= n */ \ + } + +#define SBSAQEMU_UART0_BASE 0x60000000 + +#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000 +#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00 +#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF + +#endif diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQ= emu/AcpiTables/Dsdt.asl new file mode 100644 index 000000000000..85339d4559d3 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl @@ -0,0 +1,133 @@ +/** @file +* Differentiated System Description Table Fields (DSDT). +* +* Copyright (c) 2020, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU", + FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { + Scope (_SB) { + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x60000000, 0x00001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 } + }) + } + + // AHCI Host Controller + Device (AHC0) { + Name (_HID, "LNRO001E") + Name (_CLS, Package (3) { + 0x01, + 0x06, + 0x01, + }) + Name (_CCA, 1) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x60100000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 } + }) + } + + // USB EHCI Host Controller + Device (USB0) { + Name (_HID, "LNRO0D20") + Name (_CID, "PNP0D20") + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x60110000, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive)= { 43 } + }) + Return (RBUF) + } + + // Root Hub + Device (RHUB) { + Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as= per ACPI 5.0 spec + + // Ports connected to Root Hub + Device (HUB1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0x00, // Port is NOT connectable + 0xFF, // Don't care + 0x00000000, // Reserved 0 must be zero + 0x00000000 // Reserved 1 must be zero + }) + + Device (PRT1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer(0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT1 + Device (PRT2) { + Name (_ADR, 0x00000002) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer(0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT2 + + Device (PRT3) { + Name (_ADR, 0x00000003) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer (0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT3 + + Device (PRT4) { + Name (_ADR, 0x00000004) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer (0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT4 + } // USB0_RHUB_HUB1 + } // USB0_RHUB + } // USB0 + + } // Scope (_SB) +} diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Fadt.aslc new file mode 100644 index 000000000000..894b848db8bb --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc @@ -0,0 +1,80 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmP= rofile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_0_HW_REDUCED_ACPI | + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // GAS ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchF= lags + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, + // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // GAS XPm1aEvtBlk + NULL_GAS, // GAS XPm1bEvtBlk + NULL_GAS, // GAS XPm1aCntBlk + NULL_GAS, // GAS XPm1bCntBlk + NULL_GAS, // GAS XPm2CntBlk + NULL_GAS, // GAS XPmTmrBlk + NULL_GAS, // GAS XGpe0Blk + NULL_GAS, // GAS XGpe1Blk + NULL_GAS, // GAS SleepControl= Reg + NULL_GAS, // GAS SleepStatusR= eg + 0 // UINT64 HypervisorVe= ndorId +}; + +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Fadt; diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Gtdt.aslc new file mode 100644 index 000000000000..52496acc449b --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc @@ -0,0 +1,67 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyrignt (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY= _MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERR= UPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/no= n-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_G= LOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GT= DT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LE= VEL_TRIGGERED) + + #pragma pack (1) + + typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + } GENERIC_TIMER_DESCRIPTION_TABLE; + + #pragma pack () + + GENERIC_TIMER_DESCRIPTION_TABLE Gtdt =3D { + { + SBSAQEMU_ACPI_HEADER( + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAdd= ress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1Ti= merGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1Ti= merFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL= 1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL= 1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL= 2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL= 2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBase= PhysicalAddress + 0, // UINT32 PlatformTim= erCount + 0 + }, + }; + +// Reference the table being generated to prevent the optimizer from remov= ing the +// data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Spcr.aslc new file mode 100644 index 000000000000..7498fd8c0a98 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc @@ -0,0 +1,53 @@ +/** @file +* Serial Port Console Redirection Table (SPCR). +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +#pragma pack(push, 1) + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + 2), /* New MS definition for PL011 support */ + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_= UART, + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE= }, + { + EFI_ACPI_6_0_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_0_DWORD, + SBSAQEMU_UART0_BASE + }, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + 0, /* Irq */ + 33, /* GlobalSystemInterrupt */ + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + 0, /* Flow Control */ + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + EFI_ACPI_RESERVED_BYTE, /* Language */ + 0xFFFF, /* PciDeviceId */ + 0xFFFF, /* PciVendorId */ + 0x00, /* PciBusNumber */ + 0x00, /* PciDeviceNumber */ + 0x00, /* PciFunctionNumber */ + 0, /* PciFlags */ + 0, /* PciSegment */ + EFI_ACPI_RESERVED_DWORD +}; + +#pragma pack(pop) + +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Spcr; --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64612): https://edk2.groups.io/g/devel/message/64612 Mute This Topic: https://groups.io/mt/76406664/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 12:57:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64613+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64613+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598362829; cv=none; d=zohomail.com; s=zohoarc; b=U7mCvqC58gdIqkNQnqWcPh78xc0PiYhNFg/ApixCu8+rtk+PyO2p9iwtZBLxNcytRaRykbCO7qnHmzRFAzgcYNPOAeyGLaO3GVaPv/fX0Em8S17fXycpQdV76IX53IVI6ngejB952CWtCK2R1E7sBvGPUmMpPw1ZE6fxlxPXBv0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598362829; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=IGmkhlguHR2N93v7yHhO427KHVX4h08FIDx5NTxocMQ=; b=ka0Fwjf4gCowCntmqMv04un6CH7rkD9ibAHW5I2BUC0zQhwFiH/9HQSWlX/5qnx5hPJUwAcrcoXnjOxaH+kLTX/B3b4QZs9PrlaX2oDRAbYhlCVx0ueH30Qn5Is1RMdGeZMQOnLe9pnZeCIGOC2T4zWCFTevrIa1oWAEcdAvJP0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64613+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598362829715319.9686703948611; Tue, 25 Aug 2020 06:40:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3JywYY1788612xxJE9M4aYMu; Tue, 25 Aug 2020 06:40:29 -0700 X-Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by mx.groups.io with SMTP id smtpd.web11.13796.1598362828911419088 for ; Tue, 25 Aug 2020 06:40:28 -0700 X-Received: by mail-pg1-f193.google.com with SMTP id h12so6847344pgm.7 for ; Tue, 25 Aug 2020 06:40:28 -0700 (PDT) X-Gm-Message-State: bAg1Wc1Yqs2sz776lDjAlpsMx1787277AA= X-Google-Smtp-Source: ABdhPJz7bK8E6LXdciZ4A5QNBVgREgRBk3lY96hSiGQ8YqtB2z8bKeYe0A/RbgOHrNtUH4PUAXkKqw== X-Received: by 2002:a17:902:9a0b:: with SMTP id v11mr8119198plp.236.1598362828341; Tue, 25 Aug 2020 06:40:28 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id z186sm3913768pfb.199.2020.08.25.06.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 06:40:27 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale , Graeme Gregory Subject: [edk2-devel] [PATCH v3 edk2-platforms 2/8] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Date: Tue, 25 Aug 2020 19:09:52 +0530 Message-Id: <20200825133958.17372-3-tanmay.jagdale@linaro.org> In-Reply-To: <20200825133958.17372-1-tanmay.jagdale@linaro.org> References: <20200825133958.17372-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598362829; bh=bj0hB6xPpL3tg4gCkItd0CpqAyCigDXSTpa2bUj5izo=; h=Cc:Date:From:Reply-To:Subject:To; b=uuD17i460a2+3yuoXPMnOrC1cuiNfNQRZ3V9rObyc0N1rm58O8hLSMkGUuKuZQYmXE2 uVYPGcKOkvXXPJjbxG4L/9s9YkJXMJ+lXPn6pOhkK0Od8eVzeJ55jA8D8O0AL0SMbpiu+ M7a4pOZhgBf/uiJWi7IXR3N4Uppd0keTCYs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add PCI related entries to DSDT table along with the routing entries. Also add the MCFG table. Co-authored-by: Graeme Gregory Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 316 ++++++++++++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 +++ 3 files changed, 360 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu= /SbsaQemu/AcpiTables/AcpiTables.inf index ee524895524e..57d717fefafc 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -19,6 +19,7 @@ [Sources] Dsdt.asl Fadt.aslc Gtdt.aslc + Mcfg.aslc Spcr.aslc =20 [Packages] diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQ= emu/AcpiTables/Dsdt.asl index 85339d4559d3..d9ca2f69dc9c 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl @@ -8,6 +8,23 @@ =20 #include =20 +#define LINK_DEVICE(Uid, LinkName, Irq) = \ + Device (LinkName) { = \ + Name (_HID, EISAID("PNP0C0F")) = \ + Name (_UID, Uid) = \ + Name (_PRS, ResourceTemplate() { = \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive)= { Irq } \ + }) = \ + Method (_CRS, 0) { Return (_PRS) } = \ + Method (_SRS, 1) { } = \ + Method (_DIS) { } = \ + } + +#define PRT_ENTRY(Address, Pin, Link) = \ + Package (4) { = \ + Address, Pin, Link, Zero = \ + } + DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU", FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { Scope (_SB) { @@ -129,5 +146,304 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO"= , "SBSAQEMU", } // USB0_RHUB } // USB0 =20 + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_ADR, Zero) + Name (_UID, "PCI0") + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) + + Method (_CBA, 0, NotSerialized) { + return (0xf0000000) + } + + LINK_DEVICE(0, GSI0, 0x23) + LINK_DEVICE(1, GSI1, 0x24) + LINK_DEVICE(2, GSI2, 0x25) + LINK_DEVICE(3, GSI3, 0x26) + + Name (_PRT, Package () // _PRT: PCI Routing Table + { + PRT_ENTRY(0x0000FFFF, 0, GSI0), + PRT_ENTRY(0x0000FFFF, 0, GSI1), + PRT_ENTRY(0x0000FFFF, 0, GSI2), + PRT_ENTRY(0x0000FFFF, 0, GSI3), + + PRT_ENTRY(0x0001FFFF, 0, GSI1), + PRT_ENTRY(0x0001FFFF, 1, GSI2), + PRT_ENTRY(0x0001FFFF, 2, GSI3), + PRT_ENTRY(0x0001FFFF, 3, GSI0), + + PRT_ENTRY(0x0002FFFF, 0, GSI2), + PRT_ENTRY(0x0002FFFF, 1, GSI3), + PRT_ENTRY(0x0002FFFF, 2, GSI0), + PRT_ENTRY(0x0002FFFF, 3, GSI1), + + PRT_ENTRY(0x0003FFFF, 0, GSI3), + PRT_ENTRY(0x0003FFFF, 1, GSI0), + PRT_ENTRY(0x0003FFFF, 2, GSI1), + PRT_ENTRY(0x0003FFFF, 3, GSI2), + + PRT_ENTRY(0x0004FFFF, 0, GSI0), + PRT_ENTRY(0x0004FFFF, 1, GSI1), + PRT_ENTRY(0x0004FFFF, 2, GSI2), + PRT_ENTRY(0x0004FFFF, 3, GSI3), + + PRT_ENTRY(0x0005FFFF, 0, GSI1), + PRT_ENTRY(0x0005FFFF, 1, GSI2), + PRT_ENTRY(0x0005FFFF, 2, GSI3), + PRT_ENTRY(0x0005FFFF, 3, GSI0), + + PRT_ENTRY(0x0006FFFF, 0, GSI2), + PRT_ENTRY(0x0006FFFF, 1, GSI3), + PRT_ENTRY(0x0006FFFF, 2, GSI0), + PRT_ENTRY(0x0006FFFF, 3, GSI1), + + PRT_ENTRY(0x0007FFFF, 0, GSI3), + PRT_ENTRY(0x0007FFFF, 1, GSI0), + PRT_ENTRY(0x0007FFFF, 2, GSI1), + PRT_ENTRY(0x0007FFFF, 3, GSI2), + + PRT_ENTRY(0x0008FFFF, 0, GSI0), + PRT_ENTRY(0x0008FFFF, 1, GSI1), + PRT_ENTRY(0x0008FFFF, 2, GSI2), + PRT_ENTRY(0x0008FFFF, 3, GSI3), + + PRT_ENTRY(0x0009FFFF, 0, GSI1), + PRT_ENTRY(0x0009FFFF, 1, GSI2), + PRT_ENTRY(0x0009FFFF, 2, GSI3), + PRT_ENTRY(0x0009FFFF, 3, GSI0), + + PRT_ENTRY(0x000AFFFF, 0, GSI2), + PRT_ENTRY(0x000AFFFF, 1, GSI3), + PRT_ENTRY(0x000AFFFF, 2, GSI0), + PRT_ENTRY(0x000AFFFF, 3, GSI1), + + PRT_ENTRY(0x000BFFFF, 0, GSI3), + PRT_ENTRY(0x000BFFFF, 1, GSI0), + PRT_ENTRY(0x000BFFFF, 2, GSI1), + PRT_ENTRY(0x000BFFFF, 3, GSI2), + + PRT_ENTRY(0x000CFFFF, 0, GSI0), + PRT_ENTRY(0x000CFFFF, 1, GSI1), + PRT_ENTRY(0x000CFFFF, 2, GSI2), + PRT_ENTRY(0x000CFFFF, 3, GSI3), + + PRT_ENTRY(0x000DFFFF, 0, GSI1), + PRT_ENTRY(0x000DFFFF, 1, GSI2), + PRT_ENTRY(0x000DFFFF, 2, GSI3), + PRT_ENTRY(0x000DFFFF, 3, GSI0), + + PRT_ENTRY(0x000EFFFF, 0, GSI2), + PRT_ENTRY(0x000EFFFF, 1, GSI3), + PRT_ENTRY(0x000EFFFF, 2, GSI0), + PRT_ENTRY(0x000EFFFF, 3, GSI1), + + PRT_ENTRY(0x000FFFFF, 0, GSI3), + PRT_ENTRY(0x000FFFFF, 1, GSI0), + PRT_ENTRY(0x000FFFFF, 2, GSI1), + PRT_ENTRY(0x000FFFFF, 3, GSI2), + + PRT_ENTRY(0x0010FFFF, 0, GSI0), + PRT_ENTRY(0x0010FFFF, 1, GSI1), + PRT_ENTRY(0x0010FFFF, 2, GSI2), + PRT_ENTRY(0x0010FFFF, 3, GSI3), + + PRT_ENTRY(0x0011FFFF, 0, GSI1), + PRT_ENTRY(0x0011FFFF, 1, GSI2), + PRT_ENTRY(0x0011FFFF, 2, GSI3), + PRT_ENTRY(0x0011FFFF, 3, GSI0), + + PRT_ENTRY(0x0012FFFF, 0, GSI2), + PRT_ENTRY(0x0012FFFF, 1, GSI3), + PRT_ENTRY(0x0012FFFF, 2, GSI0), + PRT_ENTRY(0x0012FFFF, 3, GSI1), + + PRT_ENTRY(0x0013FFFF, 0, GSI3), + PRT_ENTRY(0x0013FFFF, 1, GSI0), + PRT_ENTRY(0x0013FFFF, 2, GSI1), + PRT_ENTRY(0x0013FFFF, 3, GSI2), + + PRT_ENTRY(0x0014FFFF, 0, GSI0), + PRT_ENTRY(0x0014FFFF, 1, GSI1), + PRT_ENTRY(0x0014FFFF, 2, GSI2), + PRT_ENTRY(0x0014FFFF, 3, GSI3), + + PRT_ENTRY(0x0015FFFF, 0, GSI1), + PRT_ENTRY(0x0015FFFF, 1, GSI2), + PRT_ENTRY(0x0015FFFF, 2, GSI3), + PRT_ENTRY(0x0015FFFF, 3, GSI0), + + PRT_ENTRY(0x0016FFFF, 0, GSI2), + PRT_ENTRY(0x0016FFFF, 1, GSI3), + PRT_ENTRY(0x0016FFFF, 2, GSI0), + PRT_ENTRY(0x0016FFFF, 3, GSI1), + + PRT_ENTRY(0x0017FFFF, 0, GSI3), + PRT_ENTRY(0x0017FFFF, 1, GSI0), + PRT_ENTRY(0x0017FFFF, 2, GSI1), + PRT_ENTRY(0x0017FFFF, 3, GSI2), + + PRT_ENTRY(0x0018FFFF, 0, GSI0), + PRT_ENTRY(0x0018FFFF, 1, GSI1), + PRT_ENTRY(0x0018FFFF, 2, GSI2), + PRT_ENTRY(0x0018FFFF, 3, GSI3), + + PRT_ENTRY(0x0019FFFF, 0, GSI1), + PRT_ENTRY(0x0019FFFF, 1, GSI2), + PRT_ENTRY(0x0019FFFF, 2, GSI3), + PRT_ENTRY(0x0019FFFF, 3, GSI0), + + PRT_ENTRY(0x001AFFFF, 0, GSI2), + PRT_ENTRY(0x001AFFFF, 1, GSI3), + PRT_ENTRY(0x001AFFFF, 2, GSI0), + PRT_ENTRY(0x001AFFFF, 3, GSI1), + + PRT_ENTRY(0x001BFFFF, 0, GSI3), + PRT_ENTRY(0x001BFFFF, 1, GSI0), + PRT_ENTRY(0x001BFFFF, 2, GSI1), + PRT_ENTRY(0x001BFFFF, 3, GSI2), + + PRT_ENTRY(0x001CFFFF, 0, GSI0), + PRT_ENTRY(0x001CFFFF, 1, GSI1), + PRT_ENTRY(0x001CFFFF, 2, GSI2), + PRT_ENTRY(0x001CFFFF, 3, GSI3), + + PRT_ENTRY(0x001DFFFF, 0, GSI1), + PRT_ENTRY(0x001DFFFF, 1, GSI2), + PRT_ENTRY(0x001DFFFF, 2, GSI3), + PRT_ENTRY(0x001DFFFF, 3, GSI0), + + PRT_ENTRY(0x001EFFFF, 0, GSI2), + PRT_ENTRY(0x001EFFFF, 1, GSI3), + PRT_ENTRY(0x001EFFFF, 2, GSI0), + PRT_ENTRY(0x001EFFFF, 3, GSI1), + + PRT_ENTRY(0x001FFFFF, 0, GSI3), + PRT_ENTRY(0x001FFFFF, 1, GSI0), + PRT_ENTRY(0x001FFFFF, 2, GSI1), + PRT_ENTRY(0x001FFFFF, 3, GSI2), + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min Base Address + 0xEFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x70000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x100000000, // Min Base Address + 0xFFFFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0xFF00000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x0000ffff, // Max Base Address + 0x7fff0000, // Translate + 0x00010000, // Length + ,,,TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: H= ardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, N= onCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000000F0000000, // Range Minimum + 0x00000000FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + // OS Control Handoff + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + * See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC,4) { + // Check for proper UUID + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3,0,CDW1) + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If (LNotEqual(And(SUPP, 0x16), 0x16)) { + And (CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And (CTRL,0x1D,CTRL) + + If (LNotEqual(Arg1,One)) { // Unknown revision + Or (CDW1,0x08,CDW1) + } + + If (LNotEqual(CDW3,CTRL)) { // Capabilities bits were mas= ked + Or (CDW1,0x10,CDW1) + } + + // Update DWORD3 in the buffer + Store (CTRL,CDW3) + Return (Arg3) + } Else { + Or (CDW1,4,CDW1) // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } } // Scope (_SB) } diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Mcfg.aslc new file mode 100644 index 000000000000..5744884a4ad6 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc @@ -0,0 +1,43 @@ +/** @file +* ACPI Memory mapped configuration space base address Description Table (= MCFG). +* +* Copyright (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#pragma pack(push, 1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure[2]; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = =3D { + { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDR= ESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), + EFI_ACPI_RESERVED_QWORD + }, + { + { + SBSAQEMU_PCI_SEG0_CONFIG_BASE, + 0, + SBSAQEMU_PCI_SEG0_BUSNUM_MIN, + SBSAQEMU_PCI_SEG0_BUSNUM_MAX, + EFI_ACPI_RESERVED_DWORD + } + } +}; + +#pragma pack(pop) + +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Mcfg; --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64613): https://edk2.groups.io/g/devel/message/64613 Mute This Topic: https://groups.io/mt/76406673/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 12:57:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64614+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64614+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598362845; cv=none; d=zohomail.com; s=zohoarc; b=LBGkanH7rXsRjlnmD96kN1Yct4Dpqih+IoDuBmL/B1tP0Dpg6sJx9tWNkSPm9eEDJWXGns91+D+eroyC26D6VKu4K9pf2g9AGmx0diVVpsQQ8EE3tTfpJDy2Y5UCQNY5itLVtnFEG3UZJeKhjedJXdJbdz4u00WRyaR8dQUSiQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598362845; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wbJBAo3+mf+hRZkLfF1BDNLy8VjQn7gQj1uwc0rdlts=; b=Bkm9eqjkfJ8Z8atQuOfngmQJjalr1act/JLKnCgxkpL+9MJS5pufs/mgNyATndCigrFaeit9zRysyleX3Q0vsIOrHSWW7lqCvW6ZfNsNrtI4xAoQ7hWEUB1YQlsI/wkKEg7xugxjJMtoz1odTrW8HWhM+bTTePQxPRSi7NJ49G4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64614+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598362845410580.8324356192518; Tue, 25 Aug 2020 06:40:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 794CYY1788612xUtW2EmJKGm; Tue, 25 Aug 2020 06:40:45 -0700 X-Received: from mail-pj1-f66.google.com (mail-pj1-f66.google.com [209.85.216.66]) by mx.groups.io with SMTP id smtpd.web10.13839.1598362844525671270 for ; Tue, 25 Aug 2020 06:40:44 -0700 X-Received: by mail-pj1-f66.google.com with SMTP id j13so1252117pjd.4 for ; Tue, 25 Aug 2020 06:40:44 -0700 (PDT) X-Gm-Message-State: 0vLfoeQWDvYvBHG7DtIMZn6Vx1787277AA= X-Google-Smtp-Source: ABdhPJzo0I8GJGnqwRmIw05RspYi05aoJ1AMMU7fT93oBW6YBaNYfWH3+7Vp5Qz8qSAUh3GLOoR0UQ== X-Received: by 2002:a17:90a:f48e:: with SMTP id bx14mr1200524pjb.233.1598362844091; Tue, 25 Aug 2020 06:40:44 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id z186sm3913768pfb.199.2020.08.25.06.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 06:40:43 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale Subject: [edk2-devel] [PATCH v3 edk2-platforms 3/8] SbsaQemu: SbsaQemu.dsc: Move CoreCount and Fdtlib Date: Tue, 25 Aug 2020 19:09:53 +0530 Message-Id: <20200825133958.17372-4-tanmay.jagdale@linaro.org> In-Reply-To: <20200825133958.17372-1-tanmay.jagdale@linaro.org> References: <20200825133958.17372-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598362845; bh=/IMMzAZ4ZvsjW673VXVT90zOsigmGNpE05zLirehFCU=; h=Cc:Date:From:Reply-To:Subject:To; b=JE/e3j8zcoW2NrLdqiUYMofNMRqdnSczTlRZuPJ+bJn8Jua+YK7NjclUZVcTwyY/UNN MovXNFFdhM+Qrro5BAHO/7k3aTZ70D+tPC8IYUXwMPnem/anElsZ1wj1Ur8UdkkcoJiQ0 E0ypsx9sNCI+pBMIj5rrRw8+w4kZMO5670E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Since the core count is dynamic and controlled by Qemu, move the PcdCoreCount from [PcdsFixedAtBuild] to [PcdsDynamic] section. - Move FdtLib from [LibraryClasses.common.PEIM] to [LibraryClasses.common] section so that driver DXEs can use the device tree APIs. Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 ++++ Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 ++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/Sbs= aQemu.dec index 71ba55a082e2..ed87d15de003 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -35,3 +35,7 @@ [PcdsFixedAtBuild.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x00= 000003 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT3= 2|0x00000004 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x100000= 00000|UINT64|0x00000005 + +[PcdsDynamic.common] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000006 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x0000= 0007 diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 4739443cae93..d42b9cd4de49 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -75,6 +75,7 @@ [LibraryClasses.common] ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf =20 + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf =20 @@ -217,7 +218,6 @@ [LibraryClasses.common.PEIM] =20 PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf =20 - FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf ArmPlatformLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf =20 [LibraryClasses.common.DXE_CORE] @@ -376,7 +376,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE =20 - gArmPlatformTokenSpaceGuid.PcdCoreCount|1 gArmTokenSpaceGuid.PcdVFPEnabled|1 =20 # System Memory Base -- fixed @@ -477,6 +476,9 @@ [PcdsFixedAtBuild.common] [PcdsDynamicDefault.common] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 =20 + # Core and Cluster Count + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|1 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|1 =20 # System Memory Size -- 128 MB initially, actual size will be fetched fr= om DT # TODO as no DT will be used we should pass this by some other method --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64614): https://edk2.groups.io/g/devel/message/64614 Mute This Topic: https://groups.io/mt/76406679/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 12:57:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64615+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64615+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598362859; cv=none; d=zohomail.com; s=zohoarc; b=B61jtI6N9BTNa8XFqV1KdQeADqZK6XwYbhx6jFrtPhDQNRjaREOAgrUdc7nDCErSy9POqPIjCdwJtUz8qdj2MSvttcwQJ8TkJCUSB96k5+bG3e915ixrZpQPMkIlwwh/4iiOwEts0K7Ms3lgkYuS4ZaGXoRDX20chnQRd1gfQGs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598362859; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=L4NjdVmDaQ0bczQ89qn5IADCnn/SzEv69n0wuoSRaGw=; b=ei3qwRZpsxPDV0PQQSRikYa8eN6oueRbMg5gjEs1DuZYlIXlO3H+uIqWGmvbHeqri70usDhte3yFGWWM/ez6kmu5PiPtcX6alc0oJKzgrQvwv8Ttk702/DadxvBdVsOyexnFniuFW4an4g5uTf3p1fxb+dJTVnEEVu8/Lta4XkA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64615+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 159836285990755.004421918309276; Tue, 25 Aug 2020 06:40:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id NycKYY1788612xmcTZGstPqe; Tue, 25 Aug 2020 06:40:57 -0700 X-Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by mx.groups.io with SMTP id smtpd.web10.13842.1598362857153267298 for ; Tue, 25 Aug 2020 06:40:57 -0700 X-Received: by mail-pg1-f193.google.com with SMTP id d19so6840152pgl.10 for ; Tue, 25 Aug 2020 06:40:57 -0700 (PDT) X-Gm-Message-State: fgp91QutFcDB16G7l2gLRq8Ix1787277AA= X-Google-Smtp-Source: ABdhPJwxR2fcjZF/LEo0RZw4QE2cY4pvZNKl3bMhc5OL/Cb18vVnSA9A1WV3IwNMYcdUl6jWoaDXsw== X-Received: by 2002:a63:5a41:: with SMTP id k1mr6640589pgm.346.1598362856660; Tue, 25 Aug 2020 06:40:56 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id z186sm3913768pfb.199.2020.08.25.06.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 06:40:56 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale Subject: [edk2-devel] [PATCH v3 edk2-platforms 4/8] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs Date: Tue, 25 Aug 2020 19:09:54 +0530 Message-Id: <20200825133958.17372-5-tanmay.jagdale@linaro.org> In-Reply-To: <20200825133958.17372-1-tanmay.jagdale@linaro.org> References: <20200825133958.17372-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598362857; bh=exGjw3sxixZSZtIcTAPCJy5lTwsJVg8UWfwjrwz20Bk=; h=Cc:Date:From:Reply-To:Subject:To; b=pfH3LMJDGG0MXljQJ/vMRK8UV12rM0Cze8X+zhqUQ7aW4HxfFx+QJu2Lxo+LFGZZ3BU VyGPOse/DmOT0E8JgwwfmMLPHkiTRknup56Lg3luVrtVMVj8bE9uXmzbwHJ7wWk3BuyPK aTXc3M89F/AYT8m+1vOJ0jAQ4IhE17T7aRY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Add a new ACPI driver for the SbsaQemu platform which would handle any modifications needed for the ACPI tables. - Add a parser function in this driver which parses the FDT created by Qemu to determine the number of CPUs and hence update the PcdCoreCount variable. Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 1 + Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 49 +++= ++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 75 +++= +++++++++++++++++ 4 files changed, 126 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acp= i.dsc.inc index c4a8d7a27b78..593670383750 100644 --- a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc @@ -33,3 +33,4 @@ [Components.common] MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/S= bsaQemu.fdf index 4526eaaa02c5..3bcf0bf0040a 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf @@ -232,6 +232,7 @@ [FV.FvMain] # INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf INF RuleOverride =3D ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTabl= es.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf =20 diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf new file mode 100644 index 000000000000..3795a7e11639 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -0,0 +1,49 @@ +## @file +# This driver modifies ACPI tables for the Qemu SBSA platform +# +# Copyright (c) 2020, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001d + BASE_NAME =3D SbsaQemuAcpiDxe + FILE_GUID =3D 6c592dc9-76c8-474f-93b2-bf1e8f15ae35 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D InitializeSbsaQemuAcpiDxe + +[Sources] + SbsaQemuAcpiDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmVirtPkg/ArmVirtPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[LibraryClasses] + ArmLib + BaseMemoryLib + BaseLib + DebugLib + DxeServicesLib + FdtLib + PcdLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Pcd] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress + +[Depex] + TRUE diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c new file mode 100644 index 000000000000..75abdae3b8ce --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -0,0 +1,75 @@ +/** @file +* This file is an ACPI driver for the Qemu SBSA platform. +* +* Copyright (c) 2020, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include + +/* + * A function that walks through the Device Tree created + * by Qemu and counts the number of CPUs present in it. + */ +STATIC +VOID +CountCpusFromFdt ( + VOID +) +{ + VOID *DeviceTreeBase; + INT32 Node, Prev; + RETURN_STATUS PcdStatus; + INT32 CpuNode; + INT32 CpuCount; + + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); + ASSERT (DeviceTreeBase !=3D NULL); + + // Make sure we have a valid device tree blob + ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); + + CpuNode =3D fdt_path_offset (DeviceTreeBase, "/cpus"); + if (CpuNode <=3D 0) { + DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n")); + return; + } + + CpuCount =3D 0; + + // Walk through /cpus node and count the number of subnodes. + // The count of these subnodes corresponds to the number of + // CPUs created by Qemu. + Prev =3D fdt_first_subnode (DeviceTreeBase, CpuNode); + while (1) { + CpuCount++; + Node =3D fdt_next_subnode (DeviceTreeBase, Prev); + if (Node < 0) { + break; + } + Prev =3D Node; + } + + PcdStatus =3D PcdSet32S (PcdCoreCount, CpuCount); + ASSERT_RETURN_ERROR (PcdStatus); +} + +EFI_STATUS +EFIAPI +InitializeSbsaQemuAcpiDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // Parse the device tree and get the number of CPUs + CountCpusFromFdt (); + + return EFI_SUCCESS; +} --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64615): https://edk2.groups.io/g/devel/message/64615 Mute This Topic: https://groups.io/mt/76406682/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 12:57:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64616+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64616+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598362870; cv=none; d=zohomail.com; s=zohoarc; b=STwQB17+GbESTCBckY/6x0u7R78maxJz8oGwr3fbabNkDcqlEcH86Zfm/k42DkV1EPE7uIKVbgmA6+oR31AB7l3QWnSyZDoCpr54Z9b+v0cSNZy40OEttYaGhDQ3MbdyBUKGvYtMRnN2t0xE9tUihS2BHzZMMy/cadgos4F8C/s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598362870; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QPIw2t8f3gtTMDR1h9VSCEbHY5FctUT7iCs2ZqXupvs=; b=PBvEFbV5wCy2cVCBZFzQEhp06p5HzK925Zki9RzcROr9igjnNLFQbbdDhVP0X7RZnPf/tb84otTWxE/GosXoDG0VpyVKpPoS25cvofjDpl+j/rR+8LSmR2LqGIIWgIJS5enGGEM2Z1jiY6RmmRi10QUCx4uXF9/0m0vjNNFw+3g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64616+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598362870101430.5065682378457; Tue, 25 Aug 2020 06:41:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id eujbYY1788612xQaM2ZqUYUS; Tue, 25 Aug 2020 06:41:09 -0700 X-Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by mx.groups.io with SMTP id smtpd.web10.13848.1598362869210990708 for ; Tue, 25 Aug 2020 06:41:09 -0700 X-Received: by mail-pg1-f193.google.com with SMTP id 31so4598942pgy.13 for ; Tue, 25 Aug 2020 06:41:09 -0700 (PDT) X-Gm-Message-State: 0IHFUYwt5MPKEcdsrzkWYnRax1787277AA= X-Google-Smtp-Source: ABdhPJwY8G/XWJSoIieyRUoUuZlDg/DockhD5YDz7O8ayAjE511RyD9Vqf/fmzt6PxfHAhK8Bd0txQ== X-Received: by 2002:a17:902:7596:: with SMTP id j22mr7641790pll.309.1598362868753; Tue, 25 Aug 2020 06:41:08 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id z186sm3913768pfb.199.2020.08.25.06.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 06:41:08 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale Subject: [edk2-devel] [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime Date: Tue, 25 Aug 2020 19:09:55 +0530 Message-Id: <20200825133958.17372-6-tanmay.jagdale@linaro.org> In-Reply-To: <20200825133958.17372-1-tanmay.jagdale@linaro.org> References: <20200825133958.17372-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598362869; bh=C7r6dX4MjOkuW0J0fYa/jyR48zkMqViEbXHSgNbE4m4=; h=Cc:Date:From:Reply-To:Subject:To; b=vlmHk4GLK+KDuVU1bxZgbuuy5a6Ua1JZezwqQbt/iNpRkFc3vRrK4Z0hZKBAoR6P/dQ ij0/cpEXrxYihV+CG1CpdIEpPgsrU8zF5ABsjHI4kCnJ0I2X9c4zVmkJbrUwSRNfIO5dV Oeid6aQtzhqOdiN+Bi6BTV3vrtB7Ip3BIOA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Add support to create MADT table at runtime. - Included a macro for GIC Redistributor structure initialisation. Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++- Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 156 ++= ++++++++++++++++++ 3 files changed, 190 insertions(+), 1 deletion(-) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf index 3795a7e11639..8125e8ba7553 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -41,9 +41,27 @@ [LibraryClasses] UefiRuntimeServicesTableLib =20 [Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress =20 [Depex] - TRUE + gEfiAcpiTableProtocolGuid ## CONSUMES + +[Guids] + gEdkiiPlatformHasAcpiGuid + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index eac195b0585c..7a9a0061675f 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -22,6 +22,21 @@ FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevisio= n */ \ } =20 +// Defines for MADT +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000 +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000 +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23 +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000 + +// Macro for MADT GIC Redistributor Structure +#define SBSAQEMU_MADT_GICR_INIT() { = \ + EFI_ACPI_6_0_GICR, /* Type */ = \ + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ = \ + EFI_ACPI_RESERVED_WORD, /* Reserved */ = \ + FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress = */ \ + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ = \ + } + #define SBSAQEMU_UART0_BASE 0x60000000 =20 #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000 diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 75abdae3b8ce..16cb4e904e6f 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -6,11 +6,17 @@ * SPDX-License-Identifier: BSD-2-Clause-Patent * **/ +#include +#include +#include +#include #include +#include #include #include #include #include +#include #include #include =20 @@ -61,6 +67,137 @@ CountCpusFromFdt ( ASSERT_RETURN_ERROR (PcdStatus); } =20 +/* + * A Function to Compute the ACPI Table Checksum + */ +VOID +AcpiPlatformChecksum ( + IN UINT8 *Buffer, + IN UINTN Size + ) +{ + UINTN ChecksumOffset; + + ChecksumOffset =3D OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + + // Set checksum field to 0 since it is used as part of the calculation + Buffer[ChecksumOffset] =3D 0; + + Buffer[ChecksumOffset] =3D CalculateCheckSum8(Buffer, Size); +} + +/* + * A function that add the MADT ACPI table. + IN EFI_ACPI_COMMON_HEADER *CurrentTable + */ +EFI_STATUS +AddMadtTable ( + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable + ) +{ + EFI_STATUS Status; + UINTN TableHandle; + UINT32 TableSize; + EFI_PHYSICAL_ADDRESS PageAddress; + UINT8 *New; + UINT32 NumCores; + + // Initialize MADT ACPI Header + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header =3D { + SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SI= GNATURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HE= ADER, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_RE= VISION), + 0, 0 }; + + // Initialize GICC Structure + EFI_ACPI_6_0_GIC_STRUCTURE Gicc =3D EFI_ACPI_6_0_GICC_STRUCTURE_INIT ( + 0, /* GicID */ + 0, /* AcpiCpuUid */ + 0, /* Mpidr */ + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */ + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */ + FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */ + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */ + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */ + 25, /* GsivId */ + 0, /* GicRBase */ + 0 /* Efficiency */ + ); + + // Initialize GIC Distributor Structure + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =3D + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT ( + 0, + FixedPcdGet32 (PcdGicDistributorBase), + 0, + 3 /* GicVersion */ + ); + + // Initialize GIC Redistributor Structure + EFI_ACPI_6_0_GICR_STRUCTURE Gicr =3D SBSAQEMU_MADT_GICR_INIT(); + + // Get CoreCount which was determined eariler after parsing device tree + NumCores =3D PcdGet32 (PcdCoreCount); + + // Calculate the new table size based on the number of cores + TableSize =3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADE= R) + + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIReclaimMemory, + EFI_SIZE_TO_PAGES (TableSize), + &PageAddress + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MADT table\n")); + return EFI_OUT_OF_RESOURCES; + } + + New =3D (UINT8 *)(UINTN) PageAddress; + ZeroMem (New, TableSize); + + // Add the ACPI Description table header + CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TA= BLE_HEADER)); + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length =3D TableSize; + New +=3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); + + // Add new GICC structures for the Cores + for (NumCores =3D 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) { + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; + + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); + GiccPtr =3D (EFI_ACPI_6_0_GIC_STRUCTURE *) New; + GiccPtr->AcpiProcessorUid =3D NumCores; + GiccPtr->MPIDR =3D NumCores; + New +=3D sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); + } + + // GIC Distributor Structure + CopyMem (New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE)); + New +=3D sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE); + + // GIC ReDistributor Structure + CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE)); + New +=3D sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); + + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + (EFI_ACPI_COMMON_HEADER *)PageAddress, + TableSize, + &TableHandle + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to install MADT table\n")); + } + + return Status; +} + EFI_STATUS EFIAPI InitializeSbsaQemuAcpiDxe ( @@ -68,8 +205,27 @@ InitializeSbsaQemuAcpiDxe ( IN EFI_SYSTEM_TABLE *SystemTable ) { + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + // Parse the device tree and get the number of CPUs CountCpusFromFdt (); =20 + // Check if ACPI Table Protocol has been installed + Status =3D gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID **)&AcpiTable + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to locate ACPI Table Protocol\n")); + return Status; + } + + Status =3D AddMadtTable (AcpiTable); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n")); + } + return EFI_SUCCESS; } --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64616): https://edk2.groups.io/g/devel/message/64616 Mute This Topic: https://groups.io/mt/76406685/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 12:57:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64617+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64617+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598362882; cv=none; d=zohomail.com; s=zohoarc; b=m5YwXrmlyB5IskkGvYUb8Qbu1ScMfJLEc4bI4xhEHNtzx64XAl7WFMBZICuALU1Ki/BCDv3oAYhK6oZuKGdnmVE1tI/N+ibyljRLzfj05rxJR3aP0Qdz8ltHNMyJNHKtR7RUgHulqNhv4vVujiE58ecYrcj4jKoBvSTLmYZGzLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598362882; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=2Xfa2ZkQ4Vn9IGS04ccSH8f2iJyAVK4/HGQ0NG9eEfQ=; b=OtMpMEFnBNknCefkPRvpOhntnskj9JyTV9hbOPzAaKsxjL2JBHSYwZTmquQ+ajb75YCrIEWh3X5MX1Y5/3qk+5Qrw8voHnqh11YDq+ciRFAcWtO8a2cz0qgDJQ9T/3RIUI1USXJMXUC/3iDZvNf+ipSWII3AkBmUyGyjrkeVFF0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64617+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598362882940300.1184562494592; Tue, 25 Aug 2020 06:41:22 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id uDe6YY1788612xWKV31DzesL; Tue, 25 Aug 2020 06:41:22 -0700 X-Received: from mail-pj1-f66.google.com (mail-pj1-f66.google.com [209.85.216.66]) by mx.groups.io with SMTP id smtpd.web10.13855.1598362880286344222 for ; Tue, 25 Aug 2020 06:41:20 -0700 X-Received: by mail-pj1-f66.google.com with SMTP id mt12so1265579pjb.4 for ; Tue, 25 Aug 2020 06:41:20 -0700 (PDT) X-Gm-Message-State: kEI0PlYE0wuLKK2sw8FaQ9xox1787277AA= X-Google-Smtp-Source: ABdhPJwnzHlj0m3AZERIFSyLetuRlWhmzI7ztXUZEM4mjBMwuQNYSde4x6+QdiEM+9W6fmfmirTQTA== X-Received: by 2002:a17:90b:509:: with SMTP id r9mr1734452pjz.228.1598362879818; Tue, 25 Aug 2020 06:41:19 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id z186sm3913768pfb.199.2020.08.25.06.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 06:41:19 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale Subject: [edk2-devel] [PATCH v3 edk2-platforms 6/8] SbsaQemu: AcpiDxe: Create SSDT table at runtime Date: Tue, 25 Aug 2020 19:09:56 +0530 Message-Id: <20200825133958.17372-7-tanmay.jagdale@linaro.org> In-Reply-To: <20200825133958.17372-1-tanmay.jagdale@linaro.org> References: <20200825133958.17372-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598362882; bh=B8cPOwL50AM8Is/Ry4eEWR9oCnIudaQhBGDEzlXMWMA=; h=Cc:Date:From:Reply-To:Subject:To; b=VhFfWUbSVoIz878QTbM9IsxQ45hYcX9wgsKZXag44dESbGOtXrND6hiyaD9YlgC/gZ+ kErmJ8/bqB60hEpxovYkdknc7wRhY57Zh9EZLZA9pcg5Fx8GrN1Evm5xTBIIQL6kQLiTf E+q8/Eja0NCIqNJFasWIiir3ITd+aZVtF+s= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Add support to create SSDT table at runtime. Since SSDT table is a data table, added a few helper macros to create the AML entries. - Also added a function to calculate the length of Packages. Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 29 ++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 144 ++++= ++++++++++++++++ 2 files changed, 173 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index 7a9a0061675f..00c7c68256fd 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -43,4 +43,33 @@ #define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00 #define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF =20 +#define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5 + +#define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' } + +#define SBSAQEMU_ACPI_CPU_DEV_LEN 0x1C +#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' } + +// Macro to convert Integer to Character +#define SBSAQEMU_ACPI_ITOA(Byte) (0x30 + (Byte > 9 ? (Byte + 1) : = Byte)) + +#define SBSAQEMU_ACPI_CPU_HID { = \ + AML_NAME_OP, AML_NAME_CHAR__, 'H', 'I', 'D', = \ + AML_STRING_PREFIX, 'A', 'C', 'P', 'I', '0', '0', '0', '7', = \ + AML_ZERO_OP = \ + } + +#define SBSAQEMU_ACPI_CPU_UID { = \ + AML_NAME_OP, AML_NAME_CHAR__, 'U', 'I', 'D', AML_BYTE_PREFIX, = \ + AML_ZERO_OP, AML_ZERO_OP = \ + } + +typedef struct { + UINT8 device_header[2]; + UINT8 length; + UINT8 dev_name[4]; + UINT8 hid[15]; + UINT8 uid[8]; +} SBSAQEMU_ACPI_CPU_DEVICE; + #endif diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 16cb4e904e6f..06e7a5310810 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -7,6 +7,7 @@ * **/ #include +#include #include #include #include @@ -198,6 +199,144 @@ AddMadtTable ( return Status; } =20 +/* + * Function to calculate the PkgLength field in ACPI tables + */ +STATIC +UINT32 +SetPkgLength ( + IN UINT8 *TablePtr, + IN UINT32 Length +) +{ + UINT8 ByteCount; + UINT8 *PkgLeadByte =3D TablePtr; + + if (Length < 64) { + *TablePtr =3D Length; + return 1; + } + + // Set the LSB of Length in PkgLeadByte and advance Length + *PkgLeadByte =3D Length & 0xF; + Length =3D Length >> 4; + + while (Length) { + TablePtr++; + *TablePtr =3D (Length & 0xFF); + Length =3D (Length >> 8); + } + + // Calculate the number of bytes the Length field uses + // and set the ByteCount field in PkgLeadByte. + ByteCount =3D (TablePtr - PkgLeadByte) & 0xF; + *PkgLeadByte |=3D (ByteCount << 6); + + return ByteCount + 1; +} + +/* + * A function that adds SSDT ACPI table. + */ +EFI_STATUS +AddSsdtTable ( + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable + ) +{ + EFI_STATUS Status; + UINTN TableHandle; + UINT32 TableSize; + EFI_PHYSICAL_ADDRESS PageAddress; + UINT8 *New; + UINT32 CpuId; + UINT32 Offset; + UINT8 ScopeOpName[] =3D SBSAQEMU_ACPI_SCOPE_NAME; + UINT32 NumCores =3D PcdGet32 (PcdCoreCount); + + EFI_ACPI_DESCRIPTION_HEADER Header =3D + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_DESCRIPTION_HEADER, + EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION); + + SBSAQEMU_ACPI_CPU_DEVICE CpuDevice =3D { + { AML_EXT_OP, AML_EXT_DEVICE_OP }, /* Device () */ + SBSAQEMU_ACPI_CPU_DEV_LEN, /* Length */ + SBSAQEMU_ACPI_CPU_DEV_NAME, /* Device Name "C000" */ + SBSAQEMU_ACPI_CPU_HID, /* Name (HID, "ACPI0007") */ + SBSAQEMU_ACPI_CPU_UID, /* Name (UID, 0) */ + }; + + // Calculate the new table size based on the number of cores + TableSize =3D sizeof (EFI_ACPI_DESCRIPTION_HEADER) + + SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH + sizeof (ScopeOpName) + + (sizeof (CpuDevice) * NumCores); + + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIReclaimMemory, + EFI_SIZE_TO_PAGES (TableSize), + &PageAddress + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for SSDT table\n")); + return EFI_OUT_OF_RESOURCES; + } + + New =3D (UINT8 *)(UINTN) PageAddress; + ZeroMem (New, TableSize); + + // Add the ACPI Description table header + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER)); + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length =3D TableSize; + New +=3D sizeof (EFI_ACPI_DESCRIPTION_HEADER); + + // Insert the top level ScopeOp + *New =3D AML_SCOPE_OP; + New++; + Offset =3D SetPkgLength (New, + (TableSize - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - 1)); + New +=3D Offset; + CopyMem (New, &ScopeOpName, sizeof (ScopeOpName)); + New +=3D sizeof (ScopeOpName); + + // Add new Device structures for the Cores + for (CpuId =3D 0; CpuId < NumCores; CpuId++) { + SBSAQEMU_ACPI_CPU_DEVICE *CpuDevicePtr; + UINT8 CpuIdByte1, CpuIdByte2, CpuIdByte3; + + CopyMem (New, &CpuDevice, sizeof (SBSAQEMU_ACPI_CPU_DEVICE)); + CpuDevicePtr =3D (SBSAQEMU_ACPI_CPU_DEVICE *) New; + + CpuIdByte1 =3D CpuId & 0xF; + CpuIdByte2 =3D (CpuId >> 4) & 0xF; + CpuIdByte3 =3D (CpuId >> 8) & 0xF; + + CpuDevicePtr->dev_name[1] =3D SBSAQEMU_ACPI_ITOA(CpuIdByte3); + CpuDevicePtr->dev_name[2] =3D SBSAQEMU_ACPI_ITOA(CpuIdByte2); + CpuDevicePtr->dev_name[3] =3D SBSAQEMU_ACPI_ITOA(CpuIdByte1); + + CpuDevicePtr->uid[6] =3D CpuIdByte1 | CpuIdByte2; + CpuDevicePtr->uid[7] =3D CpuIdByte3; + New +=3D sizeof (SBSAQEMU_ACPI_CPU_DEVICE); + } + + // Perform Checksum + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); + + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + (EFI_ACPI_COMMON_HEADER *)PageAddress, + TableSize, + &TableHandle + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to install SSDT table\n")); + } + + return Status; +} + EFI_STATUS EFIAPI InitializeSbsaQemuAcpiDxe ( @@ -227,5 +366,10 @@ InitializeSbsaQemuAcpiDxe ( DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n")); } =20 + Status =3D AddSsdtTable (AcpiTable); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n")); + } + return EFI_SUCCESS; } --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64617): https://edk2.groups.io/g/devel/message/64617 Mute This Topic: https://groups.io/mt/76406693/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 12:57:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64618+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64618+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598362892; cv=none; d=zohomail.com; s=zohoarc; b=ip2Jk0XHXxPQ/xKFPxjAu+mJ3wWGMJ/f2HiLk45vweM2+iqx/a2nkERzPVMFk8zvX+zi7JFgrI1hUOklVzgA2yeIFBh5sfLCyenpIP3pxSa0q6zqplCFYi5DhcucZ+R3R4kjzRGR2pRnJZ06xCxSj7DMPzgoy/nPCfrHYAl0UO0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598362892; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=x0cw6838iZO3iiYPiuKQtlw/zeoztOEWSC3HHFZlghw=; b=Ze74uATHHeMfKjH2yxwMSlwBaAJQ0jZFtJFZa30htlcznkfTUM5QwjhSj7bvSZp6Z7OgquGO9xTtJqV1aUguGFyZk5s5Y69bNdTQcPR3wqunXM0/9xfrLVki1AnHzpFj1NqqEowtdNLYwr6bIkJpFN030or5g7zgb2HN0EcdztE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64618+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598362892454332.40474025379353; Tue, 25 Aug 2020 06:41:32 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Yt9lYY1788612x0TLpARWfNS; Tue, 25 Aug 2020 06:41:32 -0700 X-Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by mx.groups.io with SMTP id smtpd.web10.13860.1598362890327518412 for ; Tue, 25 Aug 2020 06:41:30 -0700 X-Received: by mail-pf1-f195.google.com with SMTP id u20so7394144pfn.0 for ; Tue, 25 Aug 2020 06:41:30 -0700 (PDT) X-Gm-Message-State: IdZeJC0GQAYRNiPEZbmwVwRyx1787277AA= X-Google-Smtp-Source: ABdhPJzmf33l6GW5JT46BcYijGPKl1dQhKBYrHmQMAXBJiMKlJ+m/sjwLQviYXIR9rA2eiWEc39LQA== X-Received: by 2002:a17:902:bb8d:: with SMTP id m13mr7837693pls.11.1598362889804; Tue, 25 Aug 2020 06:41:29 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id z186sm3913768pfb.199.2020.08.25.06.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 06:41:29 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale Subject: [edk2-devel] [PATCH v3 edk2-platforms 7/8] SbsaQemu: AcpiDxe: Create PPTT table at runtime Date: Tue, 25 Aug 2020 19:09:57 +0530 Message-Id: <20200825133958.17372-8-tanmay.jagdale@linaro.org> In-Reply-To: <20200825133958.17372-1-tanmay.jagdale@linaro.org> References: <20200825133958.17372-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598362892; bh=5Dk+oF/NEZNuGgLd0lszGEn9itQQ4jSTkQfGPxx5CRQ=; h=Cc:Date:From:Reply-To:Subject:To; b=QmJLpxtEFQ6C1Qr2KYJ/cfgPdtX8yTLA/VP/okdOA/bCV2VQIvAmMkU8gA4djBEHQYT sqE9H9vdu5B3H+RsOqxGECFoJRX/Gu36EX2xB7EjlfPdcr3JTJC4kjXgyxPvqlheklllQ n0GJxgPg+AR8eAhe3nYgmUBOJaEBMfbFfZw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add support to create Processor Properties Topology Table at runtime. The cache topology of each CPU is as follows: CPU N ------------------------ | -------- -------- | | | L1-I | | L1-D | | | | 32KB | | 32KB | | | -------- -------- | | ------------------ | | | L2 512KB | | | ------------------ | ------------------------ Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 124 ++++= ++++++++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 110 ++++= +++++++++++++ 2 files changed, 234 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index 00c7c68256fd..de6b51ccd034 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -72,4 +72,128 @@ typedef struct { UINT8 uid[8]; } SBSAQEMU_ACPI_CPU_DEVICE; =20 +#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB +#define SBSAQEMU_L1_D_CACHE_SETS 256 +#define SBSAQEMU_L1_D_CACHE_ASSC 2 + +#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB +#define SBSAQEMU_L1_I_CACHE_SETS 256 +#define SBSAQEMU_L1_I_CACHE_ASSC 2 + +#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB +#define SBSAQEMU_L2_CACHE_SETS 1024 +#define SBSAQEMU_L2_CACHE_ASSC 8 + +#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCT= URE_PROCESSOR)) +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STR= UCTURE_CACHE)) +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STR= UCTURE_CACHE)) + +#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L2_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ = \ + }, = \ + 0, /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 0, /* NumberOfPrivateResources = */ \ + } + +#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, = \ + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32)= )), \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */= \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ = \ + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ = \ + }, = \ + 0, /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResources = */ \ + } + #endif diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 06e7a5310810..89c367350e70 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -337,6 +337,111 @@ AddSsdtTable ( return Status; } =20 +/* + * A function that adds the SSDT ACPI table. + */ +EFI_STATUS +AddPpttTable ( + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable + ) +{ + EFI_STATUS Status; + UINTN TableHandle; + UINT32 TableSize; + EFI_PHYSICAL_ADDRESS PageAddress; + UINT8 *New; + UINT32 CpuId; + UINT32 NumCores =3D PcdGet32 (PcdCoreCount); + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache =3D SBSAQEMU_ACPI_PPTT_L1_D_C= ACHE_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache =3D SBSAQEMU_ACPI_PPTT_L1_I_C= ACHE_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache =3D SBSAQEMU_ACPI_PPTT_L2_CACH= E_STRUCT; + + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster =3D SBSAQEMU_ACPI_PPTT_CLU= STER_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core =3D SBSAQEMU_ACPI_PPTT_CORE_S= TRUCT; + + EFI_ACPI_DESCRIPTION_HEADER Header =3D + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_DESCRIPTION_HEADER, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION); + + TableSize =3D sizeof (EFI_ACPI_DESCRIPTION_HEADER) + + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) + + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) + + (sizeof (UINT32) * 2 * NumCores); + + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIReclaimMemory, + EFI_SIZE_TO_PAGES (TableSize), + &PageAddress + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for PPTT table\n")); + return EFI_OUT_OF_RESOURCES; + } + + New =3D (UINT8 *)(UINTN) PageAddress; + ZeroMem (New, TableSize); + + // Add the ACPI Description table header + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER)); + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length =3D TableSize; + New +=3D sizeof (EFI_ACPI_DESCRIPTION_HEADER); + + // Add the Cluster PPTT structure + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); + + // Add L1 D Cache structure + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D L2_CACH= E_INDEX; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + // Add L1 I Cache structure + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D L2_CACH= E_INDEX; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + // Add L2 Cache structure + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D 0; /* L= 2 is LLC */ + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + for (CpuId =3D 0; CpuId < NumCores; CpuId++) { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr; + UINT32 *PrivateResourcePtr; + + CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); + CorePtr =3D (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New; + CorePtr->Parent =3D CLUSTER_INDEX; + CorePtr->AcpiProcessorId =3D CpuId; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); + + PrivateResourcePtr =3D (UINT32 *) New; + PrivateResourcePtr[0] =3D L1_D_CACHE_INDEX; + PrivateResourcePtr[1] =3D L1_I_CACHE_INDEX; + New +=3D (2 * sizeof (UINT32)); + } + + // Perform Checksum + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); + + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + (EFI_ACPI_COMMON_HEADER *)PageAddress, + TableSize, + &TableHandle + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to install PPTT table\n")); + } + + return Status; +} + EFI_STATUS EFIAPI InitializeSbsaQemuAcpiDxe ( @@ -371,5 +476,10 @@ InitializeSbsaQemuAcpiDxe ( DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n")); } =20 + Status =3D AddPpttTable (AcpiTable); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to add PPTT table\n")); + } + return EFI_SUCCESS; } --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64618): https://edk2.groups.io/g/devel/message/64618 Mute This Topic: https://groups.io/mt/76406696/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 12:57:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64619+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64619+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598362902; cv=none; d=zohomail.com; s=zohoarc; b=LGCQi0zWNlfPJ7tf0oCpr6e0fUMaYgaX60DcUymbRT6EWg5/SWCHXQquBMspTOUFO/gQg8eeKHJ8P1UTFpe4mn1xXNbi+B3BtuMcwdaWfMbMJ/KqCuSmFO9CYLQE4A+UwdMgKprvqDQ49q9kQHWoQPSo0jnYGk/v4ULf1IqLJrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598362902; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4FgQOdCDmocZAjMoMMUyCVfgckyvrgiIfvkXQ8ym86Q=; b=Z9p61alQsvB+8BlAZyT0VQW4D4faLfJUnCk8Q8p3mRVE313eF9Yh8R756YzyIzuOj46RF9Cg6zN0nFDgiOnFb59n8mYQ+CXUv6nzUl/6kiT0Uq5bY5CkhRI4NJZXgt4a430n49GYAcNYX8lYOVMS12kg8P6bLyrPDUS3bIk9BV0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64619+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598362902211413.0943270904396; Tue, 25 Aug 2020 06:41:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id fTj1YY1788612x3ncAX6i6ZU; Tue, 25 Aug 2020 06:41:41 -0700 X-Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by mx.groups.io with SMTP id smtpd.web10.13863.1598362901416506650 for ; Tue, 25 Aug 2020 06:41:41 -0700 X-Received: by mail-pg1-f193.google.com with SMTP id v15so6847188pgh.6 for ; Tue, 25 Aug 2020 06:41:41 -0700 (PDT) X-Gm-Message-State: xLdBEePavrbfBGnNmyFOPMzLx1787277AA= X-Google-Smtp-Source: ABdhPJz3u/klgrDYM0BMAyUsaZnn8NGFTX1CMDMsO/2rWDYyeYYR1o3Uyx6iSvdonxjchbXqgwDSBw== X-Received: by 2002:a17:902:6841:: with SMTP id f1mr7217828pln.228.1598362900996; Tue, 25 Aug 2020 06:41:40 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id z186sm3913768pfb.199.2020.08.25.06.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 06:41:40 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, devel@edk2.groups.io Cc: shashi.mallela@linaro.org, Tanmay Jagdale Subject: [edk2-devel] [PATCH v3 edk2-platforms 8/8] SbsaQemu: AcpiTables: Add DBG2 Table Date: Tue, 25 Aug 2020 19:09:58 +0530 Message-Id: <20200825133958.17372-9-tanmay.jagdale@linaro.org> In-Reply-To: <20200825133958.17372-1-tanmay.jagdale@linaro.org> References: <20200825133958.17372-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598362901; bh=E8xFpXvOmZ2g4FegJMig7M73WqUj3cununtIaC3t3Y4=; h=Cc:Date:From:Reply-To:Subject:To; b=u+FKDyTvhbH1lryCGOWELilc6HXDdQHpWkYEQ/lzXC5gL2x4JU6XmtFEldt9e/5qGdn ypqCvjUyGVkly5O6WjbVMv1B2FYokt5wFgY3zpGFwCxSIbo/oCcySqiJ107Zuch4BkMCO PyeBanRJ4inSmLpgqCao10SQgxHd/7ZS4kQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 67 ++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu= /SbsaQemu/AcpiTables/AcpiTables.inf index 57d717fefafc..7216a53304df 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -16,6 +16,7 @@ [Defines] VERSION_STRING =3D 1.0 =20 [Sources] + Dbg2.aslc Dsdt.asl Fadt.aslc Gtdt.aslc diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Dbg2.aslc new file mode 100644 index 000000000000..c9e3ca77ab53 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc @@ -0,0 +1,67 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include + +#pragma pack(1) + +#define SBSAQEMU_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '0', = 0x00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 =3D { + { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegist= ers */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + ARM_GAS32 (SBSAQEMU_UART0_BASE), /* BaseAddressRegister */ + 0x1000, /* AddressSize */ + SBSAQEMU_UART_STR, /* NameSpaceString */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Dbg2; --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64619): https://edk2.groups.io/g/devel/message/64619 Mute This Topic: https://groups.io/mt/76406701/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-