From nobody Wed Feb 11 00:56:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64601+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64601+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1598340271; cv=none; d=zohomail.com; s=zohoarc; b=TF+Vzgnkx5KABkAL2+XAGuUiAFsqvrpTZUzo/LV1Jzgz3wtBpA48Z4TxrGi4Ox3yiul74H51sLjFoFCdEU25rED/rojKSfCwY370w4OEU4nRS8eGQeVu/b4uWcEV8nSV0OnquhvDKNQCgmjhcm8/WZ9jLcukD7hLrl/HqLQoIbQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598340271; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FPHXyO+1cltU9gJnuVjs+kfL7uFDXab85oEXbw4+lB4=; b=UPQ0ZkfRW0+ROFCQsRqEO2JCxbVW6eIVUw1ldWeIEbrlCIZoK5UYsp8zSHTfn1iLJt9J2TX510OMauZ3sQ9ZJmJXm5L6tL5z3+zrk83dXZoIIomOK5WXyM94mDN+qnkgeclc42KsnHcSGrI+KyELmCrnEuP9mG6COdoL90sB3EI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64601+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1598340271640858.7759392537832; Tue, 25 Aug 2020 00:24:31 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id qEnEYY1788612xeqzSbSrHtT; Tue, 25 Aug 2020 00:24:31 -0700 X-Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by mx.groups.io with SMTP id smtpd.web10.9002.1598340270716523489 for ; Tue, 25 Aug 2020 00:24:30 -0700 X-Received: by mail-pg1-f193.google.com with SMTP id d19so6194679pgl.10 for ; Tue, 25 Aug 2020 00:24:30 -0700 (PDT) X-Gm-Message-State: GjWjMt3O2nVyWWDNcYfQpJPxx1787277AA= X-Google-Smtp-Source: ABdhPJxouRe8fB9dYK8jxeHE9WQjrFckF9/wpLjWtJIQXFYdD/B9/rRPSVdQ1quNNIQP9DD+jK76Og== X-Received: by 2002:a17:902:d341:: with SMTP id l1mr5534176plk.36.1598340270231; Tue, 25 Aug 2020 00:24:30 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id d5sm1722417pjw.18.2020.08.25.00.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 00:24:29 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale Subject: [edk2-devel] [PATCH v2 edk2-platforms 7/8] SbsaQemu: AcpiDxe: Create PPTT table at runtime Date: Tue, 25 Aug 2020 12:53:21 +0530 Message-Id: <20200825072322.10848-8-tanmay.jagdale@linaro.org> In-Reply-To: <20200825072322.10848-1-tanmay.jagdale@linaro.org> References: <20200825072322.10848-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1598340271; bh=lXIuCqL7uaqcuc3vloCamkWoRNVV9w3qiVi9W3xCN0I=; h=Cc:Date:From:Reply-To:Subject:To; b=uU7T3hDERRg63gJZbm5NHmaQRaf652iUqf8YgUWKkMioGp0hNk62FIVpXMsE+i7tEH7 TRjaPgd6g7xrhFeOnzmIlh6Butu0xT85IbPKF0dLbGLBZ35midwulgX98SPFKNKJn4jAi nQRtOTlTTlZJvU90BMQYb3HvBl6rMxwjS6o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add support to create Processor Properties Topology Table at runtime. The cache topology of each CPU is as follows: CPU N ------------------------ | -------- -------- | | | L1-I | | L1-D | | | | 32KB | | 32KB | | | -------- -------- | | ------------------ | | | L2 512KB | | | ------------------ | ------------------------ Signed-off-by: Tanmay Jagdale --- Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 124 ++++= ++++++++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 110 ++++= +++++++++++++ 2 files changed, 234 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index 00c7c68256fd..de6b51ccd034 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -72,4 +72,128 @@ typedef struct { UINT8 uid[8]; } SBSAQEMU_ACPI_CPU_DEVICE; =20 +#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB +#define SBSAQEMU_L1_D_CACHE_SETS 256 +#define SBSAQEMU_L1_D_CACHE_ASSC 2 + +#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB +#define SBSAQEMU_L1_I_CACHE_SETS 256 +#define SBSAQEMU_L1_I_CACHE_ASSC 2 + +#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB +#define SBSAQEMU_L2_CACHE_SETS 1024 +#define SBSAQEMU_L2_CACHE_ASSC 8 + +#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCT= URE_PROCESSOR)) +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STR= UCTURE_CACHE)) +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STR= UCTURE_CACHE)) + +#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L2_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ = \ + }, = \ + 0, /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 0, /* NumberOfPrivateResources = */ \ + } + +#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, = \ + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32)= )), \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */= \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ = \ + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ = \ + }, = \ + 0, /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResources = */ \ + } + #endif diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index ebffa1db4734..e27489cd7123 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -338,6 +338,111 @@ AddSsdtTable ( return Status; } =20 +/* + * A function that adds the SSDT ACPI table. + */ +EFI_STATUS +AddPpttTable ( + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable + ) +{ + EFI_STATUS Status; + UINTN TableHandle; + UINT32 TableSize; + EFI_PHYSICAL_ADDRESS PageAddress; + UINT8 *New; + UINT32 CpuId; + UINT32 NumCores =3D PcdGet32 (PcdCoreCount); + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache =3D SBSAQEMU_ACPI_PPTT_L1_D_C= ACHE_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache =3D SBSAQEMU_ACPI_PPTT_L1_I_C= ACHE_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache =3D SBSAQEMU_ACPI_PPTT_L2_CACH= E_STRUCT; + + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster =3D SBSAQEMU_ACPI_PPTT_CLU= STER_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core =3D SBSAQEMU_ACPI_PPTT_CORE_S= TRUCT; + + EFI_ACPI_DESCRIPTION_HEADER Header =3D + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_DESCRIPTION_HEADER, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION); + + TableSize =3D sizeof (EFI_ACPI_DESCRIPTION_HEADER) + + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) + + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) + + (sizeof (UINT32) * 2 * NumCores); + + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIReclaimMemory, + EFI_SIZE_TO_PAGES (TableSize), + &PageAddress + ); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Failed to allocate pages for PPTT table\n")); + return EFI_OUT_OF_RESOURCES; + } + + New =3D (UINT8 *)(UINTN) PageAddress; + ZeroMem (New, TableSize); + + // Add the ACPI Description table header + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER)); + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length =3D TableSize; + New +=3D sizeof (EFI_ACPI_DESCRIPTION_HEADER); + + // Add the Cluster PPTT structure + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); + + // Add L1 D Cache structure + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D L2_CACH= E_INDEX; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + // Add L1 I Cache structure + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D L2_CACH= E_INDEX; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + // Add L2 Cache structure + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D 0; /* L= 2 is LLC */ + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + for (CpuId =3D 0; CpuId < NumCores; CpuId++) { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr; + UINT32 *PrivateResourcePtr; + + CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); + CorePtr =3D (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New; + CorePtr->Parent =3D CLUSTER_INDEX; + CorePtr->AcpiProcessorId =3D CpuId; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); + + PrivateResourcePtr =3D (UINT32 *) New; + PrivateResourcePtr[0] =3D L1_D_CACHE_INDEX; + PrivateResourcePtr[1] =3D L1_I_CACHE_INDEX; + New +=3D (2 * sizeof (UINT32)); + } + + // Perform Checksum + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); + + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + (EFI_ACPI_COMMON_HEADER *)PageAddress, + TableSize, + &TableHandle + ); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Failed to install PPTT table\n")); + } + + return Status; +} + EFI_STATUS EFIAPI InitializeSbsaQemuAcpiDxe ( @@ -372,5 +477,10 @@ InitializeSbsaQemuAcpiDxe ( DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n")); } =20 + Status =3D AddPpttTable (AcpiTable); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Failed to add PPTT table\n")); + } + return EFI_SUCCESS; } --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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