From nobody Sat Apr 27 16:00:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64435+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64435+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1597847426; cv=none; d=zohomail.com; s=zohoarc; b=dHw8A5e4q56ppK0zhYQwaBLo9SR/qyBNjEmQEY0PEIsUXTYr50czLEi3Bo0WYDh7gb72C8MswtsTi3oVPj+j/S90LO5oPY2HMhJU0dXAClG+HNH1evBI/2/NWnmKOBMXpSGeM5CVsJMu5URlOlbWORDZ6N4iVVFszP2wyoOwNDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1597847426; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=IBM/nQZXRwuwZa39RVHgqpEG5+hbc9ZgmewdIQbwly4=; b=dNmm647SQ4V51orrt03QjRSty/eqDvQcCSIga2BaDFQY1lnVsySdgkuoAP254hjQR/hHIPgpm1yn3QglM9oGi8gVGWQ34cy2Ucrm8ZAiALAAn64EmFBTICrvSRC+mOY0jS7o5/VLYQAKLiyui0Qbkyq+9BY3XOnRqshtsCvQ7TY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64435+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1597847426301695.449066433238; Wed, 19 Aug 2020 07:30:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id DDxeYY1788612x1Nnafs67ho; Wed, 19 Aug 2020 07:30:25 -0700 X-Received: from mail-pj1-f65.google.com (mail-pj1-f65.google.com [209.85.216.65]) by mx.groups.io with SMTP id smtpd.web12.88606.1597847425360683984 for ; Wed, 19 Aug 2020 07:30:25 -0700 X-Received: by mail-pj1-f65.google.com with SMTP id e4so1205734pjd.0 for ; Wed, 19 Aug 2020 07:30:25 -0700 (PDT) X-Gm-Message-State: 6o4tM39SmFIWvmGtHvNkiVJ9x1787277AA= X-Google-Smtp-Source: ABdhPJxqzSvz9GLhJZw39Y/vUAsfFlYM9MH8WRcv6d74zVVKci/Qljq2ETzC9rcJvfM6B90HO7nKyA== X-Received: by 2002:a17:90a:307:: with SMTP id 7mr4474574pje.37.1597847424563; Wed, 19 Aug 2020 07:30:24 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id y10sm3320752pjv.55.2020.08.19.07.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 07:30:23 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale , Graeme Gregory , Jonathan Cameron Subject: [edk2-devel] [PATCH edk2-platforms 1/7] SbsaQemu: Initial support for static ACPI tables Date: Wed, 19 Aug 2020 19:59:59 +0530 Message-Id: <20200819143005.13999-2-tanmay.jagdale@linaro.org> In-Reply-To: <20200819143005.13999-1-tanmay.jagdale@linaro.org> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1597847425; bh=HiQu+RWpnOlJtcyy5VGQDowQGzP3tLNbdqJFWoS24cE=; h=Cc:Date:From:Reply-To:Subject:To; b=Arb2CZRt/c6Sbi5hFGL0hFp1oAngQLd7CpDjRxDWmFRXwfwJNpycHCfDNu0k3JT6Rn5 R8gWQZHfBqZfcodlepfEzuW8TmqrQp2vd/GHdQAwCgBM2KesRlJWGa92r2f/K9G2Byu90 2agOMDCEOHDIf1py2ygRnL+WY4yNtRm2A5k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Add the following ACPI tables for SbsaQemu platform DSDT, FADT, GTDT, SPCR - Created an Include directory to hold common header files. - Also included the Acpiview shell utility. Co-authored-by: Graeme Gregory Co-authored-by: Jonathan Cameron Signed-off-by: Tanmay Jagdale Reviewed-by: Leif Lindholm --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 + Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 8 ++ Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 35 +++++ .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 45 ++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 133 ++++++++++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 80 +++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 67 +++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 53 +++++++ .../Include/IndustryStandard/SbsaQemuAcpi.h | 31 ++++ Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 +- 10 files changed, 460 insertions(+), 2 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc create mode 100644 Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemu= Acpi.h diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 4db3ab465163..4739443cae93 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -516,6 +516,7 @@ [Components.common] ShellPkg/Application/Shell/Shell.inf { ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf @@ -675,3 +676,8 @@ [Components.common] MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # ACPI Support +!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/S= bsaQemu.fdf index be7c78acebfd..4526eaaa02c5 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf @@ -227,6 +227,14 @@ [FV.FvMain] INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf =20 + # + # ACPI support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF RuleOverride =3D ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTabl= es.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf + # # PCI support # diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acp= i.dsc.inc new file mode 100644 index 000000000000..c4a8d7a27b78 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc @@ -0,0 +1,35 @@ +# +# Copyright (c) 2020, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LINARO" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x554D4551415342= 53 #SBSAQEMU + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20200810 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c #LNRO + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### + +[Components.common] + # + # ACPI support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu= /SbsaQemu/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000000..ee524895524e --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -0,0 +1,45 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2020, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SbsaAcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dsdt.asl + Fadt.aslc + Gtdt.aslc + Spcr.aslc + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQ= emu/AcpiTables/Dsdt.asl new file mode 100644 index 000000000000..85339d4559d3 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl @@ -0,0 +1,133 @@ +/** @file +* Differentiated System Description Table Fields (DSDT). +* +* Copyright (c) 2020, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU", + FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { + Scope (_SB) { + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x60000000, 0x00001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 } + }) + } + + // AHCI Host Controller + Device (AHC0) { + Name (_HID, "LNRO001E") + Name (_CLS, Package (3) { + 0x01, + 0x06, + 0x01, + }) + Name (_CCA, 1) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x60100000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 } + }) + } + + // USB EHCI Host Controller + Device (USB0) { + Name (_HID, "LNRO0D20") + Name (_CID, "PNP0D20") + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x60110000, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive)= { 43 } + }) + Return (RBUF) + } + + // Root Hub + Device (RHUB) { + Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as= per ACPI 5.0 spec + + // Ports connected to Root Hub + Device (HUB1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0x00, // Port is NOT connectable + 0xFF, // Don't care + 0x00000000, // Reserved 0 must be zero + 0x00000000 // Reserved 1 must be zero + }) + + Device (PRT1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer(0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT1 + Device (PRT2) { + Name (_ADR, 0x00000002) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer(0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT2 + + Device (PRT3) { + Name (_ADR, 0x00000003) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer (0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT3 + + Device (PRT4) { + Name (_ADR, 0x00000004) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer (0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT4 + } // USB0_RHUB_HUB1 + } // USB0_RHUB + } // USB0 + + } // Scope (_SB) +} diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Fadt.aslc new file mode 100644 index 000000000000..894b848db8bb --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc @@ -0,0 +1,80 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmP= rofile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_0_HW_REDUCED_ACPI | + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // GAS ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchF= lags + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, + // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // GAS XPm1aEvtBlk + NULL_GAS, // GAS XPm1bEvtBlk + NULL_GAS, // GAS XPm1aCntBlk + NULL_GAS, // GAS XPm1bCntBlk + NULL_GAS, // GAS XPm2CntBlk + NULL_GAS, // GAS XPmTmrBlk + NULL_GAS, // GAS XGpe0Blk + NULL_GAS, // GAS XGpe1Blk + NULL_GAS, // GAS SleepControl= Reg + NULL_GAS, // GAS SleepStatusR= eg + 0 // UINT64 HypervisorVe= ndorId +}; + +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Fadt; diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Gtdt.aslc new file mode 100644 index 000000000000..52496acc449b --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc @@ -0,0 +1,67 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyrignt (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY= _MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERR= UPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/no= n-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_G= LOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GT= DT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LE= VEL_TRIGGERED) + + #pragma pack (1) + + typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + } GENERIC_TIMER_DESCRIPTION_TABLE; + + #pragma pack () + + GENERIC_TIMER_DESCRIPTION_TABLE Gtdt =3D { + { + SBSAQEMU_ACPI_HEADER( + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAdd= ress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1Ti= merGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1Ti= merFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL= 1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL= 1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL= 2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL= 2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBase= PhysicalAddress + 0, // UINT32 PlatformTim= erCount + 0 + }, + }; + +// Reference the table being generated to prevent the optimizer from remov= ing the +// data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Spcr.aslc new file mode 100644 index 000000000000..7b8ab7b6942f --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc @@ -0,0 +1,53 @@ +/** @file +* Serial Port Console Redirection Table (SPCR). +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +#pragma pack(push, 1) + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + 2), /* New MS definition for PL011 support */ + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_= UART, + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE= }, + { + EFI_ACPI_6_0_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_0_DWORD, + SBSAQEMU_UART0_BASE + }, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + 0, /* Irq */ + 33, /* GlobalSystemInterrupt */ + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + 0, /* Flow Control */ + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + EFI_ACPI_RESERVED_BYTE, /* Language */ + 0xFFFF, /* PciDeviceId */ + 0xFFFF, /* PciVendorId */ + 0x00, /* PciBusNumber */ + 0x00, /* PciDeviceNumber */ + 0x00, /* PciFunctionNumber */ + 0, /* PciFlags */ + 0, /* PciSegment */ + EFI_ACPI_RESERVED_DWORD +}; + +#pragma pack(pop) + +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Spcr; diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h new file mode 100644 index 000000000000..eac195b0585c --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -0,0 +1,31 @@ +/** @file +* +* Copyright (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SBSAQEMUACPI_H +#define SBSAQEMUACPI_H + +// A macro to initialise the common header part of EFI ACPI tables as defi= ned by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define SBSAQEMU_ACPI_HEADER(Signature, Type, Revision) { = \ + Signature, /* UINT32 Signature */ = \ + sizeof (Type), /* UINT32 Length */ = \ + Revision, /* UINT8 Revision */ = \ + 0, /* UINT8 Checksum */ = \ + { 'L', 'I', 'N', 'A', 'R', 'O' }, /* UINT8 OemId[6] */ = \ + FixedPcdGet64 (PcdAcpiDefaultOemTableId), /* UINT64 OemTableId */ = \ + FixedPcdGet32 (PcdAcpiDefaultOemRevision), /* UINT32 OemRevision */= \ + FixedPcdGet32 (PcdAcpiDefaultCreatorId), /* UINT32 CreatorId */ = \ + FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevisio= n */ \ + } + +#define SBSAQEMU_UART0_BASE 0x60000000 + +#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000 +#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00 +#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF + +#endif diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/Sbs= aQemu.dec index cd879f4dbd96..71ba55a082e2 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -21,8 +21,8 @@ [Defines] # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION # ##########################################################################= ###### -#[Includes.common] -# Include # Root include for the package +[Includes] + Include # Root include for the package =20 [Guids.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid =3D { 0xaab3bea9, 0xa8e8, 0x4e7= 6, { 0xb5, 0x3a, 0x35, 0x22, 0x11, 0xce, 0xf7, 0xf7 } } --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64435): https://edk2.groups.io/g/devel/message/64435 Mute This Topic: https://groups.io/mt/76287438/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 16:00:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64436+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64436+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1597847442; cv=none; d=zohomail.com; s=zohoarc; b=ZSxgBztZ9sQ1k73tsM3Tece4zqnLWCjrGHzX0q6BCE/COQmpltfNe810qxPteeqzmlZNQlLSXNHzaGSvdGmJ8vwYScg1MnXURWqz8tNOSHlNQq/lQ9p3tfWGW6Hvz0BHwi4pY/JSMmu8fouD4ycq+WG4syc399J9fy9AAS6DR9Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1597847442; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=oPw2kmRoUXxMe4feuJDm2SBcn6kh7H2hMFUw4djf0SM=; b=I/BME8UwfgYEIxKh/xKu1wiyCJpx2bTihfVElNPFVR9tNyAWyCztCBLZ37Tl7/bGnMPdTJYgTBEhNTdGesUeODB0oke/BqhFkJgz1NndebxtUszMrou14GjIt00gCsQnPy6LNQyKE4KniP5raqahYiAGqUeYoqtKVDvMj/xJllw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64436+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1597847442873525.5153630786596; Wed, 19 Aug 2020 07:30:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3fDuYY1788612xKwRzQb1FmK; Wed, 19 Aug 2020 07:30:42 -0700 X-Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by mx.groups.io with SMTP id smtpd.web10.89393.1597847441836881480 for ; Wed, 19 Aug 2020 07:30:41 -0700 X-Received: by mail-pl1-f195.google.com with SMTP id h2so487923plr.0 for ; Wed, 19 Aug 2020 07:30:41 -0700 (PDT) X-Gm-Message-State: 1sxDitIm9wxDKPzaDLZbUWK6x1787277AA= X-Google-Smtp-Source: ABdhPJzCt9MvLKTutXX7hB6G1KtM7rIpNvD0ZbWnNgQLuTEY9nKxoowUTycDLvfAywaEz2xEWLt8HA== X-Received: by 2002:a17:90b:252:: with SMTP id fz18mr4290701pjb.48.1597847441331; Wed, 19 Aug 2020 07:30:41 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id y10sm3320752pjv.55.2020.08.19.07.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 07:30:40 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale , Graeme Gregory Subject: [edk2-devel] [PATCH edk2-platforms 2/7] SbsaQemu: AcpiTables: Add PCI support and MCFG Table Date: Wed, 19 Aug 2020 20:00:00 +0530 Message-Id: <20200819143005.13999-3-tanmay.jagdale@linaro.org> In-Reply-To: <20200819143005.13999-1-tanmay.jagdale@linaro.org> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1597847442; bh=63hAQlI8gQV0eq9zDG4i33odZVyH5GRclq9NM+Hmfow=; h=Cc:Date:From:Reply-To:Subject:To; b=IRgO+YtGg+3ZMLlXxWUR+BvWuwQVLslCzwep375hsf4OEgfCe4cCTf8eiZKxH50jP06 hoN0qcz3mqMtDIXCU8euX1SDWK6/BA3luxCz4xCTUfKC2tX1MjuQW0v27/ZmIM3nYPWTk IR/BNq6BZJcpnPfxonBZc997AId3gAiStRc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add PCI related entries to DSDT table along with the routing entries. Also add the MCFG table. Co-authored-by: Graeme Gregory Signed-off-by: Tanmay Jagdale --- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 316 ++++++++++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 +++ 3 files changed, 360 insertions(+) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu= /SbsaQemu/AcpiTables/AcpiTables.inf index ee524895524e..0b5017ce81c5 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -20,6 +20,7 @@ [Sources] Fadt.aslc Gtdt.aslc Spcr.aslc + Mcfg.aslc =20 [Packages] ArmPlatformPkg/ArmPlatformPkg.dec diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQ= emu/AcpiTables/Dsdt.asl index 85339d4559d3..2d3d4a2ddedc 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl @@ -8,6 +8,23 @@ =20 #include =20 +#define LINK_DEVICE(Uid, LinkName, Irq) = \ + Device (LinkName) { = \ + Name (_HID, EISAID("PNP0C0F")) = \ + Name (_UID, Uid) = \ + Name (_PRS, ResourceTemplate() { = \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive)= { Irq } \ + }) = \ + Method (_CRS, 0) { Return (_PRS) } = \ + Method (_SRS, 1) { } = \ + Method (_DIS) { } = \ + } + +#define PRT_ENTRY(Address, Pin, Link) = \ + Package (4) { = \ + Address, Pin, Link, Zero = \ + } + DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU", FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { Scope (_SB) { @@ -129,5 +146,304 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO"= , "SBSAQEMU", } // USB0_RHUB } // USB0 =20 + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_ADR, Zero) + Name (_UID, "PCI0") + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) + + Method (_CBA, 0, NotSerialized) { + return (0xf0000000) + } + + LINK_DEVICE(0, GSI0, 0x23) + LINK_DEVICE(1, GSI1, 0x24) + LINK_DEVICE(2, GSI2, 0x25) + LINK_DEVICE(3, GSI3, 0x26) + + Name (_PRT, Package () // _PRT: PCI Routing Table + { + PRT_ENTRY(0x0000FFFF, 0, GSI0), + PRT_ENTRY(0x0000FFFF, 0, GSI1), + PRT_ENTRY(0x0000FFFF, 0, GSI2), + PRT_ENTRY(0x0000FFFF, 0, GSI3), + + PRT_ENTRY(0x0001FFFF, 0, GSI1), + PRT_ENTRY(0x0001FFFF, 1, GSI2), + PRT_ENTRY(0x0001FFFF, 2, GSI3), + PRT_ENTRY(0x0001FFFF, 3, GSI0), + + PRT_ENTRY(0x0002FFFF, 0, GSI2), + PRT_ENTRY(0x0002FFFF, 1, GSI3), + PRT_ENTRY(0x0002FFFF, 2, GSI0), + PRT_ENTRY(0x0002FFFF, 3, GSI1), + + PRT_ENTRY(0x0003FFFF, 0, GSI3), + PRT_ENTRY(0x0003FFFF, 1, GSI0), + PRT_ENTRY(0x0003FFFF, 2, GSI1), + PRT_ENTRY(0x0003FFFF, 3, GSI2), + + PRT_ENTRY(0x0004FFFF, 0, GSI0), + PRT_ENTRY(0x0004FFFF, 1, GSI1), + PRT_ENTRY(0x0004FFFF, 2, GSI2), + PRT_ENTRY(0x0004FFFF, 3, GSI3), + + PRT_ENTRY(0x0005FFFF, 0, GSI1), + PRT_ENTRY(0x0005FFFF, 1, GSI2), + PRT_ENTRY(0x0005FFFF, 2, GSI3), + PRT_ENTRY(0x0005FFFF, 3, GSI0), + + PRT_ENTRY(0x0006FFFF, 0, GSI2), + PRT_ENTRY(0x0006FFFF, 1, GSI3), + PRT_ENTRY(0x0006FFFF, 2, GSI0), + PRT_ENTRY(0x0006FFFF, 3, GSI1), + + PRT_ENTRY(0x0007FFFF, 0, GSI3), + PRT_ENTRY(0x0007FFFF, 1, GSI0), + PRT_ENTRY(0x0007FFFF, 2, GSI1), + PRT_ENTRY(0x0007FFFF, 3, GSI2), + + PRT_ENTRY(0x0008FFFF, 0, GSI0), + PRT_ENTRY(0x0008FFFF, 1, GSI1), + PRT_ENTRY(0x0008FFFF, 2, GSI2), + PRT_ENTRY(0x0008FFFF, 3, GSI3), + + PRT_ENTRY(0x0009FFFF, 0, GSI1), + PRT_ENTRY(0x0009FFFF, 1, GSI2), + PRT_ENTRY(0x0009FFFF, 2, GSI3), + PRT_ENTRY(0x0009FFFF, 3, GSI0), + + PRT_ENTRY(0x000AFFFF, 0, GSI2), + PRT_ENTRY(0x000AFFFF, 1, GSI3), + PRT_ENTRY(0x000AFFFF, 2, GSI0), + PRT_ENTRY(0x000AFFFF, 3, GSI1), + + PRT_ENTRY(0x000BFFFF, 0, GSI3), + PRT_ENTRY(0x000BFFFF, 1, GSI0), + PRT_ENTRY(0x000BFFFF, 2, GSI1), + PRT_ENTRY(0x000BFFFF, 3, GSI2), + + PRT_ENTRY(0x000CFFFF, 0, GSI0), + PRT_ENTRY(0x000CFFFF, 1, GSI1), + PRT_ENTRY(0x000CFFFF, 2, GSI2), + PRT_ENTRY(0x000CFFFF, 3, GSI3), + + PRT_ENTRY(0x000DFFFF, 0, GSI1), + PRT_ENTRY(0x000DFFFF, 1, GSI2), + PRT_ENTRY(0x000DFFFF, 2, GSI3), + PRT_ENTRY(0x000DFFFF, 3, GSI0), + + PRT_ENTRY(0x000EFFFF, 0, GSI2), + PRT_ENTRY(0x000EFFFF, 1, GSI3), + PRT_ENTRY(0x000EFFFF, 2, GSI0), + PRT_ENTRY(0x000EFFFF, 3, GSI1), + + PRT_ENTRY(0x000FFFFF, 0, GSI3), + PRT_ENTRY(0x000FFFFF, 1, GSI0), + PRT_ENTRY(0x000FFFFF, 2, GSI1), + PRT_ENTRY(0x000FFFFF, 3, GSI2), + + PRT_ENTRY(0x0010FFFF, 0, GSI0), + PRT_ENTRY(0x0010FFFF, 1, GSI1), + PRT_ENTRY(0x0010FFFF, 2, GSI2), + PRT_ENTRY(0x0010FFFF, 3, GSI3), + + PRT_ENTRY(0x0011FFFF, 0, GSI1), + PRT_ENTRY(0x0011FFFF, 1, GSI2), + PRT_ENTRY(0x0011FFFF, 2, GSI3), + PRT_ENTRY(0x0011FFFF, 3, GSI0), + + PRT_ENTRY(0x0012FFFF, 0, GSI2), + PRT_ENTRY(0x0012FFFF, 1, GSI3), + PRT_ENTRY(0x0012FFFF, 2, GSI0), + PRT_ENTRY(0x0012FFFF, 3, GSI1), + + PRT_ENTRY(0x0013FFFF, 0, GSI3), + PRT_ENTRY(0x0013FFFF, 1, GSI0), + PRT_ENTRY(0x0013FFFF, 2, GSI1), + PRT_ENTRY(0x0013FFFF, 3, GSI2), + + PRT_ENTRY(0x0014FFFF, 0, GSI0), + PRT_ENTRY(0x0014FFFF, 1, GSI1), + PRT_ENTRY(0x0014FFFF, 2, GSI2), + PRT_ENTRY(0x0014FFFF, 3, GSI3), + + PRT_ENTRY(0x0015FFFF, 0, GSI1), + PRT_ENTRY(0x0015FFFF, 1, GSI2), + PRT_ENTRY(0x0015FFFF, 2, GSI3), + PRT_ENTRY(0x0015FFFF, 3, GSI0), + + PRT_ENTRY(0x0016FFFF, 0, GSI2), + PRT_ENTRY(0x0016FFFF, 1, GSI3), + PRT_ENTRY(0x0016FFFF, 2, GSI0), + PRT_ENTRY(0x0016FFFF, 3, GSI1), + + PRT_ENTRY(0x0017FFFF, 0, GSI3), + PRT_ENTRY(0x0017FFFF, 1, GSI0), + PRT_ENTRY(0x0017FFFF, 2, GSI1), + PRT_ENTRY(0x0017FFFF, 3, GSI2), + + PRT_ENTRY(0x0018FFFF, 0, GSI0), + PRT_ENTRY(0x0018FFFF, 1, GSI1), + PRT_ENTRY(0x0018FFFF, 2, GSI2), + PRT_ENTRY(0x0018FFFF, 3, GSI3), + + PRT_ENTRY(0x0019FFFF, 0, GSI1), + PRT_ENTRY(0x0019FFFF, 1, GSI2), + PRT_ENTRY(0x0019FFFF, 2, GSI3), + PRT_ENTRY(0x0019FFFF, 3, GSI0), + + PRT_ENTRY(0x001AFFFF, 0, GSI2), + PRT_ENTRY(0x001AFFFF, 1, GSI3), + PRT_ENTRY(0x001AFFFF, 2, GSI0), + PRT_ENTRY(0x001AFFFF, 3, GSI1), + + PRT_ENTRY(0x001BFFFF, 0, GSI3), + PRT_ENTRY(0x001BFFFF, 1, GSI0), + PRT_ENTRY(0x001BFFFF, 2, GSI1), + PRT_ENTRY(0x001BFFFF, 3, GSI2), + + PRT_ENTRY(0x001CFFFF, 0, GSI0), + PRT_ENTRY(0x001CFFFF, 1, GSI1), + PRT_ENTRY(0x001CFFFF, 2, GSI2), + PRT_ENTRY(0x001CFFFF, 3, GSI3), + + PRT_ENTRY(0x001DFFFF, 0, GSI1), + PRT_ENTRY(0x001DFFFF, 1, GSI2), + PRT_ENTRY(0x001DFFFF, 2, GSI3), + PRT_ENTRY(0x001DFFFF, 3, GSI0), + + PRT_ENTRY(0x001EFFFF, 0, GSI2), + PRT_ENTRY(0x001EFFFF, 1, GSI3), + PRT_ENTRY(0x001EFFFF, 2, GSI0), + PRT_ENTRY(0x001EFFFF, 3, GSI1), + + PRT_ENTRY(0x001FFFFF, 0, GSI3), + PRT_ENTRY(0x001FFFFF, 1, GSI0), + PRT_ENTRY(0x001FFFFF, 2, GSI1), + PRT_ENTRY(0x001FFFFF, 3, GSI2), + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min Base Address + 0xEFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x70000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x100000000, // Min Base Address + 0xFFFFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0xFF00000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x0000ffff, // Max Base Address + 0x7fff0000, // Translate + 0x00010000, // Length + ,,,TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: H= ardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, N= onCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000000F0000000, // Range Minimum + 0x00000000FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + // OS Control Handoff + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + * See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC,4) { + // Check for proper UUID + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3,0,CDW1) + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If (LNotEqual(And(SUPP, 0x16), 0x16)) { + And (CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And (CTRL,0x1D,CTRL) + + If (LNotEqual(Arg1,One)) { // Unknown revision + Or (CDW1,0x08,CDW1) + } + + If (LNotEqual(CDW3,CTRL)) { // Capabilities bits were mas= ked + Or (CDW1,0x10,CDW1) + } + + // Update DWORD3 in the buffer + Store (CTRL,CDW3) + Return (Arg3) + } Else { + Or (CDW1,4,CDW1) // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } } // Scope (_SB) } diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Mcfg.aslc new file mode 100644 index 000000000000..e78061f9fe1c --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc @@ -0,0 +1,43 @@ +/** @file +* ACPI Memory mapped configuration space base address Description Table (= MCFG). +* +* Copyright (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#pragma pack(push, 1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure[2]; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = =3D { + { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDR= ESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), + EFI_ACPI_RESERVED_QWORD + }, + { + { + SBSAQEMU_PCI_SEG0_CONFIG_BASE, + 0, + SBSAQEMU_PCI_SEG0_BUSNUM_MIN, + SBSAQEMU_PCI_SEG0_BUSNUM_MAX, + EFI_ACPI_RESERVED_DWORD + } + } +}; + +#pragma pack(pop) + +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Mcfg; --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64436): https://edk2.groups.io/g/devel/message/64436 Mute This Topic: https://groups.io/mt/76287446/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 16:00:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64437+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64437+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1597847452; cv=none; d=zohomail.com; s=zohoarc; b=gfycmFwvXCfVfKVbqvCBqaCMOsjfVLxQLwOMeILeAQFl5uaNFfzlJeEBnDPbKPOFXNWXE3Q17aUwgOMD27IKg65uuo0BPbkPaAmGkE0xtSDVNhBSYClvWyJ4nYCY832uC4u1ET+TWg4tl7ekKL1zUwLhpNcIGhUYF8WHB43oszk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1597847452; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=LqFSTMRn4le+jYLN0roTg87u9Owo/fmk+9fqc3AzODk=; b=HxeNILITG5B0pAiKQqjKrdF4kdrBIlW0oY/75FelxrmivBk+rL4LOHHHFC2Mvxh2UFTf/zSzWbh8TgqsBqXiE6WMoxKwmSqCH6a4R8MnzGeqLVfNW1JHvxnjH8uh7vHrk757sxEJr5ZvNGRosMAulVO6lyfNLtoIILi7W65PDhQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64437+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1597847452640263.78711446014165; Wed, 19 Aug 2020 07:30:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id y0Y1YY1788612xA9nBBpf0e4; Wed, 19 Aug 2020 07:30:52 -0700 X-Received: from mail-pj1-f68.google.com (mail-pj1-f68.google.com [209.85.216.68]) by mx.groups.io with SMTP id smtpd.web11.89265.1597847451615010812 for ; Wed, 19 Aug 2020 07:30:51 -0700 X-Received: by mail-pj1-f68.google.com with SMTP id d4so1197200pjx.5 for ; Wed, 19 Aug 2020 07:30:51 -0700 (PDT) X-Gm-Message-State: MD55BtHdpG7l7GsDisOMPOdcx1787277AA= X-Google-Smtp-Source: ABdhPJyMu/Y3Bi7AXHBgAOdXQa5KMLPwonXRrLaiJA6eUunJMeALKBlqbavhfzL0RHoeH7SArahgLg== X-Received: by 2002:a17:902:7d85:: with SMTP id a5mr19070712plm.148.1597847451038; Wed, 19 Aug 2020 07:30:51 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id y10sm3320752pjv.55.2020.08.19.07.30.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 07:30:50 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale Subject: [edk2-devel] [PATCH edk2-platforms 3/7] SbsaQemu: Add new ACPI driver and FDT parser to count CPUs Date: Wed, 19 Aug 2020 20:00:01 +0530 Message-Id: <20200819143005.13999-4-tanmay.jagdale@linaro.org> In-Reply-To: <20200819143005.13999-1-tanmay.jagdale@linaro.org> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1597847452; bh=s8pG2NTIfsK665CotD0VD7L4dTn2b+MnjM/0jKIGJQY=; h=Cc:Date:From:Reply-To:Subject:To; b=uEELb7GiRgqZ4DEBWe1GhoZVlPntqEumxu7QVCKLitAzX3HOWu8HvUGSwrTCzTIbJG/ sqaIQYS301YKvLeeCD48N0SP/2p/SRz8Exrjx2orS548PVdeAgGJKK1EhK+vNJK8s39W4 7Dl9ZbuV1m/iYzcg/Aa4j/aq2dexNUPjZC4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Add a new ACPI driver for the SbsaQemu platform which would handle any modifications needed for the ACPI tables. - Move FdtLib from LibraryClasses.common.PEIM to LibraryClasses.common so that SbsaQemuAcpiDxe driver can use the device tree APIs - Since the core count is controlled by Qemu, move the PcdCoreCount from PcdsFixedAtBuild to PcdsDynamic. - Add a parser function in this driver which parses the FDT created by Qemu to determine the number of CPUs and hence update the PcdCoreCount variable. Signed-off-by: Tanmay Jagdale --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +- Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 + Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 1 + .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 76 +++++++++++++++++++ .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 49 ++++++++++++ Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 + 6 files changed, 135 insertions(+), 2 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuA= cpiDxe.c create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuA= cpiDxe.inf diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 4739443cae93..d42b9cd4de49 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -75,6 +75,7 @@ [LibraryClasses.common] ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf =20 + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf =20 @@ -217,7 +218,6 @@ [LibraryClasses.common.PEIM] =20 PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf =20 - FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf ArmPlatformLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf =20 [LibraryClasses.common.DXE_CORE] @@ -376,7 +376,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE =20 - gArmPlatformTokenSpaceGuid.PcdCoreCount|1 gArmTokenSpaceGuid.PcdVFPEnabled|1 =20 # System Memory Base -- fixed @@ -477,6 +476,9 @@ [PcdsFixedAtBuild.common] [PcdsDynamicDefault.common] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 =20 + # Core and Cluster Count + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|1 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|1 =20 # System Memory Size -- 128 MB initially, actual size will be fetched fr= om DT # TODO as no DT will be used we should pass this by some other method diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/S= bsaQemu.fdf index 4526eaaa02c5..3bcf0bf0040a 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf @@ -232,6 +232,7 @@ [FV.FvMain] # INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf INF RuleOverride =3D ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTabl= es.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf =20 diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acp= i.dsc.inc index c4a8d7a27b78..593670383750 100644 --- a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc @@ -33,3 +33,4 @@ [Components.common] MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c new file mode 100644 index 000000000000..09e5ba432a59 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -0,0 +1,76 @@ +/** @file +* This file is an ACPI driver for the Qemu SBSA platform. +* +* Copyright (c) 2020, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include + +/* + * A function that walks through the Device Tree created + * by Qemu and counts the number of CPUs present in it. + */ +STATIC +VOID +CountCpusFromFdt ( + VOID +) +{ + VOID *DeviceTreeBase; + INT32 Node, Prev; + RETURN_STATUS PcdStatus; + INT32 CpuNode; + INT32 CpuCount; + + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); + ASSERT (DeviceTreeBase !=3D NULL); + + // Make sure we have a valid device tree blob + ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); + + CpuNode =3D fdt_path_offset (DeviceTreeBase, "/cpus"); + if (CpuNode <=3D 0) { + DEBUG((EFI_D_ERROR, "Unable to locate /cpus in device tree\n")); + return; + } + + CpuCount =3D 0; + + // Walk through /cpus node and count the number of subnodes. + // The count of these subnodes corresponds to the numer of + // CPUs created by Qemu. + Prev =3D fdt_first_subnode (DeviceTreeBase, CpuNode); + while (1) { + CpuCount++; + Node =3D fdt_next_subnode (DeviceTreeBase, Prev); + if (Node < 0) { + break; + } + Prev =3D Node; + } + ASSERT (CpuCount > 0); + + PcdStatus =3D PcdSet32S (PcdCoreCount, CpuCount); + ASSERT_RETURN_ERROR (PcdStatus); +} + +EFI_STATUS +EFIAPI +InitializeSbsaQemuAcpiDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // Parse the device tree and get the number of CPUs + CountCpusFromFdt (); + + return EFI_SUCCESS; +} diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf new file mode 100644 index 000000000000..efc4d295bfb7 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -0,0 +1,49 @@ +## @file +# This driver modifies ACPI tables for the Qemu SBSA platform +# +# Copyright (c) 2020, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001d + BASE_NAME =3D SbsaQemuAcpiDxe + FILE_GUID =3D 6c592dc9-76c8-474f-93b2-bf1e8f15ae35 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D InitializeSbsaQemuAcpiDxe + +[Sources] + SbsaQemuAcpiDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmVirtPkg/ArmVirtPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[LibraryClasses] + ArmLib + BaseMemoryLib + DebugLib + BaseLib + FdtLib + DxeServicesLib + PcdLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Pcd] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress + +[Depex] + TRUE diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/Sbs= aQemu.dec index 71ba55a082e2..ed87d15de003 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -35,3 +35,7 @@ [PcdsFixedAtBuild.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x00= 000003 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT3= 2|0x00000004 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x100000= 00000|UINT64|0x00000005 + +[PcdsDynamic.common] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000006 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x0000= 0007 --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64437): https://edk2.groups.io/g/devel/message/64437 Mute This Topic: https://groups.io/mt/76287454/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 16:00:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64438+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64438+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1597847460; cv=none; d=zohomail.com; s=zohoarc; b=DUIyWsJkvkwknW+tIchr9Ia8189QWFXs4JHsSnok0KbnVtiCDerkJywekFdjPw+LiLMxYv94BOExiCG5kgzqnxzR4wP+uAzInuRh0OShYw3zNWPnuargsNPB000tFe/Ibwry24PEPLzisXiR0G3EXtOIhoPeJTnlBjn2KVtaQTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1597847460; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6YJXyR3Zlks6ARF2B6STxcrMWBAmWWQt5UMb+jFyhRw=; b=CDr9U7IHAGgX7blSb9QWN+anb/yZlicAckpH6UGeHSvFXB/nUh98RUHZ7lHh2i1+kW51MPfSU1dfjN28VQmPQLj1J2T6KNOuPJ7kjLF+wNcWH4Ko2IKL0YDqce0vbxmAISh8KIHz+qDlRvQgfwbrAfBU0gT9RRfoCCoWQsKgL7M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64438+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1597847460547495.18169641327074; Wed, 19 Aug 2020 07:31:00 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id iSAFYY1788612xPjk0eMv2uG; Wed, 19 Aug 2020 07:31:00 -0700 X-Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by mx.groups.io with SMTP id smtpd.web12.88616.1597847459561360346 for ; Wed, 19 Aug 2020 07:30:59 -0700 X-Received: by mail-pf1-f196.google.com with SMTP id r11so11759680pfl.11 for ; Wed, 19 Aug 2020 07:30:59 -0700 (PDT) X-Gm-Message-State: oCM3by8s8f1vPg0LS8O5N9Z2x1787277AA= X-Google-Smtp-Source: ABdhPJxrjOUaK5o08vlgeEZs9NXIP/SZPeShR7v8AHML2jgz79LgSJFj3ertDuiAqyp7NK4ywmiBQQ== X-Received: by 2002:a63:2584:: with SMTP id l126mr16612499pgl.126.1597847458731; Wed, 19 Aug 2020 07:30:58 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id y10sm3320752pjv.55.2020.08.19.07.30.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 07:30:57 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale Subject: [edk2-devel] [PATCH edk2-platforms 4/7] SbsaQemu: AcpiDxe: Create MADT table at runtime Date: Wed, 19 Aug 2020 20:00:02 +0530 Message-Id: <20200819143005.13999-5-tanmay.jagdale@linaro.org> In-Reply-To: <20200819143005.13999-1-tanmay.jagdale@linaro.org> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1597847460; bh=x6Ymlp79bufCLRvaLjSG7I1PRAmFL19fSiwFt9YQogQ=; h=Cc:Date:From:Reply-To:Subject:To; b=g2GoYc0OKJsDNwIB434IfPiy9jJpB3cLIRlHvqxyQYpVtHjIJNnOoWsX31TSAR/2NPS W7LhDq7Hx+I+iqAuLb/0gqPeflUtEe7LH6J5E8115htb9cu9f9rYd7pLqB/4v8IpLWpRA NtdVtrFRG8GGgtQ3xMW0Oh4xpc6cIrZWPUc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Add support to create MADT table at runtime. - Included a macro for GIC Redistributor structure initialisation. Signed-off-by: Tanmay Jagdale --- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 159 ++++++++++++++++++ .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++- .../Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++ 3 files changed, 193 insertions(+), 1 deletion(-) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 09e5ba432a59..569cda8b6474 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -6,11 +6,19 @@ * SPDX-License-Identifier: BSD-2-Clause-Patent * **/ +#include +#include +#include +#include +#include +#include #include +#include #include #include #include #include +#include #include #include =20 @@ -62,6 +70,138 @@ CountCpusFromFdt ( ASSERT_RETURN_ERROR (PcdStatus); } =20 +/* + * A Function to Compute the ACPI Table Checksum + */ +VOID +AcpiPlatformChecksum ( + IN UINT8 *Buffer, + IN UINTN Size + ) +{ + UINTN ChecksumOffset; + + ChecksumOffset =3D OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + + // Set checksum to 0 first + Buffer[ChecksumOffset] =3D 0; + + // Update checksum value + Buffer[ChecksumOffset] =3D CalculateCheckSum8(Buffer, Size); +} + +/* + * A function that add the MADT ACPI table. + IN EFI_ACPI_COMMON_HEADER *CurrentTable + */ +EFI_STATUS +AddMadtTable ( + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable + ) +{ + EFI_STATUS Status; + UINTN TableHandle; + UINT32 TableSize; + EFI_PHYSICAL_ADDRESS PageAddress; + UINT8 *New; + UINT32 NumCores; + + // Initialize MADT ACPI Header + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header =3D { + SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SI= GNATURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HE= ADER, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_RE= VISION), + 0, 0 }; + + // Initialize GICC Structure + EFI_ACPI_6_0_GIC_STRUCTURE Gicc =3D EFI_ACPI_6_0_GICC_STRUCTURE_INIT ( + 0, /* GicID */ + 0, /* AcpiCpuUid */ + 0, /* Mpidr */ + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */ + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */ + FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */ + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */ + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */ + 25, /* GsivId */ + 0, /* GicRBase */ + 0 /* Efficiency */ + ); + + // Initialize GIC Distributor Structure + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =3D + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT ( + 0, + FixedPcdGet32 (PcdGicDistributorBase), + 0, + 3 /* GicVersion */ + ); + + // Initialize GIC Redistributor Structure + EFI_ACPI_6_0_GICR_STRUCTURE Gicr =3D SBSAQEMU_MADT_GICR_INIT(); + + // Get CoreCount which was determined eariler after parsing device tree + NumCores =3D PcdGet32 (PcdCoreCount); + + // Calculate the new table size based on the number of cores + TableSize =3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADE= R) + + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIReclaimMemory, + EFI_SIZE_TO_PAGES (TableSize), + &PageAddress + ); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "Failed to allocate pages for MADT table\n")); + return EFI_OUT_OF_RESOURCES; + } + + New =3D (UINT8 *)(UINTN) PageAddress; + ZeroMem (New, TableSize); + + // Add the ACPI Description table header + CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TA= BLE_HEADER)); + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length =3D TableSize; + New +=3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); + + // Add new GICC structures for the Cores + for (NumCores =3D 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) { + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; + + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); + GiccPtr =3D (EFI_ACPI_6_0_GIC_STRUCTURE *) New; + GiccPtr->AcpiProcessorUid =3D NumCores; + GiccPtr->MPIDR =3D NumCores; + New +=3D sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); + } + + // GIC Distributor Structure + CopyMem (New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE)); + New +=3D sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE); + + // GIC ReDistributor Structure + CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE)); + New +=3D sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); + + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + (EFI_ACPI_COMMON_HEADER *)PageAddress, + TableSize, + &TableHandle + ); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "Failed to install MADT table\n")); + } + + return Status; +} + EFI_STATUS EFIAPI InitializeSbsaQemuAcpiDxe ( @@ -69,8 +209,27 @@ InitializeSbsaQemuAcpiDxe ( IN EFI_SYSTEM_TABLE *SystemTable ) { + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + // Parse the device tree and get the number of CPUs CountCpusFromFdt (); =20 + // Check if ACPI Table Protocol has been installed + Status =3D gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID **)&AcpiTable + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Failed to locate ACPI Table Protocol\n")); + return Status; + } + + Status =3D AddMadtTable (AcpiTable); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Failed to add MADT table\n")); + } + return EFI_SUCCESS; } diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf index efc4d295bfb7..16bc1b0c8cb1 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -41,9 +41,27 @@ [LibraryClasses] UefiRuntimeServicesTableLib =20 [Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress =20 [Depex] - TRUE + gEfiAcpiTableProtocolGuid ## CONSUMES + +[Guids] + gEdkiiPlatformHasAcpiGuid + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index eac195b0585c..7a9a0061675f 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -22,6 +22,21 @@ FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevisio= n */ \ } =20 +// Defines for MADT +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000 +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000 +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23 +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000 + +// Macro for MADT GIC Redistributor Structure +#define SBSAQEMU_MADT_GICR_INIT() { = \ + EFI_ACPI_6_0_GICR, /* Type */ = \ + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ = \ + EFI_ACPI_RESERVED_WORD, /* Reserved */ = \ + FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress = */ \ + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ = \ + } + #define SBSAQEMU_UART0_BASE 0x60000000 =20 #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000 --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64438): https://edk2.groups.io/g/devel/message/64438 Mute This Topic: https://groups.io/mt/76287456/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 16:00:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64439+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64439+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1597847467; cv=none; d=zohomail.com; s=zohoarc; b=m5SvBcJ2NVYzGyPLofYvT/i7oMppeLnpGXQPUOOX9r7GSUgQ9NEiRjDaYD8Vpdvejsm9kZFgPOo0+pWB3zvVbd2ZzUzejcW09jy6UdQQ5W29bFmoeKNSJWZDUZET4uQqNw9ZVe1zlvCm4kvxOwEyU0aj8A2a9+rMbvSViRU7tCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1597847467; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=fbvUKe3sXLv6vreRaLCEehLS15fUtrjshF1nAZGGKRU=; b=dx8feyXK5yKt+rIO63AB6QWDv65mClTCzysIkVCT6yF1MlLQgIo9OBAXpxwbTganoZy/fqJ2I64T44dFUS/3rS2/LOjb40cP1xltblURqcdqvzY1l1YuCnDBnZ95R2zeOa9tOaJw7ItHXTyuJNd/iDZIzwaidGaENUm+LQtmS08= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64439+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1597847467281420.9280322832044; Wed, 19 Aug 2020 07:31:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id kkq5YY1788612xjQSApePMKx; Wed, 19 Aug 2020 07:31:06 -0700 X-Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by mx.groups.io with SMTP id smtpd.web10.89408.1597847466280266250 for ; Wed, 19 Aug 2020 07:31:06 -0700 X-Received: by mail-pl1-f195.google.com with SMTP id f5so10895315plr.9 for ; Wed, 19 Aug 2020 07:31:06 -0700 (PDT) X-Gm-Message-State: 6Td2KRUph84kr4VLbCYvpXjPx1787277AA= X-Google-Smtp-Source: ABdhPJy+RzfSj+SFkmnVB3THRf9QGb4UTH3s387B1GLN3HlwMsZB7yIgLld6OP6Eex4wDc95eaGxmA== X-Received: by 2002:a17:90b:4385:: with SMTP id in5mr4133279pjb.16.1597847465812; Wed, 19 Aug 2020 07:31:05 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id y10sm3320752pjv.55.2020.08.19.07.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 07:31:05 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale Subject: [edk2-devel] [PATCH edk2-platforms 5/7] SbsaQemu: AcpiDxe: Create SSDT table at runtime Date: Wed, 19 Aug 2020 20:00:03 +0530 Message-Id: <20200819143005.13999-6-tanmay.jagdale@linaro.org> In-Reply-To: <20200819143005.13999-1-tanmay.jagdale@linaro.org> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1597847466; bh=hCEEVwKvxp6ZgyckV7okfAvVN8oagHIHlZGq71TXfaU=; h=Cc:Date:From:Reply-To:Subject:To; b=omOVhJvi1hHWMMKxu1gTaTvCEAO4rnbj21OWlK22ZlRoHSDW5+IreysszIrKMQk3DOg 11bYTVDz5oc+IvSHlVLal40SGO/PmlR8a5Yo3nLmddAquwJzP/SWHScWUeqOUKtRD9eMO wIUcgYj2thFYYbO2i9cRDT21uGizph7C3BQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" - Add support to create SSDT table at runtime. Since SSDT table is a data table, added a few helper macros to create the AML entries. - Also added a function to calculate the length of Packages. Signed-off-by: Tanmay Jagdale --- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 144 ++++++++++++++++++ .../Include/IndustryStandard/SbsaQemuAcpi.h | 29 ++++ 2 files changed, 173 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 569cda8b6474..d90ce0c2a718 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -202,6 +203,144 @@ AddMadtTable ( return Status; } =20 +/* + * Function to calculate the PkgLength field in ACPI tables + */ +STATIC +UINT32 +SetPkgLength ( + IN UINT8 *TablePtr, + IN UINT32 Length +) +{ + UINT8 ByteCount; + UINT8 *PkgLeadByte =3D TablePtr; + + if (Length < 64) { + *TablePtr =3D Length; + return 1; + } + + // Set the LSB of Length in PkgLeadByte and advance Length + *PkgLeadByte =3D Length & 0xF; + Length =3D Length >> 4; + + while (Length) { + TablePtr++; + *TablePtr =3D (Length & 0xFF); + Length =3D (Length >> 8); + } + + // Calculate the number of bytes the Length field uses + // and set the ByteCount field in PkgLeadByte. + ByteCount =3D (TablePtr - PkgLeadByte) & 0xF; + *PkgLeadByte |=3D (ByteCount << 6); + + return ByteCount + 1; +} + +/* + * A function that adds SSDT ACPI table. + */ +EFI_STATUS +AddSsdtTable ( + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable + ) +{ + EFI_STATUS Status; + UINTN TableHandle; + UINT32 TableSize; + EFI_PHYSICAL_ADDRESS PageAddress; + UINT8 *New; + UINT32 CpuId; + UINT32 Offset; + UINT8 ScopeOpName[] =3D SBSAQEMU_ACPI_SCOPE_NAME; + UINT32 NumCores =3D PcdGet32 (PcdCoreCount); + + EFI_ACPI_DESCRIPTION_HEADER Header =3D + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_DESCRIPTION_HEADER, + EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION); + + SBSAQEMU_ACPI_CPU_DEVICE CpuDevice =3D { + { AML_EXT_OP, AML_EXT_DEVICE_OP }, /* Device () */ + SBSAQEMU_ACPI_CPU_DEV_LEN, /* Length */ + SBSAQEMU_ACPI_CPU_DEV_NAME, /* Device Name "C000" */ + SBSAQEMU_ACPI_CPU_HID, /* Name (HID, "ACPI0007") */ + SBSAQEMU_ACPI_CPU_UID, /* Name (UID, 0) */ + }; + + // Calculate the new table size based on the number of cores + TableSize =3D sizeof (EFI_ACPI_DESCRIPTION_HEADER) + + SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH + sizeof (ScopeOpName) + + (sizeof (CpuDevice) * NumCores); + + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIReclaimMemory, + EFI_SIZE_TO_PAGES (TableSize), + &PageAddress + ); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Failed to allocate pages for SSDT table\n")); + return EFI_OUT_OF_RESOURCES; + } + + New =3D (UINT8 *)(UINTN) PageAddress; + ZeroMem (New, TableSize); + + // Add the ACPI Description table header + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER)); + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length =3D TableSize; + New +=3D sizeof (EFI_ACPI_DESCRIPTION_HEADER); + + // Insert the top level ScopeOp + *New =3D AML_SCOPE_OP; + New++; + Offset =3D SetPkgLength (New, + (TableSize - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - 1)); + New +=3D Offset; + CopyMem (New, &ScopeOpName, sizeof (ScopeOpName)); + New +=3D sizeof (ScopeOpName); + + // Add new Device structures for the Cores + for (CpuId =3D 0; CpuId < NumCores; CpuId++) { + SBSAQEMU_ACPI_CPU_DEVICE *CpuDevicePtr; + UINT8 CpuIdByte1, CpuIdByte2, CpuIdByte3; + + CopyMem (New, &CpuDevice, sizeof (SBSAQEMU_ACPI_CPU_DEVICE)); + CpuDevicePtr =3D (SBSAQEMU_ACPI_CPU_DEVICE *) New; + + CpuIdByte1 =3D CpuId & 0xF; + CpuIdByte2 =3D (CpuId >> 4) & 0xF; + CpuIdByte3 =3D (CpuId >> 8) & 0xF; + + CpuDevicePtr->dev_name[1] =3D SBSAQEMU_ACPI_ITOA(CpuIdByte3); + CpuDevicePtr->dev_name[2] =3D SBSAQEMU_ACPI_ITOA(CpuIdByte2); + CpuDevicePtr->dev_name[3] =3D SBSAQEMU_ACPI_ITOA(CpuIdByte1); + + CpuDevicePtr->uid[6] =3D CpuIdByte1 | CpuIdByte2; + CpuDevicePtr->uid[7] =3D CpuIdByte3; + New +=3D sizeof (SBSAQEMU_ACPI_CPU_DEVICE); + } + + // Perform Checksum + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); + + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + (EFI_ACPI_COMMON_HEADER *)PageAddress, + TableSize, + &TableHandle + ); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Failed to install SSDT table\n")); + } + + return Status; +} + EFI_STATUS EFIAPI InitializeSbsaQemuAcpiDxe ( @@ -231,5 +370,10 @@ InitializeSbsaQemuAcpiDxe ( DEBUG((EFI_D_ERROR, "Failed to add MADT table\n")); } =20 + Status =3D AddSsdtTable (AcpiTable); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n")); + } + return EFI_SUCCESS; } diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index 7a9a0061675f..60acc083ddbb 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -43,4 +43,33 @@ #define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00 #define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF =20 +#define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5 + +#define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' } + +#define SBSAQEMU_ACPI_CPU_DEV_LEN 0x1C +#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' } + +// Macro to convert Integer to Character +#define SBSAQEMU_ACPI_ITOA(Byte) (0x30 + (Byte > 9 ? (Byte + 1) : Byte)) + +#define SBSAQEMU_ACPI_CPU_HID { = \ + AML_NAME_OP, AML_NAME_CHAR__, 'H', 'I', 'D', = \ + AML_STRING_PREFIX, 'A', 'C', 'P', 'I', '0', '0', '0', '7', = \ + AML_ZERO_OP = \ + } + +#define SBSAQEMU_ACPI_CPU_UID { = \ + AML_NAME_OP, AML_NAME_CHAR__, 'U', 'I', 'D', AML_BYTE_PREFIX, = \ + AML_ZERO_OP, AML_ZERO_OP = \ + } + +typedef struct { + UINT8 device_header[2]; + UINT8 length; + UINT8 dev_name[4]; + UINT8 hid[15]; + UINT8 uid[8]; +} SBSAQEMU_ACPI_CPU_DEVICE; + #endif --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#64439): https://edk2.groups.io/g/devel/message/64439 Mute This Topic: https://groups.io/mt/76287464/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 16:00:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+64440+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64440+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1597847478; cv=none; d=zohomail.com; s=zohoarc; b=keA1pk75YyBlbXkhgwF+34nPws7OPx1OwaQy3lrkGLa6OAtZiHA9iHcimF7wT2Jaj6y6SYTyP2V8x66ZiIE03LeomGWAX5AjOS7fUi0zHky5tVEWSkpDPd2OKyPiYMnaLDto03WGmbovUvXJ6yqf+d1XxKXqilVwhCtfu52ZtsY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1597847478; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Z1cUGSiKq0zzINgCCA8+SZlOq728obrgZtvZYiI9gD8=; b=PIUEdwkOdlJYuIDd5PEiRoaQfrAtgp5vs9zSMDMZPMlzt/WKuWjSPjCAlv7ixVcSV09lor54yJ0wFSlTzwT7EiAQZGkZK+MSvH/Qsg6layahWfY2cuKab4jT3Ue1tZD1iT8C4EGApN1sjCPxkjkLnlQOPdC8lJ+T/NJmJOKkGnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+64440+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1597847478069884.4788197078146; Wed, 19 Aug 2020 07:31:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id TFFvYY1788612x0Jgs7EByeZ; Wed, 19 Aug 2020 07:31:17 -0700 X-Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by mx.groups.io with SMTP id smtpd.web12.88628.1597847476958382730 for ; Wed, 19 Aug 2020 07:31:17 -0700 X-Received: by mail-pf1-f196.google.com with SMTP id u128so11771777pfb.6 for ; Wed, 19 Aug 2020 07:31:16 -0700 (PDT) X-Gm-Message-State: 956WcNqHhBczYtsPOvkn59C4x1787277AA= X-Google-Smtp-Source: ABdhPJzh6weXZBUJa37z3hPBZmJjv1FOS6BBMH+OWlW74J8pbNI1V5LWNAwcqGJQ+8zZSUbWmZtWlg== X-Received: by 2002:a63:7e42:: with SMTP id o2mr13465936pgn.260.1597847476449; Wed, 19 Aug 2020 07:31:16 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id y10sm3320752pjv.55.2020.08.19.07.31.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 07:31:16 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale Subject: [edk2-devel] [PATCH edk2-platforms 6/7] SbsaQemu: AcpiDxe: Create PPTT table at runtime Date: Wed, 19 Aug 2020 20:00:04 +0530 Message-Id: <20200819143005.13999-7-tanmay.jagdale@linaro.org> In-Reply-To: <20200819143005.13999-1-tanmay.jagdale@linaro.org> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1597847477; bh=e4tuso8kJjmV/lFqkgMZhkQPRuugqcv6/+5QavxwElY=; h=Cc:Date:From:Reply-To:Subject:To; b=mT8SQttxs6AR6U+iGiLe6mdpnC6cKch4HlKCQMicPXRFfbpXADdmiYFws2MKBl3TRG1 3rY3f2XKxsJitE114iLvcc6RaTcc+XpKQu1d9ywxsolP+vkEt6r/9BzNsu4mAYsW+9y+o IKnkeNJmZT3DonvDit0/mTfeZzfc0p6YoK0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add support to create Processor Properties Topology Table at runtime. The cache topology of each CPU is as follows: CPU N ------------------------ | -------- -------- | | | L1-I | | L1-D | | | | 32KB | | 32KB | | | -------- -------- | | ------------------ | | | L2 512KB | | | ------------------ | ------------------------ Signed-off-by: Tanmay Jagdale --- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 111 ++++++++++++++++ .../Include/IndustryStandard/SbsaQemuAcpi.h | 124 ++++++++++++++++++ 2 files changed, 235 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index d90ce0c2a718..8527b976ee33 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -341,6 +342,111 @@ AddSsdtTable ( return Status; } =20 +/* + * A function that adds the SSDT ACPI table. + */ +EFI_STATUS +AddPpttTable ( + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable + ) +{ + EFI_STATUS Status; + UINTN TableHandle; + UINT32 TableSize; + EFI_PHYSICAL_ADDRESS PageAddress; + UINT8 *New; + UINT32 CpuId; + UINT32 NumCores =3D PcdGet32 (PcdCoreCount); + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache =3D SBSAQEMU_ACPI_PPTT_L1_D_C= ACHE_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache =3D SBSAQEMU_ACPI_PPTT_L1_I_C= ACHE_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache =3D SBSAQEMU_ACPI_PPTT_L2_CACH= E_STRUCT; + + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster =3D SBSAQEMU_ACPI_PPTT_CLU= STER_STRUCT; + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core =3D SBSAQEMU_ACPI_PPTT_CORE_S= TRUCT; + + EFI_ACPI_DESCRIPTION_HEADER Header =3D + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_DESCRIPTION_HEADER, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION); + + TableSize =3D sizeof (EFI_ACPI_DESCRIPTION_HEADER) + + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) + + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) + + (sizeof (UINT32) * 2 * NumCores); + + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiACPIReclaimMemory, + EFI_SIZE_TO_PAGES (TableSize), + &PageAddress + ); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Failed to allocate pages for PPTT table\n")); + return EFI_OUT_OF_RESOURCES; + } + + New =3D (UINT8 *)(UINTN) PageAddress; + ZeroMem (New, TableSize); + + // Add the ACPI Description table header + CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER)); + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length =3D TableSize; + New +=3D sizeof (EFI_ACPI_DESCRIPTION_HEADER); + + // Add the Cluster PPTT structure + CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); + + // Add L1 D Cache structure + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D L2_CACH= E_INDEX; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + // Add L1 I Cache structure + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D L2_CACH= E_INDEX; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + // Add L2 Cache structure + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache =3D 0; /* L= 2 is LLC */ + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); + + for (CpuId =3D 0; CpuId < NumCores; CpuId++) { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr; + UINT32 *PrivateResourcePtr; + + CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); + CorePtr =3D (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New; + CorePtr->Parent =3D CLUSTER_INDEX; + CorePtr->AcpiProcessorId =3D CpuId; + New +=3D sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); + + PrivateResourcePtr =3D (UINT32 *) New; + PrivateResourcePtr[0] =3D L1_D_CACHE_INDEX; + PrivateResourcePtr[1] =3D L1_I_CACHE_INDEX; + New +=3D (2 * sizeof (UINT32)); + } + + // Perform Checksum + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); + + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + (EFI_ACPI_COMMON_HEADER *)PageAddress, + TableSize, + &TableHandle + ); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Failed to install PPTT table\n")); + } + + return Status; +} + EFI_STATUS EFIAPI InitializeSbsaQemuAcpiDxe ( @@ -375,5 +481,10 @@ InitializeSbsaQemuAcpiDxe ( DEBUG((EFI_D_ERROR, "Failed to add SSDT table\n")); } =20 + Status =3D AddPpttTable (AcpiTable); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Failed to add PPTT table\n")); + } + return EFI_SUCCESS; } diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h = b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index 60acc083ddbb..95cfca4727a6 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -72,4 +72,128 @@ typedef struct { UINT8 uid[8]; } SBSAQEMU_ACPI_CPU_DEVICE; =20 +#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB +#define SBSAQEMU_L1_D_CACHE_SETS 256 +#define SBSAQEMU_L1_D_CACHE_ASSC 2 + +#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB +#define SBSAQEMU_L1_I_CACHE_SETS 256 +#define SBSAQEMU_L1_I_CACHE_ASSC 2 + +#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB +#define SBSAQEMU_L2_CACHE_SETS 1024 +#define SBSAQEMU_L2_CACHE_ASSC 8 + +#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCT= URE_PROCESSOR)) +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STR= UCTURE_CACHE)) +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STR= UCTURE_CACHE)) + +#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SBSAQEMU_L2_CACHE_SIZE, /* Size */ = \ + SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ = \ + SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + } + +#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, = \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), = \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ = \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ = \ + }, = \ + 0, /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 0, /* NumberOfPrivateResources = */ \ + } + +#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { = \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, = \ + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32)= )), \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, = \ + { = \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ = \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */= \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ = \ + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ = \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ = \ + }, = \ + 0, /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResources = */ \ + } + #endif --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Wed, 19 Aug 2020 07:31:27 -0700 X-Received: by mail-pj1-f68.google.com with SMTP id c10so1232918pjn.1 for ; Wed, 19 Aug 2020 07:31:27 -0700 (PDT) X-Gm-Message-State: X6pQYIGaQqxYqiAKZxx8obW3x1787277AA= X-Google-Smtp-Source: ABdhPJxL0vsSKNfYZpdzge7M6zVmyuoaV5PSTft94VjfB90M8EvdHfxq7iFvQBqU1d0q959CxgL+Mg== X-Received: by 2002:a17:90a:e94c:: with SMTP id kp12mr4118821pjb.115.1597847486994; Wed, 19 Aug 2020 07:31:26 -0700 (PDT) X-Received: from bean-canyon.localdomain ([106.51.140.68]) by smtp.googlemail.com with ESMTPSA id y10sm3320752pjv.55.2020.08.19.07.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 07:31:26 -0700 (PDT) From: "Tanmay Jagdale" To: leif@nuviainc.com, graeme@nuviainc.com, shashi.mallela@linaro.org, devel@edk2.groups.io Cc: paul.isaacs@linaro.org, tanmay@marvell.com, Tanmay Jagdale Subject: [edk2-devel] [PATCH edk2-platforms 7/7] SbsaQemu: AcpiTables: Add DBG2 Table Date: Wed, 19 Aug 2020 20:00:05 +0530 Message-Id: <20200819143005.13999-8-tanmay.jagdale@linaro.org> In-Reply-To: <20200819143005.13999-1-tanmay.jagdale@linaro.org> References: <20200819143005.13999-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tanmay.jagdale@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1597847487; bh=WDphPesQ0DtkqTNmvI5c6jtyp8TvNNxy06iaxcdcdCo=; h=Cc:Date:From:Reply-To:Subject:To; b=jyhMitGHVOeXFPfu9P2rV4DCLYre7lW3XBvKXyj/fqfsPlSpmkHOQKa1PLMifm5HDna wBP2R72U3lY5ks2e4w8UyNHEBNZUxXGQqLZXX6OAWCJ0v+lienKL/910nJ+8ZmUTStNqZ 1FnoJciigCoJZe4wOZiawSuK630aayK0uEU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Tanmay Jagdale --- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 68 +++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu= /SbsaQemu/AcpiTables/AcpiTables.inf index 0b5017ce81c5..cf6628c9e491 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -17,6 +17,7 @@ [Defines] =20 [Sources] Dsdt.asl + Dbg2.aslc Fadt.aslc Gtdt.aslc Spcr.aslc diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc b/Silicon/Qemu/Sbsa= Qemu/AcpiTables/Dbg2.aslc new file mode 100644 index 000000000000..801b05b59a42 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc @@ -0,0 +1,68 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include + +#pragma pack(1) + +#define SBSAQEMU_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '0', = 0x00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 =3D { + { + SBSAQEMU_ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegist= ers */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + ARM_GAS32 (SBSAQEMU_UART0_BASE), /* BaseAddressRegister */ + 0x1000, /* AddressSize */ + SBSAQEMU_UART_STR, /* NameSpaceString */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Dbg2; --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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