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mx.microsoft.com 1; spf=pass smtp.mailfrom=hpe.com; dmarc=pass action=none header.from=hpe.com; dkim=pass header.d=hpe.com; arc=none X-Received: from DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:760d::23) by DF4PR8401MB0506.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:7606::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3239.16; Fri, 7 Aug 2020 16:44:56 +0000 X-Received: from DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM ([fe80::4cbe:3dd0:cae4:b093]) by DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM ([fe80::4cbe:3dd0:cae4:b093%3]) with mapi id 15.20.3261.020; Fri, 7 Aug 2020 16:44:56 +0000 From: "Daniel Schaefer" To: CC: Abner Chang , Gilbert Chen , Leif Lindholm , Michael D Kinney , Ard Biesheuvel Subject: [edk2-devel] [PATCH 1/1] edk2-platforms: Deduplicate RISC-V SMBIOS Date: Fri, 7 Aug 2020 18:44:44 +0200 Message-ID: <20200807164444.1304-2-daniel.schaefer@hpe.com> In-Reply-To: <20200807164444.1304-1-daniel.schaefer@hpe.com> References: <20200807164444.1304-1-daniel.schaefer@hpe.com> X-ClientProxiedBy: SN2PR01CA0059.prod.exchangelabs.com (2603:10b6:800::27) To DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:760d::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from x360-nix.fritz.box (93.215.219.173) by SN2PR01CA0059.prod.exchangelabs.com (2603:10b6:800::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,daniel.schaefer@hpe.com X-Gm-Message-State: YxUlxDGsR7o2ZXHXocTpqStWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596818704; bh=1Twpl/Bz9BTLl7/er0w4opjl1jA0d3sbZSFp6xFD6LA=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=Ig+TSfNCnQAAUI8yyygjIyLPiB5V3Mhsli1eP1SeiPjT4HUiTBxF8yeuW3Yn6dLpbFH wZfavv5jT0Qo9yNCge+p64e9l8XiERjMqwB0uZrrM9DgMNrypF+fi/5HMptJ/TkgOJILP v39BZ11EmzgFmuoyH/hNkRsahGVxA5N9oRA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" There was too much code, which wasn't called but it could have generated th= ose SMBIOS table entries: - Type 4 for each core (4xU51, 1xE51) - Type 7 L1 instruction/data for each core - Type 7 L2 for U54 - Type 44 for each core - Type 4 for the coreplex - Type 7 L2 for the coreplex Now it only has code for those entries: - Type 4 for SOC [1x] - Type 7 L1 for SOC [1x] (even though every hart has own L1, but my Laptop'= s Intel i5 does that also) - Type 7 L2 for SOC [1x] - Type 44 for each hart, associated with CPU [5x] In addition to simplifying the SMBIOS tables, the code for U54 and E51 is combined, like Leif suggested in his review. Here's what happened to the files: Expanded: - Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/F= irmwareContextProcessorSpecificLib.c Deleted file: - Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c - Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c Merged with E51 code into single file: - Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c Added SMBIOS Type 7 for L1 Cache, removed duplicated SMBIOS (Type 4 and 7 c= ode): - Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c Cc: Abner Chang Cc: Gilbert Chen Cc: Leif Lindholm Cc: Michael D Kinney Cc: Ard Biesheuvel Reviewed-by: Leif Lindholm > Reviewed-by: Leif Lindholm --- Silicon/SiFive/SiFive.dec | 2 - .../FreedomU500VC707Board/U500.dsc | 1 - .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 - .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 1 - .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 ---- .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 4 + .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 ---- .../FirmwareContextProcessorSpecificLib.h | 11 + .../Include/ProcessorSpecificHobData.h | 3 +- Silicon/SiFive/Include/Library/SiFiveE51.h | 60 ----- Silicon/SiFive/Include/Library/SiFiveU54.h | 50 ++-- .../Include/Library/SiFiveU54MCCoreplex.h | 55 ---- .../FirmwareContextProcessorSpecificLib.c | 26 ++ .../Universal/Pei/PlatformPei/Platform.c | 2 +- .../Universal/Pei/PlatformPei/Platform.c | 2 +- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 58 +---- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 235 ----------------- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 244 +++++++----------- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 ------------- 19 files changed, 178 insertions(+), 854 deletions(-) delete mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInf= oHobLib.inf delete mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= PeiCoreInfoHobLib.inf delete mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h delete mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h delete mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHo= b.c delete mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= CoreInfoHob.c diff --git a/Silicon/SiFive/SiFive.dec b/Silicon/SiFive/SiFive.dec index 85ddfe0bf235..bf280864be63 100644 --- a/Silicon/SiFive/SiFive.dec +++ b/Silicon/SiFive/SiFive.dec @@ -28,8 +28,6 @@ [PcdsFixedAtBuild] gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid |{0xD4, 0x69, 0x54,= 0x87, 0x96, 0x96, 0x48, 0x7F, 0x9F, 0x57, 0xB6, 0xF1, 0xDE, 0x7D, 0x97, 0x= 42}|VOID*|0x00001000 # U54 Core GUID gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid |{0x64, 0x70, 0xF6,= 0x90, 0x11, 0x59, 0x47, 0xF1, 0xB8, 0xD5, 0xCF, 0x89, 0x10, 0xC5, 0x30, 0x= 20}|VOID*|0x00001001 - # U54 MC Coreplex GUID - gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid |{0x67, 0xBF,= 0x15, 0xD9, 0x7E, 0x4F, 0x48, 0x27, 0x87, 0x19, 0x79, 0x0B, 0xA6, 0x22, 0x= 7C, 0xBE}|VOID*|0x00001002 # U5 MC Coreplex GUID gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU5MCCoreplexGuid |{0x06, 0x38, = 0x9F, 0x33, 0xF9, 0xDB, 0x43, 0x13, 0x9A, 0x9B, 0x1C, 0x68, 0xD6, 0x04, 0xE= A, 0xFF}|VOID*|0x00001003 =20 diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/P= latform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc index 03f7006b9bb0..61a0cdedaaf4 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc @@ -203,7 +203,6 @@ [LibraryClasses.common.PEIM] # # RISC-V core libraries # - SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/Pei= CoreInfoHobLib/PeiCoreInfoHobLib.inf =20 diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 4809c7c6b7e8..2d7dabafaceb 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -204,7 +204,6 @@ [LibraryClasses.common.PEIM] # # RISC-V core libraries # - SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/Pei= CoreInfoHobLib/PeiCoreInfoHobLib.inf =20 diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreI= nfoHobLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCo= reInfoHobLib.inf index ab248b3718b9..b3124a6daf77 100644 --- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL= ib.inf +++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL= ib.inf @@ -37,7 +37,6 @@ [LibraryClasses] PcdLib MemoryAllocationLib PrintLib - SiliconSiFiveE51CoreInfoLib SiliconSiFiveU54CoreInfoLib =20 [Guids] diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf deleted file mode 100644 index 6c06c96be580..000000000000 --- a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf +++ /dev/null @@ -1,47 +0,0 @@ -## @file -# Library instance to create core information HOB -# -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001b - BASE_NAME =3D SiliconSiFiveE51CoreInfoLib - FILE_GUID =3D 80A59B85-1245-4309-AC58-2CFA4199B46C - MODULE_TYPE =3D PEIM - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D SiliconSiFiveE51CoreInfoLib - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D RISCV64 -# - -[Sources] - CoreInfoHob.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec - Silicon/SiFive/SiFive.dec - -[LibraryClasses] - BaseLib - FirmwareContextProcessorSpecificLib - MemoryAllocationLib - PcdLib - PrintLib - RiscVEdk2SbiLib - -[FixedPcd] - gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf index 9bbe2f064190..072024dc1be3 100644 --- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -29,6 +29,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec Silicon/SiFive/SiFive.dec =20 [LibraryClasses] @@ -45,3 +46,6 @@ [FixedPcd] gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid + gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU5MCCoreplexGuid + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCore= InfoHobLib.inf b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/Pei= CoreInfoHobLib.inf deleted file mode 100644 index 89bd702b8e0f..000000000000 --- a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHob= Lib.inf +++ /dev/null @@ -1,46 +0,0 @@ -## @file -# Library instance to create core information HOB -# -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001b - BASE_NAME =3D SiliconSiFiveU54MCCoreplexInfoLib - FILE_GUID =3D 483DE090-267E-4278-A0A1-15D9836780EA - MODULE_TYPE =3D PEIM - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D SiliconSiFiveU54MCCoreplexInfoLib - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D RISCV64 -# - -[Sources] - CoreInfoHob.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/RISC-V/ProcessorPkg/RiscVPkg.dec - Silicon/SiFive/SiFive.dec - -[LibraryClasses] - BaseLib - PcdLib - MemoryAllocationLib - PrintLib - SiliconSiFiveE51CoreInfoLib - SiliconSiFiveU54CoreInfoLib - -[FixedPcd] - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid - gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid - gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid - diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextPro= cessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareC= ontextProcessorSpecificLib.h index c53d09b69eea..f3b096c257f4 100644 --- a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h +++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h @@ -39,4 +39,15 @@ CommonFirmwareContextHartSpecificInfo ( RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecDataHob ); =20 +/** + Print debug information of the processor specific data for a hart + + @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB +**/ +VOID +EFIAPI +DebugPrintHartSpecificInfo ( + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob + ); + #endif diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h= b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h index c19f355853ae..2f5847e53e07 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h @@ -86,8 +86,7 @@ typedef struct { /// typedef struct { RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor; - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCache; - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCache; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache; RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache; RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache; } RISC_V_PROCESSOR_SMBIOS_HOB_DATA; diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h b/Silicon/SiFive/In= clude/Library/SiFiveE51.h deleted file mode 100644 index 6b587661860c..000000000000 --- a/Silicon/SiFive/Include/Library/SiFiveE51.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - SiFive E51 Core library definitions. - - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef SIFIVE_E51_CORE_H_ -#define SIFIVE_E51_CORE_H_ - -#include - -#include -#include - -/** - Function to build core specific information HOB. - - @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid - could be the same as CoreGuid if one proc= essor has - only one core. - @param ParentProcessorUid Unique ID of pysical processor which owns= this core. - @param HartId Hart ID of this core. - @param IsBootHart TRUE means this is the boot HART. - @param GuidHobData Pointer to receive RISC_V_PROCESSOR_SPECI= FIC_HOB_DATA. - - @return EFI_SUCCESS The PEIM initialized successfully. - -**/ -EFI_STATUS -EFIAPI -CreateE51CoreProcessorSpecificDataHob ( - IN EFI_GUID *ParentProcessorGuid, - IN UINTN ParentProcessorUid, - IN UINTN HartId, - IN BOOLEAN IsBootHart, - OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData - ); - -/** - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect - this information and build SMBIOS Type4 and Type7 record. - - @param ProcessorUid Unique ID of pysical processor which owns this c= ore. - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers - maintained in this structure is only valid befor= e memory is discovered. - Access to those pointers after memory is install= ed will cause unexpected issues. - - @return EFI_SUCCESS The PEIM initialized successfully. - -**/ -EFI_STATUS -EFIAPI -CreateE51ProcessorSmbiosDataHob ( - IN UINTN ProcessorUid, - OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr - ); - -#endif diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h b/Silicon/SiFive/In= clude/Library/SiFiveU54.h index 9920a55309b2..ddd2b9203404 100644 --- a/Silicon/SiFive/Include/Library/SiFiveU54.h +++ b/Silicon/SiFive/Include/Library/SiFiveU54.h @@ -11,11 +11,10 @@ =20 #include =20 -#include #include =20 /** - Function to build core specific information HOB. + Function to build core specific information HOB for U54 or E51 core. =20 @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid could be the same as CoreGuid if one proc= essor has @@ -23,38 +22,55 @@ @param ParentProcessorUid Unique ID of pysical processor which owns= this core. @param HartId Hart ID of this core. @param IsBootHart TRUE means this is the boot HART. - @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_= DATA. + @param IsManagementCore TRUE means this is for the E51 management= core, not U54 + @param GuidHobData Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_= DATA. =20 @return EFI_SUCCESS The PEIM initialized successfully. =20 **/ EFI_STATUS EFIAPI -CreateU54CoreProcessorSpecificDataHob ( +CreateU54E51CoreProcessorSpecificDataHob ( IN EFI_GUID *ParentProcessorGuid, IN UINTN ParentProcessorUid, IN UINTN HartId, IN BOOLEAN IsBootHart, - OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobdata - ); + IN BOOLEAN IsManagementCore, + OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData +); =20 /** - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect - this information and build SMBIOS Type4 and Type7 record. + Function to build cache related SMBIOS information. RISC-V SMBIOS DXE dr= iver collects + this information and builds SMBIOS Type 7 record. =20 - @param ProcessorUid Unique ID of pysical processor which owns this c= ore. - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers - maintained in this structure is only valid befor= e memory is discovered. - Access to those pointers after memory is install= ed will cause unexpected issues. + The caller can adjust the allocated hob data to their needs. =20 - @return EFI_SUCCESS The PEIM initialized successfully. + @param ProcessorUid Unique ID of physical processor which owns thi= s core. + @param L1CacheDataHobPtr Pointer to allocated HOB data. =20 **/ -EFI_STATUS +VOID EFIAPI -CreateU54ProcessorSmbiosDataHob ( +CreateU54SmbiosType7L1DataHob ( IN UINTN ProcessorUid, - IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr - ); + OUT RISC_V_PROCESSOR_TYPE7_HOB_DATA **L1CacheDataHobPtr +); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collects + this information and builds SMBIOS Type 4 record. + + The caller can adjust the allocated hob data to their needs. + + @param ProcessorUid Unique ID of physical processor which owns thi= s core. + @param ProcessorDataHobPtr Pointer to allocated HOB data. + +**/ +VOID +EFIAPI +CreateU54SmbiosType4DataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_TYPE4_HOB_DATA **ProcessorDataHobPtr +); =20 #endif diff --git a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h b/Silicon= /SiFive/Include/Library/SiFiveU54MCCoreplex.h deleted file mode 100644 index 0e14b285543a..000000000000 --- a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h +++ /dev/null @@ -1,55 +0,0 @@ -/** @file - SiFive U54 Coreplex library definitions. - - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef SIFIVE_U54MC_COREPLEX_CORE_H_ -#define SIFIVE_U54MC_COREPLEX_CORE_H_ - -#include - -#include -#include - -#define SIFIVE_U54MC_COREPLEX_E51_HART_ID 0 -#define SIFIVE_U54MC_COREPLEX_U54_0_HART_ID 1 -#define SIFIVE_U54MC_COREPLEX_U54_1_HART_ID 2 -#define SIFIVE_U54MC_COREPLEX_U54_2_HART_ID 3 -#define SIFIVE_U54MC_COREPLEX_U54_3_HART_ID 4 - -/** - Build up U54MC coreplex processor core-specific information. - - @param UniqueId U54MC unique ID. - - @return EFI_STATUS - -**/ -EFI_STATUS -EFIAPI -CreateU54MCCoreplexProcessorSpecificDataHob ( - IN UINTN UniqueId - ); - -/** - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect - this information and build SMBIOS Type4 and Type7 record. - - @param ProcessorUid Unique ID of pysical processor which owns this c= ore. - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers - maintained in this structure is only valid befor= e memory is discovered. - Access to those pointers after memory is install= ed will cause unexpected issues. - - @return EFI_SUCCESS The PEIM initialized successfully. - -**/ -EFI_STATUS -EFIAPI -CreateU54MCProcessorSmbiosDataHob ( - IN UINTN ProcessorUid, - IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr - ); -#endif diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSp= ecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformP= kg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpec= ificLib.c index 066d1170c6f0..c62f77bc49ba 100644 --- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c @@ -91,3 +91,29 @@ CommonFirmwareContextHartSpecificInfo ( FirmwareContextHartSpecific->MachineImplId.Value64_H; return EFI_SUCCESS; } + +/** + Print debug information of the processor specific data for a hart + + @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB +**/ +VOID +EFIAPI +DebugPrintHartSpecificInfo ( + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob + ) +{ + DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecificDataH= ob->ProcessorSpecificData.HartId.Value64_L)); + DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.BootHartId)); + DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported)); + DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecificDataHob->ProcessorSpecificData.MModeExcepDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecificDataHob->ProcessorSpecificData.MModeInterruptDelegation.Value6= 4_L)); + DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecificDat= aHob->ProcessorSpecificData.HartXlen )); + DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= ificDataHob->ProcessorSpecificData.MachineModeXlen)); + DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecificDataHob->ProcessorSpecificData.SupervisorModeXlen)); + DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecifi= cDataHob->ProcessorSpecificData.UserModeXlen)); + DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cificDataHob->ProcessorSpecificData.InstSetSupported)); + DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= ificDataHob->ProcessorSpecificData.MachineVendorId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.MachineArchId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.MachineImplId.Value64_L)); +} diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pe= i/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Boar= d/Universal/Pei/PlatformPei/Platform.c index 3d3f67d92092..6641e10f2ec3 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf= ormPei/Platform.c +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf= ormPei/Platform.c @@ -258,7 +258,7 @@ BuildCoreInformationHob ( if (EFI_ERROR (Status)) { ASSERT(FALSE); } - Status =3D CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr); + Status =3D CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr); if (EFI_ERROR (Status)) { ASSERT(FALSE); } diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Un= iversal/Pei/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU54= 0HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c index 3d3f67d92092..6641e10f2ec3 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal= /Pei/PlatformPei/Platform.c +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal= /Pei/PlatformPei/Platform.c @@ -258,7 +258,7 @@ BuildCoreInformationHob ( if (EFI_ERROR (Status)) { ASSERT(FALSE); } - Status =3D CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr); + Status =3D CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr); if (EFI_ERROR (Status)) { ASSERT(FALSE); } diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfo= Hob.c b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c index c3bb0c45128d..57c19c8187d6 100644 --- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -22,7 +22,6 @@ #include #include #include -#include #include =20 /** @@ -51,7 +50,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob ( ParentCoreGuid =3D PcdGetPtr(PcdSiFiveU5MCCoreplexGuid); MCSupport =3D PcdGetBool (PcdE5MCSupported); if (MCSupport =3D=3D TRUE) { - Status =3D CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, Uniq= ueId, HartIdNumber, FALSE, &GuidHobData); + Status =3D CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, U= niqueId, HartIdNumber, FALSE, TRUE, &GuidHobData); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\= n")); ASSERT (FALSE); @@ -60,7 +59,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob ( DEBUG ((DEBUG_INFO, "Support E5 Monitor core on U5 platform, HOB at ad= dress 0x%x\n", GuidHobData)); } for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSu= pport); HartIdNumber ++) { - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, Uniq= ueId, HartIdNumber, (HartIdNumber =3D=3D FixedPcdGet32 (PcdBootHartId))? TR= UE: FALSE, &GuidHobData); + Status =3D CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, U= niqueId, HartIdNumber, (HartIdNumber =3D=3D FixedPcdGet32 (PcdBootHartId)),= FALSE, &GuidHobData); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\= n")); ASSERT (FALSE); @@ -83,12 +82,12 @@ CreateU5MCCoreplexProcessorSpecificDataHob ( Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect this information and build SMBIOS Type4 and Type7 record. =20 - @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param ProcessorUid Unique ID of physical processor which owns this = core. @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers maintained in this structure is only valid befor= e memory is discovered. Access to those pointers after memory is install= ed will cause unexpected issues. =20 - @return EFI_SUCCESS The PEIM initialized successfully. + @return EFI_SUCCESS The SMBIOS Hobs were created successfully. =20 **/ EFI_STATUS @@ -99,10 +98,10 @@ CreateU5MCProcessorSmbiosDataHob ( ) { EFI_GUID *GuidPtr; - RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob; RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob; RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob; RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1CacheDataHobPtr; RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr; RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr; =20 @@ -112,6 +111,9 @@ CreateU5MCProcessorSmbiosDataHob ( return EFI_INVALID_PARAMETER; } =20 + CreateU54SmbiosType7L1DataHob (ProcessorUid, &L1CacheDataHobPtr); + CreateU54SmbiosType4DataHob (ProcessorUid, &ProcessorDataHobPtr); + // // Build up SMBIOS type 7 L2 cache record. // @@ -138,51 +140,12 @@ CreateU5MCProcessorSmbiosDataHob ( ASSERT (FALSE); } =20 - // - // Build up SMBIOS type 4 record. - // - ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA)); - ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MC= CoreplexGuid)); - ProcessorDataHob.ProcessorUid =3D ProcessorUid; - ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; - ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; - SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); - ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; - ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; - ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; - ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; - ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; - ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; - ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; - ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; - ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; - ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; - ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; - ProcessorDataHob.SmbiosType4Processor.CoreCount =3D (UINT8)FixedPcdGet32= (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D (UINT8)FixedP= cdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); - ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D (UINT8)FixedPcdGet= 32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); - ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; - ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; - ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); - ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA)); - if (ProcessorDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex = RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n")); - ASSERT (FALSE); - } - ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= )); SmbiosDataHob.Processor =3D ProcessorDataHobPtr; - SmbiosDataHob.L1InstCache =3D NULL; - SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L1Cache =3D L1CacheDataHobPtr; SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A)); if (SmbiosDataHobPtr =3D=3D NULL) { @@ -191,5 +154,6 @@ CreateU5MCProcessorSmbiosDataHob ( } *SmbiosHobPtr =3D SmbiosDataHobPtr; DEBUG ((DEBUG_INFO, "%a: Exit\n", __FUNCTION__)); + return EFI_SUCCESS; } diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c deleted file mode 100644 index 0f9db4012f75..000000000000 --- a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ /dev/null @@ -1,235 +0,0 @@ -/**@file - Build up platform processor information. - - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -// -// The package level header files this module uses -// -#include - -// -// The Library classes this module consumes -// -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/** - Function to build core specific information HOB. RISC-V SMBIOS DXE drive= r collect - this information and build SMBIOS Type44. - - @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid - could be the same as CoreGuid if one proc= essor has - only one core. - @param ParentProcessorUid Unique ID of pysical processor which owns= this core. - @param HartId Hart ID of this core. - @param IsBootHart TRUE means this is the boot HART. - @param GuidHobData Pointer to receive EFI_HOB_GUID_TYPE. - - @return EFI_SUCCESS The PEIM initialized successfully. - -**/ -EFI_STATUS -EFIAPI -CreateE51CoreProcessorSpecificDataHob ( - IN EFI_GUID *ParentProcessorGuid, - IN UINTN ParentProcessorUid, - IN UINTN HartId, - IN BOOLEAN IsBootHart, - OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData - ) -{ - RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob; - EFI_GUID *ProcessorSpecDataHobGuid; - RISC_V_PROCESSOR_SPECIFIC_HOB_DATA ProcessorSpecDataHob; - EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; - EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific; - - DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); - - if (GuidHobData =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - ASSERT_EFI_ERROR (SbiGetFirmwareContext (&FirmwareContext)); - DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContex= t)); - FirmwareContextHartSpecific =3D FirmwareContext->HartSpecific[HartId]; - DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", = FirmwareContextHartSpecific)); - - // - // Build up RISC_V_PROCESSOR_SPECIFIC_HOB_DATA. - // - CommonFirmwareContextHartSpecificInfo ( - FirmwareContextHartSpecific, - ParentProcessorGuid, - ParentProcessorUid, - (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid), - HartId, - IsBootHart, - &ProcessorSpecDataHob - ); - ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED; - ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED; - ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED; - ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED; - ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64; - ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64; - ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported; - ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64; - - DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L)); - DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId)); - DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported)); - DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L)); - DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L)); - DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen )); - DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen)); - DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen)); - DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen)); - DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported)); - DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L)); - DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L)); - DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L)); - - // - // Build GUID HOB for E51 core, this is for SMBIOS type 44 - // - ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid); - CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_HOB_DATA)); - if (CoreGuidHob =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n")); - ASSERT (FALSE); - } - *GuidHobData =3D CoreGuidHob; - return EFI_SUCCESS; -} - -/** - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect - this information and build SMBIOS Type4 and Type7 record. - - @param ProcessorUid Unique ID of pysical processor which owns this c= ore. - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers - maintained in this structure is only valid befor= e memory is discovered. - Access to those pointers after memory is install= ed will cause unexpected issues. - - @return EFI_SUCCESS The PEIM initialized successfully. - -**/ -EFI_STATUS -EFIAPI -CreateE51ProcessorSmbiosDataHob ( - IN UINTN ProcessorUid, - OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr - ) -{ - EFI_GUID *GuidPtr; - RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob; - RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob; - RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob; - RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr; - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr; - RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr; - - if (SmbiosHobPtr =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - // - // Build up SMBIOS type 7 L1 instruction cache record. - // - ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_= DATA)); - CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveE51CoreGuid)); - L1InstCacheDataHob.ProcessorUid =3D ProcessorUid; - L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; - L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ - RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ - RISC_V_CACHE_CONFIGURATION_ENABLED | \ - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; - L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; - L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; - L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; - L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; - L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; - L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; - L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion; - L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); - L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _HOB_DATA)); - if (L1InstCacheDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n")); - ASSERT (FALSE); - } - - // - // Build up SMBIOS type 4 record. - // - ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA)); - CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veE51CoreGuid)); - ProcessorDataHob.ProcessorUid =3D ProcessorUid; - ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; - ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; - SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); - ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; - ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; - ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; - ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; - ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; - ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; - ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D 0xffff; - ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; - ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; - ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; - ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; - ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1; - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1; - ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1; - ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; - ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; - ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); - ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA)); - if (ProcessorDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_TYPE4_HOB_DATA.\n")); - ASSERT (FALSE); - } - - ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= )); - SmbiosDataHob.Processor =3D ProcessorDataHobPtr; - SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr; - SmbiosDataHob.L1DataCache =3D NULL; - SmbiosDataHob.L2Cache =3D NULL; - SmbiosDataHob.L3Cache =3D NULL; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); - SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A)); - if (SmbiosDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_SMBIOS_HOB_DATA.\n")); - ASSERT (FALSE); - } - *SmbiosHobPtr =3D SmbiosDataHobPtr; - return EFI_SUCCESS; -} - - diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c index 70ac13326216..d013638f58ed 100644 --- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -1,7 +1,7 @@ /**@file - Build up platform processor information. + Build up platform processor information of SiFive U54 core. =20 - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -9,11 +9,6 @@ =20 #include =20 -// -// The package level header files this module uses -// -#include - // // The Library classes this module consumes // @@ -21,35 +16,38 @@ #include #include #include +#include #include + +#include #include #include #include -#include -#include =20 /** - Function to build core specific information HOB. + Function to build core specific information HOB for U54 or E51 core. =20 - @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + @param ParentProcessorGuid Parent processor of this core. ParentProc= essorGuid could be the same as CoreGuid if one proc= essor has only one core. @param ParentProcessorUid Unique ID of pysical processor which owns= this core. @param HartId Hart ID of this core. @param IsBootHart TRUE means this is the boot HART. - @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_= DATA. + @param IsManagementCore TRUE means this is for the E51 management= core, not U54 + @param GuidHobData Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_= DATA. =20 @return EFI_SUCCESS The PEIM initialized successfully. =20 **/ EFI_STATUS EFIAPI -CreateU54CoreProcessorSpecificDataHob ( +CreateU54E51CoreProcessorSpecificDataHob ( IN EFI_GUID *ParentProcessorGuid, IN UINTN ParentProcessorUid, IN UINTN HartId, IN BOOLEAN IsBootHart, - OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobdata + IN BOOLEAN IsManagementCore, + OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData ) { RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob; @@ -60,7 +58,7 @@ CreateU54CoreProcessorSpecificDataHob ( =20 DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); =20 - if (GuidHobdata =3D=3D NULL) { + if (GuidHobData =3D=3D NULL) { return EFI_INVALID_PARAMETER; } =20 @@ -81,159 +79,112 @@ CreateU54CoreProcessorSpecificDataHob ( IsBootHart, &ProcessorSpecDataHob ); + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED; ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED; ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED; ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED; ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64; ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64; - ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported; ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64; =20 - DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L)); - DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId)); - DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported)); - DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L)); - DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L)); - DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen )); - DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen)); - DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen)); - DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen)); - DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported)); - DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L)); - DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L)); - DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L)); + if (IsManagementCore) { + // Configuration for E51 + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = =3D RegisterUnsupported; + } else { + // Configuration for U54 + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = =3D RegisterLen64; + } + + + DebugPrintHartSpecificInfo (&ProcessorSpecDataHob); =20 // - // Build GUID HOB for U54 core. + // Build GUID HOB for core, this is for SMBIOS type 44 // ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid); CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_HOB_DATA)); if (CoreGuidHob =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n")); + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core.\n")); ASSERT (FALSE); } - *GuidHobdata =3D CoreGuidHob; + *GuidHobData =3D CoreGuidHob; return EFI_SUCCESS; } =20 /** - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect - this information and build SMBIOS Type4 and Type7 record. + Function to build cache related SMBIOS information. RISC-V SMBIOS DXE dr= iver collects + this information and builds SMBIOS Type 7 record. =20 - @param ProcessorUid Unique ID of pysical processor which owns this c= ore. - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers - maintained in this structure is only valid befor= e memory is discovered. - Access to those pointers after memory is install= ed will cause unexpected issues. + The caller can adjust the allocated hob data to their needs. =20 - @return EFI_SUCCESS The PEIM initialized successfully. + @param ProcessorUid Unique ID of physical processor which owns thi= s core. + @param L1CacheDataHobPtr Pointer to allocated HOB data. =20 **/ -EFI_STATUS +VOID EFIAPI -CreateU54ProcessorSmbiosDataHob ( +CreateU54SmbiosType7L1DataHob ( IN UINTN ProcessorUid, - IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr + OUT RISC_V_PROCESSOR_TYPE7_HOB_DATA **L1CacheDataHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE7_HOB_DATA L1CacheDataHob; + + // + // Build up SMBIOS type 7 L1 cache record. + // + ZeroMem((VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA= )); + L1CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCo= replexGuid)); + L1CacheDataHob.ProcessorUid =3D ProcessorUid; + L1CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; + L1CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_1 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L1CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; + L1CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; + L1CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L1CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L1CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; + L1CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; + L1CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; + L1CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; + + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + *L1CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataH= ob (GuidPtr, (VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DA= TA)); + if (L1CacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex= L1 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n")); + ASSERT (FALSE); + } +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collects + this information and builds SMBIOS Type 4 record. + + The caller can adjust the allocated hob data to their needs. + + @param ProcessorUid Unique ID of physical processor which owns thi= s core. + @param ProcessorDataHobPtr Pointer to allocated HOB data. + +**/ +VOID +EFIAPI +CreateU54SmbiosType4DataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_TYPE4_HOB_DATA **ProcessorDataHobPtr ) { EFI_GUID *GuidPtr; RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob; - RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob; - RISC_V_PROCESSOR_TYPE7_HOB_DATA L1DataCacheDataHob; - RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob; - RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob; - RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr; - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr; - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCacheDataHobPtr; - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr; - RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr; - - if (SmbiosHobPtr =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - // - // Build up SMBIOS type 7 L1 instruction cache record. - // - ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_= DATA)); - CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveU54CoreGuid)); - L1InstCacheDataHob.ProcessorUid =3D ProcessorUid; - L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; - L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ - RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ - RISC_V_CACHE_CONFIGURATION_ENABLED | \ - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; - L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; - L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; - L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; - L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; - L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; - L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; - L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion; - L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); - L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _HOB_DATA)); - if (L1InstCacheDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n")); - ASSERT (FALSE); - } - - // - // Build up SMBIOS type 7 L1 data cache record. - // - ZeroMem((VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_= DATA)); - CopyGuid (&L1DataCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveU54CoreGuid)); - L1DataCacheDataHob.ProcessorUid =3D ProcessorUid; - L1DataCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; - L1DataCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ - RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ - RISC_V_CACHE_CONFIGURATION_ENABLED | \ - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; - L1DataCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; - L1DataCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; - L1DataCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; - L1DataCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; - L1DataCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; - L1DataCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; - L1DataCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeData; - L1DataCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); - L1DataCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _HOB_DATA)); - if (L1DataCacheDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 da= ta cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n")); - ASSERT (FALSE); - } - - // - // Build up SMBIOS type 7 L2 cache record. - // - ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA= )); - CopyGuid (&L2CacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFive= U54CoreGuid)); - L2CacheDataHob.ProcessorUid =3D ProcessorUid; - L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; - L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ - RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ - RISC_V_CACHE_CONFIGURATION_ENABLED | \ - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; - L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; - L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; - L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; - L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; - L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; - L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; - L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; - L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); - L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DAT= A)); - if (L2CacheDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L2 ca= che RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n")); - ASSERT (FALSE); - } =20 // // Build up SMBIOS type 4 record. // ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA)); - CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veU54CoreGuid)); + ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MC= CoreplexGuid)); ProcessorDataHob.ProcessorUid =3D ProcessorUid; ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; @@ -253,34 +204,19 @@ CreateU54ProcessorSmbiosDataHob ( ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; - ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1; - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1; - ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D (UINT8)FixedPcdGet32= (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D (UINT8)FixedP= cdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D (UINT8)FixedPcdGet= 32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); - ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA)); + *ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDat= aHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HO= B_DATA)); if (ProcessorDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_= V_PROCESSOR_TYPE4_HOB_DATA.\n")); + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex = RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n")); ASSERT (FALSE); } - - ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= )); - SmbiosDataHob.Processor =3D ProcessorDataHobPtr; - SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr; - SmbiosDataHob.L1DataCache =3D L1DataCacheDataHobPtr; - SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; - SmbiosDataHob.L3Cache =3D NULL; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); - SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A)); - if (SmbiosDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_= V_PROCESSOR_SMBIOS_HOB_DATA.\n")); - ASSERT (FALSE); - } - *SmbiosHobPtr =3D SmbiosDataHobPtr; - return EFI_SUCCESS; } - diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInf= oHob.c b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob= .c deleted file mode 100644 index 97bed2ac8d27..000000000000 --- a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ /dev/null @@ -1,184 +0,0 @@ -/**@file - Build up platform processor information. - - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -// -// The package level header files this module uses -// -#include - -// -// The Library classes this module consumes -// -#include -#include -#include -#include -#include -#include - -/** - Build up processor-specific HOB for U54MC Coreplex - - @param UniqueId Unique ID of this U54MC Coreplex processor - - @return EFI_SUCCESS The PEIM initialized successfully. - -**/ -EFI_STATUS -EFIAPI -CreateU54MCCoreplexProcessorSpecificDataHob ( - IN UINTN UniqueId - ) -{ - EFI_STATUS Status; - RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ThisGuidHobData; - EFI_GUID *ParentProcessorGuid; - - DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); - - ParentProcessorGuid =3D PcdGetPtr (PcdSiFiveU54MCCoreplexGuid); - Status =3D CreateE51CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54MC_COREPLEX_E51_HART_ID, FALSE, &ThisGuidHobData); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "%a: Faile to build E51 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); - return Status; - } - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_0_HART_ID, TRUE, &ThisGuidHobData); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); - return Status; - } - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_1_HART_ID, FALSE, &ThisGuidHobData); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); - return Status; - } - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_2_HART_ID, FALSE, &ThisGuidHobData); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); - return Status; - } - Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_3_HART_ID, FALSE, &ThisGuidHobData); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); - return Status; - } - return Status; -} - -/** - Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect - this information and build SMBIOS Type4 and Type7 record. - - @param ProcessorUid Unique ID of pysical processor which owns this c= ore. - @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_D= ATA. The pointers - maintained in this structure is only valid befor= e memory is discovered. - Access to those pointers after memory is install= ed will cause unexpected issues. - - @return EFI_SUCCESS The PEIM initialized successfully. - -**/ -EFI_STATUS -EFIAPI -CreateU54MCProcessorSmbiosDataHob ( - IN UINTN ProcessorUid, - IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr - ) -{ - EFI_GUID *GuidPtr; - RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob; - RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob; - RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob; - RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr; - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr; - RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr; - - if (SmbiosHobPtr =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - // - // Build up SMBIOS type 7 L2 cache record. - // - ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA= )); - L2CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCC= oreplexGuid)); - L2CacheDataHob.ProcessorUid =3D ProcessorUid; - L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; - L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ - RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ - RISC_V_CACHE_CONFIGURATION_ENABLED | \ - RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; - L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; - L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; - L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; - L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; - L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; - L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; - L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; - L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); - L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DAT= A)); - if (L2CacheDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n")); - ASSERT (FALSE); - } - - // - // Build up SMBIOS type 4 record. - // - ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DA= TA)); - ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54M= CCoreplexGuid)); - ProcessorDataHob.ProcessorUid =3D ProcessorUid; - ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; - ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; - SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); - ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; - ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; - ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; - ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; - ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; - ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; - ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; - ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; - ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; - ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; - ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; - ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; - ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 5; - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 5; - ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 5; - ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable - ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; - ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; - ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; - ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); - ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB= _DATA)); - if (ProcessorDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n")); - ASSERT (FALSE); - } - - ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA= )); - SmbiosDataHob.Processor =3D ProcessorDataHobPtr; - SmbiosDataHob.L1InstCache =3D NULL; - SmbiosDataHob.L1DataCache =3D NULL; - SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; - SmbiosDataHob.L3Cache =3D NULL; - GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); - SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DAT= A)); - if (SmbiosDataHobPtr =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54MC Coreplex= RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n")); - ASSERT (FALSE); - } - *SmbiosHobPtr =3D SmbiosDataHobPtr; - return EFI_SUCCESS; -} --=20 2.28.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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