From nobody Sat Apr 20 06:18:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+63429+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63429+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1595993657; cv=none; d=zohomail.com; s=zohoarc; b=V3TXjNofnB1c8u7rzGDlmYXfD2SHl9Lhdf6mHjQ95lPtjphzlbDyUfxiMWQFAFsci60s4a/FIIg4M+j/symPegCUVik3gX5okSGy9cZBiCJIjmHJgHRI5YKqfJ5Qdr07BdJIJGf9eKEoXH8/kAEzRuroRqaICAZM5bo5ItRuc8Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595993657; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=mwlBCy8Yn0J+zW+wyGAO3ytWM6MNT2pC43/cWnuBh/c=; b=C5szMPhgx+yWrX6LyiZ8EdkSMSIUCs1OHIWHFWeUiEJ/IJbwt77Bcwl+TLZyqarQ6GJaDEGV4+x0E9MuG+sQa8LjwtU3Ah4og445i21OkYFX/8v3IDWsJy3FCq3dh9lSBlBgTvBqyCSakiuGU0ZtAtmTTCKh/XOaawgOVyVminU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63429+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1595993657091879.184617927186; Tue, 28 Jul 2020 20:34:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id YkZCYY1788612xqO1vwUUKsd; Tue, 28 Jul 2020 20:34:16 -0700 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web12.5445.1595993655671144489 for ; Tue, 28 Jul 2020 20:34:15 -0700 IronPort-SDR: NmCi+Rd3aAzVSySqfYOhJoQ/AFCoHVAYsl5Rs8KDoW6bK8o0ssRJyVt1iTKA9J77cC+3C9iLTX uKWW3J+tTXTg== X-IronPort-AV: E=McAfee;i="6000,8403,9696"; a="138881606" X-IronPort-AV: E=Sophos;i="5.75,408,1589266800"; d="scan'208";a="138881606" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2020 20:34:14 -0700 IronPort-SDR: 63e6yTcepRDrP9WPDrq9vHanWvf55W86BT5c1Pk+NL+86qq4EWTzqIgOXTgrPIyqhLg1hGDy/G Cmj52oDHxBSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,408,1589266800"; d="scan'208";a="273770955" X-Received: from shenglei-dev.ccr.corp.intel.com ([10.239.154.36]) by fmsmga008.fm.intel.com with ESMTP; 28 Jul 2020 20:34:13 -0700 From: "Zhang, Shenglei" To: devel@edk2.groups.io Cc: Agyeman Prince Subject: [edk2-devel] [PATCH] SimicsOpenBoardPkg: Update usage of functions to be removed Date: Wed, 29 Jul 2020 11:34:07 +0800 Message-Id: <20200729033407.2120-1-shenglei.zhang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,shenglei.zhang@intel.com X-Gm-Message-State: FotwDU9o84PAnW2M2Kzjrwwox1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1595993656; bh=pkSS9aemb1pkolppK3D8g29TYB2j1WHNyKP+eO4AQu0=; h=Cc:Date:From:Reply-To:Subject:To; b=lltYeWfjukRIdGFl5amBsY+PtmO4yWBehyjTDV2kHpWS6E8df9YgznkBpb/s8tqYbK7 UcxEnC5vZh2D/bBieAnFDdhhDfsJu5qFzL/rrjt3R1gqshbTJezAJOn8XdZYCw4DukaVN lb+EAqe9EVL0PE4N7ymEvgYe+GdjG7qWC+k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2777 With some functions to be deprecated, their usage in platforms should also be updated. Cc: Agyeman Prince Signed-off-by: Shenglei Zhang Reviewed-by: Prince Agyeman --- .../Library/BoardBdsHookLib/BoardBdsHookLib.c | 2 +- .../Intel/SimicsOpenBoardPkg/SimicsDxe/Platform.c | 4 ++-- .../Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c | 6 +++--- .../Intel/SimicsOpenBoardPkg/SimicsPei/Platform.c | 12 ++++++------ 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/BoardBdsHookLib/Boar= dBdsHookLib.c b/Platform/Intel/SimicsOpenBoardPkg/Library/BoardBdsHookLib/B= oardBdsHookLib.c index 1058dbf3..ba4d2b02 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/Library/BoardBdsHookLib/BoardBdsHoo= kLib.c +++ b/Platform/Intel/SimicsOpenBoardPkg/Library/BoardBdsHookLib/BoardBdsHoo= kLib.c @@ -1206,7 +1206,7 @@ VisitingFileSystemInstance ( NULL, &mEmuVariableEventReg ); - PcdSet64 (PcdEmuVariableEvent, (UINT64)(UINTN) mEmuVariableEvent); + PcdSet64S (PcdEmuVariableEvent, (UINT64)(UINTN) mEmuVariableEvent); =20 return EFI_SUCCESS; } diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsDxe/Platform.c b/Platf= orm/Intel/SimicsOpenBoardPkg/SimicsDxe/Platform.c index b7fd4d1f..c856ff44 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsDxe/Platform.c +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsDxe/Platform.c @@ -669,9 +669,9 @@ ExecutePlatformConfig ( // // Pass the preferred resolution to GraphicsConsoleDxe via dynamic PCD= s. // - PcdSet32 (PcdVideoHorizontalResolution, + PcdSet32S (PcdVideoHorizontalResolution, PlatformConfig.HorizontalResolution); - PcdSet32 (PcdVideoVerticalResolution, + PcdSet32S (PcdVideoVerticalResolution, PlatformConfig.VerticalResolution); } =20 diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c b/Plat= form/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c index 60aa54be..127afffc 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c @@ -155,7 +155,7 @@ GetFirstNonAddress ( if (mBootMode !=3D BOOT_ON_S3_RESUME) { DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n", __FUNCTION__)); - PcdSet64 (PcdPciMmio64Size, 0); + PcdSet64S (PcdPciMmio64Size, 0); } =20 // @@ -187,8 +187,8 @@ GetFirstNonAddress ( // the GCD memory space map through our PciHostBridgeLib instance; her= e we // only need to set the PCDs. // - PcdSet64 (PcdPciMmio64Base, Pci64Base); - PcdSet64 (PcdPciMmio64Size, Pci64Size); + PcdSet64S (PcdPciMmio64Base, Pci64Base); + PcdSet64S (PcdPciMmio64Size, Pci64Size); DEBUG ((EFI_D_INFO, "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n", __FUNCTION__, Pci64Base, Pci64Size)); } diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/Platform.c b/Platf= orm/Intel/SimicsOpenBoardPkg/SimicsPei/Platform.c index 0bec76e4..6963f39a 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/Platform.c +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/Platform.c @@ -257,8 +257,8 @@ MemMapInitialization ( // PciSize =3D 0xFC000000 - PciBase; AddIoMemoryBaseSizeHob (PciBase, PciSize); - PcdSet64 (PcdPciMmio32Base, PciBase); - PcdSet64 (PcdPciMmio32Size, PciSize); + PcdSet64S (PcdPciMmio32Base, PciBase); + PcdSet64S (PcdPciMmio32Size, PciSize); AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); if (mHostBridgeDevId =3D=3D INTEL_ICH10_DEVICE_ID) { @@ -300,8 +300,8 @@ MemMapInitialization ( PciIoBase, PciIoSize ); - PcdSet64 (PcdPciIoBase, PciIoBase); - PcdSet64 (PcdPciIoSize, PciIoSize); + PcdSet64S (PcdPciIoBase, PciIoBase); + PcdSet64S (PcdPciIoSize, PciIoSize); =20 // // Add flash range. @@ -367,7 +367,7 @@ MiscInitialization ( ASSERT (FALSE); return; } - PcdSet16 (PcdSimicsX58HostBridgePciDevId, mHostBridgeDevId); + PcdSet16S (PcdSimicsX58HostBridgePciDevId, mHostBridgeDevId); =20 // // If the appropriate IOspace enable bit is set, assume the ACPI PMBA @@ -483,7 +483,7 @@ ReserveEmuVariableNvStore ( VariableStore, (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024 )); - PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore); + PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore); } =20 =20 --=20 2.18.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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