From nobody Tue Apr 16 18:32:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+63119+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63119+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1595431339; cv=none; d=zohomail.com; s=zohoarc; b=DnPkIvTxkjV8Ot5wzYmgu4TW1t7ijeaFv0oMZ8+q9ZnWtWim0f0clHubK7mCuSCyxS2YWbgcxTt8uBoRIMDh7Kfp+nKVIy42Y2fEhsuuqZSQ3iqxXL0RBSNDgu2Ipvkm9Yi2auPVRsKp0envR83ZnNsSPRDE5zOEia6zYbvEKCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595431339; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=lIdiJeo/5U/bqyo0I4zSFvYoMPNt0khK5nx80Y5DToI=; b=iuEqAEsLEIqMM1kT8hqQkNUSh7iY+Zt9HaYSeSm/7AncVuJUQzTwU4b13Tr9Qe8BLQiyBrMrYuGSLN9SRS+zSoQVdb1tsuq7dqrAQkN4uJFv/7/l5rGQtJWvMuBmadmpg4zK6t3LC7ETpmy7QozPInGOEAH92Tn79y09pmnPyXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63119+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1595431339845978.240637562105; Wed, 22 Jul 2020 08:22:19 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id bTH4YY1788612xhHrC9p6JXm; Wed, 22 Jul 2020 08:22:19 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web11.21108.1595431337293498863 for ; Wed, 22 Jul 2020 08:22:19 -0700 IronPort-SDR: Jq18qIdzepLDyyA92XCRCSfrtaoa7u8TVmYnJWsNCq1gHSEHXNJCaaXJth1qY/V1ZGHmyev7yP hDEMxy4fCpVQ== X-IronPort-AV: E=McAfee;i="6000,8403,9690"; a="235214659" X-IronPort-AV: E=Sophos;i="5.75,383,1589266800"; d="scan'208";a="235214659" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2020 08:22:18 -0700 IronPort-SDR: 3OvyrfOegkcrMXRUup3koZq7MGV3C1tUmcq6duxcl46C4Nm0qQjr8S/BUETTwqZaev1ccJ+kcc yHhEsRy7qU+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,383,1589266800"; d="scan'208";a="270775040" X-Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 22 Jul 2020 08:22:16 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1 Registers Date: Wed, 22 Jul 2020 20:51:38 +0530 Message-Id: <20200722152139.16496-2-ashraf.javeed@intel.com> In-Reply-To: <20200722152139.16496-1-ashraf.javeed@intel.com> References: <20200722152139.16496-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: oiDTBmCOA6HNQR9cMukIvYUyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1595431339; bh=+sTTjh4IkvDh/y3a0Pc6Jw/ClaVpsqmsLbS5vDF3uO0=; h=Cc:Date:From:Reply-To:Subject:To; b=tvHpQyC3w86v6n0ttesH74NnrB8QgoZQIkZqhIWzSYSym4HofbnKseqbkI2998trRuA T5AEjzHcMQWrzT+6wwrIMcQI8swWQWyrbN22zHhiRfv+GL88/QTcUPdb2DUXORdpZq/r7 hQ9F2yhw2233EjPCMI08zCVqlfSmP/GOvdo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2611 Register definitions from chapter 7 of Compute Express Link Specification Revision 1.1 are ported into the new Cxl11.h. The CXL Flex Bus registers are based on the PCIe Extended Capability DVSEC structure header, led to the inclusion of upgraded Pci.h. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao -- V2: Indentation and double declaration fix, copyright date update V3: Copyright date fix Reviewed-by: Michael D Kinney --- MdePkg/Include/IndustryStandard/Cxl11.h | 569 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++ MdePkg/Include/IndustryStandard/Pci.h | 6 ++---- 2 files changed, 571 insertions(+), 4 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/Cxl11.h b/MdePkg/Include/Indus= tryStandard/Cxl11.h new file mode 100644 index 0000000000..a261bb3fae --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl11.h @@ -0,0 +1,569 @@ +/** @file + CXL 1.1 Register definitions + + This file contains the register definitions based on the Compute Express= Link + (CXL) Specification Revision 1.1. + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CXL11_H_ +#define _CXL11_H_ + +#include +// +// DVSEC Vendor ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Tabl= e 58 +// (subject to change as per CXL assigned Vendor ID) +// +#define INTEL_CXL_DVSEC_VENDOR_ID 0x= 8086 + +// +// CXL Flex Bus Device default device and function number +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 +// +#define CXL_DEV_DEV 0 +#define CXL_DEV_FUNC 0 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// The PCIe DVSEC for Flex Bus Device +///@{ +typedef union { + struct { + UINT16 CacheCapable : 1; // bi= t 0 + UINT16 IoCapable : 1; // bi= t 1 + UINT16 MemCapable : 1; // bi= t 2 + UINT16 MemHwInitMode : 1; // bi= t 3 + UINT16 HdmCount : 2; // bi= t 4..5 + UINT16 Reserved1 : 8; // bi= t 6..13 + UINT16 ViralCapable : 1; // bi= t 14 + UINT16 Reserved2 : 1; // bi= t 15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bi= t 0 + UINT16 IoEnable : 1; // bi= t 1 + UINT16 MemEnable : 1; // bi= t 2 + UINT16 CacheSfCoverage : 5; // bi= t 3..7 + UINT16 CacheSfGranularity : 3; // bi= t 8..10 + UINT16 CacheCleanEviction : 1; // bi= t 11 + UINT16 Reserved1 : 2; // bi= t 12..13 + UINT16 ViralEnable : 1; // bi= t 14 + UINT16 Reserved2 : 1; // bi= t 15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL; + +typedef union { + struct { + UINT16 Reserved1 : 14; // b= it 0..13 + UINT16 ViralStatus : 1; // b= it 14 + UINT16 Reserved2 : 1; // b= it 15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS; + +typedef union { + struct { + UINT16 Reserved1 : 1; // b= it 0 + UINT16 Reserved2 : 1; // b= it 1 + UINT16 Reserved3 : 1; // b= it 2 + UINT16 Reserved4 : 13; // b= it 3..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2; + +typedef union { + struct { + UINT16 Reserved1 : 1; // b= it 0 + UINT16 Reserved2 : 1; // b= it 1 + UINT16 Reserved3 : 14; // b= it 2..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2; + +typedef union { + struct { + UINT16 ConfigLock : 1; // b= it 0 + UINT16 Reserved1 : 15; // b= it 1..15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK; + +typedef union { + struct { + UINT32 MemorySizeHigh : 32; // b= it 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH; + +typedef union { + struct { + UINT32 MemoryInfoValid : 1; // b= it 0 + UINT32 MemoryActive : 1; // b= it 1 + UINT32 MediaType : 3; // b= it 2..4 + UINT32 MemoryClass : 3; // b= it 5..7 + UINT32 DesiredInterleave : 3; // b= it 8..10 + UINT32 Reserved : 17; // b= it 11..27 + UINT32 MemorySizeLow : 4; // b= it 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW; + +typedef union { + struct { + UINT32 MemoryBaseHigh : 32; // b= it 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH; + +typedef union { + struct { + UINT32 Reserved : 28; // b= it 0..27 + UINT32 MemoryBaseLow : 4; // b= it 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW; + + +typedef union { + struct { + UINT32 MemorySizeHigh : 32; // b= it 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH; + +typedef union { + struct { + UINT32 MemoryInfoValid : 1; // b= it 0 + UINT32 MemoryActive : 1; // b= it 1 + UINT32 MediaType : 3; // b= it 2..4 + UINT32 MemoryClass : 3; // b= it 5..7 + UINT32 DesiredInterleave : 3; // b= it 8..10 + UINT32 Reserved : 17; // b= it 11..27 + UINT32 MemorySizeLow : 4; // b= it 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW; + +typedef union { + struct { + UINT32 MemoryBaseHigh : 32; // b= it 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH; + +typedef union { + struct { + UINT32 Reserved : 28; // b= it 0..27 + UINT32 MemoryBaseLow : 4; // b= it 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW; + +// +// Flex Bus Device DVSEC ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table= 58 +// +#define FLEX_BUS_DEVICE_DVSEC_ID 0 + +// +// PCIe DVSEC for Flex Bus Device +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figur= e 95 +// +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; = // offset 0 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 Designated= VendorSpecificHeader1; // offset 4 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 Designated= VendorSpecificHeader2; // offset 8 + CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapa= bility; // offset 10 + CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceCont= rol; // offset 12 + CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStat= us; // offset 14 + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceCont= rol2; // offset 16 + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStat= us2; // offset 18 + CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock= ; // offset 20 + UINT16 Reserved; = // offset 22 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRang= e1SizeHigh; // offset 24 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRang= e1SizeLow; // offset 28 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRang= e1BaseHigh; // offset 32 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRang= e1BaseLow; // offset 36 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRang= e2SizeHigh; // offset 40 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRang= e2SizeLow; // offset 44 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRang= e2BaseHigh; // offset 48 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRang= e2BaseLow; // offset 52 +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE; +///@} + +/// +/// PCIe DVSEC for FLex Bus Port +///@{ +typedef union { + struct { + UINT16 CacheCapable : 1; // b= it 0 + UINT16 IoCapable : 1; // b= it 1 + UINT16 MemCapable : 1; // b= it 2 + UINT16 Reserved : 13; // b= it 3..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bi= t 0 + UINT16 IoEnable : 1; // bi= t 1 + UINT16 MemEnable : 1; // bi= t 2 + UINT16 CxlSyncBypassEnable : 1; // bi= t 3 + UINT16 DriftBufferEnable : 1; // bi= t 4 + UINT16 Reserved : 3; // bi= t 5..7 + UINT16 Retimer1Present : 1; // bi= t 8 + UINT16 Retimer2Present : 1; // bi= t 9 + UINT16 Reserved2 : 6; // bi= t 10..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bi= t 0 + UINT16 IoEnable : 1; // bi= t 1 + UINT16 MemEnable : 1; // bi= t 2 + UINT16 CxlSyncBypassEnable : 1; // bi= t 3 + UINT16 DriftBufferEnable : 1; // bi= t 4 + UINT16 Reserved : 3; // bi= t 5..7 + UINT16 CxlCorrectableProtocolIdFramingError : 1; // bi= t 8 + UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bi= t 9 + UINT16 CxlUnexpectedProtocolIdDropped : 1; // bi= t 10 + UINT16 Reserved2 : 5; // bi= t 11..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS; + +// +// Flex Bus Port DVSEC ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Tab= le 62 +// +#define FLEX_BUS_PORT_DVSEC_ID 7 + +// +// PCIe DVSEC for Flex Bus Port +// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Fig= ure 99 +// +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; = // offset 0 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 Designated= VendorSpecificHeader1; // offset 4 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 Designated= VendorSpecificHeader2; // offset 8 + CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapabi= lity; // offset 10 + CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortContro= l; // offset 12 + CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus= ; // offset 14 +} CXL_1_1_DVSEC_FLEX_BUS_PORT; +///@} + +/// +/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers +/// + +/// The CXL.Cache and CXL.Memory Architectural register definitions +/// Based on chapter 7.2.2 of Compute Express Link Specification Revision:= 1.1 +///@{ + +#define CXL_CAPABILITY_HEADER_OFFSET 0 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // b= it 0..15 + UINT32 CxlCapabilityVersion : 4; // b= it 16..19 + UINT32 CxlCacheMemVersion : 4; // b= it 20..23 + UINT32 ArraySize : 8; // b= it 24..31 + } Bits; + UINT32 Uint32; +} CXL_CAPABILITY_HEADER; + +#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // b= it 0..15 + UINT32 CxlCapabilityVersion : 4; // b= it 16..19 + UINT32 CxlRasCapabilityPointer : 12; // b= it 20..31 + } Bits; + UINT32 Uint32; +} CXL_RAS_CAPABILITY_HEADER; + +#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // b= it 0..15 + UINT32 CxlCapabilityVersion : 4; // b= it 16..19 + UINT32 CxlSecurityCapabilityPointer : 12; // b= it 20..31 + } Bits; + UINT32 Uint32; +} CXL_SECURITY_CAPABILITY_HEADER; + +#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // b= it 0..15 + UINT32 CxlCapabilityVersion : 4; // b= it 16..19 + UINT32 CxlLinkCapabilityPointer : 12; // b= it 20..31 + } Bits; + UINT32 Uint32; +} CXL_LINK_CAPABILITY_HEADER; + +typedef union { + struct { + UINT32 CacheDataParity : 1; // b= it 0..0 + UINT32 CacheAddressParity : 1; // b= it 1..1 + UINT32 CacheByteEnableParity : 1; // b= it 2..2 + UINT32 CacheDataEcc : 1; // b= it 3..3 + UINT32 MemDataParity : 1; // b= it 4..4 + UINT32 MemAddressParity : 1; // b= it 5..5 + UINT32 MemByteEnableParity : 1; // b= it 6..6 + UINT32 MemDataEcc : 1; // b= it 7..7 + UINT32 ReInitThreshold : 1; // b= it 8..8 + UINT32 RsvdEncodingViolation : 1; // b= it 9..9 + UINT32 PoisonReceived : 1; // b= it 10..10 + UINT32 ReceiverOverflow : 1; // b= it 11..11 + UINT32 Reserved : 20; // b= it 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_STATUS; + +typedef union { + struct { + UINT32 CacheDataParityMask : 1; // b= it 0..0 + UINT32 CacheAddressParityMask : 1; // b= it 1..1 + UINT32 CacheByteEnableParityMask : 1; // b= it 2..2 + UINT32 CacheDataEccMask : 1; // b= it 3..3 + UINT32 MemDataParityMask : 1; // b= it 4..4 + UINT32 MemAddressParityMask : 1; // b= it 5..5 + UINT32 MemByteEnableParityMask : 1; // b= it 6..6 + UINT32 MemDataEccMask : 1; // b= it 7..7 + UINT32 ReInitThresholdMask : 1; // b= it 8..8 + UINT32 RsvdEncodingViolationMask : 1; // b= it 9..9 + UINT32 PoisonReceivedMask : 1; // b= it 10..10 + UINT32 ReceiverOverflowMask : 1; // b= it 11..11 + UINT32 Reserved : 20; // b= it 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_MASK; + +typedef union { + struct { + UINT32 CacheDataParitySeverity : 1; // b= it 0..0 + UINT32 CacheAddressParitySeverity : 1; // b= it 1..1 + UINT32 CacheByteEnableParitySeverity : 1; // b= it 2..2 + UINT32 CacheDataEccSeverity : 1; // b= it 3..3 + UINT32 MemDataParitySeverity : 1; // b= it 4..4 + UINT32 MemAddressParitySeverity : 1; // b= it 5..5 + UINT32 MemByteEnableParitySeverity : 1; // b= it 6..6 + UINT32 MemDataEccSeverity : 1; // b= it 7..7 + UINT32 ReInitThresholdSeverity : 1; // b= it 8..8 + UINT32 RsvdEncodingViolationSeverity : 1; // b= it 9..9 + UINT32 PoisonReceivedSeverity : 1; // b= it 10..10 + UINT32 ReceiverOverflowSeverity : 1; // b= it 11..11 + UINT32 Reserved : 20; // b= it 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY; + +typedef union { + struct { + UINT32 CacheDataEcc : 1; // b= it 0..0 + UINT32 MemoryDataEcc : 1; // b= it 1..1 + UINT32 CrcThreshold : 1; // b= it 2..2 + UINT32 RetryThreshold : 1; // b= it 3..3 + UINT32 CachePoisonReceived : 1; // b= it 4..4 + UINT32 MemoryPoisonReceived : 1; // b= it 5..5 + UINT32 PhysicalLayerError : 1; // b= it 6..6 + UINT32 Reserved : 25; // b= it 7..31 + } Bits; + UINT32 Uint32; +} CXL_CORRECTABLE_ERROR_STATUS; + +typedef union { + struct { + UINT32 CacheDataEccMask : 1; // b= it 0..0 + UINT32 MemoryDataEccMask : 1; // b= it 1..1 + UINT32 CrcThresholdMask : 1; // b= it 2..2 + UINT32 RetryThresholdMask : 1; // b= it 3..3 + UINT32 CachePoisonReceivedMask : 1; // b= it 4..4 + UINT32 MemoryPoisonReceivedMask : 1; // b= it 5..5 + UINT32 PhysicalLayerErrorMask : 1; // b= it 6..6 + UINT32 Reserved : 25; // b= it 7..31 + } Bits; + UINT32 Uint32; +} CXL_CORRECTABLE_ERROR_MASK; + +typedef union { + struct { + UINT32 FirstErrorPointer : 4; // b= it 0..3 + UINT32 Reserved1 : 5; // b= it 4..8 + UINT32 MultipleHeaderRecordingCapability : 1; // b= it 9..9 + UINT32 Reserved2 : 3; // b= it 10..12 + UINT32 PoisonEnabled : 1; // b= it 13..13 + UINT32 Reserved3 : 18; // b= it 14..31 + } Bits; + UINT32 Uint32; +} CXL_ERROR_CAPABILITIES_AND_CONTROL; + +typedef struct { + CXL_1_1_UNCORRECTABLE_ERROR_STATUS Uncorrecta= bleErrorStatus; + CXL_1_1_UNCORRECTABLE_ERROR_MASK Uncorrecta= bleErrorMask; + CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY Uncorrecta= bleErrorSeverity; + CXL_CORRECTABLE_ERROR_STATUS Correctabl= eErrorStatus; + CXL_CORRECTABLE_ERROR_MASK Correctabl= eErrorMask; + CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapab= ilitiesAndControl; + UINT32 HeaderLog[= 16]; +} CXL_1_1_RAS_CAPABILITY_STRUCTURE; + +typedef union { + struct { + UINT32 DeviceTrustLevel : 2; // b= it 0..1 + UINT32 Reserved : 30; // b= it 2..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_SECURITY_POLICY; + +typedef struct { + CXL_1_1_SECURITY_POLICY SecurityPo= licy; +} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE; + +typedef union { + struct { + UINT64 CxlLinkVersionSupported : 4; // b= it 0..3 + UINT64 CxlLinkVersionReceived : 4; // b= it 4..7 + UINT64 LlrWrapValueSupported : 8; // b= it 8..15 + UINT64 LlrWrapValueReceived : 8; // b= it 16..23 + UINT64 NumRetryReceived : 5; // b= it 24..28 + UINT64 NumPhyReinitReceived : 5; // b= it 29..33 + UINT64 WrPtrReceived : 8; // b= it 34..41 + UINT64 EchoEseqReceived : 8; // b= it 42..49 + UINT64 NumFreeBufReceived : 8; // b= it 50..57 + UINT64 Reserved : 6; // b= it 58..63 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_CAPABILITY; + +typedef union { + struct { + UINT16 LlReset : 1; // b= it 0..0 + UINT16 LlInitStall : 1; // b= it 1..1 + UINT16 LlCrdStall : 1; // b= it 2..2 + UINT16 InitState : 2; // b= it 3..4 + UINT16 LlRetryBufferConsumed : 8; // b= it 5..12 + UINT16 Reserved : 3; // b= it 13..15 + } Bits; + UINT16 Uint16; +} CXL_LINK_LAYER_CONTROL_AND_STATUS; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // b= it 0..9 + UINT64 CacheRspCredits : 10; // b= it 10..19 + UINT64 CacheDataCredits : 10; // b= it 20..29 + UINT64 MemReqRspCredits : 10; // b= it 30..39 + UINT64 MemDataCredits : 10; // b= it 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_RX_CREDIT_CONTROL; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // b= it 0..9 + UINT64 CacheRspCredits : 10; // b= it 10..19 + UINT64 CacheDataCredits : 10; // b= it 20..29 + UINT64 MemReqRspCredits : 10; // b= it 30..39 + UINT64 MemDataCredits : 10; // b= it 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // b= it 0..9 + UINT64 CacheRspCredits : 10; // b= it 10..19 + UINT64 CacheDataCredits : 10; // b= it 20..29 + UINT64 MemReqRspCredits : 10; // b= it 30..39 + UINT64 MemDataCredits : 10; // b= it 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_TX_CREDIT_STATUS; + +typedef union { + struct { + UINT32 AckForceThreshold : 8; // b= it 0..7 + UINT32 AckFLushRetimer : 10; // b= it 8..17 + } Bits; + UINT32 Uint32; +} CXL_LINK_LAYER_ACK_TIMER_CONTROL; + +typedef union { + struct { + UINT32 MdhDisable : 1; // b= it 0..0 + UINT32 Reserved : 31; // b= it 1..31 + } Bits; + UINT32 Uint32; +} CXL_LINK_LAYER_DEFEATURE; + +typedef struct { + CXL_LINK_LAYER_CAPABILITY LinkLayerC= apability; + CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerC= ontrolStatus; + CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerR= xCreditControl; + CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerR= xCreditReturnStatus; + CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerT= xCreditStatus; + CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerA= ckTimerControl; + CXL_LINK_LAYER_DEFEATURE LinkLayerD= efeature; +} CXL_1_1_LINK_CAPABILITY_STRUCTURE; + +#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180 +typedef union { + struct { + UINT32 Reserved1 : 4; // b= it 0..3 + UINT32 WeightedRoundRobinArbitrationWeight : 4; // b= it 4..7 + UINT32 Reserved2 : 24; // b= it 8..31 + } Bits; + UINT32 Uint32; +} CXL_IO_ARBITRATION_CONTROL; + +#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0 +typedef union { + struct { + UINT32 Reserved1 : 4; // b= it 0..3 + UINT32 WeightedRoundRobinArbitrationWeight : 4; // b= it 4..7 + UINT32 Reserved2 : 24; // b= it 8..31 + } Bits; + UINT32 Uint32; +} CXL_CACHE_MEMORY_ARBITRATION_CONTROL; +///@} + +/// The CXL.RCRB base register definition +/// Based on chapter 7.3 of Compute Express Link Specification Revision: 1= .1 +///@{ +typedef union { + struct { + UINT64 RcrbEnable : 1; // b= it 0..0 + UINT64 Reserved : 12; // b= it 1..12 + UINT64 RcrbBaseAddress : 51; // b= it 13..63 + } Bits; + UINT64 Uint64; +} CXL_RCRB_BASE; +///@} + +#pragma pack() + +// +// CXL Downstream / Upstream Port RCRB space register offsets +// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Fi= gure 97 +// +#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x= 010 +#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x= 014 +#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x= 100 + +#endif diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/Industr= yStandard/Pci.h index 8ed96b992a..42c00ac762 100644 --- a/MdePkg/Include/IndustryStandard/Pci.h +++ b/MdePkg/Include/IndustryStandard/Pci.h @@ -1,7 +1,7 @@ /** @file Support for the latest PCI standard. =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -9,9 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _PCI_H_ #define _PCI_H_ =20 -#include -#include -#include +#include #include =20 #endif --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#63119): https://edk2.groups.io/g/devel/message/63119 Mute This Topic: https://groups.io/mt/75726735/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 16 18:32:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+63120+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63120+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1595431341; cv=none; d=zohomail.com; s=zohoarc; b=FdWUmNaZ8QGNE5WzSzZvDUaAwDYKpPS7LR0rJ5BpsLy8drHnBTXW6o+ncuvshcoiHkVbyaOACa6Agp9nv+ujZ5f52XMeepUlact/74/PCz9MQu3w4CU1ZDuitGDpcSt6BUpsGfb+1r1CEKZ61+/w7Hxd13zJrVRlG8TaLqi7QfU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595431341; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NQEpki1t2QZvTfefrNvje2rgwJnq2dcnmqpeRkA11kQ=; b=SQy4Kh5Cymxs9Yr2kLNBNktkkSO5ozHaD4JeFkfhB/DLIoglULI7SblH5Z3uTcEMgXqRb5h6wbL8ndL8M9C2ag3hH+ADIzLKFCYYMDRKWWfgy/AVOeYx0TEVm8Qy4jSPbPIJLKbR8r2xE9bWEdJZjVfLgeFzNiDNpsF6U6Mcqk0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63120+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 159543134125395.09740046455522; Wed, 22 Jul 2020 08:22:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Qa00YY1788612xrRo6AJshV9; Wed, 22 Jul 2020 08:22:20 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web11.21108.1595431337293498863 for ; Wed, 22 Jul 2020 08:22:20 -0700 IronPort-SDR: rVwHUQ1zh2zWwNkQR8NQdQmPC0tf5unxUMnCkLZpHqkTB1lp1jNnM5m9ot5Smm3ybvwfiETVQd V6qz0BRLQk1A== X-IronPort-AV: E=McAfee;i="6000,8403,9690"; a="235214682" X-IronPort-AV: E=Sophos;i="5.75,383,1589266800"; d="scan'208";a="235214682" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2020 08:22:20 -0700 IronPort-SDR: UE+NakrydM38SdjPpF/xbizUSOSv13zhzjo+fbzF3aFTtQZjTn0kJajK/jChAphs3qcVoI6GlW vx3oXo91f4Mw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,383,1589266800"; d="scan'208";a="270775053" X-Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 22 Jul 2020 08:22:18 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL header Date: Wed, 22 Jul 2020 20:51:39 +0530 Message-Id: <20200722152139.16496-3-ashraf.javeed@intel.com> In-Reply-To: <20200722152139.16496-1-ashraf.javeed@intel.com> References: <20200722152139.16496-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: v50RZCb3QVKwXhKG6BXZEW3Zx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1595431340; bh=t0JvxnV5CSSKfLWDNbWCPVnxMgXrIDJqFIyVpk48MNo=; h=Cc:Date:From:Reply-To:Subject:To; b=bsh6JM34g9jXmCfVX8RKRjbyt8EZpeNPNDnWGP0/9EeS9O3yuo0kRNj85zVw4/tEMqr cpxxShof1ruzbCyX2NTbAV7LqcyZ98RM7t/G9Uh0BMO6d9FoIYd+pHaaaaZJV3qo+Md5+ 8BJ+G52Bku6lQazT2OclOhwfDaPpB8YfKVs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2611 Introducing the Cxl.h as the main header file to support all versions of Compute Express Link Specification register definitions. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao -- V2: Indentation and double declaration fix, copyright date update V3: Copyright date fix --- MdePkg/Include/IndustryStandard/Cxl.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/Industr= yStandard/Cxl.h new file mode 100644 index 0000000000..632aa146d0 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl.h @@ -0,0 +1,22 @@ +/** @file + Support for the latest CXL standard + + The main header to reference all versions of CXL Base specification regi= sters + from the MDE + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CXL_MAIN_H_ +#define _CXL_MAIN_H_ + +#include +// +// CXL assigned new Vendor ID +// +#define CXL_DVSEC_VENDOR_ID 0x= 1E98 + +#endif + --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#63120): https://edk2.groups.io/g/devel/message/63120 Mute This Topic: https://groups.io/mt/75726736/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-