From nobody Mon Apr 29 14:11:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62414+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62414+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=9elements.com ARC-Seal: i=1; a=rsa-sha256; t=1594635729; cv=none; d=zohomail.com; s=zohoarc; b=HavUh8WHhSVeiFdFgLhGHKarEyakd+jLLLfESVdORwH6E6QNBI/XSLk+B8CYTIlRn1ugD2HE0flzBRKGNm0nuREvSwqmlp6+23TL79Gu6pNx6icth4RTCEFBWkD91ZqTGMH5oy0UGj3PIAbWeTFfcL408FMfFW9ci/Gm+1J6dvU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594635729; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vynw2r4F2/JxriW/SlclGEkR52xHoLgqAAQotwa8xn0=; b=CbP4IakG7AyxwovNim/USrlqJYwuk1OU69CCuiu+zviLCSCHGDnTBwoJZc6hfRJjg7r97B+KGAOHKx44ka8ykPCQesc2Mp2lKTkJBRfz1KEZuEl+JyxRCSqKO8Wy0/r6rjEhWOco6sBz3y6hD//IGH7cgDHsAVkWJYhXYPBWHs8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62414+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594635729766412.12930646349594; Mon, 13 Jul 2020 03:22:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jAgHYY1788612xajjGzzvST1; Mon, 13 Jul 2020 03:22:09 -0700 X-Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) by mx.groups.io with SMTP id smtpd.web10.16469.1594635728391343412 for ; Mon, 13 Jul 2020 03:22:08 -0700 X-Received: by mail-ej1-f67.google.com with SMTP id y10so16255309eje.1 for ; Mon, 13 Jul 2020 03:22:08 -0700 (PDT) X-Gm-Message-State: ObkGjwae0yB1VrURSPc9XJ47x1787277AA= X-Google-Smtp-Source: ABdhPJylg+3Qpl5LkYR+x8er8WE+1RTkERINFuyAxMsbJGeMBRqXRkzgY78WYdTp1Xx+K1XjPpIpIw== X-Received: by 2002:a17:906:abc9:: with SMTP id kq9mr74155968ejb.493.1594635726650; Mon, 13 Jul 2020 03:22:06 -0700 (PDT) X-Received: from T580.dut.n1ce.space ([2a02:908:e851:d750:f570:655a:1f30:429f]) by smtp.gmail.com with ESMTPSA id rv16sm9587106ejb.60.2020.07.13.03.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2020 03:22:06 -0700 (PDT) From: "Marcello Sylvester Bauer" To: devel@edk2.groups.io Cc: Patrick Rudolph , Christian Walter , Maurice Ma , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH v1 1/2] MdeModulePkg: Fix OptionROM scanning Date: Mon, 13 Jul 2020 12:22:01 +0200 Message-Id: <20200713102202.814-2-marcello.bauer@9elements.com> In-Reply-To: <20200713102202.814-1-marcello.bauer@9elements.com> References: <20200713102202.814-1-marcello.bauer@9elements.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcello.bauer@9elements.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594635729; bh=PR/q7WScgMR4mlUuJdkBWCUxRAib4qLBivv43rk4pBw=; h=Cc:Date:From:Reply-To:Subject:To; b=dpE9/NLhCkVFp1bMj3+OpBG4lWGbh9RCOVSc+bexhATrDUVB/zZUMnD4S5BaWyy5pKU B0rs9xDOkzwVJPwOvfSDBqQ9cQ4v69z+YEPccjYopgAPg+GuIX/p6i1gwc2KYe73GQ+Xo 3ZhyATnpXE9zk9n3pe8Fsq95fVa09od05HY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Patrick Rudolph The Option ROM scanner can't work as enumeration was done by the first stage bootloader. Running it will disable the ability of the PCIPlatform code to scan for ROMs. Required for the following patch that enables custom Option ROM scanning using gPciPlatformProtocol. Signed-off-by: Patrick Rudolph Signed-off-by: Marcello Sylvester Bauer Cc: Patrick Rudolph Cc: Christian Walter Cc: Maurice Ma Cc: Nate DeSimone Cc: Star Zeng --- MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 6c68a97d4e46..7420f0079f7d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -2530,10 +2530,12 @@ PciEnumeratorLight ( // RemoveRejectedPciDevices (RootBridgeDev->Handle, RootBridgeDev); =20 - // - // Process option rom light - // - ProcessOptionRomLight (RootBridgeDev); + if (!PcdGetBool (PcdPciDisableBusEnumeration)) { + // + // Process option rom light + // + ProcessOptionRomLight (RootBridgeDev); + } =20 // // Determine attributes for all devices under this root bridge --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62414): https://edk2.groups.io/g/devel/message/62414 Mute This Topic: https://groups.io/mt/75474021/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 14:11:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62415+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62415+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=9elements.com ARC-Seal: i=1; a=rsa-sha256; t=1594635730; cv=none; d=zohomail.com; s=zohoarc; b=fXN5kthL/DzjT13iyrTgs4JVi7PBjtACkjafEbaVIyVtk882cxs/s1ae95ei+ikvR6x9KyqgYAh4tnNpqBPn0GCII2qwZ8fpQ8O8jhtIDN3CRazyCcrGoYgzfCXdrybTzhqUClZAnFu3Etb/2lk1FyobTgVTXsimVI7Vyax6khg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594635730; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=U1QgR2OZ37Ag75CA0tR5Y2ADUOcwQ58BSKro9MaEepc=; b=IXDT4iomc4x+9wfOuIaTHqLf19XKRaX+NuqEWO2zjs9e58eY0t8djYu317nOPIPMm57zk2aBx/i+v6dU2l7n+hPg1qZh+NmanUNo83A359cLiVo1j7gO2/qRwRGMENhP+/KJwyDC4wlNBcl5sDBiCuRxVOc/BbmDBAKrlLL2API= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62415+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594635730617866.8302283580239; Mon, 13 Jul 2020 03:22:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id lJ41YY1788612xgHQWKhPvKz; Mon, 13 Jul 2020 03:22:10 -0700 X-Received: from mail-ed1-f65.google.com (mail-ed1-f65.google.com [209.85.208.65]) by mx.groups.io with SMTP id smtpd.web11.16275.1594635729396119817 for ; Mon, 13 Jul 2020 03:22:09 -0700 X-Received: by mail-ed1-f65.google.com with SMTP id dg28so12931149edb.3 for ; Mon, 13 Jul 2020 03:22:09 -0700 (PDT) X-Gm-Message-State: AH6XBpEGgPgGThDuF2026sBtx1787277AA= X-Google-Smtp-Source: ABdhPJyXGQXWQ5HdnjqBtVuN/SUVK12anVQ2VaefR6wHJErHM1zIt+/1g0RSVXLMzBRuUvPbs17v5Q== X-Received: by 2002:aa7:da56:: with SMTP id w22mr93229477eds.124.1594635727441; Mon, 13 Jul 2020 03:22:07 -0700 (PDT) X-Received: from T580.dut.n1ce.space ([2a02:908:e851:d750:f570:655a:1f30:429f]) by smtp.gmail.com with ESMTPSA id rv16sm9587106ejb.60.2020.07.13.03.22.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2020 03:22:06 -0700 (PDT) From: "Marcello Sylvester Bauer" To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH v1 2/2] UefiPayloadPkg: Scan for Option ROMs Date: Mon, 13 Jul 2020 12:22:02 +0200 Message-Id: <20200713102202.814-3-marcello.bauer@9elements.com> In-Reply-To: <20200713102202.814-1-marcello.bauer@9elements.com> References: <20200713102202.814-1-marcello.bauer@9elements.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcello.bauer@9elements.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594635730; bh=8uUNCR6XP6OZMrOz/wby9zuG9guWb68ulu3DVMzZd2o=; h=Date:From:Reply-To:Subject:To; b=HmEp0qWBes3VtSLsvyP2LchFX0eJXCvuEthZHUw1FM1xx5Pr2a9kCAzbZEUMfJJ64L6 CZDZL7y92J3KtDiHLpKKHjcY/U8xTAzRPvocFMM22JXQ2FjzLGiu1qRQdED/siIjI6l+e c69XCV+dp0csifeDexTsyuT6+EtImLYu1UI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Patrick Rudolph Install the gPciPlatformProtocol to scan for Option ROMs. For every device we probe the Option ROM and provide a pointer to the activated BAR if found. It's safe to assume that all ROM bars have been enumerated, reserved in the bridge resources and are disabled by default. Enabling them and leaving them enabled will do no harm. Signed-off-by: Patrick Rudolph --- UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 1 + UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 1 + UefiPayloadPkg/UefiPayloadPkg.fdf | 1 + UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf | 46 +++ UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h | 19 + UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c | 365 ++++++++++++++++++++ 6 files changed, 433 insertions(+) diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc b/UefiPayloadPkg/UefiPay= loadPkgIa32.dsc index 6ac10f086bf9..f3bd9cf543af 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc @@ -511,6 +511,7 @@ [Components.IA32] !endif MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf + UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf =20 #------------------------------ # Build the shell diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/Uefi= PayloadPkgIa32X64.dsc index 650a72162a29..6531de9a2df9 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc @@ -512,6 +512,7 @@ [Components.X64] !endif MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf + UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf =20 #------------------------------ # Build the shell diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayload= Pkg.fdf index 570a8ee7fdc1..9b188724221d 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.fdf +++ b/UefiPayloadPkg/UefiPayloadPkg.fdf @@ -151,6 +151,7 @@ [FV.DXEFV] INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf !endif INF UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf +INF UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf =20 # # SCSI/ATA/IDE/DISK Support diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf b/UefiPayload= Pkg/PciPlatformDxe/PciPlatformDxe.inf new file mode 100644 index 000000000000..96cedad5afc3 --- /dev/null +++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf @@ -0,0 +1,46 @@ +## @file +# This driver produces gEfiPciPlatform protocol to load PCI Option ROMs +# +# Copyright (c) 2020, 9elements Agency GmbH +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PciPlatformDxe + FILE_GUID =3D 86D58F7B-6E7C-401F-BDD4-E32E6D582AAD + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InstallPciPlatformProtocol + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources.common] + PciPlatformDxe.h + PciPlatformDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DxeServicesTableLib + DebugLib + MemoryAllocationLib + BaseMemoryLib + DevicePathLib + UefiLib + HobLib + +[Protocols] + gEfiPciPlatformProtocolGuid ## PRODUCES + gEfiPciIoProtocolGuid ## COMSUMES diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h b/UefiPayloadPk= g/PciPlatformDxe/PciPlatformDxe.h new file mode 100644 index 000000000000..c40518c703f8 --- /dev/null +++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h @@ -0,0 +1,19 @@ +/** @file + Header file for a PCI platform driver. + +Copyright (c) 2016, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ +#ifndef _PCI_PLATFORM_DXE_H_ +#define _PCI_PLATFORM_DXE_H_ +#include + +#include +#include +#include +#include +#include + +#endif diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c b/UefiPayloadPk= g/PciPlatformDxe/PciPlatformDxe.c new file mode 100644 index 000000000000..05a8544c3ce7 --- /dev/null +++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c @@ -0,0 +1,365 @@ +/** @file + Implementation for a generic GOP driver. + +Copyright (c) 2016, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include "PciPlatformDxe.h" +#include +#include + +// +// The driver should only start on one graphics controller. +// So a global flag is used to remember that the driver is already started. +// +EFI_HANDLE mDriverHandle =3D NULL; + +EFI_STATUS +EFIAPI +PciPlatformNotify( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +PciPlatformPrepController( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +PciGetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +{ + EFI_STATUS Status; + IN EFI_PCI_IO_PROTOCOL *PciIo; + UINTN PciSegment; + UINTN PciBus; + UINTN PciDevice; + UINTN PciFunction; + UINTN RomBarIndex; + UINT32 Buffer; + UINT32 AllOnes; + PCI_IO_DEVICE *PciIoDevice; + UINT8 Indicator; + UINT16 OffsetPcir; + UINT32 RomBarOffset; + UINT32 RomBar; + BOOLEAN FirstCheck; + PCI_EXPANSION_ROM_HEADER *RomHeader; + PCI_DATA_STRUCTURE *RomPcir; + UINT64 RomImageSize; + UINT32 LegacyImageLength; + UINT8 *RomInMemory; + UINT8 CodeType; + + if (!RomImage || !RomSize) { + return EFI_INVALID_PARAMETER; + } + + *RomImage =3D NULL; + *RomSize =3D 0; + + Status =3D gBS->HandleProtocol ( + PciHandle, + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: Failed to open gEfiPciIoProtocolGuid\n", __= FUNCTION__)); + + return EFI_UNSUPPORTED; + } + PciIoDevice =3D PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo); + + // + // Get the location of the PCI device + // + PciIo->GetLocation ( + PciIo, + &PciSegment, + &PciBus, + &PciDevice, + &PciFunction + ); + + DEBUG ((DEBUG_INFO, "%a: Searching Option ROM on device:\n", __FUNCTION_= _)); + DEBUG ((DEBUG_INFO, " PciSegment - %02x\n", PciSegment)); + DEBUG ((DEBUG_INFO, " PciBus - %02x\n", PciBus)); + DEBUG ((DEBUG_INFO, " PciDevice - %02x\n", PciDevice)); + DEBUG ((DEBUG_INFO, " PciFunction - %02x\n", PciFunction)); + + // + // 0x30 + // + RomBarIndex =3D PCI_EXPANSION_ROM_BASE; + + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { + // + // If is ppb, 0x38 + // + RomBarIndex =3D PCI_BRIDGE_ROMBAR; + } + // + // Backup BAR + // + + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciWidthUint32, + RomBarIndex, + 1, + &Buffer + ); + if (EFI_ERROR (Status)) { + goto CloseAndReturn; + return Status; + } + + // + // The bit0 is 0 to prevent the enabling of the Rom address decoder + // + AllOnes =3D 0xfffffffe; + + Status =3D PciIo->Pci.Write ( + PciIo, + EfiPciWidthUint32, + RomBarIndex, + 1, + &AllOnes + ); + if (EFI_ERROR (Status)) { + goto CloseAndReturn; + } + + // + // Read back + // + Status =3D PciIo->Pci.Read( + PciIo, + EfiPciWidthUint32, + RomBarIndex, + 1, + &AllOnes + ); + if (EFI_ERROR (Status)) { + goto CloseAndReturn; + } + + // + // Bits [1, 10] are reserved + // + AllOnes &=3D 0xFFFFF800; + if ((AllOnes =3D=3D 0) || (AllOnes =3D=3D 0xFFFFF800)) { + DEBUG ((DEBUG_INFO, "%a: No Option ROM found\n", __FUNCTION__)); + return EFI_NOT_FOUND; + } + + *RomSize =3D (~AllOnes) + 1; + + DEBUG ((DEBUG_INFO, "%a: Option ROM with size %d\n", __FUNCTION__, *RomS= ize)); + + // + // Restore BAR and enable it + // + Buffer |=3D 1; + Status =3D PciIo->Pci.Write ( + PciIo, + EfiPciWidthUint32, + RomBarIndex, + 1, + &Buffer + ); + if (EFI_ERROR (Status)) { + goto CloseAndReturn; + } + + // + // Allocate memory for Rom header and PCIR + // + RomHeader =3D AllocatePool (sizeof (PCI_EXPANSION_ROM_HEADER)); + if (RomHeader =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto CloseAndReturn; + } + + RomPcir =3D AllocatePool (sizeof (PCI_DATA_STRUCTURE)); + if (RomPcir =3D=3D NULL) { + FreePool (RomHeader); + Status =3D EFI_OUT_OF_RESOURCES; + goto CloseAndReturn; + } + + // FIXME: Use gEfiPciRootBridgeIoProtocolGuid + RomBar =3D (UINT32) Buffer &~1; + + RomBarOffset =3D RomBar; + FirstCheck =3D TRUE; + LegacyImageLength =3D 0; + RomImageSize =3D 0; + + do { + // FIXME: Use gEfiPciRootBridgeIoProtocolGuid + CopyMem(RomHeader, (VOID *)(UINTN)RomBarOffset, sizeof (PCI_EXPANSION_= ROM_HEADER)); + + DEBUG ((DEBUG_INFO, "%a: RomHeader->Signature %x\n", __FUNCTION__, Rom= Header->Signature)); + + if (RomHeader->Signature !=3D PCI_EXPANSION_ROM_HEADER_SIGNATURE) { + + RomBarOffset =3D RomBarOffset + 512; + if (FirstCheck) { + break; + } else { + RomImageSize =3D RomImageSize + 512; + continue; + } + } + + FirstCheck =3D FALSE; + OffsetPcir =3D RomHeader->PcirOffset; + // + // If the pointer to the PCI Data Structure is invalid, no further ima= ges can be located. + // The PCI Data Structure must be DWORD aligned. + // + if (OffsetPcir =3D=3D 0 || + (OffsetPcir & 3) !=3D 0 || + RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > *RomSize= ) { + break; + } + // FIXME: Use gEfiPciRootBridgeIoProtocolGuid + CopyMem(RomPcir, (VOID *)(UINTN)RomBarOffset + OffsetPcir, sizeof (PCI= _DATA_STRUCTURE)); + + DEBUG ((DEBUG_INFO, "%a: RomPcir->Signature %x\n", __FUNCTION__, RomPc= ir->Signature)); + + // + // If a valid signature is not present in the PCI Data Structure, no f= urther images can be located. + // + if (RomPcir->Signature !=3D PCI_DATA_STRUCTURE_SIGNATURE) { + break; + } + if (RomImageSize + RomPcir->ImageLength * 512 > *RomSize) { + break; + } + if (RomPcir->CodeType =3D=3D PCI_CODE_TYPE_PCAT_IMAGE) { + CodeType =3D PCI_CODE_TYPE_PCAT_IMAGE; + LegacyImageLength =3D ((UINT32)((EFI_LEGACY_EXPANSION_ROM_HEADER *)R= omHeader)->Size512) * 512; + } + Indicator =3D RomPcir->Indicator; + RomImageSize =3D RomImageSize + RomPcir->ImageLength * 512; + RomBarOffset =3D RomBarOffset + RomPcir->ImageLength * 512; + } while (((Indicator & 0x80) =3D=3D 0x00) && ((RomBarOffset - RomBar) < = *RomSize)); + + // + // Some Legacy Cards do not report the correct ImageLength so used the m= aximum + // of the legacy length and the PCIR Image Length + // + if (CodeType =3D=3D PCI_CODE_TYPE_PCAT_IMAGE) { + RomImageSize =3D MAX (RomImageSize, LegacyImageLength); + } + + if (RomImageSize > 0) { + // FIXME: Use gEfiPciRootBridgeIoProtocolGuid + RomInMemory =3D (VOID *)(UINTN)RomBar; + } + + // + // Free allocated memory + // + FreePool (RomHeader); + FreePool (RomPcir); + + if (RomImageSize > 0) { + *RomImage =3D RomInMemory; + *RomSize =3D RomImageSize; + DEBUG ((DEBUG_INFO, "%a: Found Option ROM at %p, length 0x%x\n", __FUN= CTION__, + RomInMemory, RomImageSize)); + + Status =3D EFI_SUCCESS; + } else { + Status =3D EFI_NOT_FOUND; + } + +CloseAndReturn: + // + // Close the I/O Abstraction(s) used to perform the supported test + // + gBS->CloseProtocol ( + PciHandle, + &gEfiPciIoProtocolGuid, + PciIo, + PciHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +PciGetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + if (PciPolicy =3D=3D NULL) + return EFI_INVALID_PARAMETER; + + *PciPolicy =3D 0; + + return EFI_SUCCESS; +} + +EFI_PCI_PLATFORM_PROTOCOL mPciPlatformProtocol =3D { + PciPlatformNotify, + PciPlatformPrepController, + PciGetPlatformPolicy, + PciGetPciRom, +}; + +/** + The Entry Point for Option ROM driver. + + It installs DriverBinding. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +InstallPciPlatformProtocol ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D gBS->InstallProtocolInterface ( + &mDriverHandle, + &gEfiPciPlatformProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPciPlatformProtocol + ); + + return Status; +} --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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