From nobody Sun Feb 8 22:49:46 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62355+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62355+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433351; cv=none; d=zohomail.com; s=zohoarc; b=FXtqGZjIoueB0e0FVScp0Oi+ktjjE6MNY/pugVR9eKV5Y2PMqGhCfIly/YGZkfwYDW0lqym3QtjAL+tN+NqW8jpI9dywcsMT+c5uWr310LoUKCK6gS/q7/D9SiCriRKvzQaXRx227XTsBgyZDxk+XJ9sJa2xIiJ2ImFtNVl00l8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433351; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=LgJm+6WGEuc6X3VcR69gJcI0HgQ4rXOb8x9wHMXBqYQ=; b=MyGmo5QrFPj+cFg6ohUB9kbLnQsnr5pgPNxa1Rb7Pw2lut7oFz/eWfHRTN3cYdnKhgjgLkkMcr/eJD1vbU8kAuINzbarwsShyICUQoQYr9+EIYrhVQdL+R4ctkcrsZP91XrXA3I0dFm7JR9mkvpDWgc9aGSW5tNmUnldHlFCH4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62355+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433351549724.6422619282282; Fri, 10 Jul 2020 19:09:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VlCDYY1788612xwBTWyfahJ6; Fri, 10 Jul 2020 19:09:11 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web10.2144.1594433349022222645 for ; Fri, 10 Jul 2020 19:09:09 -0700 IronPort-SDR: TN7OjzZWXJKYgCjDiupAaHZGLoTmVkmlAOmlD/jN9dKkcoV5WbBh0MyHZO8f3i06QZOHlIdk/k 6SP964gAxkyg== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380535" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380535" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:08 -0700 IronPort-SDR: xp2ItVLr9409NdWugJzCNAMbbTE0Grm/fND5nIKkD38FdMhoOtj01gZVt55aBNzKKaPW3J2hw5 MnPp8CL1EWYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602240" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:08 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao , Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 03/16] MdePkg/BaseCacheMaintenanceLibNull: Add Null instance for host testing Date: Fri, 10 Jul 2020 19:08:51 -0700 Message-Id: <20200711020904.24116-4-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: BHsQt47YCkCH8q9KC63Sj9bpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433351; bh=hio/y6cx1CIVqwqJ0+zS2BHYvwKL1RBaM7qtWP5UgTk=; h=Cc:Date:From:Reply-To:Subject:To; b=X0fjIQNI2RKVBzDcUZoKxOV4ahiMtyo6Q+eK1zr1yRxAqWTxQypy56xLpxcBge7sdIf RljG8vx3W76aGdYnNdBsB1Gt6I902zLxjvJoXjFp+ktly2stpM/IlmdDom2YR7bHFg6GT PLhHs+l7SsNaiwQt6YQGDz9f9Djd5DNaUUo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2799 The services in CacheMaintenanceLib usually generate exceptions in a unit test host application. Provide a Null instance that can be safely used. This Null instance can also be used as a template for implementing new instances of CacheMaintenanceLib. Cc: Liming Gao Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Liming Gao --- .../BaseCacheMaintenanceLibNull.c | 225 ++++++++++++++++++ .../BaseCacheMaintenanceLibNull.inf | 29 +++ .../BaseCacheMaintenanceLibNull.uni | 12 + MdePkg/MdePkg.dsc | 1 + 4 files changed, 267 insertions(+) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMai= ntenanceLibNull.c create mode 100644 MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMai= ntenanceLibNull.inf create mode 100644 MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMai= ntenanceLibNull.uni diff --git a/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanc= eLibNull.c b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanc= eLibNull.c new file mode 100644 index 0000000000..fd5b9d4710 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanceLibNul= l.c @@ -0,0 +1,225 @@ +/** @file + Null Cache Maintenance Librfary implementation. + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); + return Address; +} + +/** + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ +} + +/** + Writes back and invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes Back and Invalidate the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); + return Address; +} + +/** + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ +} + +/** + Writes back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); + return Address; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, then no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); + return Address; +} diff --git a/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanc= eLibNull.inf b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintena= nceLibNull.inf new file mode 100644 index 0000000000..8d6eaaeaa0 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanceLibNul= l.inf @@ -0,0 +1,29 @@ +## @file +# Null Cache Maintenance Library implementation. +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseCacheMaintenanceLibNull + MODULE_UNI_FILE =3D BaseCacheMaintenanceLibNull.uni + FILE_GUID =3D 13F13249-AC31-4373-8B2B-AFC5755A6FCD + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.1 + LIBRARY_CLASS =3D CacheMaintenanceLib + +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# + +[Sources] + BaseCacheMaintenanceLibNull.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib diff --git a/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanc= eLibNull.uni b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintena= nceLibNull.uni new file mode 100644 index 0000000000..260c756190 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanceLibNul= l.uni @@ -0,0 +1,12 @@ +// /** @file +// Null Cache Maintenance Library implementation. +// +// Copyright (c) 2020, Intel Corporation. All rights reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "Null instance of = Cache Maintenance Library" + +#string STR_MODULE_DESCRIPTION #language en-US "Null instance of = the Cache Maintenance Library." + diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 3abe65ec7f..472fa37774 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -35,6 +35,7 @@ [LibraryClasses] [Components] MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanceLibNull.i= nf MdePkg/Library/BaseCpuLib/BaseCpuLib.inf MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.inf MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62355): https://edk2.groups.io/g/devel/message/62355 Mute This Topic: https://groups.io/mt/75432215/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-