From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62352+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62352+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433350; cv=none; d=zohomail.com; s=zohoarc; b=MAfsopPafPggRjrYVuSwM6LvDCGHtBfqFkDQFD2/DBFKRYlJoti6wdJCo0coNosLEnuIX+14bai//QlHBn0UFRjQLr19YvJ62At2tyj6HW+w84dLSUfbC4Y+Jo5Qpdf2SCFObMzJtPSwbxnbTfZNZ6CpnKeANBGSYb2kNXZaQWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433350; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=g3lSQ4IYn0uPklridWdfK8ExE0KxjOMz1aYv3G6UsvM=; b=kryZ2LGOfj2vKk0cEn5e+gGKawEtctuM0B0p/mNlckJwkKed2A9vUeOKi9VQSem977ybPefYB1jtmJIeazcFTuo4XKyuda/3fGdiFPMRykMtRpOHpQh577r0IWnaxy2GkjTVhaFp+gPRrzYPsU5s0rq1NeRhEXjwIZfDKhQV09k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62352+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433350289620.4009858202552; Fri, 10 Jul 2020 19:09:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id CuxvYY1788612xYImfsMumDy; Fri, 10 Jul 2020 19:09:09 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.2144.1594433349022222645 for ; Fri, 10 Jul 2020 19:09:09 -0700 IronPort-SDR: OdfBwlJicXyjCW8F1pTGSUuiV06OSkmyyG9J/2Lp6VBJZxLfWulLZdJk5TcUv5EPR+trMRA0o1 XsZNBAfFykPQ== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380533" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380533" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:08 -0700 IronPort-SDR: tTDA9THtgkVXRhlMsaiQLn/mx101B3ozhaLDur0/Hhp7k2HW6PCAZbkrfwcfpjaRAj2MAHrYEp aalFAAJzsbag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602222" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:07 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Bob Feng , Liming Gao , Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 01/16] BaseTools/Python: Allow HOST_APPLICATION to use NULL libraries Date: Fri, 10 Jul 2020 19:08:49 -0700 Message-Id: <20200711020904.24116-2-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: oeyL5RNBITxdZIlju3zgaqx4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433349; bh=r67TqDJR//sw5lauRmZNZxYIdWvZYYZauFS9/yakh9c=; h=Cc:Date:From:Reply-To:Subject:To; b=TUSXHCGceXuAnX64Nu7Pi+sb7o2TpvgOgO3JQd2+qyj+jwKsi6YoMxUGtwTcNwYJ6/B Wzob5g3IPsUoeEX2kaqe65MA7rDaoH/GdI/2ixN8+TxZJj/sDmNBPJbAxao/iWK2htoDm HlYPpm7DYxabaS38a7IQw6NRltKPLvOcOAs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2797 Update HOST_APPLICATION module type to use NULL library instances. Cc: Bob Feng Cc: Liming Gao Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bob Feng Reviewed-by: Sean Brogan Reviewed-by: Bret Barkelew --- BaseTools/Source/Python/Workspace/WorkspaceCommon.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/BaseTools/Source/Python/Workspace/WorkspaceCommon.py b/BaseToo= ls/Source/Python/Workspace/WorkspaceCommon.py index 913e710fd9..53027a0e30 100644 --- a/BaseTools/Source/Python/Workspace/WorkspaceCommon.py +++ b/BaseTools/Source/Python/Workspace/WorkspaceCommon.py @@ -1,7 +1,7 @@ ## @file # Common routines used by workspace # -# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2012 - 2020, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # =20 @@ -100,7 +100,7 @@ def GetModuleLibInstances(Module, Platform, BuildDataba= se, Arch, Target, Toolcha # If a module has a MODULE_TYPE of USER_DEFINED, # do not link in NULL library class instances from the global [Library= Classes.*] sections. # - if Module.ModuleType !=3D SUP_MODULE_USER_DEFINED and Module.ModuleTyp= e !=3D SUP_MODULE_HOST_APPLICATION: + if Module.ModuleType !=3D SUP_MODULE_USER_DEFINED: for LibraryClass in Platform.LibraryClasses.GetKeys(): if LibraryClass.startswith("NULL") and Platform.LibraryClasses= [LibraryClass, Module.ModuleType]: Module.LibraryClasses[LibraryClass] =3D Platform.LibraryCl= asses[LibraryClass, Module.ModuleType] --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62352): https://edk2.groups.io/g/devel/message/62352 Mute This Topic: https://groups.io/mt/75432212/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62354+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62354+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433350; cv=none; d=zohomail.com; s=zohoarc; b=FxTnYVElvh4joNiQh8L7wgj9S8/GReUgVx/LPr1uXt2fFVigScEoS5Giios6jxmYhEnr72a5Miq+GxrMe7uJ0mrUknRYupWyhSDe2x7xQ09esu71sIPm9fs54/RUNW9zASakKEjU9kaJqunPdf+XyCsYYA/IUXgR9Vy60GTH/7Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433350; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4mm2k+WKT4AESjFHeH03qmPkr9EdpDtZ8zQXRjhW5zs=; b=W1vIeI84Mdnov/d22XtufVxMamT0QOELM+cXVLnGfNGfLhMbfa958rZLUGfx12fnhI6B0/gcF0CpS635ZDxT4YrpJUe51n+g0TuQoQW55gmtaO/ikMelKK0stmZ82WiMOeb/8qvfHfugzIA3lDUxU5HusQAhJaEG8UbsWQK8p5A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62354+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433350698776.397924759718; Fri, 10 Jul 2020 19:09:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id j6vzYY1788612xp1dhPsJGfO; Fri, 10 Jul 2020 19:09:10 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web10.2144.1594433349022222645 for ; Fri, 10 Jul 2020 19:09:09 -0700 IronPort-SDR: CTNui496gNAb/D1j4CFdlaG/d2NsDxv6NHm7u8ZBIkuNYuBJ5EODr4gVb+QRNt4gU7lgQnV8TM GqGy14V5j1eA== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380534" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380534" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:08 -0700 IronPort-SDR: geg/1LbofqBmhfmNyNXP96R7VWqspx8/XiS5DAi6laKuXcGT3SC/CsLbBbkkWhbSD+Z9moYBtH ONiwGCMfFQWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602231" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:08 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao , Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 02/16] MdePkg/BaseCpuLibNull: Add Null version of CpuLib for host testing Date: Fri, 10 Jul 2020 19:08:50 -0700 Message-Id: <20200711020904.24116-3-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: wkdzxWR3LEyXw2ysEgwyNOlKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433350; bh=JdwLHWM01PlGkhG4luuOLk4OnaeQdtCJ/5fiYKSrw2c=; h=Cc:Date:From:Reply-To:Subject:To; b=H4bxhqw+eUQSK1HTEIYr0Hz0k3t/+J9n1HaXpJy/vYqxiqiAQK6wZ/I7iqurvdnEjAS mhAWPJFmHoS0U/ch5y5nOivwd/M385d8IGO84pDHAx7jlIgylay5FG2b2K/f2cZR99k6E ebEtKVjyIQTAz6mAMONaDPkuaOz923oqUuk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2798 The services in CpuLib usually generate exceptions in a unit test host application. Provide a Null instance that can be safely used. This Null instance can also be used as a template for implementing new instances of CpuLib. Cc: Liming Gao Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Liming Gao Reviewed-by: Sean Brogan Reviewed-by: Bret Barkelew --- .../Library/BaseCpuLibNull/BaseCpuLibNull.c | 37 +++++++++++++++++++ .../Library/BaseCpuLibNull/BaseCpuLibNull.inf | 26 +++++++++++++ .../Library/BaseCpuLibNull/BaseCpuLibNull.uni | 11 ++++++ MdePkg/MdePkg.dsc | 3 +- 4 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.c create mode 100644 MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.inf create mode 100644 MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.uni diff --git a/MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.c b/MdePkg/Librar= y/BaseCpuLibNull/BaseCpuLibNull.c new file mode 100644 index 0000000000..3ba7a35096 --- /dev/null +++ b/MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.c @@ -0,0 +1,37 @@ +/** @file + Null instance of CPU Library. + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + Places the CPU in a sleep state until an interrupt is received. + + Places the CPU in a sleep state until an interrupt is received. If inter= rupts + are disabled prior to calling this function, then the CPU will be placed= in a + sleep state indefinitely. + +**/ +VOID +EFIAPI +CpuSleep ( + VOID + ) +{ +} + +/** + Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU. + + Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU. + +**/ +VOID +EFIAPI +CpuFlushTlb ( + VOID + ) +{ +} diff --git a/MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.inf b/MdePkg/Libr= ary/BaseCpuLibNull/BaseCpuLibNull.inf new file mode 100644 index 0000000000..a9e8399038 --- /dev/null +++ b/MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.inf @@ -0,0 +1,26 @@ +## @file +# Null instance of CPU Library. +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseCpuLibNull + MODULE_UNI_FILE =3D BaseCpuLibNull.uni + FILE_GUID =3D 8A29AAA5-0FB7-44CC-8709-1344FE89B878 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CpuLib + +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 +# + +[Sources] + BaseCpuLibNull.c + +[Packages] + MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.uni b/MdePkg/Libr= ary/BaseCpuLibNull/BaseCpuLibNull.uni new file mode 100644 index 0000000000..1030221d5c --- /dev/null +++ b/MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.uni @@ -0,0 +1,11 @@ +// /** @file +// Null instance of CPU Library. +// +// Copyright (c) 2020, Intel Corporation. All rights reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "Null Instance of = CPU Library" + +#string STR_MODULE_DESCRIPTION #language en-US "Null instance of = CPU Library." diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 6cd38e7ec3..3abe65ec7f 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -1,7 +1,7 @@ ## @file # EFI/PI MdePkg Package # -# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP
# @@ -36,6 +36,7 @@ [Components] MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.inf MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.i= nf --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62354): https://edk2.groups.io/g/devel/message/62354 Mute This Topic: https://groups.io/mt/75432214/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62355+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62355+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433351; cv=none; d=zohomail.com; s=zohoarc; b=FXtqGZjIoueB0e0FVScp0Oi+ktjjE6MNY/pugVR9eKV5Y2PMqGhCfIly/YGZkfwYDW0lqym3QtjAL+tN+NqW8jpI9dywcsMT+c5uWr310LoUKCK6gS/q7/D9SiCriRKvzQaXRx227XTsBgyZDxk+XJ9sJa2xIiJ2ImFtNVl00l8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433351; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=LgJm+6WGEuc6X3VcR69gJcI0HgQ4rXOb8x9wHMXBqYQ=; b=MyGmo5QrFPj+cFg6ohUB9kbLnQsnr5pgPNxa1Rb7Pw2lut7oFz/eWfHRTN3cYdnKhgjgLkkMcr/eJD1vbU8kAuINzbarwsShyICUQoQYr9+EIYrhVQdL+R4ctkcrsZP91XrXA3I0dFm7JR9mkvpDWgc9aGSW5tNmUnldHlFCH4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62355+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433351549724.6422619282282; Fri, 10 Jul 2020 19:09:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VlCDYY1788612xwBTWyfahJ6; Fri, 10 Jul 2020 19:09:11 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web10.2144.1594433349022222645 for ; Fri, 10 Jul 2020 19:09:09 -0700 IronPort-SDR: TN7OjzZWXJKYgCjDiupAaHZGLoTmVkmlAOmlD/jN9dKkcoV5WbBh0MyHZO8f3i06QZOHlIdk/k 6SP964gAxkyg== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380535" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380535" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:08 -0700 IronPort-SDR: xp2ItVLr9409NdWugJzCNAMbbTE0Grm/fND5nIKkD38FdMhoOtj01gZVt55aBNzKKaPW3J2hw5 MnPp8CL1EWYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602240" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:08 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao , Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 03/16] MdePkg/BaseCacheMaintenanceLibNull: Add Null instance for host testing Date: Fri, 10 Jul 2020 19:08:51 -0700 Message-Id: <20200711020904.24116-4-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: BHsQt47YCkCH8q9KC63Sj9bpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433351; bh=hio/y6cx1CIVqwqJ0+zS2BHYvwKL1RBaM7qtWP5UgTk=; h=Cc:Date:From:Reply-To:Subject:To; b=X0fjIQNI2RKVBzDcUZoKxOV4ahiMtyo6Q+eK1zr1yRxAqWTxQypy56xLpxcBge7sdIf RljG8vx3W76aGdYnNdBsB1Gt6I902zLxjvJoXjFp+ktly2stpM/IlmdDom2YR7bHFg6GT PLhHs+l7SsNaiwQt6YQGDz9f9Djd5DNaUUo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2799 The services in CacheMaintenanceLib usually generate exceptions in a unit test host application. Provide a Null instance that can be safely used. This Null instance can also be used as a template for implementing new instances of CacheMaintenanceLib. Cc: Liming Gao Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Liming Gao Reviewed-by: Bret Barkelew --- .../BaseCacheMaintenanceLibNull.c | 225 ++++++++++++++++++ .../BaseCacheMaintenanceLibNull.inf | 29 +++ .../BaseCacheMaintenanceLibNull.uni | 12 + MdePkg/MdePkg.dsc | 1 + 4 files changed, 267 insertions(+) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMai= ntenanceLibNull.c create mode 100644 MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMai= ntenanceLibNull.inf create mode 100644 MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMai= ntenanceLibNull.uni diff --git a/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanc= eLibNull.c b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanc= eLibNull.c new file mode 100644 index 0000000000..fd5b9d4710 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanceLibNul= l.c @@ -0,0 +1,225 @@ +/** @file + Null Cache Maintenance Librfary implementation. + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); + return Address; +} + +/** + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ +} + +/** + Writes back and invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes Back and Invalidate the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); + return Address; +} + +/** + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ +} + +/** + Writes back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); + return Address; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, then no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); + return Address; +} diff --git a/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanc= eLibNull.inf b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintena= nceLibNull.inf new file mode 100644 index 0000000000..8d6eaaeaa0 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanceLibNul= l.inf @@ -0,0 +1,29 @@ +## @file +# Null Cache Maintenance Library implementation. +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseCacheMaintenanceLibNull + MODULE_UNI_FILE =3D BaseCacheMaintenanceLibNull.uni + FILE_GUID =3D 13F13249-AC31-4373-8B2B-AFC5755A6FCD + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.1 + LIBRARY_CLASS =3D CacheMaintenanceLib + +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# + +[Sources] + BaseCacheMaintenanceLibNull.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib diff --git a/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanc= eLibNull.uni b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintena= nceLibNull.uni new file mode 100644 index 0000000000..260c756190 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanceLibNul= l.uni @@ -0,0 +1,12 @@ +// /** @file +// Null Cache Maintenance Library implementation. +// +// Copyright (c) 2020, Intel Corporation. All rights reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "Null instance of = Cache Maintenance Library" + +#string STR_MODULE_DESCRIPTION #language en-US "Null instance of = the Cache Maintenance Library." + diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 3abe65ec7f..472fa37774 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -35,6 +35,7 @@ [LibraryClasses] [Components] MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCacheMaintenanceLibNull.i= nf MdePkg/Library/BaseCpuLib/BaseCpuLib.inf MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.inf MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62355): https://edk2.groups.io/g/devel/message/62355 Mute This Topic: https://groups.io/mt/75432215/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62356+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62356+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433351; cv=none; d=zohomail.com; s=zohoarc; b=Xz85h9VyLxT+qD0irkdj3i+yMceNM+pVvFZMc0vIAkc6CTmbzrAsOzKQ15/BrkW2pgamOITbmO/wlGfbcXLjqb7DYpUa2po9hvx9xtAfc2e7iydy0FOp3AKMTNWcY27Uk1wfKYGqe6DMlKQpMkeOwdZKXsnkqwNPXisWwXm6RQI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433351; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=pclE+t2kg+2qpRVkWFPYBP321Hb/8PPip6U0OXpcHyk=; b=IbkM+laLAB6ayN4vkJGuoT2QOJ5g142HH3auxhdqxwkCiIja2hp1YFKt0vaQXxzZEDta4KEuLAZ3uQ8wZdlDUrB3zTsft/HjzjgdvHFSESiX1aXUvquJEVPC/uvkPvf++VfkfsiqDoNHJWeZaTjp76A8cMEgvoUUepyqT7VXyLk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62356+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433351944784.5549549460222; Fri, 10 Jul 2020 19:09:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id je0DYY1788612xZOPvgzjr0x; Fri, 10 Jul 2020 19:09:11 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web10.2144.1594433349022222645 for ; Fri, 10 Jul 2020 19:09:10 -0700 IronPort-SDR: m/gQ7yh5LvzuSmHAbLSugG3vAG/29dZm5XSkn9WD/oLcUeVVRMRQQmhe2yJpMZYkI0vy8xMiUx slCfQ37zTKkw== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380537" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380537" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:09 -0700 IronPort-SDR: JVH6Bh4IE2Q6ojjShk8+HxdBYzKyVuMtRNnTnLMQgkoNyjG3c5Sd8FhAQfLRwWGutgmdVDHXy+ D+lGU1MRE3qA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602248" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:09 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao , Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 04/16] MdePkg/BaseLib: Break out IA32/X64 GCC inline privileged functions Date: Fri, 10 Jul 2020 19:08:52 -0700 Message-Id: <20200711020904.24116-5-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: Id20taPqO6aRQNmtRvEa6k2Zx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433351; bh=2+R4CVvBED99y3KFOn+gzCvZUfTmYbBR7eiZ/qodBE4=; h=Cc:Date:From:Reply-To:Subject:To; b=W7lIcMbWDzB0natjlpbpHH6Hol9m64DJYIjDUrRCB/VDA6fqAKaH6pvBtXfXJYQH8pl yI+ZN8Q9/pfDrBKerO8pi4Lq22qDgiW2Qn7kHY74aA393SXQiqdTadbRJOGn19Vt8FADs cIx4i1NwzRdKBJZO6LJfaIrvVPc2LzNHcgo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2800 Break out the IA32/X64 GCC inline functions that can not be used in a unit test host application into their own source file. This does not make any changes to the BaseLib library instance. This is in preparation for a new BaseLib instances that is safe to use with host-based unit test applications. Cc: Liming Gao Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- MdePkg/Library/BaseLib/BaseLib.inf | 4 +- MdePkg/Library/BaseLib/Ia32/GccInline.c | 1181 +--------------- .../Ia32/{GccInline.c =3D> GccInlinePriv.c} | 601 +------- MdePkg/Library/BaseLib/X64/GccInline.c | 1240 +---------------- .../X64/{GccInline.c =3D> GccInlinePriv.c} | 572 +------- 5 files changed, 11 insertions(+), 3587 deletions(-) copy MdePkg/Library/BaseLib/Ia32/{GccInline.c =3D> GccInlinePriv.c} (62%) copy MdePkg/Library/BaseLib/X64/{GccInline.c =3D> GccInlinePriv.c} (65%) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index a57ae2da31..c740a819ca 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -1,7 +1,7 @@ ## @file # Base Library implementation. # -# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
@@ -156,6 +156,7 @@ [Sources.Ia32] =20 =20 Ia32/GccInline.c | GCC + Ia32/GccInlinePriv.c | GCC Ia32/Thunk16.nasm Ia32/EnableDisableInterrupts.nasm| GCC Ia32/EnablePaging64.nasm @@ -310,6 +311,7 @@ [Sources.X64] X86PatchInstruction.c X86SpeculationBarrier.c X64/GccInline.c | GCC + X64/GccInlinePriv.c | GCC X64/EnableDisableInterrupts.nasm X64/DisablePaging64.nasm X64/RdRand.nasm diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseL= ib/Ia32/GccInline.c index 5287200f87..6ed938187a 100644 --- a/MdePkg/Library/BaseLib/Ia32/GccInline.c +++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c @@ -1,7 +1,7 @@ /** @file GCC inline implementation of BaseLib processor specific functions. =20 - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -10,8 +10,6 @@ =20 #include "BaseLibInternals.h" =20 - - /** Used to serialize load and store operations. =20 @@ -31,41 +29,6 @@ MemoryFence ( __asm__ __volatile__ ("":::"memory"); } =20 - -/** - Enables CPU interrupts. - - Enables CPU interrupts. - -**/ -VOID -EFIAPI -EnableInterrupts ( - VOID - ) -{ - __asm__ __volatile__ ("sti"::: "memory"); -} - - -/** - Disables CPU interrupts. - - Disables CPU interrupts. - -**/ -VOID -EFIAPI -DisableInterrupts ( - VOID - ) -{ - __asm__ __volatile__ ("cli"::: "memory"); -} - - - - /** Requests CPU to pause for a short period of time. =20 @@ -82,7 +45,6 @@ CpuPause ( __asm__ __volatile__ ("pause"); } =20 - /** Generates a breakpoint on the CPU. =20 @@ -99,75 +61,6 @@ CpuBreakpoint ( __asm__ __volatile__ ("int $3"); } =20 - - -/** - Returns a 64-bit Machine Specific Register(MSR). - - Reads and returns the 64-bit MSR specified by Index. No parameter checki= ng is - performed on Index, and some Index values may cause CPU exceptions. The - caller must either guarantee that Index is valid, or the caller must set= up - exception handlers to catch the exceptions. This function is only availa= ble - on IA-32 and X64. - - @param Index The 32-bit MSR index to read. - - @return The value of the MSR identified by Index. - -**/ -UINT64 -EFIAPI -AsmReadMsr64 ( - IN UINT32 Index - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "rdmsr" - : "=3DA" (Data) // %0 - : "c" (Index) // %1 - ); - - return Data; -} - -/** - Writes a 64-bit value to a Machine Specific Register(MSR), and returns t= he - value. - - Writes the 64-bit value specified by Value to the MSR specified by Index= . The - 64-bit value written to the MSR is returned. No parameter checking is - performed on Index or Value, and some of these may cause CPU exceptions.= The - caller must either guarantee that Index and Value are valid, or the call= er - must establish proper exception handlers. This function is only availabl= e on - IA-32 and X64. - - @param Index The 32-bit MSR index to write. - @param Value The 64-bit value to write to the MSR. - - @return Value - -**/ -UINT64 -EFIAPI -AsmWriteMsr64 ( - IN UINT32 Index, - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "wrmsr" - : - : "c" (Index), - "A" (Value) - ); - - return Value; -} - - - /** Reads the current value of the EFLAGS register. =20 @@ -195,965 +88,6 @@ AsmReadEflags ( return Eflags; } =20 - - -/** - Reads the current value of the Control Register 0 (CR0). - - Reads and returns the current value of CR0. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of the Control Register 0 (CR0). - -**/ -UINTN -EFIAPI -AsmReadCr0 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%cr0,%0" - : "=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of the Control Register 2 (CR2). - - Reads and returns the current value of CR2. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of the Control Register 2 (CR2). - -**/ -UINTN -EFIAPI -AsmReadCr2 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%cr2, %0" - : "=3Dr" (Data) - ); - - return Data; -} - -/** - Reads the current value of the Control Register 3 (CR3). - - Reads and returns the current value of CR3. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of the Control Register 3 (CR3). - -**/ -UINTN -EFIAPI -AsmReadCr3 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%cr3, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of the Control Register 4 (CR4). - - Reads and returns the current value of CR4. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of the Control Register 4 (CR4). - -**/ -UINTN -EFIAPI -AsmReadCr4 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%cr4, %0" - : "=3Da" (Data) - ); - - return Data; -} - - -/** - Writes a value to Control Register 0 (CR0). - - Writes and returns a new value to CR0. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Cr0 The value to write to CR0. - - @return The value written to CR0. - -**/ -UINTN -EFIAPI -AsmWriteCr0 ( - UINTN Cr0 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%cr0" - : - : "r" (Cr0) - ); - return Cr0; -} - - -/** - Writes a value to Control Register 2 (CR2). - - Writes and returns a new value to CR2. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Cr2 The value to write to CR2. - - @return The value written to CR2. - -**/ -UINTN -EFIAPI -AsmWriteCr2 ( - UINTN Cr2 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%cr2" - : - : "r" (Cr2) - ); - return Cr2; -} - - -/** - Writes a value to Control Register 3 (CR3). - - Writes and returns a new value to CR3. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Cr3 The value to write to CR3. - - @return The value written to CR3. - -**/ -UINTN -EFIAPI -AsmWriteCr3 ( - UINTN Cr3 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%cr3" - : - : "r" (Cr3) - ); - return Cr3; -} - - -/** - Writes a value to Control Register 4 (CR4). - - Writes and returns a new value to CR4. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Cr4 The value to write to CR4. - - @return The value written to CR4. - -**/ -UINTN -EFIAPI -AsmWriteCr4 ( - UINTN Cr4 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%cr4" - : - : "r" (Cr4) - ); - return Cr4; -} - - -/** - Reads the current value of Debug Register 0 (DR0). - - Reads and returns the current value of DR0. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 0 (DR0). - -**/ -UINTN -EFIAPI -AsmReadDr0 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%dr0, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 1 (DR1). - - Reads and returns the current value of DR1. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 1 (DR1). - -**/ -UINTN -EFIAPI -AsmReadDr1 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%dr1, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 2 (DR2). - - Reads and returns the current value of DR2. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 2 (DR2). - -**/ -UINTN -EFIAPI -AsmReadDr2 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%dr2, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 3 (DR3). - - Reads and returns the current value of DR3. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 3 (DR3). - -**/ -UINTN -EFIAPI -AsmReadDr3 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%dr3, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 4 (DR4). - - Reads and returns the current value of DR4. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 4 (DR4). - -**/ -UINTN -EFIAPI -AsmReadDr4 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%dr4, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 5 (DR5). - - Reads and returns the current value of DR5. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 5 (DR5). - -**/ -UINTN -EFIAPI -AsmReadDr5 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%dr5, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 6 (DR6). - - Reads and returns the current value of DR6. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 6 (DR6). - -**/ -UINTN -EFIAPI -AsmReadDr6 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%dr6, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 7 (DR7). - - Reads and returns the current value of DR7. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 7 (DR7). - -**/ -UINTN -EFIAPI -AsmReadDr7 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "movl %%dr7, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Writes a value to Debug Register 0 (DR0). - - Writes and returns a new value to DR0. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr0 The value to write to Dr0. - - @return The value written to Debug Register 0 (DR0). - -**/ -UINTN -EFIAPI -AsmWriteDr0 ( - UINTN Dr0 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%dr0" - : - : "r" (Dr0) - ); - return Dr0; -} - - -/** - Writes a value to Debug Register 1 (DR1). - - Writes and returns a new value to DR1. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr1 The value to write to Dr1. - - @return The value written to Debug Register 1 (DR1). - -**/ -UINTN -EFIAPI -AsmWriteDr1 ( - UINTN Dr1 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%dr1" - : - : "r" (Dr1) - ); - return Dr1; -} - - -/** - Writes a value to Debug Register 2 (DR2). - - Writes and returns a new value to DR2. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr2 The value to write to Dr2. - - @return The value written to Debug Register 2 (DR2). - -**/ -UINTN -EFIAPI -AsmWriteDr2 ( - UINTN Dr2 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%dr2" - : - : "r" (Dr2) - ); - return Dr2; -} - - -/** - Writes a value to Debug Register 3 (DR3). - - Writes and returns a new value to DR3. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr3 The value to write to Dr3. - - @return The value written to Debug Register 3 (DR3). - -**/ -UINTN -EFIAPI -AsmWriteDr3 ( - UINTN Dr3 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%dr3" - : - : "r" (Dr3) - ); - return Dr3; -} - - -/** - Writes a value to Debug Register 4 (DR4). - - Writes and returns a new value to DR4. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr4 The value to write to Dr4. - - @return The value written to Debug Register 4 (DR4). - -**/ -UINTN -EFIAPI -AsmWriteDr4 ( - UINTN Dr4 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%dr4" - : - : "r" (Dr4) - ); - return Dr4; -} - - -/** - Writes a value to Debug Register 5 (DR5). - - Writes and returns a new value to DR5. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr5 The value to write to Dr5. - - @return The value written to Debug Register 5 (DR5). - -**/ -UINTN -EFIAPI -AsmWriteDr5 ( - UINTN Dr5 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%dr5" - : - : "r" (Dr5) - ); - return Dr5; -} - - -/** - Writes a value to Debug Register 6 (DR6). - - Writes and returns a new value to DR6. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr6 The value to write to Dr6. - - @return The value written to Debug Register 6 (DR6). - -**/ -UINTN -EFIAPI -AsmWriteDr6 ( - UINTN Dr6 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%dr6" - : - : "r" (Dr6) - ); - return Dr6; -} - - -/** - Writes a value to Debug Register 7 (DR7). - - Writes and returns a new value to DR7. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr7 The value to write to Dr7. - - @return The value written to Debug Register 7 (DR7). - -**/ -UINTN -EFIAPI -AsmWriteDr7 ( - UINTN Dr7 - ) -{ - __asm__ __volatile__ ( - "movl %0, %%dr7" - : - : "r" (Dr7) - ); - return Dr7; -} - - -/** - Reads the current value of Code Segment Register (CS). - - Reads and returns the current value of CS. This function is only availab= le on - IA-32 and X64. - - @return The current value of CS. - -**/ -UINT16 -EFIAPI -AsmReadCs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%cs, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Data Segment Register (DS). - - Reads and returns the current value of DS. This function is only availab= le on - IA-32 and X64. - - @return The current value of DS. - -**/ -UINT16 -EFIAPI -AsmReadDs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%ds, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Extra Segment Register (ES). - - Reads and returns the current value of ES. This function is only availab= le on - IA-32 and X64. - - @return The current value of ES. - -**/ -UINT16 -EFIAPI -AsmReadEs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%es, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of FS Data Segment Register (FS). - - Reads and returns the current value of FS. This function is only availab= le on - IA-32 and X64. - - @return The current value of FS. - -**/ -UINT16 -EFIAPI -AsmReadFs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%fs, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of GS Data Segment Register (GS). - - Reads and returns the current value of GS. This function is only availab= le on - IA-32 and X64. - - @return The current value of GS. - -**/ -UINT16 -EFIAPI -AsmReadGs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%gs, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Stack Segment Register (SS). - - Reads and returns the current value of SS. This function is only availab= le on - IA-32 and X64. - - @return The current value of SS. - -**/ -UINT16 -EFIAPI -AsmReadSs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%ds, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Task Register (TR). - - Reads and returns the current value of TR. This function is only availab= le on - IA-32 and X64. - - @return The current value of TR. - -**/ -UINT16 -EFIAPI -AsmReadTr ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "str %0" - : "=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current Global Descriptor Table Register(GDTR) descriptor. - - Reads and returns the current GDTR descriptor and returns it in Gdtr. Th= is - function is only available on IA-32 and X64. - - @param Gdtr The pointer to a GDTR descriptor. - -**/ -VOID -EFIAPI -InternalX86ReadGdtr ( - OUT IA32_DESCRIPTOR *Gdtr - ) -{ - __asm__ __volatile__ ( - "sgdt %0" - : "=3Dm" (*Gdtr) - ); -} - - -/** - Writes the current Global Descriptor Table Register (GDTR) descriptor. - - Writes and the current GDTR descriptor specified by Gdtr. This function = is - only available on IA-32 and X64. - - @param Gdtr The pointer to a GDTR descriptor. - -**/ -VOID -EFIAPI -InternalX86WriteGdtr ( - IN CONST IA32_DESCRIPTOR *Gdtr - ) -{ - __asm__ __volatile__ ( - "lgdt %0" - : - : "m" (*Gdtr) - ); - -} - - -/** - Reads the current Interrupt Descriptor Table Register(GDTR) descriptor. - - Reads and returns the current IDTR descriptor and returns it in Idtr. Th= is - function is only available on IA-32 and X64. - - @param Idtr The pointer to a IDTR descriptor. - -**/ -VOID -EFIAPI -InternalX86ReadIdtr ( - OUT IA32_DESCRIPTOR *Idtr - ) -{ - __asm__ __volatile__ ( - "sidt %0" - : "=3Dm" (*Idtr) - ); -} - - -/** - Writes the current Interrupt Descriptor Table Register(GDTR) descriptor. - - Writes the current IDTR descriptor and returns it in Idtr. This function= is - only available on IA-32 and X64. - - @param Idtr The pointer to a IDTR descriptor. - -**/ -VOID -EFIAPI -InternalX86WriteIdtr ( - IN CONST IA32_DESCRIPTOR *Idtr - ) -{ - __asm__ __volatile__ ( - "lidt %0" - : - : "m" (*Idtr) - ); -} - - -/** - Reads the current Local Descriptor Table Register(LDTR) selector. - - Reads and returns the current 16-bit LDTR descriptor value. This functio= n is - only available on IA-32 and X64. - - @return The current selector of LDT. - -**/ -UINT16 -EFIAPI -AsmReadLdtr ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "sldt %0" - : "=3Dg" (Data) // %0 - ); - - return Data; -} - - -/** - Writes the current Local Descriptor Table Register (GDTR) selector. - - Writes and the current LDTR descriptor specified by Ldtr. This function = is - only available on IA-32 and X64. - - @param Ldtr 16-bit LDTR selector value. - -**/ -VOID -EFIAPI -AsmWriteLdtr ( - IN UINT16 Ldtr - ) -{ - __asm__ __volatile__ ( - "lldtw %0" - : - : "g" (Ldtr) // %0 - ); -} - - /** Save the current floating point/SSE/SSE2 context to a buffer. =20 @@ -1650,116 +584,3 @@ AsmReadTsc ( =20 return Data; } - - -/** - Reads the current value of a Performance Counter (PMC). - - Reads and returns the current value of performance counter specified by - Index. This function is only available on IA-32 and X64. - - @param Index The 32-bit Performance Counter index to read. - - @return The value of the PMC specified by Index. - -**/ -UINT64 -EFIAPI -AsmReadPmc ( - IN UINT32 Index - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "rdpmc" - : "=3DA" (Data) - : "c" (Index) - ); - - return Data; -} - - - - -/** - Executes a WBINVD instruction. - - Executes a WBINVD instruction. This function is only available on IA-32 = and - X64. - -**/ -VOID -EFIAPI -AsmWbinvd ( - VOID - ) -{ - __asm__ __volatile__ ("wbinvd":::"memory"); -} - - -/** - Executes a INVD instruction. - - Executes a INVD instruction. This function is only available on IA-32 and - X64. - -**/ -VOID -EFIAPI -AsmInvd ( - VOID - ) -{ - __asm__ __volatile__ ("invd":::"memory"); - -} - - -/** - Flushes a cache line from all the instruction and data caches within the - coherency domain of the CPU. - - Flushed the cache line specified by LinearAddress, and returns LinearAdd= ress. - This function is only available on IA-32 and X64. - - @param LinearAddress The address of the cache line to flush. If the CPU= is - in a physical addressing mode, then LinearAddress = is a - physical address. If the CPU is in a virtual - addressing mode, then LinearAddress is a virtual - address. - - @return LinearAddress -**/ -VOID * -EFIAPI -AsmFlushCacheLine ( - IN VOID *LinearAddress - ) -{ - UINT32 RegEdx; - - // - // If the CPU does not support CLFLUSH instruction, - // then promote flush range to flush entire cache. - // - AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx); - if ((RegEdx & BIT19) =3D=3D 0) { - __asm__ __volatile__ ("wbinvd":::"memory"); - return LinearAddress; - } - - - __asm__ __volatile__ ( - "clflush (%0)" - : "+a" (LinearAddress) - : - : "memory" - ); - - return LinearAddress; -} - - diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseL= ib/Ia32/GccInlinePriv.c similarity index 62% copy from MdePkg/Library/BaseLib/Ia32/GccInline.c copy to MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c index 5287200f87..30aa63243b 100644 --- a/MdePkg/Library/BaseLib/Ia32/GccInline.c +++ b/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c @@ -1,7 +1,8 @@ /** @file - GCC inline implementation of BaseLib processor specific functions. + GCC inline implementation of BaseLib processor specific functions that u= se + privlidged instructions. =20 - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -10,28 +11,6 @@ =20 #include "BaseLibInternals.h" =20 - - -/** - Used to serialize load and store operations. - - All loads and stores that proceed calls to this function are guaranteed = to be - globally visible when this function returns. - -**/ -VOID -EFIAPI -MemoryFence ( - VOID - ) -{ - // This is a little bit of overkill and it is more about the compiler th= at it is - // actually processor synchronization. This is like the _ReadWriteBarrier - // Microsoft specific intrinsic - __asm__ __volatile__ ("":::"memory"); -} - - /** Enables CPU interrupts. =20 @@ -63,44 +42,6 @@ DisableInterrupts ( __asm__ __volatile__ ("cli"::: "memory"); } =20 - - - -/** - Requests CPU to pause for a short period of time. - - Requests CPU to pause for a short period of time. Typically used in MP - systems to prevent memory starvation while waiting for a spin lock. - -**/ -VOID -EFIAPI -CpuPause ( - VOID - ) -{ - __asm__ __volatile__ ("pause"); -} - - -/** - Generates a breakpoint on the CPU. - - Generates a breakpoint on the CPU. The breakpoint must be implemented su= ch - that code can resume normal execution after the breakpoint. - -**/ -VOID -EFIAPI -CpuBreakpoint ( - VOID - ) -{ - __asm__ __volatile__ ("int $3"); -} - - - /** Returns a 64-bit Machine Specific Register(MSR). =20 @@ -166,37 +107,6 @@ AsmWriteMsr64 ( return Value; } =20 - - -/** - Reads the current value of the EFLAGS register. - - Reads and returns the current value of the EFLAGS register. This functio= n is - only available on IA-32 and X64. This returns a 32-bit value on IA-32 an= d a - 64-bit value on X64. - - @return EFLAGS on IA-32 or RFLAGS on X64. - -**/ -UINTN -EFIAPI -AsmReadEflags ( - VOID - ) -{ - UINTN Eflags; - - __asm__ __volatile__ ( - "pushfl \n\t" - "popl %0 " - : "=3Dr" (Eflags) - ); - - return Eflags; -} - - - /** Reads the current value of the Control Register 0 (CR0). =20 @@ -1153,505 +1063,6 @@ AsmWriteLdtr ( ); } =20 - -/** - Save the current floating point/SSE/SSE2 context to a buffer. - - Saves the current floating point/SSE/SSE2 state to the buffer specified = by - Buffer. Buffer must be aligned on a 16-byte boundary. This function is o= nly - available on IA-32 and X64. - - @param Buffer The pointer to a buffer to save the floating point/SSE/S= SE2 context. - -**/ -VOID -EFIAPI -InternalX86FxSave ( - OUT IA32_FX_BUFFER *Buffer - ) -{ - __asm__ __volatile__ ( - "fxsave %0" - : - : "m" (*Buffer) // %0 - ); -} - - -/** - Restores the current floating point/SSE/SSE2 context from a buffer. - - Restores the current floating point/SSE/SSE2 state from the buffer speci= fied - by Buffer. Buffer must be aligned on a 16-byte boundary. This function is - only available on IA-32 and X64. - - @param Buffer The pointer to a buffer to save the floating point/SSE/S= SE2 context. - -**/ -VOID -EFIAPI -InternalX86FxRestore ( - IN CONST IA32_FX_BUFFER *Buffer - ) -{ - __asm__ __volatile__ ( - "fxrstor %0" - : - : "m" (*Buffer) // %0 - ); -} - - -/** - Reads the current value of 64-bit MMX Register #0 (MM0). - - Reads and returns the current value of MM0. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM0. - -**/ -UINT64 -EFIAPI -AsmReadMm0 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "push %%eax \n\t" - "push %%eax \n\t" - "movq %%mm0, (%%esp)\n\t" - "pop %%eax \n\t" - "pop %%edx \n\t" - : "=3DA" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #1 (MM1). - - Reads and returns the current value of MM1. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM1. - -**/ -UINT64 -EFIAPI -AsmReadMm1 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "push %%eax \n\t" - "push %%eax \n\t" - "movq %%mm1, (%%esp)\n\t" - "pop %%eax \n\t" - "pop %%edx \n\t" - : "=3DA" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #2 (MM2). - - Reads and returns the current value of MM2. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM2. - -**/ -UINT64 -EFIAPI -AsmReadMm2 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "push %%eax \n\t" - "push %%eax \n\t" - "movq %%mm2, (%%esp)\n\t" - "pop %%eax \n\t" - "pop %%edx \n\t" - : "=3DA" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #3 (MM3). - - Reads and returns the current value of MM3. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM3. - -**/ -UINT64 -EFIAPI -AsmReadMm3 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "push %%eax \n\t" - "push %%eax \n\t" - "movq %%mm3, (%%esp)\n\t" - "pop %%eax \n\t" - "pop %%edx \n\t" - : "=3DA" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #4 (MM4). - - Reads and returns the current value of MM4. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM4. - -**/ -UINT64 -EFIAPI -AsmReadMm4 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "push %%eax \n\t" - "push %%eax \n\t" - "movq %%mm4, (%%esp)\n\t" - "pop %%eax \n\t" - "pop %%edx \n\t" - : "=3DA" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #5 (MM5). - - Reads and returns the current value of MM5. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM5. - -**/ -UINT64 -EFIAPI -AsmReadMm5 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "push %%eax \n\t" - "push %%eax \n\t" - "movq %%mm5, (%%esp)\n\t" - "pop %%eax \n\t" - "pop %%edx \n\t" - : "=3DA" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #6 (MM6). - - Reads and returns the current value of MM6. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM6. - -**/ -UINT64 -EFIAPI -AsmReadMm6 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "push %%eax \n\t" - "push %%eax \n\t" - "movq %%mm6, (%%esp)\n\t" - "pop %%eax \n\t" - "pop %%edx \n\t" - : "=3DA" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #7 (MM7). - - Reads and returns the current value of MM7. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM7. - -**/ -UINT64 -EFIAPI -AsmReadMm7 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "push %%eax \n\t" - "push %%eax \n\t" - "movq %%mm7, (%%esp)\n\t" - "pop %%eax \n\t" - "pop %%edx \n\t" - : "=3DA" (Data) // %0 - ); - - return Data; -} - - -/** - Writes the current value of 64-bit MMX Register #0 (MM0). - - Writes the current value of MM0. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM0. - -**/ -VOID -EFIAPI -AsmWriteMm0 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movq %0, %%mm0" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #1 (MM1). - - Writes the current value of MM1. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM1. - -**/ -VOID -EFIAPI -AsmWriteMm1 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movq %0, %%mm1" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #2 (MM2). - - Writes the current value of MM2. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM2. - -**/ -VOID -EFIAPI -AsmWriteMm2 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movq %0, %%mm2" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #3 (MM3). - - Writes the current value of MM3. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM3. - -**/ -VOID -EFIAPI -AsmWriteMm3 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movq %0, %%mm3" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #4 (MM4). - - Writes the current value of MM4. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM4. - -**/ -VOID -EFIAPI -AsmWriteMm4 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movq %0, %%mm4" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #5 (MM5). - - Writes the current value of MM5. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM5. - -**/ -VOID -EFIAPI -AsmWriteMm5 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movq %0, %%mm5" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #6 (MM6). - - Writes the current value of MM6. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM6. - -**/ -VOID -EFIAPI -AsmWriteMm6 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movq %0, %%mm6" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #7 (MM7). - - Writes the current value of MM7. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM7. - -**/ -VOID -EFIAPI -AsmWriteMm7 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movq %0, %%mm7" // %0 - : - : "m" (Value) - ); -} - - -/** - Reads the current value of Time Stamp Counter (TSC). - - Reads and returns the current value of TSC. This function is only availa= ble - on IA-32 and X64. - - @return The current value of TSC - -**/ -UINT64 -EFIAPI -AsmReadTsc ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "rdtsc" - : "=3DA" (Data) - ); - - return Data; -} - - /** Reads the current value of a Performance Counter (PMC). =20 @@ -1680,9 +1091,6 @@ AsmReadPmc ( return Data; } =20 - - - /** Executes a WBINVD instruction. =20 @@ -1699,7 +1107,6 @@ AsmWbinvd ( __asm__ __volatile__ ("wbinvd":::"memory"); } =20 - /** Executes a INVD instruction. =20 @@ -1761,5 +1168,3 @@ AsmFlushCacheLine ( =20 return LinearAddress; } - - diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c b/MdePkg/Library/BaseLi= b/X64/GccInline.c index 154ce1f57e..40a208f198 100644 --- a/MdePkg/Library/BaseLib/X64/GccInline.c +++ b/MdePkg/Library/BaseLib/X64/GccInline.c @@ -1,7 +1,7 @@ /** @file GCC inline implementation of BaseLib processor specific functions. =20 - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -33,40 +33,6 @@ MemoryFence ( } =20 =20 -/** - Enables CPU interrupts. - - Enables CPU interrupts. - -**/ -VOID -EFIAPI -EnableInterrupts ( - VOID - ) -{ - __asm__ __volatile__ ("sti"::: "memory"); -} - - -/** - Disables CPU interrupts. - - Disables CPU interrupts. - -**/ -VOID -EFIAPI -DisableInterrupts ( - VOID - ) -{ - __asm__ __volatile__ ("cli"::: "memory"); -} - - - - /** Requests CPU to pause for a short period of time. =20 @@ -101,83 +67,6 @@ CpuBreakpoint ( } =20 =20 - -/** - Returns a 64-bit Machine Specific Register(MSR). - - Reads and returns the 64-bit MSR specified by Index. No parameter checki= ng is - performed on Index, and some Index values may cause CPU exceptions. The - caller must either guarantee that Index is valid, or the caller must set= up - exception handlers to catch the exceptions. This function is only availa= ble - on IA-32 and X64. - - @param Index The 32-bit MSR index to read. - - @return The value of the MSR identified by Index. - -**/ -UINT64 -EFIAPI -AsmReadMsr64 ( - IN UINT32 Index - ) -{ - UINT32 LowData; - UINT32 HighData; - - __asm__ __volatile__ ( - "rdmsr" - : "=3Da" (LowData), // %0 - "=3Dd" (HighData) // %1 - : "c" (Index) // %2 - ); - - return (((UINT64)HighData) << 32) | LowData; -} - -/** - Writes a 64-bit value to a Machine Specific Register(MSR), and returns t= he - value. - - Writes the 64-bit value specified by Value to the MSR specified by Index= . The - 64-bit value written to the MSR is returned. No parameter checking is - performed on Index or Value, and some of these may cause CPU exceptions.= The - caller must either guarantee that Index and Value are valid, or the call= er - must establish proper exception handlers. This function is only availabl= e on - IA-32 and X64. - - @param Index The 32-bit MSR index to write. - @param Value The 64-bit value to write to the MSR. - - @return Value - -**/ -UINT64 -EFIAPI -AsmWriteMsr64 ( - IN UINT32 Index, - IN UINT64 Value - ) -{ - UINT32 LowData; - UINT32 HighData; - - LowData =3D (UINT32)(Value); - HighData =3D (UINT32)(Value >> 32); - - __asm__ __volatile__ ( - "wrmsr" - : - : "c" (Index), - "a" (LowData), - "d" (HighData) - ); - - return Value; -} - - - /** Reads the current value of the EFLAGS register. =20 @@ -205,965 +94,6 @@ AsmReadEflags ( return Eflags; } =20 - - -/** - Reads the current value of the Control Register 0 (CR0). - - Reads and returns the current value of CR0. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of the Control Register 0 (CR0). - -**/ -UINTN -EFIAPI -AsmReadCr0 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%cr0,%0" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of the Control Register 2 (CR2). - - Reads and returns the current value of CR2. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of the Control Register 2 (CR2). - -**/ -UINTN -EFIAPI -AsmReadCr2 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%cr2, %0" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - -/** - Reads the current value of the Control Register 3 (CR3). - - Reads and returns the current value of CR3. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of the Control Register 3 (CR3). - -**/ -UINTN -EFIAPI -AsmReadCr3 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%cr3, %0" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of the Control Register 4 (CR4). - - Reads and returns the current value of CR4. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of the Control Register 4 (CR4). - -**/ -UINTN -EFIAPI -AsmReadCr4 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%cr4, %0" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Writes a value to Control Register 0 (CR0). - - Writes and returns a new value to CR0. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Cr0 The value to write to CR0. - - @return The value written to CR0. - -**/ -UINTN -EFIAPI -AsmWriteCr0 ( - UINTN Cr0 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%cr0" - : - : "r" (Cr0) - ); - return Cr0; -} - - -/** - Writes a value to Control Register 2 (CR2). - - Writes and returns a new value to CR2. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Cr2 The value to write to CR2. - - @return The value written to CR2. - -**/ -UINTN -EFIAPI -AsmWriteCr2 ( - UINTN Cr2 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%cr2" - : - : "r" (Cr2) - ); - return Cr2; -} - - -/** - Writes a value to Control Register 3 (CR3). - - Writes and returns a new value to CR3. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Cr3 The value to write to CR3. - - @return The value written to CR3. - -**/ -UINTN -EFIAPI -AsmWriteCr3 ( - UINTN Cr3 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%cr3" - : - : "r" (Cr3) - ); - return Cr3; -} - - -/** - Writes a value to Control Register 4 (CR4). - - Writes and returns a new value to CR4. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Cr4 The value to write to CR4. - - @return The value written to CR4. - -**/ -UINTN -EFIAPI -AsmWriteCr4 ( - UINTN Cr4 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%cr4" - : - : "r" (Cr4) - ); - return Cr4; -} - - -/** - Reads the current value of Debug Register 0 (DR0). - - Reads and returns the current value of DR0. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 0 (DR0). - -**/ -UINTN -EFIAPI -AsmReadDr0 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%dr0, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 1 (DR1). - - Reads and returns the current value of DR1. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 1 (DR1). - -**/ -UINTN -EFIAPI -AsmReadDr1 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%dr1, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 2 (DR2). - - Reads and returns the current value of DR2. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 2 (DR2). - -**/ -UINTN -EFIAPI -AsmReadDr2 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%dr2, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 3 (DR3). - - Reads and returns the current value of DR3. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 3 (DR3). - -**/ -UINTN -EFIAPI -AsmReadDr3 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%dr3, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 4 (DR4). - - Reads and returns the current value of DR4. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 4 (DR4). - -**/ -UINTN -EFIAPI -AsmReadDr4 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%dr4, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 5 (DR5). - - Reads and returns the current value of DR5. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 5 (DR5). - -**/ -UINTN -EFIAPI -AsmReadDr5 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%dr5, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 6 (DR6). - - Reads and returns the current value of DR6. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 6 (DR6). - -**/ -UINTN -EFIAPI -AsmReadDr6 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%dr6, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Debug Register 7 (DR7). - - Reads and returns the current value of DR7. This function is only availa= ble - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on - X64. - - @return The value of Debug Register 7 (DR7). - -**/ -UINTN -EFIAPI -AsmReadDr7 ( - VOID - ) -{ - UINTN Data; - - __asm__ __volatile__ ( - "mov %%dr7, %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Writes a value to Debug Register 0 (DR0). - - Writes and returns a new value to DR0. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr0 The value to write to Dr0. - - @return The value written to Debug Register 0 (DR0). - -**/ -UINTN -EFIAPI -AsmWriteDr0 ( - UINTN Dr0 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%dr0" - : - : "r" (Dr0) - ); - return Dr0; -} - - -/** - Writes a value to Debug Register 1 (DR1). - - Writes and returns a new value to DR1. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr1 The value to write to Dr1. - - @return The value written to Debug Register 1 (DR1). - -**/ -UINTN -EFIAPI -AsmWriteDr1 ( - UINTN Dr1 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%dr1" - : - : "r" (Dr1) - ); - return Dr1; -} - - -/** - Writes a value to Debug Register 2 (DR2). - - Writes and returns a new value to DR2. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr2 The value to write to Dr2. - - @return The value written to Debug Register 2 (DR2). - -**/ -UINTN -EFIAPI -AsmWriteDr2 ( - UINTN Dr2 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%dr2" - : - : "r" (Dr2) - ); - return Dr2; -} - - -/** - Writes a value to Debug Register 3 (DR3). - - Writes and returns a new value to DR3. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr3 The value to write to Dr3. - - @return The value written to Debug Register 3 (DR3). - -**/ -UINTN -EFIAPI -AsmWriteDr3 ( - UINTN Dr3 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%dr3" - : - : "r" (Dr3) - ); - return Dr3; -} - - -/** - Writes a value to Debug Register 4 (DR4). - - Writes and returns a new value to DR4. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr4 The value to write to Dr4. - - @return The value written to Debug Register 4 (DR4). - -**/ -UINTN -EFIAPI -AsmWriteDr4 ( - UINTN Dr4 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%dr4" - : - : "r" (Dr4) - ); - return Dr4; -} - - -/** - Writes a value to Debug Register 5 (DR5). - - Writes and returns a new value to DR5. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr5 The value to write to Dr5. - - @return The value written to Debug Register 5 (DR5). - -**/ -UINTN -EFIAPI -AsmWriteDr5 ( - UINTN Dr5 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%dr5" - : - : "r" (Dr5) - ); - return Dr5; -} - - -/** - Writes a value to Debug Register 6 (DR6). - - Writes and returns a new value to DR6. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr6 The value to write to Dr6. - - @return The value written to Debug Register 6 (DR6). - -**/ -UINTN -EFIAPI -AsmWriteDr6 ( - UINTN Dr6 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%dr6" - : - : "r" (Dr6) - ); - return Dr6; -} - - -/** - Writes a value to Debug Register 7 (DR7). - - Writes and returns a new value to DR7. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on= X64. - - @param Dr7 The value to write to Dr7. - - @return The value written to Debug Register 7 (DR7). - -**/ -UINTN -EFIAPI -AsmWriteDr7 ( - UINTN Dr7 - ) -{ - __asm__ __volatile__ ( - "mov %0, %%dr7" - : - : "r" (Dr7) - ); - return Dr7; -} - - -/** - Reads the current value of Code Segment Register (CS). - - Reads and returns the current value of CS. This function is only availab= le on - IA-32 and X64. - - @return The current value of CS. - -**/ -UINT16 -EFIAPI -AsmReadCs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%cs, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Data Segment Register (DS). - - Reads and returns the current value of DS. This function is only availab= le on - IA-32 and X64. - - @return The current value of DS. - -**/ -UINT16 -EFIAPI -AsmReadDs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%ds, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Extra Segment Register (ES). - - Reads and returns the current value of ES. This function is only availab= le on - IA-32 and X64. - - @return The current value of ES. - -**/ -UINT16 -EFIAPI -AsmReadEs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%es, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of FS Data Segment Register (FS). - - Reads and returns the current value of FS. This function is only availab= le on - IA-32 and X64. - - @return The current value of FS. - -**/ -UINT16 -EFIAPI -AsmReadFs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%fs, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of GS Data Segment Register (GS). - - Reads and returns the current value of GS. This function is only availab= le on - IA-32 and X64. - - @return The current value of GS. - -**/ -UINT16 -EFIAPI -AsmReadGs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%gs, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Stack Segment Register (SS). - - Reads and returns the current value of SS. This function is only availab= le on - IA-32 and X64. - - @return The current value of SS. - -**/ -UINT16 -EFIAPI -AsmReadSs ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "mov %%ds, %0" - :"=3Da" (Data) - ); - - return Data; -} - - -/** - Reads the current value of Task Register (TR). - - Reads and returns the current value of TR. This function is only availab= le on - IA-32 and X64. - - @return The current value of TR. - -**/ -UINT16 -EFIAPI -AsmReadTr ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "str %0" - : "=3Dr" (Data) - ); - - return Data; -} - - -/** - Reads the current Global Descriptor Table Register(GDTR) descriptor. - - Reads and returns the current GDTR descriptor and returns it in Gdtr. Th= is - function is only available on IA-32 and X64. - - @param Gdtr The pointer to a GDTR descriptor. - -**/ -VOID -EFIAPI -InternalX86ReadGdtr ( - OUT IA32_DESCRIPTOR *Gdtr - ) -{ - __asm__ __volatile__ ( - "sgdt %0" - : "=3Dm" (*Gdtr) - ); -} - - -/** - Writes the current Global Descriptor Table Register (GDTR) descriptor. - - Writes and the current GDTR descriptor specified by Gdtr. This function = is - only available on IA-32 and X64. - - @param Gdtr The pointer to a GDTR descriptor. - -**/ -VOID -EFIAPI -InternalX86WriteGdtr ( - IN CONST IA32_DESCRIPTOR *Gdtr - ) -{ - __asm__ __volatile__ ( - "lgdt %0" - : - : "m" (*Gdtr) - ); - -} - - -/** - Reads the current Interrupt Descriptor Table Register(GDTR) descriptor. - - Reads and returns the current IDTR descriptor and returns it in Idtr. Th= is - function is only available on IA-32 and X64. - - @param Idtr The pointer to a IDTR descriptor. - -**/ -VOID -EFIAPI -InternalX86ReadIdtr ( - OUT IA32_DESCRIPTOR *Idtr - ) -{ - __asm__ __volatile__ ( - "sidt %0" - : "=3Dm" (*Idtr) - ); -} - - -/** - Writes the current Interrupt Descriptor Table Register(GDTR) descriptor. - - Writes the current IDTR descriptor and returns it in Idtr. This function= is - only available on IA-32 and X64. - - @param Idtr The pointer to a IDTR descriptor. - -**/ -VOID -EFIAPI -InternalX86WriteIdtr ( - IN CONST IA32_DESCRIPTOR *Idtr - ) -{ - __asm__ __volatile__ ( - "lidt %0" - : - : "m" (*Idtr) - ); -} - - -/** - Reads the current Local Descriptor Table Register(LDTR) selector. - - Reads and returns the current 16-bit LDTR descriptor value. This functio= n is - only available on IA-32 and X64. - - @return The current selector of LDT. - -**/ -UINT16 -EFIAPI -AsmReadLdtr ( - VOID - ) -{ - UINT16 Data; - - __asm__ __volatile__ ( - "sldt %0" - : "=3Dg" (Data) // %0 - ); - - return Data; -} - - -/** - Writes the current Local Descriptor Table Register (GDTR) selector. - - Writes and the current LDTR descriptor specified by Ldtr. This function = is - only available on IA-32 and X64. - - @param Ldtr 16-bit LDTR selector value. - -**/ -VOID -EFIAPI -AsmWriteLdtr ( - IN UINT16 Ldtr - ) -{ - __asm__ __volatile__ ( - "lldtw %0" - : - : "g" (Ldtr) // %0 - ); -} - - /** Save the current floating point/SSE/SSE2 context to a buffer. =20 @@ -1630,171 +560,3 @@ AsmReadTsc ( =20 return (((UINT64)HiData) << 32) | LowData; } - - -/** - Reads the current value of a Performance Counter (PMC). - - Reads and returns the current value of performance counter specified by - Index. This function is only available on IA-32 and X64. - - @param Index The 32-bit Performance Counter index to read. - - @return The value of the PMC specified by Index. - -**/ -UINT64 -EFIAPI -AsmReadPmc ( - IN UINT32 Index - ) -{ - UINT32 LowData; - UINT32 HiData; - - __asm__ __volatile__ ( - "rdpmc" - : "=3Da" (LowData), - "=3Dd" (HiData) - : "c" (Index) - ); - - return (((UINT64)HiData) << 32) | LowData; -} - - -/** - Sets up a monitor buffer that is used by AsmMwait(). - - Executes a MONITOR instruction with the register state specified by Eax,= Ecx - and Edx. Returns Eax. This function is only available on IA-32 and X64. - - @param Eax The value to load into EAX or RAX before executing the MONIT= OR - instruction. - @param Ecx The value to load into ECX or RCX before executing the MONIT= OR - instruction. - @param Edx The value to load into EDX or RDX before executing the MONIT= OR - instruction. - - @return Eax - -**/ -UINTN -EFIAPI -AsmMonitor ( - IN UINTN Eax, - IN UINTN Ecx, - IN UINTN Edx - ) -{ - __asm__ __volatile__ ( - "monitor" - : - : "a" (Eax), - "c" (Ecx), - "d" (Edx) - ); - - return Eax; -} - - -/** - Executes an MWAIT instruction. - - Executes an MWAIT instruction with the register state specified by Eax a= nd - Ecx. Returns Eax. This function is only available on IA-32 and X64. - - @param Eax The value to load into EAX or RAX before executing the MONIT= OR - instruction. - @param Ecx The value to load into ECX or RCX before executing the MONIT= OR - instruction. - - @return Eax - -**/ -UINTN -EFIAPI -AsmMwait ( - IN UINTN Eax, - IN UINTN Ecx - ) -{ - __asm__ __volatile__ ( - "mwait" - : - : "a" (Eax), - "c" (Ecx) - ); - - return Eax; -} - - -/** - Executes a WBINVD instruction. - - Executes a WBINVD instruction. This function is only available on IA-32 = and - X64. - -**/ -VOID -EFIAPI -AsmWbinvd ( - VOID - ) -{ - __asm__ __volatile__ ("wbinvd":::"memory"); -} - - -/** - Executes a INVD instruction. - - Executes a INVD instruction. This function is only available on IA-32 and - X64. - -**/ -VOID -EFIAPI -AsmInvd ( - VOID - ) -{ - __asm__ __volatile__ ("invd":::"memory"); - -} - - -/** - Flushes a cache line from all the instruction and data caches within the - coherency domain of the CPU. - - Flushed the cache line specified by LinearAddress, and returns LinearAdd= ress. - This function is only available on IA-32 and X64. - - @param LinearAddress The address of the cache line to flush. If the CPU= is - in a physical addressing mode, then LinearAddress = is a - physical address. If the CPU is in a virtual - addressing mode, then LinearAddress is a virtual - address. - - @return LinearAddress -**/ -VOID * -EFIAPI -AsmFlushCacheLine ( - IN VOID *LinearAddress - ) -{ - __asm__ __volatile__ ( - "clflush (%0)" - : - : "r" (LinearAddress) - : "memory" - ); - - return LinearAddress; -} - - diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c b/MdePkg/Library/BaseLi= b/X64/GccInlinePriv.c similarity index 65% copy from MdePkg/Library/BaseLib/X64/GccInline.c copy to MdePkg/Library/BaseLib/X64/GccInlinePriv.c index 154ce1f57e..98be19b3c7 100644 --- a/MdePkg/Library/BaseLib/X64/GccInline.c +++ b/MdePkg/Library/BaseLib/X64/GccInlinePriv.c @@ -1,7 +1,8 @@ /** @file - GCC inline implementation of BaseLib processor specific functions. + GCC inline implementation of BaseLib processor specific functions that u= se + privlidged instructions. =20 - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -10,29 +11,6 @@ =20 #include "BaseLibInternals.h" =20 - - - -/** - Used to serialize load and store operations. - - All loads and stores that proceed calls to this function are guaranteed = to be - globally visible when this function returns. - -**/ -VOID -EFIAPI -MemoryFence ( - VOID - ) -{ - // This is a little bit of overkill and it is more about the compiler th= at it is - // actually processor synchronization. This is like the _ReadWriteBarrier - // Microsoft specific intrinsic - __asm__ __volatile__ ("":::"memory"); -} - - /** Enables CPU interrupts. =20 @@ -64,44 +42,6 @@ DisableInterrupts ( __asm__ __volatile__ ("cli"::: "memory"); } =20 - - - -/** - Requests CPU to pause for a short period of time. - - Requests CPU to pause for a short period of time. Typically used in MP - systems to prevent memory starvation while waiting for a spin lock. - -**/ -VOID -EFIAPI -CpuPause ( - VOID - ) -{ - __asm__ __volatile__ ("pause"); -} - - -/** - Generates a breakpoint on the CPU. - - Generates a breakpoint on the CPU. The breakpoint must be implemented su= ch - that code can resume normal execution after the breakpoint. - -**/ -VOID -EFIAPI -CpuBreakpoint ( - VOID - ) -{ - __asm__ __volatile__ ("int $3"); -} - - - /** Returns a 64-bit Machine Specific Register(MSR). =20 @@ -176,37 +116,6 @@ AsmWriteMsr64 ( return Value; } =20 - - -/** - Reads the current value of the EFLAGS register. - - Reads and returns the current value of the EFLAGS register. This functio= n is - only available on IA-32 and X64. This returns a 32-bit value on IA-32 an= d a - 64-bit value on X64. - - @return EFLAGS on IA-32 or RFLAGS on X64. - -**/ -UINTN -EFIAPI -AsmReadEflags ( - VOID - ) -{ - UINTN Eflags; - - __asm__ __volatile__ ( - "pushfq \n\t" - "pop %0 " - : "=3Dr" (Eflags) // %0 - ); - - return Eflags; -} - - - /** Reads the current value of the Control Register 0 (CR0). =20 @@ -1163,475 +1072,6 @@ AsmWriteLdtr ( ); } =20 - -/** - Save the current floating point/SSE/SSE2 context to a buffer. - - Saves the current floating point/SSE/SSE2 state to the buffer specified = by - Buffer. Buffer must be aligned on a 16-byte boundary. This function is o= nly - available on IA-32 and X64. - - @param Buffer The pointer to a buffer to save the floating point/SSE/S= SE2 context. - -**/ -VOID -EFIAPI -InternalX86FxSave ( - OUT IA32_FX_BUFFER *Buffer - ) -{ - __asm__ __volatile__ ( - "fxsave %0" - : - : "m" (*Buffer) // %0 - ); -} - - -/** - Restores the current floating point/SSE/SSE2 context from a buffer. - - Restores the current floating point/SSE/SSE2 state from the buffer speci= fied - by Buffer. Buffer must be aligned on a 16-byte boundary. This function is - only available on IA-32 and X64. - - @param Buffer The pointer to a buffer to save the floating point/SSE/S= SE2 context. - -**/ -VOID -EFIAPI -InternalX86FxRestore ( - IN CONST IA32_FX_BUFFER *Buffer - ) -{ - __asm__ __volatile__ ( - "fxrstor %0" - : - : "m" (*Buffer) // %0 - ); -} - - -/** - Reads the current value of 64-bit MMX Register #0 (MM0). - - Reads and returns the current value of MM0. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM0. - -**/ -UINT64 -EFIAPI -AsmReadMm0 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "movd %%mm0, %0 \n\t" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #1 (MM1). - - Reads and returns the current value of MM1. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM1. - -**/ -UINT64 -EFIAPI -AsmReadMm1 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "movd %%mm1, %0 \n\t" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #2 (MM2). - - Reads and returns the current value of MM2. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM2. - -**/ -UINT64 -EFIAPI -AsmReadMm2 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "movd %%mm2, %0 \n\t" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #3 (MM3). - - Reads and returns the current value of MM3. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM3. - -**/ -UINT64 -EFIAPI -AsmReadMm3 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "movd %%mm3, %0 \n\t" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #4 (MM4). - - Reads and returns the current value of MM4. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM4. - -**/ -UINT64 -EFIAPI -AsmReadMm4 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "movd %%mm4, %0 \n\t" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #5 (MM5). - - Reads and returns the current value of MM5. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM5. - -**/ -UINT64 -EFIAPI -AsmReadMm5 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "movd %%mm5, %0 \n\t" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #6 (MM6). - - Reads and returns the current value of MM6. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM6. - -**/ -UINT64 -EFIAPI -AsmReadMm6 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "movd %%mm6, %0 \n\t" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Reads the current value of 64-bit MMX Register #7 (MM7). - - Reads and returns the current value of MM7. This function is only availa= ble - on IA-32 and X64. - - @return The current value of MM7. - -**/ -UINT64 -EFIAPI -AsmReadMm7 ( - VOID - ) -{ - UINT64 Data; - - __asm__ __volatile__ ( - "movd %%mm7, %0 \n\t" - : "=3Dr" (Data) // %0 - ); - - return Data; -} - - -/** - Writes the current value of 64-bit MMX Register #0 (MM0). - - Writes the current value of MM0. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM0. - -**/ -VOID -EFIAPI -AsmWriteMm0 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movd %0, %%mm0" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #1 (MM1). - - Writes the current value of MM1. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM1. - -**/ -VOID -EFIAPI -AsmWriteMm1 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movd %0, %%mm1" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #2 (MM2). - - Writes the current value of MM2. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM2. - -**/ -VOID -EFIAPI -AsmWriteMm2 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movd %0, %%mm2" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #3 (MM3). - - Writes the current value of MM3. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM3. - -**/ -VOID -EFIAPI -AsmWriteMm3 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movd %0, %%mm3" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #4 (MM4). - - Writes the current value of MM4. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM4. - -**/ -VOID -EFIAPI -AsmWriteMm4 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movd %0, %%mm4" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #5 (MM5). - - Writes the current value of MM5. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM5. - -**/ -VOID -EFIAPI -AsmWriteMm5 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movd %0, %%mm5" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #6 (MM6). - - Writes the current value of MM6. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM6. - -**/ -VOID -EFIAPI -AsmWriteMm6 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movd %0, %%mm6" // %0 - : - : "m" (Value) - ); -} - - -/** - Writes the current value of 64-bit MMX Register #7 (MM7). - - Writes the current value of MM7. This function is only available on IA32= and - X64. - - @param Value The 64-bit value to write to MM7. - -**/ -VOID -EFIAPI -AsmWriteMm7 ( - IN UINT64 Value - ) -{ - __asm__ __volatile__ ( - "movd %0, %%mm7" // %0 - : - : "m" (Value) - ); -} - - -/** - Reads the current value of Time Stamp Counter (TSC). - - Reads and returns the current value of TSC. This function is only availa= ble - on IA-32 and X64. - - @return The current value of TSC - -**/ -UINT64 -EFIAPI -AsmReadTsc ( - VOID - ) -{ - UINT32 LowData; - UINT32 HiData; - - __asm__ __volatile__ ( - "rdtsc" - : "=3Da" (LowData), - "=3Dd" (HiData) - ); - - return (((UINT64)HiData) << 32) | LowData; -} - - /** Reads the current value of a Performance Counter (PMC). =20 @@ -1662,7 +1102,6 @@ AsmReadPmc ( return (((UINT64)HiData) << 32) | LowData; } =20 - /** Sets up a monitor buffer that is used by AsmMwait(). =20 @@ -1698,7 +1137,6 @@ AsmMonitor ( return Eax; } =20 - /** Executes an MWAIT instruction. =20 @@ -1730,7 +1168,6 @@ AsmMwait ( return Eax; } =20 - /** Executes a WBINVD instruction. =20 @@ -1747,7 +1184,6 @@ AsmWbinvd ( __asm__ __volatile__ ("wbinvd":::"memory"); } =20 - /** Executes a INVD instruction. =20 @@ -1796,5 +1232,3 @@ AsmFlushCacheLine ( =20 return LinearAddress; } - - --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62356): https://edk2.groups.io/g/devel/message/62356 Mute This Topic: https://groups.io/mt/75432216/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62359+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62359+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433353; cv=none; d=zohomail.com; s=zohoarc; b=L8oG+8nidAYKyQbgEsnEkHX/KAHKA+ef+i99Dpz0R/stMKsyKZcO/jqFMWXTnQiWeviaSPaohH20T9Sm5CjFxTCYbRk0aRogSoxsVQ3LG3914e7RSNVSapNBojwX1HoJteLyFObruRug676lNPvB6ZkkK/SlBzhbrO2CDUrS4gk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433353; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=iPgdatov4yY9xNZYtHrIjdRDwHzGrDt6VCHlw0ZeobU=; b=KDSYesmUR3wopAKB9CuEjMVC/RpiRlvZoFN65vlP4tb74PsnCVu2QPylbARuIytcA+4unuy/NawmdFI7edhOq+63M7aJVagLhc6FQhEGVWpPte3N4YDHm+IT1a9cvCysSwFtQ/K32xfXL4COVjoA3khvRvWdvh3r7YMxqHuSVgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62359+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433353690198.80043878508638; Fri, 10 Jul 2020 19:09:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id z3fuYY1788612xCK5zsF69zO; Fri, 10 Jul 2020 19:09:13 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.2145.1594433351713145665 for ; Fri, 10 Jul 2020 19:09:11 -0700 IronPort-SDR: nbQlQ3WRkamBp6nCUaHnT0rcdiQnloHtVuwqQHUZPS6mCcv+GDR4ellLaELhz/YF6Uy2DQWp8O 4s8WrzYixepg== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380543" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380543" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:10 -0700 IronPort-SDR: peJTRg04Vy2CRIuiOuZwEmiecn9464P59a23DAbQU3GXRt93bNJTsREHcVdOH0jCdEylLM+WMt csYk/54ZXEJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602260" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:09 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao , Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 05/16] MdePkg/Library/BaseLib: Add BaseLib instance for host based unit tests Date: Fri, 10 Jul 2020 19:08:53 -0700 Message-Id: <20200711020904.24116-6-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: ggdwRdoT2aASDKpTwGrlM0lix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433353; bh=wv74vLJLjqUcRaDBJDXyt1f/c+5LwmC2zELee+w3KsA=; h=Cc:Date:From:Reply-To:Subject:To; b=fcnJB7QE6Iwituj9WAulgqDEQFTe1SeRx/Q3I8KVggvlnoKc7sSEjO3L36YZU1xXxNG JsXrqYBse3CGeeCljk3hnCN091aPqHYKzTJB9RpqrrIzXYkVHrrJStahih7D75z53fuSl J2Y64jcAipAN9VBx39Duvcxpqj06R7IQJng= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2800 Add a new version of BaseLib that is safe for use from host based unit test applications. Host based unit test applications may need to provide implementations of some BaseLib functions that provide simple emulation to exercise the code under test. The structure UNIT_TEST_HOST_BASE_LIB is filled in with services that provide default emulation for BaseLib APIs that would normally generate exceptions in a host based unit test application. This structure allows an individual unit test to replace the default emulation of a BaseLib service with an alternate version that is required by a specific unit test. A global variable of type UNIT_TEST_HOST_BASE_LIB is provided through the new UnitTestHostBaseLib library class. Normally cmocka would be used to mock services the code under test calls. However, the BaseLib is used by the Unit Test Framework itself, so using a mocked interface is not possible. The use of a structure to provide hooks for unit test is not expected to be a common feature. It should only be required for libraries that are used by both the Unit Test Framework and the code under test where the code under test requires a different behavior than the Unit Test Framework. Cc: Liming Gao Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- MdePkg/Library/BaseLib/UnitTestHost.c | 140 + MdePkg/Library/BaseLib/UnitTestHost.h | 66 + .../Library/BaseLib/UnitTestHostBaseLib.inf | 217 ++ .../Library/BaseLib/UnitTestHostBaseLib.uni | 11 + MdePkg/Library/BaseLib/X86UnitTestHost.c | 2977 +++++++++++++++++ MdePkg/MdePkg.dec | 8 +- MdePkg/Test/MdePkgHostTest.dsc | 5 + .../Include/Library/UnitTestHostBaseLib.h | 582 ++++ 8 files changed, 4005 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseLib/UnitTestHost.c create mode 100644 MdePkg/Library/BaseLib/UnitTestHost.h create mode 100644 MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf create mode 100644 MdePkg/Library/BaseLib/UnitTestHostBaseLib.uni create mode 100644 MdePkg/Library/BaseLib/X86UnitTestHost.c create mode 100644 MdePkg/Test/UnitTest/Include/Library/UnitTestHostBaseLi= b.h diff --git a/MdePkg/Library/BaseLib/UnitTestHost.c b/MdePkg/Library/BaseLib= /UnitTestHost.c new file mode 100644 index 0000000000..79eec7caca --- /dev/null +++ b/MdePkg/Library/BaseLib/UnitTestHost.c @@ -0,0 +1,140 @@ +/** @file + Common Unit Test Host functions. + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UnitTestHost.h" + +/// +/// Module global variable for simple system emulation of interrupt state +/// +STATIC BOOLEAN mUnitTestHostBaseLibInterruptState; + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibEnableInterrupts ( + VOID + ) +{ + mUnitTestHostBaseLibInterruptState =3D TRUE; +} + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibDisableInterrupts ( + VOID + ) +{ + mUnitTestHostBaseLibInterruptState =3D FALSE; +} + +/** + Enables CPU interrupts for the smallest window required to capture any + pending interrupts. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibEnableDisableInterrupts ( + VOID + ) +{ + mUnitTestHostBaseLibInterruptState =3D FALSE; +} + +/** + Set the current CPU interrupt state. + + Sets the current CPU interrupt state to the state specified by + InterruptState. If InterruptState is TRUE, then interrupts are enabled. = If + InterruptState is FALSE, then interrupts are disabled. InterruptState is + returned. + + @param InterruptState TRUE if interrupts should enabled. FALSE if + interrupts should be disabled. + + @return InterruptState + +**/ +BOOLEAN +EFIAPI +UnitTestHostBaseLibGetInterruptState ( + VOID + ) +{ + return mUnitTestHostBaseLibInterruptState; +} + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +EnableInterrupts ( + VOID + ) +{ + gUnitTestHostBaseLib.Common->EnableInterrupts (); +} + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +DisableInterrupts ( + VOID + ) +{ + gUnitTestHostBaseLib.Common->DisableInterrupts (); +} + +/** + Enables CPU interrupts for the smallest window required to capture any + pending interrupts. + +**/ +VOID +EFIAPI +EnableDisableInterrupts ( + VOID + ) +{ + gUnitTestHostBaseLib.Common->EnableDisableInterrupts (); +} + +/** + Set the current CPU interrupt state. + + Sets the current CPU interrupt state to the state specified by + InterruptState. If InterruptState is TRUE, then interrupts are enabled. = If + InterruptState is FALSE, then interrupts are disabled. InterruptState is + returned. + + @param InterruptState TRUE if interrupts should enabled. FALSE if + interrupts should be disabled. + + @return InterruptState + +**/ +BOOLEAN +EFIAPI +GetInterruptState ( + VOID + ) +{ + return gUnitTestHostBaseLib.Common->GetInterruptState (); +} diff --git a/MdePkg/Library/BaseLib/UnitTestHost.h b/MdePkg/Library/BaseLib= /UnitTestHost.h new file mode 100644 index 0000000000..42bc6b7773 --- /dev/null +++ b/MdePkg/Library/BaseLib/UnitTestHost.h @@ -0,0 +1,66 @@ +/** @file + Unit Test Host functions. + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UNIT_TEST_HOST_H__ +#define __UNIT_TEST_HOST_H__ + +#include "BaseLibInternals.h" +#include + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibEnableInterrupts ( + VOID + ); + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibDisableInterrupts ( + VOID + ); + +/** + Enables CPU interrupts for the smallest window required to capture any + pending interrupts. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibEnableDisableInterrupts ( + VOID + ); + +/** + Set the current CPU interrupt state. + + Sets the current CPU interrupt state to the state specified by + InterruptState. If InterruptState is TRUE, then interrupts are enabled. = If + InterruptState is FALSE, then interrupts are disabled. InterruptState is + returned. + + @param InterruptState TRUE if interrupts should enabled. FALSE if + interrupts should be disabled. + + @return InterruptState + +**/ +BOOLEAN +EFIAPI +UnitTestHostBaseLibGetInterruptState ( + VOID + ); + +#endif diff --git a/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf b/MdePkg/Librar= y/BaseLib/UnitTestHostBaseLib.inf new file mode 100644 index 0000000000..01fda55bec --- /dev/null +++ b/MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf @@ -0,0 +1,217 @@ +## @file +# Base Library implementation for use with host based unit tests. +# +# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UnitTestHostBaseLib + MODULE_UNI_FILE =3D UnitTestHostBaseLib.uni + FILE_GUID =3D 9555A0D3-09BA-46C4-A51A-45198E3C765E + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.1 + LIBRARY_CLASS =3D BaseLib|HOST_APPLICATION + LIBRARY_CLASS =3D UnitTestHostBaseLib|HOST_APPLICATION + +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 +# + +[Sources] + CheckSum.c + SwitchStack.c + SwapBytes64.c + SwapBytes32.c + SwapBytes16.c + LongJump.c + SetJump.c + RShiftU64.c + RRotU64.c + RRotU32.c + MultU64x64.c + MultU64x32.c + MultS64x64.c + ModU64x32.c + LShiftU64.c + LRotU64.c + LRotU32.c + LowBitSet64.c + LowBitSet32.c + HighBitSet64.c + HighBitSet32.c + GetPowerOfTwo64.c + GetPowerOfTwo32.c + DivU64x64Remainder.c + DivU64x32Remainder.c + DivU64x32.c + DivS64x64Remainder.c + ARShiftU64.c + BitField.c + CpuDeadLoop.c + Cpu.c + LinkedList.c + SafeString.c + String.c + FilePaths.c + BaseLibInternals.h + UnitTestHost.c + UnitTestHost.h + +[Sources.Ia32] + Ia32/SwapBytes64.c | MSFT + Ia32/RRotU64.c | MSFT + Ia32/RShiftU64.c | MSFT + Ia32/ReadTsc.c | MSFT + Ia32/ReadEflags.c | MSFT + Ia32/ModU64x32.c | MSFT + Ia32/MultU64x64.c | MSFT + Ia32/MultU64x32.c | MSFT + Ia32/LShiftU64.c | MSFT + Ia32/LRotU64.c | MSFT + Ia32/FxRestore.c | MSFT + Ia32/FxSave.c | MSFT + Ia32/DivU64x32Remainder.c | MSFT + Ia32/DivU64x32.c | MSFT + Ia32/CpuPause.c | MSFT + Ia32/CpuBreakpoint.c | MSFT + Ia32/ARShiftU64.c | MSFT + Ia32/GccInline.c | GCC + Ia32/LongJump.nasm + Ia32/SetJump.nasm + Ia32/SwapBytes64.nasm| GCC + Ia32/DivU64x64Remainder.nasm + Ia32/DivU64x32Remainder.nasm| GCC + Ia32/ModU64x32.nasm| GCC + Ia32/DivU64x32.nasm| GCC + Ia32/MultU64x64.nasm| GCC + Ia32/MultU64x32.nasm| GCC + Ia32/RRotU64.nasm| GCC + Ia32/LRotU64.nasm| GCC + Ia32/ARShiftU64.nasm| GCC + Ia32/RShiftU64.nasm| GCC + Ia32/LShiftU64.nasm| GCC + Ia32/RdRand.nasm + Ia32/DivS64x64Remainder.c + Ia32/InternalSwitchStack.c | MSFT + Ia32/InternalSwitchStack.nasm | GCC + Ia32/Non-existing.c + Unaligned.c + X86FxSave.c + X86FxRestore.c + X86Msr.c + X86RdRand.c + X86SpeculationBarrier.c + X86UnitTestHost.c + +[Sources.X64] + X64/LongJump.nasm + X64/SetJump.nasm + X64/SwitchStack.nasm + X64/CpuBreakpoint.c | MSFT + X64/CpuPause.nasm| MSFT + X64/ReadTsc.nasm| MSFT + X64/FxRestore.nasm| MSFT + X64/FxSave.nasm| MSFT + X64/ReadEflags.nasm| MSFT + X64/Non-existing.c + Math64.c + Unaligned.c + X86FxSave.c + X86FxRestore.c + X86Msr.c + X86RdRand.c + X86SpeculationBarrier.c + X64/GccInline.c | GCC + X64/RdRand.nasm + ChkStkGcc.c | GCC + X86UnitTestHost.c + +[Sources.EBC] + Ebc/CpuBreakpoint.c + Ebc/SetJumpLongJump.c + Ebc/SwitchStack.c + Ebc/SpeculationBarrier.c + Unaligned.c + Math64.c + +[Sources.ARM] + Arm/InternalSwitchStack.c + Arm/Unaligned.c + Math64.c | RVCT + Math64.c | MSFT + + Arm/SwitchStack.asm | RVCT + Arm/SetJumpLongJump.asm | RVCT + Arm/CpuPause.asm | RVCT + Arm/CpuBreakpoint.asm | RVCT + Arm/MemoryFence.asm | RVCT + Arm/SpeculationBarrier.S | RVCT + + Arm/SwitchStack.asm | MSFT + Arm/SetJumpLongJump.asm | MSFT + Arm/CpuPause.asm | MSFT + Arm/CpuBreakpoint.asm | MSFT + Arm/MemoryFence.asm | MSFT + Arm/SpeculationBarrier.asm | MSFT + + Arm/Math64.S | GCC + Arm/SwitchStack.S | GCC + Arm/SetJumpLongJump.S | GCC + Arm/CpuBreakpoint.S | GCC + Arm/MemoryFence.S | GCC + Arm/SpeculationBarrier.S | GCC + +[Sources.AARCH64] + Arm/InternalSwitchStack.c + Arm/Unaligned.c + Math64.c + + AArch64/MemoryFence.S | GCC + AArch64/SwitchStack.S | GCC + AArch64/SetJumpLongJump.S | GCC + AArch64/CpuBreakpoint.S | GCC + AArch64/SpeculationBarrier.S | GCC + + AArch64/MemoryFence.asm | MSFT + AArch64/SwitchStack.asm | MSFT + AArch64/SetJumpLongJump.asm | MSFT + AArch64/CpuBreakpoint.asm | MSFT + AArch64/SpeculationBarrier.asm | MSFT + +[Sources.RISCV64] + Math64.c + Unaligned.c + RiscV64/InternalSwitchStack.c + RiscV64/CpuBreakpoint.c + RiscV64/CpuPause.c + RiscV64/RiscVSetJumpLongJump.S | GCC + RiscV64/RiscVCpuBreakpoint.S | GCC + RiscV64/RiscVCpuPause.S | GCC + RiscV64/RiscVInterrupt.S | GCC + RiscV64/FlushCache.S | GCC + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + PcdLib + DebugLib + BaseMemoryLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CO= NSUMES + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CO= NSUMES + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CO= NSUMES + gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOME= TIMES_CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType ## SOMETIMES_CO= NSUMES + +[FeaturePcd] + gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES diff --git a/MdePkg/Library/BaseLib/UnitTestHostBaseLib.uni b/MdePkg/Librar= y/BaseLib/UnitTestHostBaseLib.uni new file mode 100644 index 0000000000..e63ecef82c --- /dev/null +++ b/MdePkg/Library/BaseLib/UnitTestHostBaseLib.uni @@ -0,0 +1,11 @@ +// /** @file +// Base Library implementation for use with host based unit tests. +// +// Copyright (c) 2020, Intel Corporation. All rights reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "Base Library impl= ementation for use with host based unit tests." + +#string STR_MODULE_DESCRIPTION #language en-US "Base Library impl= ementation for use with host based unit tests." diff --git a/MdePkg/Library/BaseLib/X86UnitTestHost.c b/MdePkg/Library/Base= Lib/X86UnitTestHost.c new file mode 100644 index 0000000000..d0e428457e --- /dev/null +++ b/MdePkg/Library/BaseLib/X86UnitTestHost.c @@ -0,0 +1,2977 @@ +/** @file + IA32/X64 specific Unit Test Host functions. + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UnitTestHost.h" + +/// +/// Defines for mUnitTestHostBaseLibSegment indexes +/// +#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0 +#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1 +#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2 +#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3 +#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4 +#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5 +#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6 +#define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7 + +/// +/// Module global variables for simple system emulation of MSRs, CRx, DRx, +/// GDTR, IDTR, and Segment Selectors. +/// +STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000]; +STATIC UINTN mUnitTestHostBaseLibCr[5]; +STATIC UINTN mUnitTestHostBaseLibDr[8]; +STATIC UINT16 mUnitTestHostBaseLibSegment[8]; +STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr; +STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr; + +/** + Retrieves CPUID information. + + Executes the CPUID instruction with EAX set to the value specified by In= dex. + This function always returns Index. + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + This function is only available on IA-32 and x64. + + @param Index The 32-bit value to load into EAX prior to invoking the CP= UID + instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ebx The pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ecx The pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Edx The pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + + @return Index. + +**/ +UINT32 +EFIAPI +UnitTestHostBaseLibAsmCpuid ( + IN UINT32 Index, + OUT UINT32 *Eax, OPTIONAL + OUT UINT32 *Ebx, OPTIONAL + OUT UINT32 *Ecx, OPTIONAL + OUT UINT32 *Edx OPTIONAL + ) +{ + if (Eax !=3D NULL) { + *Eax =3D 0; + } + if (Ebx !=3D NULL) { + *Ebx =3D 0; + } + if (Ecx !=3D NULL) { + *Ecx =3D 0; + } + if (Edx !=3D NULL) { + *Edx =3D 0; + } + return Index; +} + +/** + Retrieves CPUID information using an extended leaf identifier. + + Executes the CPUID instruction with EAX set to the value specified by In= dex + and ECX set to the value specified by SubIndex. This function always ret= urns + Index. This function is only available on IA-32 and x64. + + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + + @param Index The 32-bit value to load into EAX prior to invoking the + CPUID instruction. + @param SubIndex The 32-bit value to load into ECX prior to invoking the + CPUID instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ebx The pointer to the 32-bit EBX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ecx The pointer to the 32-bit ECX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Edx The pointer to the 32-bit EDX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + + @return Index. + +**/ +UINT32 +EFIAPI +UnitTestHostBaseLibAsmCpuidEx ( + IN UINT32 Index, + IN UINT32 SubIndex, + OUT UINT32 *Eax, OPTIONAL + OUT UINT32 *Ebx, OPTIONAL + OUT UINT32 *Ecx, OPTIONAL + OUT UINT32 *Edx OPTIONAL + ) +{ + if (Eax !=3D NULL) { + *Eax =3D 0; + } + if (Ebx !=3D NULL) { + *Ebx =3D 0; + } + if (Ecx !=3D NULL) { + *Ecx =3D 0; + } + if (Edx !=3D NULL) { + *Edx =3D 0; + } + return Index; +} + +/** + Set CD bit and clear NW bit of CR0 followed by a WBINVD. + + Disables the caches by setting the CD bit of CR0 to 1, clearing the NW b= it of CR0 to 0, + and executing a WBINVD instruction. This function is only available on = IA-32 and x64. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmDisableCache ( + VOID + ) +{ +} + +/** + Perform a WBINVD and clear both the CD and NW bits of CR0. + + Enables the caches by executing a WBINVD instruction and then clear both= the CD and NW + bits of CR0 to 0. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmEnableCache ( + VOID + ) +{ +} + +/** + Returns a 64-bit Machine Specific Register(MSR). + + Reads and returns the 64-bit MSR specified by Index. No parameter checki= ng is + performed on Index, and some Index values may cause CPU exceptions. The + caller must either guarantee that Index is valid, or the caller must set= up + exception handlers to catch the exceptions. This function is only availa= ble + on IA-32 and x64. + + @param Index The 32-bit MSR index to read. + + @return The value of the MSR identified by Index. + +**/ +UINT64 +EFIAPI +UnitTestHostBaseLibAsmReadMsr64 ( + IN UINT32 Index + ) +{ + if (Index < 0x1000) { + return mUnitTestHostBaseLibMsr[0][Index]; + } + if (Index >=3D 0xC0000000 && Index < 0xC0001000) { + return mUnitTestHostBaseLibMsr[1][Index]; + } + return 0; +} + +/** + Writes a 64-bit value to a Machine Specific Register(MSR), and returns t= he + value. + + Writes the 64-bit value specified by Value to the MSR specified by Index= . The + 64-bit value written to the MSR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions.= The + caller must either guarantee that Index and Value are valid, or the call= er + must establish proper exception handlers. This function is only availabl= e on + IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param Value The 64-bit value to write to the MSR. + + @return Value + +**/ +UINT64 +EFIAPI +UnitTestHostBaseLibAsmWriteMsr64 ( + IN UINT32 Index, + IN UINT64 Value + ) +{ + if (Index < 0x1000) { + mUnitTestHostBaseLibMsr[0][Index] =3D Value; + } + if (Index >=3D 0xC0000000 && Index < 0xC0001000) { + mUnitTestHostBaseLibMsr[1][Index - 0xC00000000] =3D Value; + } + return Value; +} + +/** + Reads the current value of the Control Register 0 (CR0). + + Reads and returns the current value of CR0. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of the Control Register 0 (CR0). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadCr0 ( + VOID + ) +{ + return mUnitTestHostBaseLibCr[0]; +} + +/** + Reads the current value of the Control Register 2 (CR2). + + Reads and returns the current value of CR2. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of the Control Register 2 (CR2). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadCr2 ( + VOID + ) +{ + return mUnitTestHostBaseLibCr[2]; +} + +/** + Reads the current value of the Control Register 3 (CR3). + + Reads and returns the current value of CR3. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of the Control Register 3 (CR3). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadCr3 ( + VOID + ) +{ + return mUnitTestHostBaseLibCr[3]; +} + +/** + Reads the current value of the Control Register 4 (CR4). + + Reads and returns the current value of CR4. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of the Control Register 4 (CR4). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadCr4 ( + VOID + ) +{ + return mUnitTestHostBaseLibCr[4]; +} + +/** + Writes a value to Control Register 0 (CR0). + + Writes and returns a new value to CR0. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Cr0 The value to write to CR0. + + @return The value written to CR0. + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteCr0 ( + UINTN Cr0 + ) +{ + mUnitTestHostBaseLibCr[0] =3D Cr0; + return Cr0; +} + +/** + Writes a value to Control Register 2 (CR2). + + Writes and returns a new value to CR2. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Cr2 The value to write to CR2. + + @return The value written to CR2. + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteCr2 ( + UINTN Cr2 + ) +{ + mUnitTestHostBaseLibCr[2] =3D Cr2; + return Cr2; +} + +/** + Writes a value to Control Register 3 (CR3). + + Writes and returns a new value to CR3. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Cr3 The value to write to CR3. + + @return The value written to CR3. + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteCr3 ( + UINTN Cr3 + ) +{ + mUnitTestHostBaseLibCr[3] =3D Cr3; + return Cr3; +} + +/** + Writes a value to Control Register 4 (CR4). + + Writes and returns a new value to CR4. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Cr4 The value to write to CR4. + + @return The value written to CR4. + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteCr4 ( + UINTN Cr4 + ) +{ + mUnitTestHostBaseLibCr[4] =3D Cr4; + return Cr4; +} + +/** + Reads the current value of Debug Register 0 (DR0). + + Reads and returns the current value of DR0. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadDr0 ( + VOID + ) +{ + return mUnitTestHostBaseLibDr[0]; +} + +/** + Reads the current value of Debug Register 1 (DR1). + + Reads and returns the current value of DR1. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadDr1 ( + VOID + ) +{ + return mUnitTestHostBaseLibDr[1]; +} + +/** + Reads the current value of Debug Register 2 (DR2). + + Reads and returns the current value of DR2. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadDr2 ( + VOID + ) +{ + return mUnitTestHostBaseLibDr[2]; +} + +/** + Reads the current value of Debug Register 3 (DR3). + + Reads and returns the current value of DR3. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadDr3 ( + VOID + ) +{ + return mUnitTestHostBaseLibDr[3]; +} + +/** + Reads the current value of Debug Register 4 (DR4). + + Reads and returns the current value of DR4. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadDr4 ( + VOID + ) +{ + return mUnitTestHostBaseLibDr[4]; +} + +/** + Reads the current value of Debug Register 5 (DR5). + + Reads and returns the current value of DR5. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadDr5 ( + VOID + ) +{ + return mUnitTestHostBaseLibDr[5]; +} + +/** + Reads the current value of Debug Register 6 (DR6). + + Reads and returns the current value of DR6. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadDr6 ( + VOID + ) +{ + return mUnitTestHostBaseLibDr[6]; +} + +/** + Reads the current value of Debug Register 7 (DR7). + + Reads and returns the current value of DR7. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmReadDr7 ( + VOID + ) +{ + return mUnitTestHostBaseLibDr[7]; +} + +/** + Writes a value to Debug Register 0 (DR0). + + Writes and returns a new value to DR0. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr0 The value to write to Dr0. + + @return The value written to Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteDr0 ( + UINTN Dr0 + ) +{ + mUnitTestHostBaseLibDr[0] =3D Dr0; + return Dr0; +} + +/** + Writes a value to Debug Register 1 (DR1). + + Writes and returns a new value to DR1. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr1 The value to write to Dr1. + + @return The value written to Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteDr1 ( + UINTN Dr1 + ) +{ + mUnitTestHostBaseLibDr[1] =3D Dr1; + return Dr1; +} + +/** + Writes a value to Debug Register 2 (DR2). + + Writes and returns a new value to DR2. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr2 The value to write to Dr2. + + @return The value written to Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteDr2 ( + UINTN Dr2 + ) +{ + mUnitTestHostBaseLibDr[2] =3D Dr2; + return Dr2; +} + +/** + Writes a value to Debug Register 3 (DR3). + + Writes and returns a new value to DR3. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr3 The value to write to Dr3. + + @return The value written to Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteDr3 ( + UINTN Dr3 + ) +{ + mUnitTestHostBaseLibDr[3] =3D Dr3; + return Dr3; +} + +/** + Writes a value to Debug Register 4 (DR4). + + Writes and returns a new value to DR4. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr4 The value to write to Dr4. + + @return The value written to Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteDr4 ( + UINTN Dr4 + ) +{ + mUnitTestHostBaseLibDr[4] =3D Dr4; + return Dr4; +} + +/** + Writes a value to Debug Register 5 (DR5). + + Writes and returns a new value to DR5. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr5 The value to write to Dr5. + + @return The value written to Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteDr5 ( + UINTN Dr5 + ) +{ + mUnitTestHostBaseLibDr[5] =3D Dr5; + return Dr5; +} + +/** + Writes a value to Debug Register 6 (DR6). + + Writes and returns a new value to DR6. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr6 The value to write to Dr6. + + @return The value written to Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteDr6 ( + UINTN Dr6 + ) +{ + mUnitTestHostBaseLibDr[6] =3D Dr6; + return Dr6; +} + +/** + Writes a value to Debug Register 7 (DR7). + + Writes and returns a new value to DR7. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr7 The value to write to Dr7. + + @return The value written to Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmWriteDr7 ( + UINTN Dr7 + ) +{ + mUnitTestHostBaseLibDr[7] =3D Dr7; + return Dr7; +} + +/** + Reads the current value of Code Segment Register (CS). + + Reads and returns the current value of CS. This function is only availab= le on + IA-32 and x64. + + @return The current value of CS. + +**/ +UINT16 +EFIAPI +UnitTestHostBaseLibAsmReadCs ( + VOID + ) +{ + return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS]; +} + +/** + Reads the current value of Data Segment Register (DS). + + Reads and returns the current value of DS. This function is only availab= le on + IA-32 and x64. + + @return The current value of DS. + +**/ +UINT16 +EFIAPI +UnitTestHostBaseLibAsmReadDs ( + VOID + ) +{ + return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS]; +} + +/** + Reads the current value of Extra Segment Register (ES). + + Reads and returns the current value of ES. This function is only availab= le on + IA-32 and x64. + + @return The current value of ES. + +**/ +UINT16 +EFIAPI +UnitTestHostBaseLibAsmReadEs ( + VOID + ) +{ + return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES]; +} + +/** + Reads the current value of FS Data Segment Register (FS). + + Reads and returns the current value of FS. This function is only availab= le on + IA-32 and x64. + + @return The current value of FS. + +**/ +UINT16 +EFIAPI +UnitTestHostBaseLibAsmReadFs ( + VOID + ) +{ + return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS]; +} + +/** + Reads the current value of GS Data Segment Register (GS). + + Reads and returns the current value of GS. This function is only availab= le on + IA-32 and x64. + + @return The current value of GS. + +**/ +UINT16 +EFIAPI +UnitTestHostBaseLibAsmReadGs ( + VOID + ) +{ + return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS]; +} + +/** + Reads the current value of Stack Segment Register (SS). + + Reads and returns the current value of SS. This function is only availab= le on + IA-32 and x64. + + @return The current value of SS. + +**/ +UINT16 +EFIAPI +UnitTestHostBaseLibAsmReadSs ( + VOID + ) +{ + return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS]; +} + +/** + Reads the current value of Task Register (TR). + + Reads and returns the current value of TR. This function is only availab= le on + IA-32 and x64. + + @return The current value of TR. + +**/ +UINT16 +EFIAPI +UnitTestHostBaseLibAsmReadTr ( + VOID + ) +{ + return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR]; +} + +/** + Reads the current Global Descriptor Table Register(GDTR) descriptor. + + Reads and returns the current GDTR descriptor and returns it in Gdtr. Th= is + function is only available on IA-32 and x64. + + If Gdtr is NULL, then ASSERT(). + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmReadGdtr ( + OUT IA32_DESCRIPTOR *Gdtr + ) +{ + Gdtr =3D &mUnitTestHostBaseLibGdtr; +} + +/** + Writes the current Global Descriptor Table Register (GDTR) descriptor. + + Writes and the current GDTR descriptor specified by Gdtr. This function = is + only available on IA-32 and x64. + + If Gdtr is NULL, then ASSERT(). + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmWriteGdtr ( + IN CONST IA32_DESCRIPTOR *Gdtr + ) +{ + CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr, sizeof (IA32_DESCRIPTOR)); +} + +/** + Reads the current Interrupt Descriptor Table Register(IDTR) descriptor. + + Reads and returns the current IDTR descriptor and returns it in Idtr. Th= is + function is only available on IA-32 and x64. + + If Idtr is NULL, then ASSERT(). + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmReadIdtr ( + OUT IA32_DESCRIPTOR *Idtr + ) +{ + Idtr =3D &mUnitTestHostBaseLibIdtr; +} + +/** + Writes the current Interrupt Descriptor Table Register(IDTR) descriptor. + + Writes the current IDTR descriptor and returns it in Idtr. This function= is + only available on IA-32 and x64. + + If Idtr is NULL, then ASSERT(). + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmWriteIdtr ( + IN CONST IA32_DESCRIPTOR *Idtr + ) +{ + CopyMem (&mUnitTestHostBaseLibIdtr, Idtr, sizeof (IA32_DESCRIPTOR)); +} + +/** + Reads the current Local Descriptor Table Register(LDTR) selector. + + Reads and returns the current 16-bit LDTR descriptor value. This functio= n is + only available on IA-32 and x64. + + @return The current selector of LDT. + +**/ +UINT16 +EFIAPI +UnitTestHostBaseLibAsmReadLdtr ( + VOID + ) +{ + return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR]; +} + +/** + Writes the current Local Descriptor Table Register (LDTR) selector. + + Writes and the current LDTR descriptor specified by Ldtr. This function = is + only available on IA-32 and x64. + + @param Ldtr 16-bit LDTR selector value. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmWriteLdtr ( + IN UINT16 Ldtr + ) +{ + mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] =3D Ld= tr; +} + +/** + Reads the current value of a Performance Counter (PMC). + + Reads and returns the current value of performance counter specified by + Index. This function is only available on IA-32 and x64. + + @param Index The 32-bit Performance Counter index to read. + + @return The value of the PMC specified by Index. + +**/ +UINT64 +EFIAPI +UnitTestHostBaseLibAsmReadPmc ( + IN UINT32 Index + ) +{ + return 0; +} + +/** + Sets up a monitor buffer that is used by AsmMwait(). + + Executes a MONITOR instruction with the register state specified by Eax,= Ecx + and Edx. Returns Eax. This function is only available on IA-32 and x64. + + @param Eax The value to load into EAX or RAX before executing the MONIT= OR + instruction. + @param Ecx The value to load into ECX or RCX before executing the MONIT= OR + instruction. + @param Edx The value to load into EDX or RDX before executing the MONIT= OR + instruction. + + @return Eax + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmMonitor ( + IN UINTN Eax, + IN UINTN Ecx, + IN UINTN Edx + ) +{ + return Eax; +} + +/** + Executes an MWAIT instruction. + + Executes an MWAIT instruction with the register state specified by Eax a= nd + Ecx. Returns Eax. This function is only available on IA-32 and x64. + + @param Eax The value to load into EAX or RAX before executing the MONIT= OR + instruction. + @param Ecx The value to load into ECX or RCX before executing the MONIT= OR + instruction. + + @return Eax + +**/ +UINTN +EFIAPI +UnitTestHostBaseLibAsmMwait ( + IN UINTN Eax, + IN UINTN Ecx + ) +{ + return Eax; +} + +/** + Executes a WBINVD instruction. + + Executes a WBINVD instruction. This function is only available on IA-32 = and + x64. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmWbinvd ( + VOID + ) +{ +} + +/** + Executes a INVD instruction. + + Executes a INVD instruction. This function is only available on IA-32 and + x64. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmInvd ( + VOID + ) +{ +} + +/** + Flushes a cache line from all the instruction and data caches within the + coherency domain of the CPU. + + Flushed the cache line specified by LinearAddress, and returns LinearAdd= ress. + This function is only available on IA-32 and x64. + + @param LinearAddress The address of the cache line to flush. If the CPU= is + in a physical addressing mode, then LinearAddress = is a + physical address. If the CPU is in a virtual + addressing mode, then LinearAddress is a virtual + address. + + @return LinearAddress. +**/ +VOID * +EFIAPI +UnitTestHostBaseLibAsmFlushCacheLine ( + IN VOID *LinearAddress + ) +{ + return LinearAddress; +} + +/** + Enables the 32-bit paging mode on the CPU. + + Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page t= ables + must be properly initialized prior to calling this service. This function + assumes the current execution mode is 32-bit protected mode. This functi= on is + only available on IA-32. After the 32-bit paging mode is enabled, contro= l is + transferred to the function specified by EntryPoint using the new stack + specified by NewStack and passing in the parameters specified by Context= 1 and + Context2. Context1 and Context2 are optional and may be NULL. The functi= on + EntryPoint must never return. + + If the current execution mode is not 32-bit protected mode, then ASSERT(= ). + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + There are a number of constraints that must be followed before calling t= his + function: + 1) Interrupts must be disabled. + 2) The caller must be in 32-bit protected mode with flat descriptors. T= his + means all descriptors must have a base of 0 and a limit of 4GB. + 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat + descriptors. + 4) CR3 must point to valid page tables that will be used once the trans= ition + is complete, and those page tables must guarantee that the pages for= this + function and the stack are identity mapped. + + @param EntryPoint A pointer to function to call with the new stack aft= er + paging is enabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is enab= led. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is ena= bled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is enabled. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmEnablePaging32 ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ) +{ + EntryPoint (Context1, Context2); +} + +/** + Disables the 32-bit paging mode on the CPU. + + Disables the 32-bit paging mode on the CPU and returns to 32-bit protect= ed + mode. This function assumes the current execution mode is 32-paged prote= cted + mode. This function is only available on IA-32. After the 32-bit paging = mode + is disabled, control is transferred to the function specified by EntryPo= int + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional a= nd + may be NULL. The function EntryPoint must never return. + + If the current execution mode is not 32-bit paged mode, then ASSERT(). + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + There are a number of constraints that must be followed before calling t= his + function: + 1) Interrupts must be disabled. + 2) The caller must be in 32-bit paged mode. + 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode. + 4) CR3 must point to valid page tables that guarantee that the pages for + this function and the stack are identity mapped. + + @param EntryPoint A pointer to function to call with the new stack aft= er + paging is disabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is disa= bled. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is + disabled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is disabled. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmDisablePaging32 ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ) +{ + EntryPoint (Context1, Context2); +} + +/** + Enables the 64-bit paging mode on the CPU. + + Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page t= ables + must be properly initialized prior to calling this service. This function + assumes the current execution mode is 32-bit protected mode with flat + descriptors. This function is only available on IA-32. After the 64-bit + paging mode is enabled, control is transferred to the function specified= by + EntryPoint using the new stack specified by NewStack and passing in the + parameters specified by Context1 and Context2. Context1 and Context2 are + optional and may be 0. The function EntryPoint must never return. + + If the current execution mode is not 32-bit protected mode with flat + descriptors, then ASSERT(). + If EntryPoint is 0, then ASSERT(). + If NewStack is 0, then ASSERT(). + + @param Cs The 16-bit selector to load in the CS before EntryPo= int + is called. The descriptor in the GDT that this selec= tor + references must be setup for long mode. + @param EntryPoint The 64-bit virtual address of the function to call w= ith + the new stack after paging is enabled. + @param Context1 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the first parameter after + paging is enabled. + @param Context2 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the second parameter after + paging is enabled. + @param NewStack The 64-bit virtual address of the new stack to use f= or + the EntryPoint function after paging is enabled. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmEnablePaging64 ( + IN UINT16 Cs, + IN UINT64 EntryPoint, + IN UINT64 Context1, OPTIONAL + IN UINT64 Context2, OPTIONAL + IN UINT64 NewStack + ) +{ + SWITCH_STACK_ENTRY_POINT NewEntryPoint; + + NewEntryPoint =3D (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint); + NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2); +} + +/** + Disables the 64-bit paging mode on the CPU. + + Disables the 64-bit paging mode on the CPU and returns to 32-bit protect= ed + mode. This function assumes the current execution mode is 64-paging mode. + This function is only available on x64. After the 64-bit paging mode is + disabled, control is transferred to the function specified by EntryPoint + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional a= nd + may be 0. The function EntryPoint must never return. + + If the current execution mode is not 64-bit paged mode, then ASSERT(). + If EntryPoint is 0, then ASSERT(). + If NewStack is 0, then ASSERT(). + + @param Cs The 16-bit selector to load in the CS before EntryPo= int + is called. The descriptor in the GDT that this selec= tor + references must be setup for 32-bit protected mode. + @param EntryPoint The 64-bit virtual address of the function to call w= ith + the new stack after paging is disabled. + @param Context1 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the first parameter after + paging is disabled. + @param Context2 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the second parameter after + paging is disabled. + @param NewStack The 64-bit virtual address of the new stack to use f= or + the EntryPoint function after paging is disabled. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmDisablePaging64 ( + IN UINT16 Cs, + IN UINT32 EntryPoint, + IN UINT32 Context1, OPTIONAL + IN UINT32 Context2, OPTIONAL + IN UINT32 NewStack + ) +{ + SWITCH_STACK_ENTRY_POINT NewEntryPoint; + + NewEntryPoint =3D (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint); + NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2); +} + +/** + Retrieves the properties for 16-bit thunk functions. + + Computes the size of the buffer and stack below 1MB required to use the + AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. = This + buffer size is returned in RealModeBufferSize, and the stack size is ret= urned + in ExtraStackSize. If parameters are passed to the 16-bit real mode code, + then the actual minimum stack size is ExtraStackSize plus the maximum nu= mber + of bytes that need to be passed to the 16-bit real mode code. + + If RealModeBufferSize is NULL, then ASSERT(). + If ExtraStackSize is NULL, then ASSERT(). + + @param RealModeBufferSize A pointer to the size of the buffer below 1MB + required to use the 16-bit thunk functions. + @param ExtraStackSize A pointer to the extra size of stack below 1= MB + that the 16-bit thunk functions require for + temporary storage in the transition to and f= rom + 16-bit real mode. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmGetThunk16Properties ( + OUT UINT32 *RealModeBufferSize, + OUT UINT32 *ExtraStackSize + ) +{ + *RealModeBufferSize =3D 0; + *ExtraStackSize =3D 0; +} + +/** + Prepares all structures a code required to use AsmThunk16(). + + Prepares all structures and code required to use AsmThunk16(). + + This interface is limited to be used in either physical mode or virtual = modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1= :1. + + If ThunkContext is NULL, then ASSERT(). + + @param ThunkContext A pointer to the context structure that describes = the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmPrepareThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ) +{ +} + +/** + Transfers control to a 16-bit real mode entry point and returns the resu= lts. + + Transfers control to a 16-bit real mode entry point and returns the resu= lts. + AsmPrepareThunk16() must be called with ThunkContext before this functio= n is used. + This function must be called with interrupts disabled. + + The register state from the RealModeState field of ThunkContext is resto= red just prior + to calling the 16-bit real mode entry point. This includes the EFLAGS f= ield of RealModeState, + which is used to set the interrupt state when a 16-bit real mode entry p= oint is called. + Control is transferred to the 16-bit real mode entry point specified by = the CS and Eip fields of RealModeState. + The stack is initialized to the SS and ESP fields of RealModeState. Any= parameters passed to + the 16-bit real mode code must be populated by the caller at SS:ESP prio= r to calling this function. + The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instr= uction, + so when accessing stack contents, the 16-bit real mode code must account= for the 16-bit segment + and 16-bit offset of the return address that were pushed onto the stack.= The 16-bit real mode entry + point must exit with a RETF instruction. The register state is captured = into RealModeState immediately + after the RETF instruction is executed. + + If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode c= ode enables interrupts, + or any of the 16-bit real mode code makes a SW interrupt, then the calle= r is responsible for making sure + the IDT at address 0 is initialized to handle any HW or SW interrupts th= at may occur while in 16-bit real mode. + + If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode c= ode enables interrupts, + then the caller is responsible for making sure the 8259 PIC is in a stat= e compatible with 16-bit real mode. + This includes the base vectors, the interrupt masks, and the edge/level = trigger mode. + + If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of = ThunkContext, then the user code + is invoked in big real mode. Otherwise, the user code is invoked in 16-= bit real mode with 64KB segment limits. + + If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_D= ISABLE_A20_MASK_KBD_CTRL are set in + ThunkAttributes, then it is assumed that the user code did not enable th= e A20 mask, and no attempt is made to + disable the A20 mask. + + If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DI= SABLE_A20_MASK_KBD_CTRL is clear in + ThunkAttributes, then attempt to use the INT 15 service to disable the A= 20 mask. If this INT 15 call fails, + then attempt to disable the A20 mask by directly accessing the 8042 keyb= oard controller I/O ports. + + If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_= DISABLE_A20_MASK_KBD_CTRL is set in + ThunkAttributes, then attempt to disable the A20 mask by directly access= ing the 8042 keyboard controller I/O ports. + + If ThunkContext is NULL, then ASSERT(). + If AsmPrepareThunk16() was not previously called with ThunkContext, then= ASSERT(). + If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISA= BLE_A20_MASK_KBD_CTRL are set in + ThunkAttributes, then ASSERT(). + + This interface is limited to be used in either physical mode or virtual = modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer are mapped = 1:1. + + @param ThunkContext A pointer to the context structure that describes = the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ) +{ +} + +/** + Prepares all structures and code for a 16-bit real mode thunk, transfers + control to a 16-bit real mode entry point, and returns the results. + + Prepares all structures and code for a 16-bit real mode thunk, transfers + control to a 16-bit real mode entry point, and returns the results. If t= he + caller only need to perform a single 16-bit real mode thunk, then this + service should be used. If the caller intends to make more than one 16-b= it + real mode thunk, then it is more efficient if AsmPrepareThunk16() is cal= led + once and AsmThunk16() can be called for each 16-bit real mode thunk. + + This interface is limited to be used in either physical mode or virtual = modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1= :1. + + See AsmPrepareThunk16() and AsmThunk16() for the detailed description an= d ASSERT() conditions. + + @param ThunkContext A pointer to the context structure that describes = the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmPrepareAndThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ) +{ +} + +/** + Load given selector into TR register. + + @param[in] Selector Task segment selector +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmWriteTr ( + IN UINT16 Selector + ) +{ + mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] =3D Sele= ctor; +} + +/** + Performs a serializing operation on all load-from-memory instructions th= at + were issued prior the AsmLfence function. + + Executes a LFENCE instruction. This function is only available on IA-32 = and x64. + +**/ +VOID +EFIAPI +UnitTestHostBaseLibAsmLfence ( + VOID + ) +{ +} + +/** + Patch the immediate operand of an IA32 or X64 instruction such that the = byte, + word, dword or qword operand is encoded at the end of the instruction's + binary representation. + + This function should be used to update object code that was compiled with + NASM from assembly source code. Example: + + NASM source code: + + mov eax, strict dword 0 ; the imm32 zero operand will be patch= ed + ASM_PFX(gPatchCr3): + mov cr3, eax + + C source code: + + X86_ASSEMBLY_PATCH_LABEL gPatchCr3; + PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4); + + @param[out] InstructionEnd Pointer right past the instruction to patch.= The + immediate operand to patch is expected to + comprise the trailing bytes of the instructi= on. + If InstructionEnd is closer to address 0 than + ValueSize permits, then ASSERT(). + + @param[in] PatchValue The constant to write to the immediate opera= nd. + The caller is responsible for ensuring that + PatchValue can be represented in the byte, w= ord, + dword or qword operand (as indicated through + ValueSize); otherwise ASSERT(). + + @param[in] ValueSize The size of the operand in bytes; must be 1,= 2, + 4, or 8. ASSERT() otherwise. +**/ +VOID +EFIAPI +UnitTestHostBaseLibPatchInstructionX86 ( + OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, + IN UINT64 PatchValue, + IN UINTN ValueSize + ) +{ +} + +/** + Retrieves CPUID information. + + Executes the CPUID instruction with EAX set to the value specified by In= dex. + This function always returns Index. + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + This function is only available on IA-32 and x64. + + @param Index The 32-bit value to load into EAX prior to invoking the CP= UID + instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ebx The pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ecx The pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Edx The pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + + @return Index. + +**/ +UINT32 +EFIAPI +AsmCpuid ( + IN UINT32 Index, + OUT UINT32 *Eax, OPTIONAL + OUT UINT32 *Ebx, OPTIONAL + OUT UINT32 *Ecx, OPTIONAL + OUT UINT32 *Edx OPTIONAL + ) +{ + return gUnitTestHostBaseLib.X86->AsmCpuid (Index, Eax, Ebx, Ecx, Edx); +} + +/** + Retrieves CPUID information using an extended leaf identifier. + + Executes the CPUID instruction with EAX set to the value specified by In= dex + and ECX set to the value specified by SubIndex. This function always ret= urns + Index. This function is only available on IA-32 and x64. + + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + + @param Index The 32-bit value to load into EAX prior to invoking the + CPUID instruction. + @param SubIndex The 32-bit value to load into ECX prior to invoking the + CPUID instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ebx The pointer to the 32-bit EBX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ecx The pointer to the 32-bit ECX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Edx The pointer to the 32-bit EDX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + + @return Index. + +**/ +UINT32 +EFIAPI +AsmCpuidEx ( + IN UINT32 Index, + IN UINT32 SubIndex, + OUT UINT32 *Eax, OPTIONAL + OUT UINT32 *Ebx, OPTIONAL + OUT UINT32 *Ecx, OPTIONAL + OUT UINT32 *Edx OPTIONAL + ) +{ + return gUnitTestHostBaseLib.X86->AsmCpuidEx (Index, SubIndex, Eax, Ebx, = Ecx, Edx); +} + +/** + Set CD bit and clear NW bit of CR0 followed by a WBINVD. + + Disables the caches by setting the CD bit of CR0 to 1, clearing the NW b= it of CR0 to 0, + and executing a WBINVD instruction. This function is only available on = IA-32 and x64. + +**/ +VOID +EFIAPI +AsmDisableCache ( + VOID + ) +{ + gUnitTestHostBaseLib.X86->AsmDisableCache (); +} + +/** + Perform a WBINVD and clear both the CD and NW bits of CR0. + + Enables the caches by executing a WBINVD instruction and then clear both= the CD and NW + bits of CR0 to 0. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmEnableCache ( + VOID + ) +{ + gUnitTestHostBaseLib.X86->AsmEnableCache (); +} + +/** + Returns a 64-bit Machine Specific Register(MSR). + + Reads and returns the 64-bit MSR specified by Index. No parameter checki= ng is + performed on Index, and some Index values may cause CPU exceptions. The + caller must either guarantee that Index is valid, or the caller must set= up + exception handlers to catch the exceptions. This function is only availa= ble + on IA-32 and x64. + + @param Index The 32-bit MSR index to read. + + @return The value of the MSR identified by Index. + +**/ +UINT64 +EFIAPI +AsmReadMsr64 ( + IN UINT32 Index + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadMsr64 (Index); +} + +/** + Writes a 64-bit value to a Machine Specific Register(MSR), and returns t= he + value. + + Writes the 64-bit value specified by Value to the MSR specified by Index= . The + 64-bit value written to the MSR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions.= The + caller must either guarantee that Index and Value are valid, or the call= er + must establish proper exception handlers. This function is only availabl= e on + IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param Value The 64-bit value to write to the MSR. + + @return Value + +**/ +UINT64 +EFIAPI +AsmWriteMsr64 ( + IN UINT32 Index, + IN UINT64 Value + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteMsr64 (Index, Value); +} + +/** + Reads the current value of the Control Register 0 (CR0). + + Reads and returns the current value of CR0. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of the Control Register 0 (CR0). + +**/ +UINTN +EFIAPI +AsmReadCr0 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadCr0 (); +} + +/** + Reads the current value of the Control Register 2 (CR2). + + Reads and returns the current value of CR2. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of the Control Register 2 (CR2). + +**/ +UINTN +EFIAPI +AsmReadCr2 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadCr2 (); +} + +/** + Reads the current value of the Control Register 3 (CR3). + + Reads and returns the current value of CR3. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of the Control Register 3 (CR3). + +**/ +UINTN +EFIAPI +AsmReadCr3 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadCr3 (); +} + +/** + Reads the current value of the Control Register 4 (CR4). + + Reads and returns the current value of CR4. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of the Control Register 4 (CR4). + +**/ +UINTN +EFIAPI +AsmReadCr4 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadCr4 (); +} + +/** + Writes a value to Control Register 0 (CR0). + + Writes and returns a new value to CR0. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Cr0 The value to write to CR0. + + @return The value written to CR0. + +**/ +UINTN +EFIAPI +AsmWriteCr0 ( + UINTN Cr0 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteCr0 (Cr0); +} + +/** + Writes a value to Control Register 2 (CR2). + + Writes and returns a new value to CR2. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Cr2 The value to write to CR2. + + @return The value written to CR2. + +**/ +UINTN +EFIAPI +AsmWriteCr2 ( + UINTN Cr2 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteCr2 (Cr2); +} + +/** + Writes a value to Control Register 3 (CR3). + + Writes and returns a new value to CR3. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Cr3 The value to write to CR3. + + @return The value written to CR3. + +**/ +UINTN +EFIAPI +AsmWriteCr3 ( + UINTN Cr3 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteCr3 (Cr3); +} + +/** + Writes a value to Control Register 4 (CR4). + + Writes and returns a new value to CR4. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Cr4 The value to write to CR4. + + @return The value written to CR4. + +**/ +UINTN +EFIAPI +AsmWriteCr4 ( + UINTN Cr4 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteCr4 (Cr4); +} + +/** + Reads the current value of Debug Register 0 (DR0). + + Reads and returns the current value of DR0. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +AsmReadDr0 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDr0 (); +} + +/** + Reads the current value of Debug Register 1 (DR1). + + Reads and returns the current value of DR1. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +AsmReadDr1 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDr1 (); +} + +/** + Reads the current value of Debug Register 2 (DR2). + + Reads and returns the current value of DR2. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +AsmReadDr2 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDr2 (); +} + +/** + Reads the current value of Debug Register 3 (DR3). + + Reads and returns the current value of DR3. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +AsmReadDr3 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDr3 (); +} + +/** + Reads the current value of Debug Register 4 (DR4). + + Reads and returns the current value of DR4. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +AsmReadDr4 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDr4 (); +} + +/** + Reads the current value of Debug Register 5 (DR5). + + Reads and returns the current value of DR5. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +AsmReadDr5 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDr5 (); +} + +/** + Reads the current value of Debug Register 6 (DR6). + + Reads and returns the current value of DR6. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +AsmReadDr6 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDr6 (); +} + +/** + Reads the current value of Debug Register 7 (DR7). + + Reads and returns the current value of DR7. This function is only availa= ble + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit valu= e on + x64. + + @return The value of Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +AsmReadDr7 ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDr7 (); +} + +/** + Writes a value to Debug Register 0 (DR0). + + Writes and returns a new value to DR0. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr0 The value to write to Dr0. + + @return The value written to Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +AsmWriteDr0 ( + UINTN Dr0 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteDr0 (Dr0); +} + +/** + Writes a value to Debug Register 1 (DR1). + + Writes and returns a new value to DR1. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr1 The value to write to Dr1. + + @return The value written to Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +AsmWriteDr1 ( + UINTN Dr1 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteDr1 (Dr1); +} + +/** + Writes a value to Debug Register 2 (DR2). + + Writes and returns a new value to DR2. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr2 The value to write to Dr2. + + @return The value written to Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +AsmWriteDr2 ( + UINTN Dr2 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteDr2 (Dr2); +} + +/** + Writes a value to Debug Register 3 (DR3). + + Writes and returns a new value to DR3. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr3 The value to write to Dr3. + + @return The value written to Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +AsmWriteDr3 ( + UINTN Dr3 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteDr3 (Dr3); +} + +/** + Writes a value to Debug Register 4 (DR4). + + Writes and returns a new value to DR4. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr4 The value to write to Dr4. + + @return The value written to Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +AsmWriteDr4 ( + UINTN Dr4 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteDr4 (Dr4); +} + +/** + Writes a value to Debug Register 5 (DR5). + + Writes and returns a new value to DR5. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr5 The value to write to Dr5. + + @return The value written to Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +AsmWriteDr5 ( + UINTN Dr5 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteDr5 (Dr5); +} + +/** + Writes a value to Debug Register 6 (DR6). + + Writes and returns a new value to DR6. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr6 The value to write to Dr6. + + @return The value written to Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +AsmWriteDr6 ( + UINTN Dr6 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteDr6 (Dr6); +} + +/** + Writes a value to Debug Register 7 (DR7). + + Writes and returns a new value to DR7. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on= x64. + + @param Dr7 The value to write to Dr7. + + @return The value written to Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +AsmWriteDr7 ( + UINTN Dr7 + ) +{ + return gUnitTestHostBaseLib.X86->AsmWriteDr7 (Dr7); +} + +/** + Reads the current value of Code Segment Register (CS). + + Reads and returns the current value of CS. This function is only availab= le on + IA-32 and x64. + + @return The current value of CS. + +**/ +UINT16 +EFIAPI +AsmReadCs ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadCs (); +} + +/** + Reads the current value of Data Segment Register (DS). + + Reads and returns the current value of DS. This function is only availab= le on + IA-32 and x64. + + @return The current value of DS. + +**/ +UINT16 +EFIAPI +AsmReadDs ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadDs (); +} + +/** + Reads the current value of Extra Segment Register (ES). + + Reads and returns the current value of ES. This function is only availab= le on + IA-32 and x64. + + @return The current value of ES. + +**/ +UINT16 +EFIAPI +AsmReadEs ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadEs (); +} + +/** + Reads the current value of FS Data Segment Register (FS). + + Reads and returns the current value of FS. This function is only availab= le on + IA-32 and x64. + + @return The current value of FS. + +**/ +UINT16 +EFIAPI +AsmReadFs ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadFs (); +} + +/** + Reads the current value of GS Data Segment Register (GS). + + Reads and returns the current value of GS. This function is only availab= le on + IA-32 and x64. + + @return The current value of GS. + +**/ +UINT16 +EFIAPI +AsmReadGs ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadGs (); +} + +/** + Reads the current value of Stack Segment Register (SS). + + Reads and returns the current value of SS. This function is only availab= le on + IA-32 and x64. + + @return The current value of SS. + +**/ +UINT16 +EFIAPI +AsmReadSs ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadSs (); +} + +/** + Reads the current value of Task Register (TR). + + Reads and returns the current value of TR. This function is only availab= le on + IA-32 and x64. + + @return The current value of TR. + +**/ +UINT16 +EFIAPI +AsmReadTr ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadTr (); +} + +/** + Reads the current Global Descriptor Table Register(GDTR) descriptor. + + Reads and returns the current GDTR descriptor and returns it in Gdtr. Th= is + function is only available on IA-32 and x64. + + If Gdtr is NULL, then ASSERT(). + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +AsmReadGdtr ( + OUT IA32_DESCRIPTOR *Gdtr + ) +{ + gUnitTestHostBaseLib.X86->AsmReadGdtr (Gdtr); +} + +/** + Writes the current Global Descriptor Table Register (GDTR) descriptor. + + Writes and the current GDTR descriptor specified by Gdtr. This function = is + only available on IA-32 and x64. + + If Gdtr is NULL, then ASSERT(). + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +AsmWriteGdtr ( + IN CONST IA32_DESCRIPTOR *Gdtr + ) +{ + gUnitTestHostBaseLib.X86->AsmWriteGdtr (Gdtr); +} + +/** + Reads the current Interrupt Descriptor Table Register(IDTR) descriptor. + + Reads and returns the current IDTR descriptor and returns it in Idtr. Th= is + function is only available on IA-32 and x64. + + If Idtr is NULL, then ASSERT(). + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +AsmReadIdtr ( + OUT IA32_DESCRIPTOR *Idtr + ) +{ + gUnitTestHostBaseLib.X86->AsmReadIdtr (Idtr); +} + +/** + Writes the current Interrupt Descriptor Table Register(IDTR) descriptor. + + Writes the current IDTR descriptor and returns it in Idtr. This function= is + only available on IA-32 and x64. + + If Idtr is NULL, then ASSERT(). + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +AsmWriteIdtr ( + IN CONST IA32_DESCRIPTOR *Idtr + ) +{ + gUnitTestHostBaseLib.X86->AsmWriteIdtr (Idtr); +} + +/** + Reads the current Local Descriptor Table Register(LDTR) selector. + + Reads and returns the current 16-bit LDTR descriptor value. This functio= n is + only available on IA-32 and x64. + + @return The current selector of LDT. + +**/ +UINT16 +EFIAPI +AsmReadLdtr ( + VOID + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadLdtr (); +} + +/** + Writes the current Local Descriptor Table Register (LDTR) selector. + + Writes and the current LDTR descriptor specified by Ldtr. This function = is + only available on IA-32 and x64. + + @param Ldtr 16-bit LDTR selector value. + +**/ +VOID +EFIAPI +AsmWriteLdtr ( + IN UINT16 Ldtr + ) +{ + gUnitTestHostBaseLib.X86->AsmWriteLdtr (Ldtr); +} + +/** + Reads the current value of a Performance Counter (PMC). + + Reads and returns the current value of performance counter specified by + Index. This function is only available on IA-32 and x64. + + @param Index The 32-bit Performance Counter index to read. + + @return The value of the PMC specified by Index. + +**/ +UINT64 +EFIAPI +AsmReadPmc ( + IN UINT32 Index + ) +{ + return gUnitTestHostBaseLib.X86->AsmReadPmc (Index); +} + +/** + Sets up a monitor buffer that is used by AsmMwait(). + + Executes a MONITOR instruction with the register state specified by Eax,= Ecx + and Edx. Returns Eax. This function is only available on IA-32 and x64. + + @param Eax The value to load into EAX or RAX before executing the MONIT= OR + instruction. + @param Ecx The value to load into ECX or RCX before executing the MONIT= OR + instruction. + @param Edx The value to load into EDX or RDX before executing the MONIT= OR + instruction. + + @return Eax + +**/ +UINTN +EFIAPI +AsmMonitor ( + IN UINTN Eax, + IN UINTN Ecx, + IN UINTN Edx + ) +{ + return gUnitTestHostBaseLib.X86->AsmMonitor (Eax, Ecx, Edx); +} + +/** + Executes an MWAIT instruction. + + Executes an MWAIT instruction with the register state specified by Eax a= nd + Ecx. Returns Eax. This function is only available on IA-32 and x64. + + @param Eax The value to load into EAX or RAX before executing the MONIT= OR + instruction. + @param Ecx The value to load into ECX or RCX before executing the MONIT= OR + instruction. + + @return Eax + +**/ +UINTN +EFIAPI +AsmMwait ( + IN UINTN Eax, + IN UINTN Ecx + ) +{ + return gUnitTestHostBaseLib.X86->AsmMwait (Eax, Ecx); +} + +/** + Executes a WBINVD instruction. + + Executes a WBINVD instruction. This function is only available on IA-32 = and + x64. + +**/ +VOID +EFIAPI +AsmWbinvd ( + VOID + ) +{ + gUnitTestHostBaseLib.X86->AsmWbinvd (); +} + +/** + Executes a INVD instruction. + + Executes a INVD instruction. This function is only available on IA-32 and + x64. + +**/ +VOID +EFIAPI +AsmInvd ( + VOID + ) +{ + gUnitTestHostBaseLib.X86->AsmInvd (); +} + +/** + Flushes a cache line from all the instruction and data caches within the + coherency domain of the CPU. + + Flushed the cache line specified by LinearAddress, and returns LinearAdd= ress. + This function is only available on IA-32 and x64. + + @param LinearAddress The address of the cache line to flush. If the CPU= is + in a physical addressing mode, then LinearAddress = is a + physical address. If the CPU is in a virtual + addressing mode, then LinearAddress is a virtual + address. + + @return LinearAddress. +**/ +VOID * +EFIAPI +AsmFlushCacheLine ( + IN VOID *LinearAddress + ) +{ + return gUnitTestHostBaseLib.X86->AsmFlushCacheLine (LinearAddress); +} + +/** + Enables the 32-bit paging mode on the CPU. + + Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page t= ables + must be properly initialized prior to calling this service. This function + assumes the current execution mode is 32-bit protected mode. This functi= on is + only available on IA-32. After the 32-bit paging mode is enabled, contro= l is + transferred to the function specified by EntryPoint using the new stack + specified by NewStack and passing in the parameters specified by Context= 1 and + Context2. Context1 and Context2 are optional and may be NULL. The functi= on + EntryPoint must never return. + + If the current execution mode is not 32-bit protected mode, then ASSERT(= ). + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + There are a number of constraints that must be followed before calling t= his + function: + 1) Interrupts must be disabled. + 2) The caller must be in 32-bit protected mode with flat descriptors. T= his + means all descriptors must have a base of 0 and a limit of 4GB. + 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat + descriptors. + 4) CR3 must point to valid page tables that will be used once the trans= ition + is complete, and those page tables must guarantee that the pages for= this + function and the stack are identity mapped. + + @param EntryPoint A pointer to function to call with the new stack aft= er + paging is enabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is enab= led. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is ena= bled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is enabled. + +**/ +VOID +EFIAPI +AsmEnablePaging32 ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ) +{ + gUnitTestHostBaseLib.X86->AsmEnablePaging32 (EntryPoint, Context1, Conte= xt2, NewStack); +} + +/** + Disables the 32-bit paging mode on the CPU. + + Disables the 32-bit paging mode on the CPU and returns to 32-bit protect= ed + mode. This function assumes the current execution mode is 32-paged prote= cted + mode. This function is only available on IA-32. After the 32-bit paging = mode + is disabled, control is transferred to the function specified by EntryPo= int + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional a= nd + may be NULL. The function EntryPoint must never return. + + If the current execution mode is not 32-bit paged mode, then ASSERT(). + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + There are a number of constraints that must be followed before calling t= his + function: + 1) Interrupts must be disabled. + 2) The caller must be in 32-bit paged mode. + 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode. + 4) CR3 must point to valid page tables that guarantee that the pages for + this function and the stack are identity mapped. + + @param EntryPoint A pointer to function to call with the new stack aft= er + paging is disabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is disa= bled. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is + disabled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is disabled. + +**/ +VOID +EFIAPI +AsmDisablePaging32 ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ) +{ + gUnitTestHostBaseLib.X86->AsmDisablePaging32 (EntryPoint, Context1, Cont= ext2, NewStack); +} + +/** + Enables the 64-bit paging mode on the CPU. + + Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page t= ables + must be properly initialized prior to calling this service. This function + assumes the current execution mode is 32-bit protected mode with flat + descriptors. This function is only available on IA-32. After the 64-bit + paging mode is enabled, control is transferred to the function specified= by + EntryPoint using the new stack specified by NewStack and passing in the + parameters specified by Context1 and Context2. Context1 and Context2 are + optional and may be 0. The function EntryPoint must never return. + + If the current execution mode is not 32-bit protected mode with flat + descriptors, then ASSERT(). + If EntryPoint is 0, then ASSERT(). + If NewStack is 0, then ASSERT(). + + @param Cs The 16-bit selector to load in the CS before EntryPo= int + is called. The descriptor in the GDT that this selec= tor + references must be setup for long mode. + @param EntryPoint The 64-bit virtual address of the function to call w= ith + the new stack after paging is enabled. + @param Context1 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the first parameter after + paging is enabled. + @param Context2 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the second parameter after + paging is enabled. + @param NewStack The 64-bit virtual address of the new stack to use f= or + the EntryPoint function after paging is enabled. + +**/ +VOID +EFIAPI +AsmEnablePaging64 ( + IN UINT16 Cs, + IN UINT64 EntryPoint, + IN UINT64 Context1, OPTIONAL + IN UINT64 Context2, OPTIONAL + IN UINT64 NewStack + ) +{ + gUnitTestHostBaseLib.X86->AsmEnablePaging64 (Cs, EntryPoint, Context1, C= ontext2, NewStack); +} + +/** + Disables the 64-bit paging mode on the CPU. + + Disables the 64-bit paging mode on the CPU and returns to 32-bit protect= ed + mode. This function assumes the current execution mode is 64-paging mode. + This function is only available on x64. After the 64-bit paging mode is + disabled, control is transferred to the function specified by EntryPoint + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional a= nd + may be 0. The function EntryPoint must never return. + + If the current execution mode is not 64-bit paged mode, then ASSERT(). + If EntryPoint is 0, then ASSERT(). + If NewStack is 0, then ASSERT(). + + @param Cs The 16-bit selector to load in the CS before EntryPo= int + is called. The descriptor in the GDT that this selec= tor + references must be setup for 32-bit protected mode. + @param EntryPoint The 64-bit virtual address of the function to call w= ith + the new stack after paging is disabled. + @param Context1 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the first parameter after + paging is disabled. + @param Context2 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the second parameter after + paging is disabled. + @param NewStack The 64-bit virtual address of the new stack to use f= or + the EntryPoint function after paging is disabled. + +**/ +VOID +EFIAPI +AsmDisablePaging64 ( + IN UINT16 Cs, + IN UINT32 EntryPoint, + IN UINT32 Context1, OPTIONAL + IN UINT32 Context2, OPTIONAL + IN UINT32 NewStack + ) +{ + gUnitTestHostBaseLib.X86->AsmDisablePaging64 (Cs, EntryPoint, Context1, = Context2, NewStack); +} + +/** + Retrieves the properties for 16-bit thunk functions. + + Computes the size of the buffer and stack below 1MB required to use the + AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. = This + buffer size is returned in RealModeBufferSize, and the stack size is ret= urned + in ExtraStackSize. If parameters are passed to the 16-bit real mode code, + then the actual minimum stack size is ExtraStackSize plus the maximum nu= mber + of bytes that need to be passed to the 16-bit real mode code. + + If RealModeBufferSize is NULL, then ASSERT(). + If ExtraStackSize is NULL, then ASSERT(). + + @param RealModeBufferSize A pointer to the size of the buffer below 1MB + required to use the 16-bit thunk functions. + @param ExtraStackSize A pointer to the extra size of stack below 1= MB + that the 16-bit thunk functions require for + temporary storage in the transition to and f= rom + 16-bit real mode. + +**/ +VOID +EFIAPI +AsmGetThunk16Properties ( + OUT UINT32 *RealModeBufferSize, + OUT UINT32 *ExtraStackSize + ) +{ + gUnitTestHostBaseLib.X86->AsmGetThunk16Properties (RealModeBufferSize, E= xtraStackSize); +} + +/** + Prepares all structures a code required to use AsmThunk16(). + + Prepares all structures and code required to use AsmThunk16(). + + This interface is limited to be used in either physical mode or virtual = modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1= :1. + + If ThunkContext is NULL, then ASSERT(). + + @param ThunkContext A pointer to the context structure that describes = the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +AsmPrepareThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ) +{ + gUnitTestHostBaseLib.X86->AsmPrepareThunk16 (ThunkContext); +} + +/** + Transfers control to a 16-bit real mode entry point and returns the resu= lts. + + Transfers control to a 16-bit real mode entry point and returns the resu= lts. + AsmPrepareThunk16() must be called with ThunkContext before this functio= n is used. + This function must be called with interrupts disabled. + + The register state from the RealModeState field of ThunkContext is resto= red just prior + to calling the 16-bit real mode entry point. This includes the EFLAGS f= ield of RealModeState, + which is used to set the interrupt state when a 16-bit real mode entry p= oint is called. + Control is transferred to the 16-bit real mode entry point specified by = the CS and Eip fields of RealModeState. + The stack is initialized to the SS and ESP fields of RealModeState. Any= parameters passed to + the 16-bit real mode code must be populated by the caller at SS:ESP prio= r to calling this function. + The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instr= uction, + so when accessing stack contents, the 16-bit real mode code must account= for the 16-bit segment + and 16-bit offset of the return address that were pushed onto the stack.= The 16-bit real mode entry + point must exit with a RETF instruction. The register state is captured = into RealModeState immediately + after the RETF instruction is executed. + + If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode c= ode enables interrupts, + or any of the 16-bit real mode code makes a SW interrupt, then the calle= r is responsible for making sure + the IDT at address 0 is initialized to handle any HW or SW interrupts th= at may occur while in 16-bit real mode. + + If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode c= ode enables interrupts, + then the caller is responsible for making sure the 8259 PIC is in a stat= e compatible with 16-bit real mode. + This includes the base vectors, the interrupt masks, and the edge/level = trigger mode. + + If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of = ThunkContext, then the user code + is invoked in big real mode. Otherwise, the user code is invoked in 16-= bit real mode with 64KB segment limits. + + If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_D= ISABLE_A20_MASK_KBD_CTRL are set in + ThunkAttributes, then it is assumed that the user code did not enable th= e A20 mask, and no attempt is made to + disable the A20 mask. + + If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DI= SABLE_A20_MASK_KBD_CTRL is clear in + ThunkAttributes, then attempt to use the INT 15 service to disable the A= 20 mask. If this INT 15 call fails, + then attempt to disable the A20 mask by directly accessing the 8042 keyb= oard controller I/O ports. + + If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_= DISABLE_A20_MASK_KBD_CTRL is set in + ThunkAttributes, then attempt to disable the A20 mask by directly access= ing the 8042 keyboard controller I/O ports. + + If ThunkContext is NULL, then ASSERT(). + If AsmPrepareThunk16() was not previously called with ThunkContext, then= ASSERT(). + If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISA= BLE_A20_MASK_KBD_CTRL are set in + ThunkAttributes, then ASSERT(). + + This interface is limited to be used in either physical mode or virtual = modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer are mapped = 1:1. + + @param ThunkContext A pointer to the context structure that describes = the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +AsmThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ) +{ + gUnitTestHostBaseLib.X86->AsmThunk16 (ThunkContext); +} + +/** + Prepares all structures and code for a 16-bit real mode thunk, transfers + control to a 16-bit real mode entry point, and returns the results. + + Prepares all structures and code for a 16-bit real mode thunk, transfers + control to a 16-bit real mode entry point, and returns the results. If t= he + caller only need to perform a single 16-bit real mode thunk, then this + service should be used. If the caller intends to make more than one 16-b= it + real mode thunk, then it is more efficient if AsmPrepareThunk16() is cal= led + once and AsmThunk16() can be called for each 16-bit real mode thunk. + + This interface is limited to be used in either physical mode or virtual = modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1= :1. + + See AsmPrepareThunk16() and AsmThunk16() for the detailed description an= d ASSERT() conditions. + + @param ThunkContext A pointer to the context structure that describes = the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +AsmPrepareAndThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ) +{ + gUnitTestHostBaseLib.X86->AsmPrepareAndThunk16 (ThunkContext); +} + +/** + Load given selector into TR register. + + @param[in] Selector Task segment selector +**/ +VOID +EFIAPI +AsmWriteTr ( + IN UINT16 Selector + ) +{ + gUnitTestHostBaseLib.X86->AsmWriteTr (Selector); +} + +/** + Performs a serializing operation on all load-from-memory instructions th= at + were issued prior the AsmLfence function. + + Executes a LFENCE instruction. This function is only available on IA-32 = and x64. + +**/ +VOID +EFIAPI +AsmLfence ( + VOID + ) +{ + gUnitTestHostBaseLib.X86->AsmLfence (); +} + +/** + Patch the immediate operand of an IA32 or X64 instruction such that the = byte, + word, dword or qword operand is encoded at the end of the instruction's + binary representation. + + This function should be used to update object code that was compiled with + NASM from assembly source code. Example: + + NASM source code: + + mov eax, strict dword 0 ; the imm32 zero operand will be patch= ed + ASM_PFX(gPatchCr3): + mov cr3, eax + + C source code: + + X86_ASSEMBLY_PATCH_LABEL gPatchCr3; + PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4); + + @param[out] InstructionEnd Pointer right past the instruction to patch.= The + immediate operand to patch is expected to + comprise the trailing bytes of the instructi= on. + If InstructionEnd is closer to address 0 than + ValueSize permits, then ASSERT(). + + @param[in] PatchValue The constant to write to the immediate opera= nd. + The caller is responsible for ensuring that + PatchValue can be represented in the byte, w= ord, + dword or qword operand (as indicated through + ValueSize); otherwise ASSERT(). + + @param[in] ValueSize The size of the operand in bytes; must be 1,= 2, + 4, or 8. ASSERT() otherwise. +**/ +VOID +EFIAPI +PatchInstructionX86 ( + OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, + IN UINT64 PatchValue, + IN UINTN ValueSize + ) +{ + gUnitTestHostBaseLib.X86->PatchInstructionX86 (InstructionEnd, PatchValu= e, ValueSize); +} + +/// +/// Common services +/// +STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon =3D { + UnitTestHostBaseLibEnableInterrupts, + UnitTestHostBaseLibDisableInterrupts, + UnitTestHostBaseLibEnableDisableInterrupts, + UnitTestHostBaseLibGetInterruptState, +}; + +/// +/// IA32/X64 services +/// +STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86 =3D { + UnitTestHostBaseLibAsmCpuid, + UnitTestHostBaseLibAsmCpuidEx, + UnitTestHostBaseLibAsmDisableCache, + UnitTestHostBaseLibAsmEnableCache, + UnitTestHostBaseLibAsmReadMsr64, + UnitTestHostBaseLibAsmWriteMsr64, + UnitTestHostBaseLibAsmReadCr0, + UnitTestHostBaseLibAsmReadCr2, + UnitTestHostBaseLibAsmReadCr3, + UnitTestHostBaseLibAsmReadCr4, + UnitTestHostBaseLibAsmWriteCr0, + UnitTestHostBaseLibAsmWriteCr2, + UnitTestHostBaseLibAsmWriteCr3, + UnitTestHostBaseLibAsmWriteCr4, + UnitTestHostBaseLibAsmReadDr0, + UnitTestHostBaseLibAsmReadDr1, + UnitTestHostBaseLibAsmReadDr2, + UnitTestHostBaseLibAsmReadDr3, + UnitTestHostBaseLibAsmReadDr4, + UnitTestHostBaseLibAsmReadDr5, + UnitTestHostBaseLibAsmReadDr6, + UnitTestHostBaseLibAsmReadDr7, + UnitTestHostBaseLibAsmWriteDr0, + UnitTestHostBaseLibAsmWriteDr1, + UnitTestHostBaseLibAsmWriteDr2, + UnitTestHostBaseLibAsmWriteDr3, + UnitTestHostBaseLibAsmWriteDr4, + UnitTestHostBaseLibAsmWriteDr5, + UnitTestHostBaseLibAsmWriteDr6, + UnitTestHostBaseLibAsmWriteDr7, + UnitTestHostBaseLibAsmReadCs, + UnitTestHostBaseLibAsmReadDs, + UnitTestHostBaseLibAsmReadEs, + UnitTestHostBaseLibAsmReadFs, + UnitTestHostBaseLibAsmReadGs, + UnitTestHostBaseLibAsmReadSs, + UnitTestHostBaseLibAsmReadTr, + UnitTestHostBaseLibAsmReadGdtr, + UnitTestHostBaseLibAsmWriteGdtr, + UnitTestHostBaseLibAsmReadIdtr, + UnitTestHostBaseLibAsmWriteIdtr, + UnitTestHostBaseLibAsmReadLdtr, + UnitTestHostBaseLibAsmWriteLdtr, + UnitTestHostBaseLibAsmReadPmc, + UnitTestHostBaseLibAsmMonitor, + UnitTestHostBaseLibAsmMwait, + UnitTestHostBaseLibAsmWbinvd, + UnitTestHostBaseLibAsmInvd, + UnitTestHostBaseLibAsmFlushCacheLine, + UnitTestHostBaseLibAsmEnablePaging32, + UnitTestHostBaseLibAsmDisablePaging32, + UnitTestHostBaseLibAsmEnablePaging64, + UnitTestHostBaseLibAsmDisablePaging64, + UnitTestHostBaseLibAsmGetThunk16Properties, + UnitTestHostBaseLibAsmPrepareThunk16, + UnitTestHostBaseLibAsmThunk16, + UnitTestHostBaseLibAsmPrepareAndThunk16, + UnitTestHostBaseLibAsmWriteTr, + UnitTestHostBaseLibAsmLfence, + UnitTestHostBaseLibPatchInstructionX86 +}; + +/// +/// Structure of hook functions for BaseLib functions that can not be used= from +/// a host application. A simple emulation of these function is provided = by +/// default. A specific unit test can provide its own implementation for = any +/// of these functions. +/// +UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib =3D { + &mUnitTestHostBaseLibCommon, + &mUnitTestHostBaseLibX86 +}; diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 682e61cb88..73f6c24073 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -4,7 +4,7 @@ # It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of # EFI1.10/UEFI2.7/PI1.7 and some Industry Standards. # -# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# (C) Copyright 2016 - 2020 Hewlett Packard Enterprise Development LP
# @@ -23,6 +23,7 @@ [Defines] =20 [Includes] Include + Test/UnitTest/Include =20 [Includes.IA32] Include/Ia32 @@ -251,6 +252,11 @@ [LibraryClasses] # UnitTestLib|Include/Library/UnitTestLib.h =20 + ## @libraryclass Extension to BaseLib for host based unit tests that all= ows a + # subset of BaseLib services to be hooked for emulation. + # + UnitTestHostBaseLib|Test/UnitTest/Include/Library/UnitTestHostBaseLib.h + [LibraryClasses.IA32, LibraryClasses.X64] ## @libraryclass Abstracts both S/W SMI generation and detection. ## diff --git a/MdePkg/Test/MdePkgHostTest.dsc b/MdePkg/Test/MdePkgHostTest.dsc index 3d677ee75c..0cac14f0e5 100644 --- a/MdePkg/Test/MdePkgHostTest.dsc +++ b/MdePkg/Test/MdePkgHostTest.dsc @@ -28,3 +28,8 @@ [Components] # MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibHost.inf MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsHost.inf + + # + # Build HOST_APPLICATION Libraries + # + MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf diff --git a/MdePkg/Test/UnitTest/Include/Library/UnitTestHostBaseLib.h b/M= dePkg/Test/UnitTest/Include/Library/UnitTestHostBaseLib.h new file mode 100644 index 0000000000..4ad05a5af1 --- /dev/null +++ b/MdePkg/Test/UnitTest/Include/Library/UnitTestHostBaseLib.h @@ -0,0 +1,582 @@ +/** @file + Unit Test Host BaseLib hooks. + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UNIT_TEST_HOST_BASE_LIB_H__ +#define __UNIT_TEST_HOST_BASE_LIB_H__ + +/** + Prototype of service with no parameters and no return value. +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_VOID)( + VOID + ); + +/** + Prototype of service that reads and returns a BOOLEAN value. + + @return The value read. +**/ +typedef +BOOLEAN +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN)( + VOID + ); + +/** + Prototype of service that reads and returns a UINT16 value. + + @return The value read. +**/ +typedef +UINT16 +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINT16)( + VOID + ); + +/** + Prototype of service that reads and returns a UINTN value. + + @return The value read. +**/ +typedef +UINTN +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINTN)( + VOID + ); + +/** + Prototype of service that writes and returns a UINT16 value. + + @param[in] Value The value to write. + + @return The value written. +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16)( + IN UINT16 Value + ); + +/** + Prototype of service that writes and returns a UINTN value. + + @param[in] Value The value to write. + + @return The value written. +**/ +typedef +UINTN +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN)( + IN UINTN Value + ); + +/** + Prototype of service that reads and returns an IA32_DESCRIPTOR. + + @param[out] Ia32Descriptor Pointer to the descriptor read. +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR)( + OUT IA32_DESCRIPTOR *Ia32Descriptor + ); + +/** + Prototype of service that writes an IA32_DESCRIPTOR. + + @param[in] Ia32Descriptor Pointer to the descriptor to write. +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR)( + IN CONST IA32_DESCRIPTOR *Ia32Descriptor + ); + +/** + Retrieves CPUID information. + + Executes the CPUID instruction with EAX set to the value specified by In= dex. + This function always returns Index. + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + This function is only available on IA-32 and x64. + + @param Index The 32-bit value to load into EAX prior to invoking the CP= UID + instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ebx The pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ecx The pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Edx The pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + + @return Index. + +**/ +typedef +UINT32 +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID)( + IN UINT32 Index, + OUT UINT32 *Eax, OPTIONAL + OUT UINT32 *Ebx, OPTIONAL + OUT UINT32 *Ecx, OPTIONAL + OUT UINT32 *Edx OPTIONAL + ); + +/** + Retrieves CPUID information using an extended leaf identifier. + + Executes the CPUID instruction with EAX set to the value specified by In= dex + and ECX set to the value specified by SubIndex. This function always ret= urns + Index. This function is only available on IA-32 and x64. + + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + + @param Index The 32-bit value to load into EAX prior to invoking the + CPUID instruction. + @param SubIndex The 32-bit value to load into ECX prior to invoking the + CPUID instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ebx The pointer to the 32-bit EBX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ecx The pointer to the 32-bit ECX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Edx The pointer to the 32-bit EDX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + + @return Index. + +**/ +typedef +UINT32 +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX)( + IN UINT32 Index, + IN UINT32 SubIndex, + OUT UINT32 *Eax, OPTIONAL + OUT UINT32 *Ebx, OPTIONAL + OUT UINT32 *Ecx, OPTIONAL + OUT UINT32 *Edx OPTIONAL + ); + +/** + Returns a 64-bit Machine Specific Register(MSR). + + Reads and returns the 64-bit MSR specified by Index. No parameter checki= ng is + performed on Index, and some Index values may cause CPU exceptions. The + caller must either guarantee that Index is valid, or the caller must set= up + exception handlers to catch the exceptions. This function is only availa= ble + on IA-32 and x64. + + @param Index The 32-bit MSR index to read. + + @return The value of the MSR identified by Index. + +**/ +typedef +UINT64 +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64)( + IN UINT32 Index + ); + +/** + Writes a 64-bit value to a Machine Specific Register(MSR), and returns t= he + value. + + Writes the 64-bit value specified by Value to the MSR specified by Index= . The + 64-bit value written to the MSR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions.= The + caller must either guarantee that Index and Value are valid, or the call= er + must establish proper exception handlers. This function is only availabl= e on + IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param Value The 64-bit value to write to the MSR. + + @return Value + +**/ +typedef +UINT64 +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64)( + IN UINT32 Index, + IN UINT64 Value + ); + +/** + Reads the current value of a Performance Counter (PMC). + + Reads and returns the current value of performance counter specified by + Index. This function is only available on IA-32 and x64. + + @param Index The 32-bit Performance Counter index to read. + + @return The value of the PMC specified by Index. + +**/ +typedef +UINT64 +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC)( + IN UINT32 Index + ); + +/** + Sets up a monitor buffer that is used by AsmMwait(). + + Executes a MONITOR instruction with the register state specified by Eax,= Ecx + and Edx. Returns Eax. This function is only available on IA-32 and x64. + + @param Eax The value to load into EAX or RAX before executing the MONIT= OR + instruction. + @param Ecx The value to load into ECX or RCX before executing the MONIT= OR + instruction. + @param Edx The value to load into EDX or RDX before executing the MONIT= OR + instruction. + + @return Eax + +**/ +typedef +UINTN +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR)( + IN UINTN Eax, + IN UINTN Ecx, + IN UINTN Edx + ); + +/** + Executes an MWAIT instruction. + + Executes an MWAIT instruction with the register state specified by Eax a= nd + Ecx. Returns Eax. This function is only available on IA-32 and x64. + + @param Eax The value to load into EAX or RAX before executing the MONIT= OR + instruction. + @param Ecx The value to load into ECX or RCX before executing the MONIT= OR + instruction. + + @return Eax + +**/ +typedef +UINTN +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT)( + IN UINTN Eax, + IN UINTN Ecx + ); + +/** + Flushes a cache line from all the instruction and data caches within the + coherency domain of the CPU. + + Flushed the cache line specified by LinearAddress, and returns LinearAdd= ress. + This function is only available on IA-32 and x64. + + @param LinearAddress The address of the cache line to flush. If the CPU= is + in a physical addressing mode, then LinearAddress = is a + physical address. If the CPU is in a virtual + addressing mode, then LinearAddress is a virtual + address. + + @return LinearAddress. +**/ +typedef +VOID * +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE)( + IN VOID *LinearAddress + ); + +/** + Prototype of service that enables ot disables 32-bit paging modes. + + @param EntryPoint A pointer to function to call with the new stack aft= er + paging is enabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is enab= led. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is ena= bled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is enabled. + +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32)( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ); + +/** + Enables the 64-bit paging mode on the CPU. + + Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page t= ables + must be properly initialized prior to calling this service. This function + assumes the current execution mode is 32-bit protected mode with flat + descriptors. This function is only available on IA-32. After the 64-bit + paging mode is enabled, control is transferred to the function specified= by + EntryPoint using the new stack specified by NewStack and passing in the + parameters specified by Context1 and Context2. Context1 and Context2 are + optional and may be 0. The function EntryPoint must never return. + + If the current execution mode is not 32-bit protected mode with flat + descriptors, then ASSERT(). + If EntryPoint is 0, then ASSERT(). + If NewStack is 0, then ASSERT(). + + @param Cs The 16-bit selector to load in the CS before EntryPo= int + is called. The descriptor in the GDT that this selec= tor + references must be setup for long mode. + @param EntryPoint The 64-bit virtual address of the function to call w= ith + the new stack after paging is enabled. + @param Context1 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the first parameter after + paging is enabled. + @param Context2 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the second parameter after + paging is enabled. + @param NewStack The 64-bit virtual address of the new stack to use f= or + the EntryPoint function after paging is enabled. + +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64)( + IN UINT16 Cs, + IN UINT64 EntryPoint, + IN UINT64 Context1, OPTIONAL + IN UINT64 Context2, OPTIONAL + IN UINT64 NewStack + ); + +/** + Disables the 64-bit paging mode on the CPU. + + Disables the 64-bit paging mode on the CPU and returns to 32-bit protect= ed + mode. This function assumes the current execution mode is 64-paging mode. + This function is only available on x64. After the 64-bit paging mode is + disabled, control is transferred to the function specified by EntryPoint + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional a= nd + may be 0. The function EntryPoint must never return. + + If the current execution mode is not 64-bit paged mode, then ASSERT(). + If EntryPoint is 0, then ASSERT(). + If NewStack is 0, then ASSERT(). + + @param Cs The 16-bit selector to load in the CS before EntryPo= int + is called. The descriptor in the GDT that this selec= tor + references must be setup for 32-bit protected mode. + @param EntryPoint The 64-bit virtual address of the function to call w= ith + the new stack after paging is disabled. + @param Context1 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the first parameter after + paging is disabled. + @param Context2 The 64-bit virtual address of the context to pass in= to + the EntryPoint function as the second parameter after + paging is disabled. + @param NewStack The 64-bit virtual address of the new stack to use f= or + the EntryPoint function after paging is disabled. + +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64)( + IN UINT16 Cs, + IN UINT32 EntryPoint, + IN UINT32 Context1, OPTIONAL + IN UINT32 Context2, OPTIONAL + IN UINT32 NewStack + ); + +/** + Retrieves the properties for 16-bit thunk functions. + + Computes the size of the buffer and stack below 1MB required to use the + AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. = This + buffer size is returned in RealModeBufferSize, and the stack size is ret= urned + in ExtraStackSize. If parameters are passed to the 16-bit real mode code, + then the actual minimum stack size is ExtraStackSize plus the maximum nu= mber + of bytes that need to be passed to the 16-bit real mode code. + + If RealModeBufferSize is NULL, then ASSERT(). + If ExtraStackSize is NULL, then ASSERT(). + + @param RealModeBufferSize A pointer to the size of the buffer below 1MB + required to use the 16-bit thunk functions. + @param ExtraStackSize A pointer to the extra size of stack below 1= MB + that the 16-bit thunk functions require for + temporary storage in the transition to and f= rom + 16-bit real mode. + +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES)( + OUT UINT32 *RealModeBufferSize, + OUT UINT32 *ExtraStackSize + ); + +/** + Prototype of services that operates on a THUNK_CONTEXT structure. + + @param ThunkContext A pointer to the context structure that describes = the + 16-bit real mode code to call. + +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16)( + IN OUT THUNK_CONTEXT *ThunkContext + ); + +/** + Patch the immediate operand of an IA32 or X64 instruction such that the = byte, + word, dword or qword operand is encoded at the end of the instruction's + binary representation. + + This function should be used to update object code that was compiled with + NASM from assembly source code. Example: + + NASM source code: + + mov eax, strict dword 0 ; the imm32 zero operand will be patch= ed + ASM_PFX(gPatchCr3): + mov cr3, eax + + C source code: + + X86_ASSEMBLY_PATCH_LABEL gPatchCr3; + PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4); + + @param[out] InstructionEnd Pointer right past the instruction to patch.= The + immediate operand to patch is expected to + comprise the trailing bytes of the instructi= on. + If InstructionEnd is closer to address 0 than + ValueSize permits, then ASSERT(). + + @param[in] PatchValue The constant to write to the immediate opera= nd. + The caller is responsible for ensuring that + PatchValue can be represented in the byte, w= ord, + dword or qword operand (as indicated through + ValueSize); otherwise ASSERT(). + + @param[in] ValueSize The size of the operand in bytes; must be 1,= 2, + 4, or 8. ASSERT() otherwise. +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86)( + OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, + IN UINT64 PatchValue, + IN UINTN ValueSize + ); + +/// +/// Common services +/// +typedef struct { + UNIT_TEST_HOST_BASE_LIB_VOID EnableInterrupts; + UNIT_TEST_HOST_BASE_LIB_VOID DisableInterrupts; + UNIT_TEST_HOST_BASE_LIB_VOID EnableDisableInterrupts; + UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN GetInterruptState; +} UNIT_TEST_HOST_BASE_LIB_COMMON; + +/// +/// IA32/X64 services +/// +typedef struct { + UNIT_TEST_HOST_BASE_LIB_ASM_CPUID AsmCpuid; + UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX AsmCpuidEx; + UNIT_TEST_HOST_BASE_LIB_VOID AsmDisableCache; + UNIT_TEST_HOST_BASE_LIB_VOID AsmEnableCache; + UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64 AsmReadMsr64; + UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64 AsmWriteMsr64; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr0; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr2; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr3; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr4; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr0; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr2; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr3; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr4; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr0; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr1; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr2; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr3; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr4; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr5; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr6; + UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr7; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr0; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr1; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr2; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr3; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr4; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr5; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr6; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr7; + UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadCs; + UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadDs; + UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadEs; + UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadFs; + UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadGs; + UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadSs; + UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadTr; + UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadGdtr; + UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteGdtr; + UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadIdtr; + UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteIdtr; + UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadLdtr; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteLdtr; + UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC AsmReadPmc; + UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR AsmMonitor; + UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT AsmMwait; + UNIT_TEST_HOST_BASE_LIB_VOID AsmWbinvd; + UNIT_TEST_HOST_BASE_LIB_VOID AsmInvd; + UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE AsmFlushCacheLine; + UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmEnablePaging32; + UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmDisablePaging32; + UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64 AsmEnablePaging64; + UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64 AsmDisablePaging64; + UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES AsmGetThunk16Proper= ties; + UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareThunk16; + UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmThunk16; + UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareAndThunk1= 6; + UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteTr; + UNIT_TEST_HOST_BASE_LIB_VOID AsmLfence; + UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86 PatchInstructionX86; +} UNIT_TEST_HOST_BASE_LIB_X86; + +/// +/// Data structure that contains pointers structures of common services an= d CPU +/// architctuire specific services. Support for additional CPU architectu= res +/// can be added to the end of this structure. +/// +typedef struct { + UNIT_TEST_HOST_BASE_LIB_COMMON *Common; + UNIT_TEST_HOST_BASE_LIB_X86 *X86; +} UNIT_TEST_HOST_BASE_LIB; + +extern UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib; + +#endif --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62359): https://edk2.groups.io/g/devel/message/62359 Mute This Topic: https://groups.io/mt/75432219/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62357+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62357+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433352; cv=none; d=zohomail.com; s=zohoarc; b=cNdP42R0f1z8z3cD4ITS86gR7r+e3/0npmVFpN2RKmonJ2SnjKsR3hU4KuS6X3vOJbgXL6pSoaN50wKSiRladbKLkc8vi5TqAlqXQ/utLT160+LbuuMgoqP7PiD+kAn0PnQioaz0+d7sk7HJqUPkirQmmDE1S1SlsABa7Eh9nU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433352; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=0wRgglqJLBwGZ1TXfa/NRbWNmXeOS7hrQNjqDoT/tNs=; b=Gyi6E5+Dky1y5O795fXG6RchhiykKYvB7duOKX0MRMXO+swXi4+2nb2jL26fRMj78VqYyb7sDF7Z+mZAYKA+lvqwrPJXptlwYCRMKFmpW+3NmgjdXYrUV8XAkzMX4micKc2rm6/mqsy5p8T/QA92f+NTHwnfyCA7bkYjXwdAs4Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62357+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433352342330.3316466760763; Fri, 10 Jul 2020 19:09:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id xo5rYY1788612x1JTqQ5PZya; Fri, 10 Jul 2020 19:09:12 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web10.2144.1594433349022222645 for ; Fri, 10 Jul 2020 19:09:11 -0700 IronPort-SDR: GZF1evRQ+gJRBtP4WM6WjHm+DrDizWc1xFnX7lucvjaV3lVXwicG/9II11jSkbNG7gSAyta7c4 9BwIK0n+tlOA== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380548" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380548" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:10 -0700 IronPort-SDR: yYE2Pb3j0hrS0dTdS18/cYUxVthMSdA7QvvOENWwDKzJaDHQuAF1/rR4rojy3UM93Gcae6yP88 rXZVf5fzf8Pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602267" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:10 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 06/16] UnitTestFrameworkPkg: Use host libraries from MdePkg Date: Fri, 10 Jul 2020 19:08:54 -0700 Message-Id: <20200711020904.24116-7-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: GPFVxB51tRK5AutpwZrrqClUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433352; bh=Gnv5jCzT2adPjcNvqoELTvgETEyevyYaQrQCsjvvRo4=; h=Cc:Date:From:Reply-To:Subject:To; b=J965Y6qaMerJEbg2KmssEndFa4AwWpS84OYacOrYlQ5/ez3zy3TdgBGbF1lCjMWhFmy snSawj6siBwXQ+AcuiDjw4X52w44mBKvchgBbmyDqoMOEio++NpEyf1mjdwNvxrXKt6ux KKcMA3CQs/jrZzUYL42awD+40m//KnUPTKg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2800 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2799 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2798 Update the default unit test library mappings to use the library instances from the MdePkg that are safe for host based unit tests. Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc b/UnitTe= stFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc index e954968efc..c22085fae1 100644 --- a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc +++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc @@ -9,6 +9,10 @@ !include UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc =20 [LibraryClasses.common.HOST_APPLICATION] + BaseLib|MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf + UnitTestHostBaseLib|MdePkg/Library/BaseLib/UnitTestHostBaseLib.inf + CpuLib|MdePkg/Library/BaseCpuLibNull/BaseCpuLibNull.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLibNull/BaseCache= MaintenanceLibNull.inf CmockaLib|UnitTestFrameworkPkg/Library/CmockaLib/CmockaLib.inf UnitTestLib|UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLibCmocka.i= nf DebugLib|UnitTestFrameworkPkg/Library/Posix/DebugLibPosix/DebugLibPosix.= inf --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62357): https://edk2.groups.io/g/devel/message/62357 Mute This Topic: https://groups.io/mt/75432217/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62358+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62358+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433352; cv=none; d=zohomail.com; s=zohoarc; b=esNfG4gbhsJhx1JegjUCQ9ysnuZe0WS9ukSr0FAtvHsUQSSPPaWp4ZYLxyK/XLNflJAu+7r9Zz3YvpowgrOzAmCK7Wfq/IoZitDFiXTv8sWHBqAvOjRsDYFr11/XDWG+0CPTEAwyFX54+/uOQsETaLv6bX/uazji0qPKZS3u4CY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433352; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xXKVjmOfZPrEaUJTIQ3JNPqtjL8u3lzwoHzG54FNBxg=; b=FUUS/ez+XzDBodPWLGh8ES93DS8nq7udXvJ25fB92jEyufYwiC0N8A7DpwWe7xgXKtghzx4oERrXyH5EIatcq5qyp2eWszRYqc62+t8OpcowtfwEXHapUpPK9ydn4zwGCDNcD0sE5+TDy+wkmgzbPrHGhlXjGwI1b2o0nkQdbh8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62358+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433352503839.5507588378383; Fri, 10 Jul 2020 19:09:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BqkLYY1788612xRHuwv4gBpI; Fri, 10 Jul 2020 19:09:12 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web10.2144.1594433349022222645 for ; Fri, 10 Jul 2020 19:09:11 -0700 IronPort-SDR: aKmN62YjzGCntY0TkFDkikgcVDNMHyoN5XInGEzgtlCp5jyqWz/s+jFqHiKgf1miVv0SLhanUq vlrMKeG34Mdw== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380552" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380552" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:11 -0700 IronPort-SDR: etObQOheEEYf39AsObOon9/cXLB0c2muOJgvMqJejHcPKnuCVk2KJkXvZKzz2U3AwPBCXzApzz GoFoF3N2uOQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602273" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:10 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 07/16] UnitTestFrameworkPkg: Enable source level debug for host tests Date: Fri, 10 Jul 2020 19:08:55 -0700 Message-Id: <20200711020904.24116-8-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: O7vk5ZyAqEkkTJSflVFJZMqvx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433352; bh=qvalx6KpiOCgFRDf2EioZ2FTnwR7sXvCJc4Q9OU1vL4=; h=Cc:Date:From:Reply-To:Subject:To; b=kIWyzP3cklEf9FPHIpSAhH0PlbjFueuTJ1X9F9Z/kvpQ8vdbcnB6Gi8FKpY312eP3NZ Z0iRzgHGp0ICuYmabTzGbfF/1GDgRLRCOs1AANSLadM0x60eGvdYWVVmtUlcaC3+Po/Pv H421kxVmhU1xA7g1QqTTOYlaDwSIoghH0ko= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2804 Optionally enable a feature to support source level debug of a host based unit test. By default, this feature is disabled. Exceptions are caught by the unit test framework and are interpreted as a test failure. When a unit test is under development, bugs may generate exceptions or a unit test developer may want to trace the execution of unit tests to debug some unexpected behavior. Defining UNIT_TESTING_DEBUG in the DSC file or from the build command line allows exceptions to be caught by the host OS and allows the developer to debug their unit test under development or debug the Unit Test Framework itself. Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc b/UnitTe= stFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc index c22085fae1..c4e6e0e0a6 100644 --- a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc +++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc @@ -20,6 +20,11 @@ [LibraryClasses.common.HOST_APPLICATION] =20 [BuildOptions] GCC:*_*_*_CC_FLAGS =3D -fno-pie +!ifdef $(UNIT_TESTING_DEBUG) + MSFT:*_*_*_CC_FLAGS =3D -D UNIT_TESTING_DEBUG=3D1 + GCC:*_*_*_CC_FLAGS =3D -D UNIT_TESTING_DEBUG=3D1 + XCODE:*_*_*_CC_FLAGS =3D -D UNIT_TESTING_DEBUG=3D1 +!endif =20 [BuildOptions.common.EDKII.HOST_APPLICATION] # --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62358): https://edk2.groups.io/g/devel/message/62358 Mute This Topic: https://groups.io/mt/75432218/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62360+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62360+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433353; cv=none; d=zohomail.com; s=zohoarc; b=G5rTsJ49BspoWfMlZCz3UEe47IvbGUQnCg7SLLFS9g3adf8d5lW6Vmlm3/EXE/ejKDfsIVPXmZiU1SZd39w+fTPVYYobtC1OkEebqIZkF7bht8sArgHddswc8gL+mTMkZXJcjB3NaM4U+fViDAR5zWA8T0FKF/0IIMqEyAmtm50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433353; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GyLwG+qQPw3jC6LQ7xLcSjA8o1yjgYRbZTApOKzobqo=; b=MRU4buGQ77i7GWem0+dgbRq7lx2vn3r85tlVWFX0G/YU3747btjayFANBT4EgzPAH8QdQrd/cmMCS32O73aiFfeSX68zbx/S4htFmfloOn6NFS9RlgmFYyUkbbbUIxL4W8sNAxJzd6kxoWBN7G02PbBjxZkz28rywkDqLh0RRQA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62360+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433353532867.4644978930038; Fri, 10 Jul 2020 19:09:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id lmDgYY1788612x1DIvDQpu36; Fri, 10 Jul 2020 19:09:13 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web10.2144.1594433349022222645 for ; Fri, 10 Jul 2020 19:09:11 -0700 IronPort-SDR: tGBwfL19LrC9Xl7DB/odCirubEAHKZqUVMNGDLaq99PiXpdKSD8Q1la7rcyEg14hdBIEskiEYi 5U/pRY6zgKPA== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380557" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380557" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:11 -0700 IronPort-SDR: mxceq28npAESB7gEAuB722f33Pz37+BioZUk7ImOn1tUmrNjC/TKfuTuFYPE87bGW7KZUFriFA GZQOeKMba0nw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602279" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:11 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 08/16] UnitTestFrameworkPkg: Set host application stack size to 256KB Date: Fri, 10 Jul 2020 19:08:56 -0700 Message-Id: <20200711020904.24116-9-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: lH2uTpoqRTIqawMKIVlsbWhlx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433353; bh=DlozgU84h83t4t5TO96mohZalcUtWRObYtMXPWlCNmM=; h=Cc:Date:From:Reply-To:Subject:To; b=B7EqsuGCAwKl3riDZRiwGi8xF8PULfHjkJkOoWUflZfGfiNKiQYXQPirWVdC4B/s21I vGv1VTZINZdMe4HvuRUyU3BKGQSHEEtg0+9OGadzP5Oa03yirbzpMAeRAl5NRYxyketJF NwMvWNyUrbbzhSC6ySfAENPjLl69qzehljY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2803 The UEFI Specification defines the minimum stack size before ExitBootServices() to be 128KB. When running a host based unit test, there may be additional stack overhead from the host application environment and cmocka. Update the build flags to set the size of the stack to 256KB which is double the UEFI Specification requirement. Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc b/UnitTe= stFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc index c4e6e0e0a6..4dd8d4ac67 100644 --- a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc +++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc @@ -30,7 +30,7 @@ [BuildOptions.common.EDKII.HOST_APPLICATION] # # MSFT # - MSFT:*_*_*_DLINK_FLAGS =3D=3D /out:"$(BIN_DIR)\$(BASE_NAME).e= xe" /pdb:"$(BIN_DIR)\$(BASE_NAME).pdb" /IGNORE:4001 /NOLOGO /SUBSYSTEM:CONS= OLE /DEBUG /NODEFAULTLIB:libcmt.lib libcmtd.lib + MSFT:*_*_*_DLINK_FLAGS =3D=3D /out:"$(BIN_DIR)\$(BASE_NAME).e= xe" /pdb:"$(BIN_DIR)\$(BASE_NAME).pdb" /IGNORE:4001 /NOLOGO /SUBSYSTEM:CONS= OLE /DEBUG /STACK:0x40000,0x40000 /NODEFAULTLIB:libcmt.lib libcmtd.lib MSFT:*_*_IA32_DLINK_FLAGS =3D /MACHINE:I386 MSFT:*_*_X64_DLINK_FLAGS =3D /MACHINE:AMD64 =20 --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62360): https://edk2.groups.io/g/devel/message/62360 Mute This Topic: https://groups.io/mt/75432220/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62361+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62361+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433354; cv=none; d=zohomail.com; s=zohoarc; b=eRhBs0HhbzKcFFbYeBa4eVWk2ynZSCtbR5c1A5tVtuKI/XJs/P6SY5/42rPkpv1llYC4nirHUN6n1ewTQ/zicFglw2EWDJEb5lw/Lo/WQjc8LQPA7soZ86eAPxOFWCkbohp0hGBuHKM1o9WII1hclhZsc8OHPHPy+oUIbrrj9zA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433354; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=WzXAuTrB5B1rgm7KFqVq3AmO4KAL5plUNQSKVFqiSs4=; b=TLq/xQQrC9q5KdS8l0Rdtwp/QRwarHdiCGN9ok/LQysyrtiNrrhQNqMfNLbZjkYEUijlXGxJGdDlmSDQ5usR8Cr26/cOoRy31Aiz2+s/hDPZ39DMJkZ9rD5KvayLPtQSVQADVeoj45iSoEM8e2t6u9S7ieLHTBNV+vpS6tMb8jA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62361+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433354185376.8146236391983; Fri, 10 Jul 2020 19:09:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 0sgaYY1788612xSngFkhyeNV; Fri, 10 Jul 2020 19:09:13 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.2047.1594433352364265985 for ; Fri, 10 Jul 2020 19:09:12 -0700 IronPort-SDR: sWUxIeDCRRA94k7B8HRe6m+iB6EpqXmQC0jfRfHxBmIDQzMjH/xsUYMZFbMBTNp2r4AwY19xld EhNsyb50eg2g== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380559" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380559" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:12 -0700 IronPort-SDR: 0LmCqy24cVeZojno2pRtsYfIJ88a2spVEC2Xy9UcgtRR0mnj90FxpQxpX4TKGJB8EVOw7QIQT5 k+HVftLf8mRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602285" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:11 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 09/16] UnitTestFrameworkPkg: Change target mode DebugLib mapping Date: Fri, 10 Jul 2020 19:08:57 -0700 Message-Id: <20200711020904.24116-10-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: OiO99ds377J6K42rasBSb2jUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433353; bh=mmT4Ru67J6hIWH8b52W7G6ayeeYUpkqUZJJgE0+lI1w=; h=Cc:Date:From:Reply-To:Subject:To; b=TG7b+U97JL7vsbDwfSXtXtn9NIQ0v8ArQfuJUM2q3Rat24BLGb4sLbLtFBGlMMnQaQs 3cHjICN0074GA08hYsFx/8Nl0IDozCKkZXJZiewFJ/ReMxgNzcGB+Jw+7W97K4OTZsWx5 FH992NML+X10kQkkZq7ZObbGFZnAm/IUEJ8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2801 The default DebugLib for target mode was DebugLibNull. This library instance disables all ASSERT() and DEBUG() macros which removes the ability to write unit tests that check for ASSERT() behaviors. The DebugLib is changed to PeiDxeDebugLibReportStatusCode.inf that guarantees that DEBUG() and ASSERT() macros are active. The default ReportStatusCodeLib is set to BaseReportStatusCodeLibNull.inf so no messages are sent to any devices preserving the DebugLibNull behavior. A platform specific unit test can always override these mappings with a platform specific DebugLib. Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc b/Unit= TestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc index c29b056fca..0881278ab0 100644 --- a/UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc +++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc @@ -16,7 +16,9 @@ [LibraryClasses] =20 BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62361): https://edk2.groups.io/g/devel/message/62361 Mute This Topic: https://groups.io/mt/75432221/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62362+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62362+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433354; cv=none; d=zohomail.com; s=zohoarc; b=BbAsqJg/rIqg0ZgVVs5ewz1zML2WIyDxZn7iEOLEV4O701oanjkIFT+PAX3ISqVmr//h9riizbEmc/bmJydPmoQ/8SzTCL47U8eKOY5pDkm/R0th9zNv00nvM1vMCB6qDxlk465u8BPHngF/Fe5+1dYJzzZdaajDeo1ybXZ0CQs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433354; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=B4uKv9TgZjGYC41nfiJxe28ICqlvAzeWNhKcmBuRpjs=; b=QMPZ72g2ilHOL+Ds8fFmTrxis3c/Plp1s7P/VwfQk+X2GBgSs9+wzy7gq3szNxEiFmu97w+rP2rHVXJtgQ5/5Jdgx/UK0QL5YMQSC4rK56nsA6ij4gwY2CuDz0QiHfEB87m5oHBaAFbalER1s0lP1yPw6I9fbIprFV8IoPbsZKg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62362+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433354557849.3552037755544; Fri, 10 Jul 2020 19:09:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id urFmYY1788612x6m9Cmbrqcn; Fri, 10 Jul 2020 19:09:14 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2047.1594433352364265985 for ; Fri, 10 Jul 2020 19:09:12 -0700 IronPort-SDR: nLQJEyxaYh9UNo1FNMCru6DGTMk28StcQhLN00UUYfLlptM27ikDcWR/qZwL0khTyivG2+o73V MFm0RmBdxcmw== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380561" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380561" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:12 -0700 IronPort-SDR: NytwLSl/y4lTv7NReVXR/IsoJsi0ZSqyB9j+R304h5Dvv9z/+PzoK0/gv5PoF/DH6/S6qVg5xA 2o4r4fAxNYqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602295" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:12 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 10/16] UnitTestFrameworkPkg/UnitTestLib: Move print log into cleanup Date: Fri, 10 Jul 2020 19:08:58 -0700 Message-Id: <20200711020904.24116-11-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: ZvQwtminclBHJXdDcco3rMyJx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433354; bh=rbFJxJvtRbOgVMtjfz152FmuboRGJBfZlIKTsRfWdBg=; h=Cc:Date:From:Reply-To:Subject:To; b=xVPbx267TpzehIdbrYD0I/DkZAt2R2bN0fFu3/8bEOaupwBZ2QalF3OXmhNj+cyL8b8 i436jdvSxGhR9jv2aVyWp95iEanlFHg7+UuXTsAwJcMElwKKDnl34B1Vf0X+Ucu5hEey5 2Oszud51Ec7YgUMWE9i1yJhO5+O+cm4Ysm4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2805 If a unit test fails with an exception or an assert, then the CmockaUnitTestFunctionRunner() is terminated and the logic that follows the invocation of the unit test is skipped. This currently skips the logic that prints log messages. Move the print of log messages to the end of the function CmockaUnitTestTeardownFunctionRunner() that is guaranteed to be executed when a unit test completes normally or is terminated with an exception or an assert. Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- .../Library/UnitTestLib/RunTestsCmocka.c | 33 +++++++++---------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/UnitTestFrameworkPkg/Library/UnitTestLib/RunTestsCmocka.c b/Un= itTestFrameworkPkg/Library/UnitTestLib/RunTestsCmocka.c index fb81cc9658..96aa4d9b13 100644 --- a/UnitTestFrameworkPkg/Library/UnitTestLib/RunTestsCmocka.c +++ b/UnitTestFrameworkPkg/Library/UnitTestLib/RunTestsCmocka.c @@ -53,21 +53,9 @@ CmockaUnitTestFunctionRunner ( UnitTest->Result =3D UNIT_TEST_SKIPPED; } else { UnitTest->Result =3D UNIT_TEST_RUNNING; - Framework->CurrentTest =3D UnitTest; UnitTest->Result =3D UnitTest->RunTest (UnitTest->Context); Framework->CurrentTest =3D NULL; - - // Print out the log messages - This is a partial solution as it - // does not get the log into the XML. Need cmocka changes to support - // stdout and stderr in their xml format - // - if (UnitTest->Log !=3D NULL) { - print_message("UnitTest: %s - %s\n", UnitTest->Name, UnitTest->Descr= iption); - print_message("Log Output Start\n"); - print_message("%s", UnitTest->Log); - print_message("Log Output End\n"); - } } } =20 @@ -112,13 +100,24 @@ CmockaUnitTestTeardownFunctionRunner ( Suite =3D (UNIT_TEST_SUITE *)(UnitTest->ParentSuite); Framework =3D (UNIT_TEST_FRAMEWORK *)(Suite->ParentFramework); =20 - if (UnitTest->CleanUp =3D=3D NULL) { - return 0; + if (UnitTest->CleanUp !=3D NULL) { + Framework->CurrentTest =3D UnitTest; + UnitTest->CleanUp (UnitTest->Context); + Framework->CurrentTest =3D NULL; + } + + // + // Print out the log messages - This is a partial solution as it + // does not get the log into the XML. Need cmocka changes to support + // stdout and stderr in their xml format + // + if (UnitTest->Log !=3D NULL) { + print_message("UnitTest: %s - %s\n", UnitTest->Name, UnitTest->Descrip= tion); + print_message("Log Output Start\n"); + print_message("%s", UnitTest->Log); + print_message("Log Output End\n"); } =20 - Framework->CurrentTest =3D UnitTest; - UnitTest->CleanUp (UnitTest->Context); - Framework->CurrentTest =3D NULL; // // Return 0 for success. Non-zero for error. // --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62362): https://edk2.groups.io/g/devel/message/62362 Mute This Topic: https://groups.io/mt/75432222/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62363+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62363+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433354; cv=none; d=zohomail.com; s=zohoarc; b=AiWIdC5GQY9LfautybjbFu1hyKxoZdNwDE6n8QzVK3V6EnKQ9Tm2kaahfj3wWLIcbZAIVS4clviS2EL2sBXRZ1llP+LJKYTf0vf1PHXS84ZedggtI7GLszGNXghatvJ1m8DePi2y1kNr9mCNb/0xYuuUXip5R/14zy4qo6lgGac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433354; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KC6PSAeJonOG0Uiog7I5/PZ5ytURShbldsDsRIiE7jA=; b=BCMdsbHfaqgjveDpx38gHRlWGKoTawnuKyEEIgtULtMtXrjuSunnQQqON9jzp7LAylLala10y47avdzxb1DsodBYhWr7bRkMJkPRsEm5VID2/H3653D9+WMQfAD5U8qT7t1jQQDMiGVmBLhxuTO6kxnC0CRbDiCy7oPPlF9uP8c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62363+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433354953940.2364818092468; Fri, 10 Jul 2020 19:09:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id P8qxYY1788612xTzTgSFXzS8; Fri, 10 Jul 2020 19:09:14 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2047.1594433352364265985 for ; Fri, 10 Jul 2020 19:09:13 -0700 IronPort-SDR: LF+JlpHzTvG3oxGxJ/T47JdFm6s+bJLhRdhSAVpn2G22ri/QsGjRGgstChhzh2ZOQrH7VslInc Tyt3A7bu8lvA== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380565" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380565" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:13 -0700 IronPort-SDR: 1e8bYpfE5kv32wARA0LYQRRl0MGHl7zszMkWFhJatzYPcdXYUgPbKIfD1aglc+9izaBXKNq9v9 iYTbziIv/TRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602302" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:12 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 11/16] UnitTestFrameworkPkg/UnitTestLib: Fix target mode log messages Date: Fri, 10 Jul 2020 19:08:59 -0700 Message-Id: <20200711020904.24116-12-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: ujUQ2Ve7pQ2dL8FWmYghOsJ2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433354; bh=vR/ahv+ZTMkMbtqhFvI/Z6SIPSmulB30IGv1iyloLdk=; h=Cc:Date:From:Reply-To:Subject:To; b=bD7HX9h/aEhVU2M7Da3KDyimgFcn6eijWtDOo38uUbvHtDMRzf/NiM9pUQNJFjr0dvJ tUZetGQL/ZZSQrcfiBZ5IFoaT6ZnV4zpUezrEy/L8LSeqNDwX+ZO7HQT7aRF8IfR0leZa SWbyqZNRmgKPYOlDcaZ9/5wsrnnxgx6AsHE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2806 Update the log messages generated in target mode to use FileName instead of FunctionName. FunctionName is an empty string so the log messages generated do not provide enough information to know the source of a unit test failure. Using FileName combined with LineNumber provides the right information to identify the location of a unit test failure. Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- .../Library/UnitTestLib/Assert.c | 64 +++++++++---------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/UnitTestFrameworkPkg/Library/UnitTestLib/Assert.c b/UnitTestFr= ameworkPkg/Library/UnitTestLib/Assert.c index c327ba88f1..8a131fab2b 100644 --- a/UnitTestFrameworkPkg/Library/UnitTestLib/Assert.c +++ b/UnitTestFrameworkPkg/Library/UnitTestLib/Assert.c @@ -105,14 +105,14 @@ UnitTestAssertTrue ( if (!Expression) { UnitTestLogFailure ( FAILURETYPE_ASSERTTRUE, - "%a::%d Expression (%a) is not TRUE!\n", - FunctionName, + "%a:%d: Expression (%a) is not TRUE!\n", + FileName, LineNumber, Description ); UT_LOG_ERROR ( - "[ASSERT FAIL] %a::%d Expression (%a) is not TRUE!\n", - FunctionName, + "[ASSERT FAIL] %a:%d: Expression (%a) is not TRUE!\n", + FileName, LineNumber, Description ); @@ -151,14 +151,14 @@ UnitTestAssertFalse ( if (Expression) { UnitTestLogFailure ( FAILURETYPE_ASSERTFALSE, - "%a::%d Expression(%a) is not FALSE!\n", - FunctionName, + "%a:%d: Expression(%a) is not FALSE!\n", + FileName, LineNumber, Description ); UT_LOG_ERROR ( - "[ASSERT FAIL] %a::%d Expression (%a) is not FALSE!\n", - FunctionName, + "[ASSERT FAIL] %a:%d: Expression (%a) is not FALSE!\n", + FileName, LineNumber, Description ); @@ -197,15 +197,15 @@ UnitTestAssertNotEfiError ( if (EFI_ERROR (Status)) { UnitTestLogFailure ( FAILURETYPE_ASSERTNOTEFIERROR, - "%a::%d Status '%a' is EFI_ERROR (%r)!\n", - FunctionName, + "%a:%d: Status '%a' is EFI_ERROR (%r)!\n", + FileName, LineNumber, Description, Status ); UT_LOG_ERROR ( - "[ASSERT FAIL] %a::%d Status '%a' is EFI_ERROR (%r)!\n", - FunctionName, + "[ASSERT FAIL] %a:%d: Status '%a' is EFI_ERROR (%r)!\n", + FileName, LineNumber, Description, Status @@ -250,8 +250,8 @@ UnitTestAssertEqual ( if (ValueA !=3D ValueB) { UnitTestLogFailure ( FAILURETYPE_ASSERTEQUAL, - "%a::%d Value %a !=3D %a (%d !=3D %d)!\n", - FunctionName, + "%a:%d: Value %a !=3D %a (%d !=3D %d)!\n", + FileName, LineNumber, DescriptionA, DescriptionB, @@ -259,8 +259,8 @@ UnitTestAssertEqual ( ValueB ); UT_LOG_ERROR ( - "[ASSERT FAIL] %a::%d Value %a !=3D %a (%d !=3D %d)!\n", - FunctionName, + "[ASSERT FAIL] %a:%d: Value %a !=3D %a (%d !=3D %d)!\n", + FileName, LineNumber, DescriptionA, DescriptionB, @@ -312,16 +312,16 @@ UnitTestAssertMemEqual ( if (CompareMem(BufferA, BufferB, Length) !=3D 0) { UnitTestLogFailure ( FAILURETYPE_ASSERTEQUAL, - "%a::%d Memory at %a !=3D %a for length %d bytes!\n", - FunctionName, + "%a:%d: Memory at %a !=3D %a for length %d bytes!\n", + FileName, LineNumber, DescriptionA, DescriptionB, Length ); UT_LOG_ERROR ( - "[ASSERT FAIL] %a::%d Value %a !=3D %a for length %d bytes!\n", - FunctionName, + "[ASSERT FAIL] %a:%d: Value %a !=3D %a for length %d bytes!\n", + FileName, LineNumber, DescriptionA, DescriptionB, @@ -368,8 +368,8 @@ UnitTestAssertNotEqual ( if (ValueA =3D=3D ValueB) { UnitTestLogFailure ( FAILURETYPE_ASSERTNOTEQUAL, - "%a::%d Value %a =3D=3D %a (%d =3D=3D %d)!\n", - FunctionName, + "%a:%d: Value %a =3D=3D %a (%d =3D=3D %d)!\n", + FileName, LineNumber, DescriptionA, DescriptionB, @@ -377,8 +377,8 @@ UnitTestAssertNotEqual ( ValueB ); UT_LOG_ERROR ( - "[ASSERT FAIL] %a::%d Value %a =3D=3D %a (%d =3D=3D %d)!\n", - FunctionName, + "[ASSERT FAIL] %a:%d: Value %a =3D=3D %a (%d =3D=3D %d)!\n", + FileName, LineNumber, DescriptionA, DescriptionB, @@ -423,16 +423,16 @@ UnitTestAssertStatusEqual ( if (Status !=3D Expected) { UnitTestLogFailure ( FAILURETYPE_ASSERTSTATUSEQUAL, - "%a::%d Status '%a' is %r, should be %r!\n", - FunctionName, + "%a:%d: Status '%a' is %r, should be %r!\n", + FileName, LineNumber, Description, Status, Expected ); UT_LOG_ERROR ( - "[ASSERT FAIL] %a::%d Status '%a' is %r, should be %r!\n", - FunctionName, + "[ASSERT FAIL] %a:%d: Status '%a' is %r, should be %r!\n", + FileName, LineNumber, Description, Status, @@ -475,14 +475,14 @@ UnitTestAssertNotNull ( if (Pointer =3D=3D NULL) { UnitTestLogFailure ( FAILURETYPE_ASSERTNOTNULL, - "%a::%d Pointer (%a) is NULL!\n", - FunctionName, + "%a:%d: Pointer (%a) is NULL!\n", + FileName, LineNumber, PointerName ); UT_LOG_ERROR ( - "[ASSERT FAIL] %a::%d Pointer (%a) is NULL!\n", - FunctionName, + "[ASSERT FAIL] %a:%d: Pointer (%a) is NULL!\n", + FileName, LineNumber, PointerName ); --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62363): https://edk2.groups.io/g/devel/message/62363 Mute This Topic: https://groups.io/mt/75432223/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62364+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62364+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433355; cv=none; d=zohomail.com; s=zohoarc; b=jyZ+IVfpBWdDdQs8ATbyx9nes6XnEEXHV2CWRixaLamyWcXcFJMKhOA60T0gQj/jXzweP0VtfnWcpBpO6wYJNdhEJ/DyUz01LSno7ddbdilH3pw5vy1xbhg7xrVp0skctrWuvPfCV1P4YCMPZxoBnDEwNRBPsszSrlqF+b2YssA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433355; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=XA2QRkDpEh9A50zySqzxqRigrMcqteuh2pwY4i4WEFk=; b=bUNH1OIOowqhABBQ2aBnrtTGjB4x2z5o8d2hgbaDfnZr+BvM5jhpn/Xv7EaggfY1cSKoesRGuaT/zrg9qZXWJAvKbDGEAroWZ0DSa8vniPZ44hHmzaucniloWmQkauSIKSQlbgQGlrExt3eMeEtFNWz8BLN3KBIFqJNZnW5aUW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62364+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433355335988.5538266955565; Fri, 10 Jul 2020 19:09:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id CkCkYY1788612xYnOVWxaG4X; Fri, 10 Jul 2020 19:09:15 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2047.1594433352364265985 for ; Fri, 10 Jul 2020 19:09:13 -0700 IronPort-SDR: TsjUca+iR6PY0E0VHhgk1MWFyIGn6bAMeLyAjb1mV7t1yH20IFN1U1/O0qQ33/6mYGKw2i6hpe 8hnomGhk1UxQ== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380566" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380566" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:13 -0700 IronPort-SDR: GE5xEtUH/B6obrqEUOFrWdcPEUtRW239EEgdsbYc7ERjehoTwYL4fJlVytC5xlIwOpfLhHDOhF 87mASsZeqOOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602310" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:13 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 12/16] UnitTestFrameworkPkg/UnitTestLib: Add checks for ASSERT() Date: Fri, 10 Jul 2020 19:09:00 -0700 Message-Id: <20200711020904.24116-13-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: yNyM6tTqpJFc9NRgPHzsDYZlx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433355; bh=v+TIqbxC5i0adX813SPMKhoN+J9HyjGrDaWTLfzvJFM=; h=Cc:Date:From:Reply-To:Subject:To; b=f842HFnIZQnXeh2ppJOrbOqNkx8byMEeGqdsxZZl3YZF7Hf4hhtpyTGxsHDyfDnUIRb JhdG+d/zYFx54mSBhpVLcBrcf90gzNLa8f025dKMUlzIaXCvmapPvOyAr01ocfrPngOZ/ OzOaqD7mK5/R/KxGKN6C/NYrEXU2fH3hhDY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2801 Add UnitTestDebugAssertLib that provides the UnitTestDebugAssert() service and the gUnitTestExpectAssertFailureJumpBuffer global variable. This NULL library is linked against all host and target unit test builds. This guarantees that the UnitTestDebugAssert() service is available to link against all libraries and modules that use the DebugLib class. EDKII_UNIT_TEST_FRAMEWORK_ENABLED must always be defined when building unit tests so the behavior of the DebugLib ASSERT() macros can be adjusted to allow the unit test framework to catch an ASSERT() if it is triggered by a function under test. Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- .../UnitTestDebugAssertLib.c | 49 +++++ .../UnitTestDebugAssertLib.inf | 31 +++ .../UnitTestDebugAssertLib.uni | 11 + .../Library/UnitTestLib/Assert.c | 203 ++++++++++++------ .../Library/UnitTestLib/AssertCmocka.c | 68 ++++++ .../Library/UnitTestLib/RunTests.c | 23 +- .../UnitTestResultReportLib.c | 3 +- .../PrivateInclude/UnitTestFrameworkTypes.h | 1 + .../Test/UnitTestFrameworkPkgHostTest.dsc | 2 +- UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc | 1 + .../UnitTestFrameworkPkgTarget.dsc.inc | 6 +- 11 files changed, 328 insertions(+), 70 deletions(-) create mode 100644 UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/Uni= tTestDebugAssertLib.c create mode 100644 UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/Uni= tTestDebugAssertLib.inf create mode 100644 UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/Uni= tTestDebugAssertLib.uni diff --git a/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTestDe= bugAssertLib.c b/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTe= stDebugAssertLib.c new file mode 100644 index 0000000000..0a4001e182 --- /dev/null +++ b/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTestDebugAsse= rtLib.c @@ -0,0 +1,49 @@ +/** @file + Unit Test Debug Assert Library + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/// +/// Point to jump buffer used with SetJump()/LongJump() to test if a funct= ion +/// under test generates an expected ASSERT() condition. +/// +BASE_LIBRARY_JUMP_BUFFER *gUnitTestExpectAssertFailureJumpBuffer =3D NULL; + +/** + Unit test library replacement for DebugAssert() in DebugLib. + + If FileName is NULL, then a string of "(NULL) Filename" is pr= inted. + If Description is NULL, then a string of "(NULL) Descripti= on" is printed. + + @param FileName The pointer to the name of the source file that gen= erated the assert condition. + @param LineNumber The line number in the source file that generated t= he assert condition + @param Description The pointer to the description of the assert condit= ion. + +**/ +VOID +EFIAPI +UnitTestDebugAssert ( + IN CONST CHAR8 *FileName, + IN UINTN LineNumber, + IN CONST CHAR8 *Description + ) +{ + CHAR8 Message[256]; + + if (gUnitTestExpectAssertFailureJumpBuffer !=3D NULL) { + UT_LOG_INFO ("Detected expected ASSERT: %a(%d): %a\n", FileName, LineN= umber, Description); + LongJump (gUnitTestExpectAssertFailureJumpBuffer, 1); + } else { + AsciiStrCpyS (Message, sizeof(Message), "Detected unexpected ASSERT("); + AsciiStrCatS (Message, sizeof(Message), Description); + AsciiStrCatS (Message, sizeof(Message), ")"); + UnitTestAssertTrue (FALSE, "", LineNumber, FileName, Message); + } +} diff --git a/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTestDe= bugAssertLib.inf b/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/Unit= TestDebugAssertLib.inf new file mode 100644 index 0000000000..e6ccab0dd9 --- /dev/null +++ b/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTestDebugAsse= rtLib.inf @@ -0,0 +1,31 @@ +## @file +# Unit Test Debug Assert Library +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UnitTestDebugAssertLib + MODULE_UNI_FILE =3D UnitTestDebugAssertLib.uni + FILE_GUID =3D 9D53AD0D-5416-451F-A5BF-E5420051A99B + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + +# +# VALID_ARCHITECTURES =3D ARM AARCH64 +# + +[Sources] + UnitTestDebugAssertLib.c + +[Packages] + MdePkg/MdePkg.dec + UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec + +[LibraryClasses] + BaseLib + UnitTestLib diff --git a/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTestDe= bugAssertLib.uni b/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/Unit= TestDebugAssertLib.uni new file mode 100644 index 0000000000..9b794aa205 --- /dev/null +++ b/UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTestDebugAsse= rtLib.uni @@ -0,0 +1,11 @@ +// /** @file +// Unit Test Debug Assert Library +// +// Copyright (c) 2020, Intel Corporation. All rights reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "Unit Test Debug A= ssert Library" + +#string STR_MODULE_DESCRIPTION #language en-US "Unit Test Debug A= ssert Library" diff --git a/UnitTestFrameworkPkg/Library/UnitTestLib/Assert.c b/UnitTestFr= ameworkPkg/Library/UnitTestLib/Assert.c index 8a131fab2b..3669d63701 100644 --- a/UnitTestFrameworkPkg/Library/UnitTestLib/Assert.c +++ b/UnitTestFrameworkPkg/Library/UnitTestLib/Assert.c @@ -13,6 +13,8 @@ #include #include =20 +extern BASE_LIBRARY_JUMP_BUFFER gUnitTestJumpBuffer; + STATIC EFI_STATUS AddUnitTestFailure ( @@ -71,7 +73,7 @@ UnitTestLogFailure ( FailureType ); =20 - return; + LongJump (&gUnitTestJumpBuffer, 1); } =20 /** @@ -103,6 +105,12 @@ UnitTestAssertTrue ( ) { if (!Expression) { + UT_LOG_ERROR ( + "[ASSERT FAIL] %a:%d: Expression (%a) is not TRUE!\n", + FileName, + LineNumber, + Description + ); UnitTestLogFailure ( FAILURETYPE_ASSERTTRUE, "%a:%d: Expression (%a) is not TRUE!\n", @@ -110,12 +118,6 @@ UnitTestAssertTrue ( LineNumber, Description ); - UT_LOG_ERROR ( - "[ASSERT FAIL] %a:%d: Expression (%a) is not TRUE!\n", - FileName, - LineNumber, - Description - ); } return Expression; } @@ -149,6 +151,12 @@ UnitTestAssertFalse ( ) { if (Expression) { + UT_LOG_ERROR ( + "[ASSERT FAIL] %a:%d: Expression (%a) is not FALSE!\n", + FileName, + LineNumber, + Description + ); UnitTestLogFailure ( FAILURETYPE_ASSERTFALSE, "%a:%d: Expression(%a) is not FALSE!\n", @@ -156,12 +164,6 @@ UnitTestAssertFalse ( LineNumber, Description ); - UT_LOG_ERROR ( - "[ASSERT FAIL] %a:%d: Expression (%a) is not FALSE!\n", - FileName, - LineNumber, - Description - ); } return !Expression; } @@ -195,6 +197,13 @@ UnitTestAssertNotEfiError ( ) { if (EFI_ERROR (Status)) { + UT_LOG_ERROR ( + "[ASSERT FAIL] %a:%d: Status '%a' is EFI_ERROR (%r)!\n", + FileName, + LineNumber, + Description, + Status + ); UnitTestLogFailure ( FAILURETYPE_ASSERTNOTEFIERROR, "%a:%d: Status '%a' is EFI_ERROR (%r)!\n", @@ -203,13 +212,6 @@ UnitTestAssertNotEfiError ( Description, Status ); - UT_LOG_ERROR ( - "[ASSERT FAIL] %a:%d: Status '%a' is EFI_ERROR (%r)!\n", - FileName, - LineNumber, - Description, - Status - ); } return !EFI_ERROR( Status ); } @@ -248,16 +250,6 @@ UnitTestAssertEqual ( ) { if (ValueA !=3D ValueB) { - UnitTestLogFailure ( - FAILURETYPE_ASSERTEQUAL, - "%a:%d: Value %a !=3D %a (%d !=3D %d)!\n", - FileName, - LineNumber, - DescriptionA, - DescriptionB, - ValueA, - ValueB - ); UT_LOG_ERROR ( "[ASSERT FAIL] %a:%d: Value %a !=3D %a (%d !=3D %d)!\n", FileName, @@ -267,6 +259,16 @@ UnitTestAssertEqual ( ValueA, ValueB ); + UnitTestLogFailure ( + FAILURETYPE_ASSERTEQUAL, + "%a:%d: Value %a !=3D %a (%d !=3D %d)!\n", + FileName, + LineNumber, + DescriptionA, + DescriptionB, + ValueA, + ValueB + ); } return (ValueA =3D=3D ValueB); } @@ -310,15 +312,6 @@ UnitTestAssertMemEqual ( ) { if (CompareMem(BufferA, BufferB, Length) !=3D 0) { - UnitTestLogFailure ( - FAILURETYPE_ASSERTEQUAL, - "%a:%d: Memory at %a !=3D %a for length %d bytes!\n", - FileName, - LineNumber, - DescriptionA, - DescriptionB, - Length - ); UT_LOG_ERROR ( "[ASSERT FAIL] %a:%d: Value %a !=3D %a for length %d bytes!\n", FileName, @@ -327,6 +320,15 @@ UnitTestAssertMemEqual ( DescriptionB, Length ); + UnitTestLogFailure ( + FAILURETYPE_ASSERTEQUAL, + "%a:%d: Memory at %a !=3D %a for length %d bytes!\n", + FileName, + LineNumber, + DescriptionA, + DescriptionB, + Length + ); return FALSE; } return TRUE; @@ -366,6 +368,15 @@ UnitTestAssertNotEqual ( ) { if (ValueA =3D=3D ValueB) { + UT_LOG_ERROR ( + "[ASSERT FAIL] %a:%d: Value %a =3D=3D %a (%d =3D=3D %d)!\n", + FileName, + LineNumber, + DescriptionA, + DescriptionB, + ValueA, + ValueB + ); UnitTestLogFailure ( FAILURETYPE_ASSERTNOTEQUAL, "%a:%d: Value %a =3D=3D %a (%d =3D=3D %d)!\n", @@ -376,15 +387,6 @@ UnitTestAssertNotEqual ( ValueA, ValueB ); - UT_LOG_ERROR ( - "[ASSERT FAIL] %a:%d: Value %a =3D=3D %a (%d =3D=3D %d)!\n", - FileName, - LineNumber, - DescriptionA, - DescriptionB, - ValueA, - ValueB - ); } return (ValueA !=3D ValueB); } @@ -421,6 +423,14 @@ UnitTestAssertStatusEqual ( ) { if (Status !=3D Expected) { + UT_LOG_ERROR ( + "[ASSERT FAIL] %a:%d: Status '%a' is %r, should be %r!\n", + FileName, + LineNumber, + Description, + Status, + Expected + ); UnitTestLogFailure ( FAILURETYPE_ASSERTSTATUSEQUAL, "%a:%d: Status '%a' is %r, should be %r!\n", @@ -430,14 +440,6 @@ UnitTestAssertStatusEqual ( Status, Expected ); - UT_LOG_ERROR ( - "[ASSERT FAIL] %a:%d: Status '%a' is %r, should be %r!\n", - FileName, - LineNumber, - Description, - Status, - Expected - ); } return (Status =3D=3D Expected); } @@ -473,6 +475,12 @@ UnitTestAssertNotNull ( ) { if (Pointer =3D=3D NULL) { + UT_LOG_ERROR ( + "[ASSERT FAIL] %a:%d: Pointer (%a) is NULL!\n", + FileName, + LineNumber, + PointerName + ); UnitTestLogFailure ( FAILURETYPE_ASSERTNOTNULL, "%a:%d: Pointer (%a) is NULL!\n", @@ -480,12 +488,83 @@ UnitTestAssertNotNull ( LineNumber, PointerName ); - UT_LOG_ERROR ( - "[ASSERT FAIL] %a:%d: Pointer (%a) is NULL!\n", - FileName, - LineNumber, - PointerName - ); } return (Pointer !=3D NULL); } + +/** + If UnitTestStatus is UNIT_TEST_PASSED, then log an info message and retu= rn + TRUE because an ASSERT() was expected when FunctionCall was executed and= an + ASSERT() was triggered. If UnitTestStatus is UNIT_TEST_SKIPPED, then log= a + warning message and return TRUE because ASSERT() macros are disabled. If + UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED, then log an error message= and + return FALSE because an ASSERT() was expected when FunctionCall was exec= uted, + but no ASSERT() conditions were triggered. The log messages contain + FunctionName, LineNumber, and FileName strings to provide the location o= f the + UT_EXPECT_ASSERT_FAILURE() macro. + + @param[in] UnitTestStatus The status from UT_EXPECT_ASSERT_FAILURE() t= hat + is either pass, skipped, or failed. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] LineNumber The source file line number of the the funct= ion + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] FunctionCall Null-terminated ASCII string of the function= call + executed by the UT_EXPECT_ASSERT_FAILURE() m= acro. + @param[out] ResultStatus Used to return the UnitTestStatus value to t= he + caller of UT_EXPECT_ASSERT_FAILURE(). This = is + optional parameter that may be NULL. + + @retval TRUE UnitTestStatus is UNIT_TEST_PASSED. + @retval TRUE UnitTestStatus is UNIT_TEST_SKIPPED. + @retval FALSE UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED. +**/ +BOOLEAN +EFIAPI +UnitTestExpectAssertFailure ( + IN UNIT_TEST_STATUS UnitTestStatus, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *FunctionCall, + OUT UNIT_TEST_STATUS *ResultStatus OPTIONAL + ) +{ + if (ResultStatus !=3D NULL) { + *ResultStatus =3D UnitTestStatus; + } + if (UnitTestStatus =3D=3D UNIT_TEST_PASSED) { + UT_LOG_INFO ( + "[ASSERT PASS] %a:%d: UT_EXPECT_ASSERT_FAILURE(%a) detected expected= assert\n", + FileName, + LineNumber, + FunctionCall + ); + } + if (UnitTestStatus =3D=3D UNIT_TEST_SKIPPED) { + UT_LOG_WARNING ( + "[ASSERT WARN] %a:%d: UT_EXPECT_ASSERT_FAILURE(%a) disabled\n", + FileName, + LineNumber, + FunctionCall + ); + } + if (UnitTestStatus =3D=3D UNIT_TEST_ERROR_TEST_FAILED) { + UT_LOG_ERROR ( + "[ASSERT FAIL] %a:%d: Function call (%a) did not ASSERT()!\n", + FileName, + LineNumber, + FunctionCall + ); + UnitTestLogFailure ( + FAILURETYPE_EXPECTASSERT, + "%a:%d: Function call (%a) did not ASSERT()!\n", + FileName, + LineNumber, + FunctionCall + ); + } + return (UnitTestStatus !=3D UNIT_TEST_ERROR_TEST_FAILED); +} diff --git a/UnitTestFrameworkPkg/Library/UnitTestLib/AssertCmocka.c b/Unit= TestFrameworkPkg/Library/UnitTestLib/AssertCmocka.c index e48d614976..687c6243ab 100644 --- a/UnitTestFrameworkPkg/Library/UnitTestLib/AssertCmocka.c +++ b/UnitTestFrameworkPkg/Library/UnitTestLib/AssertCmocka.c @@ -333,3 +333,71 @@ UnitTestAssertNotNull ( =20 return (Pointer !=3D NULL); } + +/** + If UnitTestStatus is UNIT_TEST_PASSED, then log an info message and retu= rn + TRUE because an ASSERT() was expected when FunctionCall was executed and= an + ASSERT() was triggered. If UnitTestStatus is UNIT_TEST_SKIPPED, then log= a + warning message and return TRUE because ASSERT() macros are disabled. If + UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED, then log an error message= and + return FALSE because an ASSERT() was expected when FunctionCall was exec= uted, + but no ASSERT() conditions were triggered. The log messages contain + FunctionName, LineNumber, and FileName strings to provide the location o= f the + UT_EXPECT_ASSERT_FAILURE() macro. + + @param[in] UnitTestStatus The status from UT_EXPECT_ASSERT_FAILURE() t= hat + is either pass, skipped, or failed. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] LineNumber The source file line number of the the funct= ion + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] FunctionCall Null-terminated ASCII string of the function= call + executed by the UT_EXPECT_ASSERT_FAILURE() m= acro. + @param[out] ResultStatus Used to return the UnitTestStatus value to t= he + caller of UT_EXPECT_ASSERT_FAILURE(). This = is + optional parameter that may be NULL. + + @retval TRUE UnitTestStatus is UNIT_TEST_PASSED. + @retval TRUE UnitTestStatus is UNIT_TEST_SKIPPED. + @retval FALSE UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED. +**/ +BOOLEAN +EFIAPI +UnitTestExpectAssertFailure ( + IN UNIT_TEST_STATUS UnitTestStatus, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *FunctionCall, + OUT UNIT_TEST_STATUS *ResultStatus OPTIONAL + ) +{ + CHAR8 TempStr[MAX_STRING_SIZE]; + + if (ResultStatus !=3D NULL) { + *ResultStatus =3D UnitTestStatus; + } + if (UnitTestStatus =3D=3D UNIT_TEST_PASSED) { + UT_LOG_INFO ( + "[ASSERT PASS] %a:%d: UT_EXPECT_ASSERT_FAILURE(%a) detected expected= assert\n", + FileName, + LineNumber, + FunctionCall + ); + } + if (UnitTestStatus =3D=3D UNIT_TEST_SKIPPED) { + UT_LOG_WARNING ( + "[ASSERT WARN] %a:%d: UT_EXPECT_ASSERT_FAILURE(%a) disabled\n", + FileName, + LineNumber, + FunctionCall + ); + } + if (UnitTestStatus =3D=3D UNIT_TEST_ERROR_TEST_FAILED) { + snprintf (TempStr, sizeof(TempStr), "UT_EXPECT_ASSERT_FAILURE(%s) did = not trigger ASSERT()", FunctionCall); + _assert_true (FALSE, TempStr, FileName, (INT32)LineNumber); + } + return (UnitTestStatus !=3D UNIT_TEST_ERROR_TEST_FAILED); +} diff --git a/UnitTestFrameworkPkg/Library/UnitTestLib/RunTests.c b/UnitTest= FrameworkPkg/Library/UnitTestLib/RunTests.c index 793335fd0f..2dc1d159d5 100644 --- a/UnitTestFrameworkPkg/Library/UnitTestLib/RunTests.c +++ b/UnitTestFrameworkPkg/Library/UnitTestLib/RunTests.c @@ -14,6 +14,8 @@ =20 STATIC UNIT_TEST_FRAMEWORK_HANDLE mFrameworkHandle =3D NULL; =20 +BASE_LIBRARY_JUMP_BUFFER gUnitTestJumpBuffer; + UNIT_TEST_FRAMEWORK_HANDLE GetActiveFrameworkHandle ( VOID @@ -75,7 +77,14 @@ RunTestSuite ( // Next, if we're still running, make sure that our test prerequisites= are in place. if (Test->Result =3D=3D UNIT_TEST_PENDING && Test->Prerequisite !=3D N= ULL) { DEBUG ((DEBUG_VERBOSE, "PREREQ\n")); - if (Test->Prerequisite (Test->Context) !=3D UNIT_TEST_PASSED) { + if (SetJump (&gUnitTestJumpBuffer) =3D=3D 0) { + if (Test->Prerequisite (Test->Context) !=3D UNIT_TEST_PASSED) { + DEBUG ((DEBUG_ERROR, "Prerequisite Not Met\n")); + Test->Result =3D UNIT_TEST_ERROR_PREREQUISITE_NOT_MET; + ParentFramework->CurrentTest =3D NULL; + continue; + } + } else { DEBUG ((DEBUG_ERROR, "Prerequisite Not Met\n")); Test->Result =3D UNIT_TEST_ERROR_PREREQUISITE_NOT_MET; ParentFramework->CurrentTest =3D NULL; @@ -88,14 +97,20 @@ RunTestSuite ( // We set the status to UNIT_TEST_RUNNING in case the test needs to re= boot // or quit. The UNIT_TEST_RUNNING state will allow the test to resume // but will prevent the Prerequisite from being dispatched a second ti= me. - Test->Result =3D UNIT_TEST_RUNNING; - Test->Result =3D Test->RunTest (Test->Context); + if (SetJump (&gUnitTestJumpBuffer) =3D=3D 0) { + Test->Result =3D UNIT_TEST_RUNNING; + Test->Result =3D Test->RunTest (Test->Context); + } else { + Test->Result =3D UNIT_TEST_ERROR_TEST_FAILED; + } =20 // // Finally, clean everything up, if need be. if (Test->CleanUp !=3D NULL) { DEBUG ((DEBUG_VERBOSE, "CLEANUP\n")); - Test->CleanUp (Test->Context); + if (SetJump (&gUnitTestJumpBuffer) =3D=3D 0) { + Test->CleanUp (Test->Context); + } } =20 // diff --git a/UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestR= esultReportLib.c b/UnitTestFrameworkPkg/Library/UnitTestResultReportLib/Uni= tTestResultReportLib.c index eba68e330c..66c9db457d 100644 --- a/UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultRe= portLib.c +++ b/UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultRe= portLib.c @@ -49,7 +49,8 @@ struct _UNIT_TEST_FAILURE_TYPE_STRING mFailureTypeStrings= [] =3D { { FAILURETYPE_ASSERTNOTEQUAL, "ASSERT_NOTEQUAL FAILURE"}, { FAILURETYPE_ASSERTNOTEFIERROR, "ASSERT_NOTEFIERROR FAILURE"}, { FAILURETYPE_ASSERTSTATUSEQUAL, "ASSERT_STATUSEQUAL FAILURE"}, - { FAILURETYPE_ASSERTNOTNULL , "ASSERT_NOTNULL FAILURE"}, + { FAILURETYPE_ASSERTNOTNULL, "ASSERT_NOTNULL FAILURE"}, + { FAILURETYPE_EXPECTASSERT, "EXPECT_ASSERT FAILURE"}, { 0, "*UNKNOWN* Failure"} }; =20 diff --git a/UnitTestFrameworkPkg/PrivateInclude/UnitTestFrameworkTypes.h b= /UnitTestFrameworkPkg/PrivateInclude/UnitTestFrameworkTypes.h index e58b30093e..b0e2f61bbf 100644 --- a/UnitTestFrameworkPkg/PrivateInclude/UnitTestFrameworkTypes.h +++ b/UnitTestFrameworkPkg/PrivateInclude/UnitTestFrameworkTypes.h @@ -44,6 +44,7 @@ typedef UINT32 FAILURE_TYPE; #define FAILURETYPE_ASSERTNOTEFIERROR (6) #define FAILURETYPE_ASSERTSTATUSEQUAL (7) #define FAILURETYPE_ASSERTNOTNULL (8) +#define FAILURETYPE_EXPECTASSERT (9) =20 /// /// Unit Test context structure tracked by the unit test framework. diff --git a/UnitTestFrameworkPkg/Test/UnitTestFrameworkPkgHostTest.dsc b/U= nitTestFrameworkPkg/Test/UnitTestFrameworkPkgHostTest.dsc index 701e7299d7..70affddead 100644 --- a/UnitTestFrameworkPkg/Test/UnitTestFrameworkPkgHostTest.dsc +++ b/UnitTestFrameworkPkg/Test/UnitTestFrameworkPkgHostTest.dsc @@ -25,7 +25,7 @@ [Components] UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTestH= ost.inf =20 # - # Build Libraries + # Build HOST_APPLICATION Libraries # UnitTestFrameworkPkg/Library/CmockaLib/CmockaLib.inf UnitTestFrameworkPkg/Library/Posix/DebugLibPosix/DebugLibPosix.inf diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc b/UnitTestFramew= orkPkg/UnitTestFrameworkPkg.dsc index 2d84691bf1..0dfd98f2a8 100644 --- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc +++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc @@ -28,6 +28,7 @@ [Components] UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultRepor= tLibConOut.inf UnitTestFrameworkPkg/Library/UnitTestBootLibUsbClass/UnitTestBootLibUsbC= lass.inf UnitTestFrameworkPkg/Library/UnitTestPersistenceLibSimpleFileSystem/Unit= TestPersistenceLibSimpleFileSystem.inf + UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTestDebugAssertL= ib.inf =20 UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTestD= xe.inf UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTestP= ei.inf diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc b/Unit= TestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc index 0881278ab0..8adf690098 100644 --- a/UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc +++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc @@ -29,6 +29,7 @@ [LibraryClasses] UnitTestLib|UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLib.inf UnitTestPersistenceLib|UnitTestFrameworkPkg/Library/UnitTestPersistenceL= ibNull/UnitTestPersistenceLibNull.inf UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultRepor= tLib/UnitTestResultReportLibDebugLib.inf + NULL|UnitTestFrameworkPkg/Library/UnitTestDebugAssertLib/UnitTestDebugAs= sertLib.inf =20 [LibraryClasses.ARM, LibraryClasses.AARCH64] # @@ -56,5 +57,6 @@ [PcdsFixedAtBuild] gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 =20 [BuildOptions] - MSFT:*_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES - GCC:*_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES + MSFT:*_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES -D EDKII_U= NIT_TEST_FRAMEWORK_ENABLED + GCC:*_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES -D EDKII_U= NIT_TEST_FRAMEWORK_ENABLED + XCODE:*_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES -D EDKII_U= NIT_TEST_FRAMEWORK_ENABLED --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62364): https://edk2.groups.io/g/devel/message/62364 Mute This Topic: https://groups.io/mt/75432224/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62365+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62365+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433355; cv=none; d=zohomail.com; s=zohoarc; b=LxuHYoRRRsyp0I7rrDAmcxqGGZD3Noh+ue/vhAA2OJCauCwg1zg/NUgqlQUqDQwYlO1q9SvBmhnI3pr9HoTCswIEpJTcEaWga9fBo307Pl5kx3uhO50uAm8oIuj7RksXsiwc5iApnjtEg2QJPdSluLP90ZUBvtkm9T/vfu48Zpw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433355; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rZu4Fyw3FfH/WWm4t48LAru6uFuQ8LAG6WfiKVFSmZ8=; b=Oss3g3xJvhQ7v9BDsDCPCV4vnxHyDwmIGWUrmMhVuYDO8tr+yFn0iP62CaPhXS4JPCVXTqI07J6e3gVdtuxb7BQLZK/mtShccPVrVk0AntckTGg3LalRS41ZpgZAOTyXzxK/PA0FnsueqmIDYWpzFeSXc+MDbXra/Xs2LC90+V8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62365+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433355955312.710489105056; Fri, 10 Jul 2020 19:09:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pO0BYY1788612xOlsG3Ppt4J; Fri, 10 Jul 2020 19:09:15 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2047.1594433352364265985 for ; Fri, 10 Jul 2020 19:09:14 -0700 IronPort-SDR: g0exrOW+k1qdWWl1ROXdBLhA5UPnvuDNcaIXisdQ9nPitnNrsxSa4qZixea1slKMbHecUvnhIA cAgHUIfvGspQ== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380569" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380569" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:13 -0700 IronPort-SDR: zdpGRln5YzCdd4UVsSCpdWq4JTb7x90xHxWC2+V2rBXltJpMY8V3uh7/uE5hN23TSwk5r55ULt hcLHtNQtmVzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602314" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:13 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao , Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 13/16] MdePkg/Include: Hook DebugLib _ASSERT() for unit tests Date: Fri, 10 Jul 2020 19:09:01 -0700 Message-Id: <20200711020904.24116-14-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: 6kjuu4z9zWU3O1HHkaLEJqCNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433355; bh=dJ1ATfHWt4N2eyhjY5BsIwd04/hC75kpEj7ayKFZkAw=; h=Cc:Date:From:Reply-To:Subject:To; b=nAuA86TJae+1BErzFaKtBhcUTo8QpJOWMtJ0vtvX7z8IK0bJt0MdT4vWSUrDEXij6Fm KNVBlq6yCG1yHrETXa481enAl6wNWI6IewAjV2O1jpYPgFwtOEbhwYnQT5DXjx1rKTpWk GwtC1YBc6wqgMAAwLRA+AD4ncMbCX8hpuFo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2801 Update DebugLib.h _ASSERT() macro to check if unit testing is enabled and call UnitTestDebugAssert() instead of DebugAssert() so the an ASSERT() condition that is triggered by a function under test can be handled by the Unit Test Framework. If EDKII_UNIT_TEST_FRAMEWORK_ENABLED is not defined, then the existing DebugLib behavior is preserved. Cc: Liming Gao Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- MdePkg/Include/Library/DebugLib.h | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/MdePkg/Include/Library/DebugLib.h b/MdePkg/Include/Library/Deb= ugLib.h index baab34bf05..4cacd4b8e2 100644 --- a/MdePkg/Include/Library/DebugLib.h +++ b/MdePkg/Include/Library/DebugLib.h @@ -289,12 +289,38 @@ DebugPrintLevelEnabled ( @param Expression Boolean expression that evaluated to FALSE =20 **/ +#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED) +/** + Unit test library replacement for DebugAssert() in DebugLib. + + If FileName is NULL, then a string of "(NULL) Filename" is pr= inted. + If Description is NULL, then a string of "(NULL) Descripti= on" is printed. + + @param FileName The pointer to the name of the source file that gen= erated the assert condition. + @param LineNumber The line number in the source file that generated t= he assert condition + @param Description The pointer to the description of the assert condit= ion. + +**/ +VOID +EFIAPI +UnitTestDebugAssert ( + IN CONST CHAR8 *FileName, + IN UINTN LineNumber, + IN CONST CHAR8 *Description + ); + +#if defined(__clang__) && defined(__FILE_NAME__) +#define _ASSERT(Expression) UnitTestDebugAssert (__FILE_NAME__, __LINE__,= #Expression) +#else +#define _ASSERT(Expression) UnitTestDebugAssert (__FILE__, __LINE__, #Exp= ression) +#endif +#else #if defined(__clang__) && defined(__FILE_NAME__) #define _ASSERT(Expression) DebugAssert (__FILE_NAME__, __LINE__, #Expres= sion) #else #define _ASSERT(Expression) DebugAssert (__FILE__, __LINE__, #Expression) #endif - +#endif =20 /** Internal worker macro that calls DebugPrint(). --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62365): https://edk2.groups.io/g/devel/message/62365 Mute This Topic: https://groups.io/mt/75432225/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62366+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62366+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433356; cv=none; d=zohomail.com; s=zohoarc; b=huLQQ8ZBRgVNe9Aids2bDmvfNBS+UMf4IMPbJEW/uYk/VGWCd2WcCms0aOVWMJyMNQ4T20GTas/6vECGn6fGQoSOOqQhyOR5ew85WH8zfOvBnOjcc+/fAMjoIb/IwqIMtDRRtsYF9FBML3Y7TK7d6ajNn5bZOAwUCV9fPENPau8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433356; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=IGUYzcMNd+4AfyXTXC90ymNGY6rY+Q+W283zm4oR6zI=; b=itXqc5utGbzxrKknPJfsb+fYal0YcEVv6DhzYwBZy65O03BozaHWiPAPMNfgxrFd/aQ/oTiu9dqRiMvT1utgkDfQHauw7ogtBBR1/4YmjBsHd3FleDbhgLorLNJGXqFajt11jAs138StxVdchNb0nj/vgg+IdwDKUCRC5sRgR4Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62366+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433356030966.3821837289361; Fri, 10 Jul 2020 19:09:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id l1O8YY1788612xWa6fVlWJoc; Fri, 10 Jul 2020 19:09:15 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2047.1594433352364265985 for ; Fri, 10 Jul 2020 19:09:14 -0700 IronPort-SDR: Qw8I8WyPsGgZzGttxwlf0kp2Du44NBDy2pHLlMwJF+F02c6DfOcAhkEcR+MhsapCaFsNmvjEqE ZvNbdEGRuHBQ== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380576" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380576" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:14 -0700 IronPort-SDR: zDKYPt5eHsWOKgAv/PDqhGmHYncDqx08CNTipEeOdgRxvVsY9KPbGZ8UTCQgxQkAMooJfsvZ15 I9L+YhwUvufQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602319" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:13 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao , Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 14/16] MdePkg/Include: Add UT_EXPECT_ASSERT_FAILURE() to UnitTestLib Date: Fri, 10 Jul 2020 19:09:02 -0700 Message-Id: <20200711020904.24116-15-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: ZbwZCk9Py1pSl7erYoUn3WLex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433355; bh=MkEZAja65gN/FZqVQDT3wTzO1F50Asjjjo4yznPYC8U=; h=Cc:Date:From:Reply-To:Subject:To; b=DMcSVbMgub0dohhFYxg1qWjMm/Y4VpHHwUt1by4E0OP0cLeNVdTOKGUjBfGifiVibn1 a7n+/sgw+Tf4FUsVu86E6nrNYafmTmGmF3raexK8CX5HMb4L1Z2vRnWrgz3ZO7dSlBM28 ubcCN2CXZW/MMpZNLtJrK8BWF/13QKItQX0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2801 Add the UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) macro to the UnitTestLib that can be used to check if a function under test triggers an ASSERT() condition. If an ASSERT() condition is triggered, then the macro returns. If the ASSERT() condition is not triggered, then the current unit test fails with a status of UNIT_TEST_ERROR_TEST_FAILED. If ASSERT()s are disabled, then this check for ASSERT() behavior is not possible, and the check is skipped. The global variable gUnitTestExpectAssertFailureJumpBuffer is added to the UnitTestLib to save/restore context when the UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) macro is used. The UT_EXPECT_ASSERT_FAILURE() macro uses the SetJump() service with this global variable. The UnitTestLib service UnitTestDebugAssert() uses the LongJump() service with this global to restore context if an ASSERT() is triggered by the code under test. Add UnitTestExpectAssertFailure() to the UnitTestLib class. The UnitTestExpectAssertFailure() is called from the new UT_EXPECT_ASSERT_FAILURE() macro after the status of this macro check is known. Add UnitTestDebugAssert() to the UnitTestLib class. The UnitTestDebugAssert() service is the same as the DebugLib DebugAssert() service and is invoked from the DebugLib _ASSERT() macro if unit testing is enabled. This allows the Unit Test Framework to know when code under test triggers an ASSERT() condition. Cc: Liming Gao Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- MdePkg/Include/Library/UnitTestLib.h | 90 ++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/MdePkg/Include/Library/UnitTestLib.h b/MdePkg/Include/Library/= UnitTestLib.h index a4374580a8..99175496c8 100644 --- a/MdePkg/Include/Library/UnitTestLib.h +++ b/MdePkg/Include/Library/UnitTestLib.h @@ -441,6 +441,56 @@ SaveFrameworkState ( return UNIT_TEST_ERROR_TEST_FAILED; = \ } =20 +/** + This macro uses the framework assertion logic to check whether a functio= n call + triggers an ASSERT() condition. The BaseLib SetJump()/LongJump() servic= es + are used to establish a safe return point when an ASSERT() is triggered. + If an ASSERT() is triggered, unit test execution continues and Status is= set + to UNIT_TEST_PASSED. Otherwise, a unit test case failure is raised and + Status is set to UNIT_TEST_ERROR_TEST_FAILED. + + If ASSERT() macros are disabled, then the test case is skipped and a war= ning + message is added to the unit test log. Status is set to UNIT_TEST_SKIPP= ED. + + @param[in] FunctionCall Function call that is expected to trigger ASSE= RT(). + @param[out] Status Pointer to a UNIT_TEST_STATUS return value. T= his + is an optional parameter that may be NULL. +**/ +#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED) + #include + + /// + /// Pointer to jump buffer used with SetJump()/LongJump() to test if a + /// function under test generates an expected ASSERT() condition. + /// + extern BASE_LIBRARY_JUMP_BUFFER *gUnitTestExpectAssertFailureJumpBuffer; + + #define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) \ + do { \ + UNIT_TEST_STATUS UnitTestJumpStatus; \ + BASE_LIBRARY_JUMP_BUFFER UnitTestJumpBuffer; \ + UnitTestJumpStatus =3D UNIT_TEST_SKIPPED; \ + if (DebugAssertEnabled ()) { \ + gUnitTestExpectAssertFailureJumpBuffer =3D &UnitTestJumpBuffer; \ + if (SetJump (gUnitTestExpectAssertFailureJumpBuffer) =3D=3D 0) { = \ + FunctionCall; \ + UnitTestJumpStatus =3D UNIT_TEST_ERROR_TEST_FAILED; \ + } else { \ + UnitTestJumpStatus =3D UNIT_TEST_PASSED; \ + } \ + gUnitTestExpectAssertFailureJumpBuffer =3D NULL; \ + } \ + if (!UnitTestExpectAssertFailure ( \ + UnitTestJumpStatus, \ + __FUNCTION__, __LINE__, __FILE__, \ + #FunctionCall, Status)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } \ + } while (FALSE) +#else + #define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) FunctionCall; +#endif + /** If Expression is TRUE, then TRUE is returned. If Expression is FALSE, then an assert is triggered and the location of = the @@ -690,6 +740,46 @@ UnitTestAssertNotNull ( IN CONST CHAR8 *PointerName ); =20 +/** + If UnitTestStatus is UNIT_TEST_PASSED, then log an info message and retu= rn + TRUE because an ASSERT() was expected when FunctionCall was executed and= an + ASSERT() was triggered. If UnitTestStatus is UNIT_TEST_SKIPPED, then log= a + warning message and return TRUE because ASSERT() macros are disabled. If + UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED, then log an error message= and + return FALSE because an ASSERT() was expected when FunctionCall was exec= uted, + but no ASSERT() conditions were triggered. The log messages contain + FunctionName, LineNumber, and FileName strings to provide the location o= f the + UT_EXPECT_ASSERT_FAILURE() macro. + + @param[in] UnitTestStatus The status from UT_EXPECT_ASSERT_FAILURE() t= hat + is either pass, skipped, or failed. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] LineNumber The source file line number of the the funct= ion + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the UT_EXPECT_ASSERT_FAILURE() mac= ro. + @param[in] FunctionCall Null-terminated ASCII string of the function= call + executed by the UT_EXPECT_ASSERT_FAILURE() m= acro. + @param[out] ResultStatus Used to return the UnitTestStatus value to t= he + caller of UT_EXPECT_ASSERT_FAILURE(). This = is + optional parameter that may be NULL. + + @retval TRUE UnitTestStatus is UNIT_TEST_PASSED. + @retval TRUE UnitTestStatus is UNIT_TEST_SKIPPED. + @retval FALSE UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED. +**/ +BOOLEAN +EFIAPI +UnitTestExpectAssertFailure ( + IN UNIT_TEST_STATUS UnitTestStatus, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *FunctionCall, + OUT UNIT_TEST_STATUS *ResultStatus OPTIONAL + ); + /** Test logging macro that records an ERROR message in the test framework l= og. Record is associated with the currently executing test case. --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62366): https://edk2.groups.io/g/devel/message/62366 Mute This Topic: https://groups.io/mt/75432226/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62367+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62367+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433356; cv=none; d=zohomail.com; s=zohoarc; b=A7Av39otCzbQTPWcveKt/urn/F6EdCxuZqP5QOfFcXaWxzq++JPGW7WTkm5hBr8dDmyK9h0f1cSlWdIWO7jv7k8AExK9ciZ4RF5WgmnmXTTAbvzsZiNFAQxI/D1XI885QPGSz0nE6hT09gInDaZ22Cl2JTRwjO3Uyi2Dofle0zI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433356; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=y552fqsEEWf73bOZtB8j2i7TJOwCrjhcO5oDTR9f3Ps=; b=bJRHI4MBtJrnMD9C7NmgvWYLmSOhWildEDrp+M1ztUzQQMTB2luclaltbpwH3xdlQRsRikQ9HxuXDJubfAvwyG0R/UPsHKsfBbubTCQHtiAeQrWHp+PkLXy5+Uxxfm2xNYd7cvjeRnJARboG4wm9x3wgtsPWV0TkmU4RMbCFwP8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62367+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433356679116.25863333191467; Fri, 10 Jul 2020 19:09:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id xk1mYY1788612x0mDuQA0tgL; Fri, 10 Jul 2020 19:09:16 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2047.1594433352364265985 for ; Fri, 10 Jul 2020 19:09:14 -0700 IronPort-SDR: 9FgPhuQLSKxVXNVsJqvf7cgmFTWLhRfQ1VshzGyOfh8sl5EnwwjTFUYbnOS1+DtrLgeD9vvrno aJruFyhQhXTA== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380577" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380577" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:14 -0700 IronPort-SDR: W/uS2vdQTqw3yvoRhlv9Nym/EOPduMcvpbMj6Vjk++UWevUNVjdNnzV6jaMgewkUy3ua/U3KGw RanYcaMqEa7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602325" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:14 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Liming Gao Subject: [edk2-devel] [Patch v3 15/16] MdePkg/Library/BaseStackCheckLib: Fix PCD type in INF Date: Fri, 10 Jul 2020 19:09:03 -0700 Message-Id: <20200711020904.24116-16-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: Fror5cB44UiU55ng0nTyTeNlx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433356; bh=MiinaoQzBJamtN/CmfqDW0lnwcgN/xDCjYjgEybPYL0=; h=Cc:Date:From:Reply-To:Subject:To; b=K2L2t/8Q048UGxRiQ+XXZzNH7Kg/otiyQE0PkAz3B5nPKA3AMA99BZdPoyJjIL4sM+3 jd4I0Z3IxQCFgO+09LUxrM6TVFvWGQQVCp4ATDy4uvkuhVqA0dC2Y9AtOYipMu3mJk/RE K/c3au5VlyXIcy96XYliBSAggK+6xYAFIsc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Update INF file to use a [Pcd] section instead of a [FixedPcd] section. [FixedPcd] should only be used in an INF file if the source code looks up the PCD value using the PcdLib FixedPcdGetxx() services. Using [FixedPcd] forces a platform to configure the PCD to type FixedAtBuild. In this case, PcdDebugPropertyMask supports PCD types FixedAtBuild and PatchableInModule. Without this change any platform that wants to use PcdDebugPropertyMask as type PatchableInModule breaks the build. Cc: Liming Gao Signed-off-by: Michael D Kinney Reviewed-by: Liming Gao Reviewed-by: Bret Barkelew --- MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf b/MdePk= g/Library/BaseStackCheckLib/BaseStackCheckLib.inf index 4ae3bd1a82..0dc3c4a83a 100644 --- a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf +++ b/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf @@ -36,5 +36,5 @@ [LibraryClasses] BaseLib DebugLib =20 -[FixedPcd] +[Pcd] gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask ## CONSUMES --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#62367): https://edk2.groups.io/g/devel/message/62367 Mute This Topic: https://groups.io/mt/75432227/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 14:30:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+62368+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62368+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1594433357; cv=none; d=zohomail.com; s=zohoarc; b=GvqNW6WBwMXSDbTik3y1KfD1MMho6THZjqOU35/c6+VK5LqtQYiv+t/oKAnZzgMaMWh7IOIt/ywK/lYnwArWpoXTh0WgZkEfcYn5vPO52YQSX8ZRbXAgFnH5WX8ao6JabXcYgcF0csWyU5VnkmVVHk9yTNr9nAhGgkwJQKfkeGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1594433357; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ob8xLRZYIfjslI9qlXLJykvzWRQNhMJt+3Nxs6BnZ9Q=; b=aahRvU1Wq4FxvOtCiXBnQKNjNDAtj9xXAH3NwVp0S/ZCtFxzYJ72gbVlt2yf4s3U81HX4WQ+x51/O3JGYJGmR+vsMlPpnrSThAbNo8LLxvf0wM59n/tflKAIONwrU69goohlF11FyU5Q19RoWbriQjfLebwx5gGL22eLv57OX6s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+62368+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1594433357095163.204607020474; Fri, 10 Jul 2020 19:09:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id sXBnYY1788612xm3jD5tnGqi; Fri, 10 Jul 2020 19:09:16 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2047.1594433352364265985 for ; Fri, 10 Jul 2020 19:09:15 -0700 IronPort-SDR: Wq5bZYpGJLHOmyXaAXpzaD3IEKIzil4ME4hpNIkxddwYxDxHApDEbTaPjjIDoyyf5GXgF9qCr8 /gptyy6iSAJg== X-IronPort-AV: E=McAfee;i="6000,8403,9678"; a="146380579" X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="146380579" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 19:09:15 -0700 IronPort-SDR: LhWBDsU58Ri/Un0QIAmQghfNx7ZRubZ9DREkzMTwfR9+Qg9bcB4gvmRdivnu0aRV8HZixRXXfe m8k0L6dWvvZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,337,1589266800"; d="scan'208";a="298602331" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.254.75.186]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2020 19:09:14 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Bret Barkelew , Jiewen Yao Subject: [edk2-devel] [Patch v3 16/16] UnitTestFramewokPkg/SampleUnitTest: Use UT_EXPECT_ASSERT_FAILURE() Date: Fri, 10 Jul 2020 19:09:04 -0700 Message-Id: <20200711020904.24116-17-michael.d.kinney@intel.com> In-Reply-To: <20200711020904.24116-1-michael.d.kinney@intel.com> References: <20200711020904.24116-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: RABQKgC4Wu1APWLkbtOTDbR3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1594433356; bh=hj/Lb0zF3rJChh7WPza45BMOTpdH2/5K2uoTi5PLzpc=; h=Cc:Date:From:Reply-To:Subject:To; b=cen2Hyvhfup+fEr3PTMaPywWrQNouPoePFrgy6oI2sG48GrkO5ReKskIB36nNzTEAOo NGjZMWqYE2iVKdxPrlLvhSVRE2WzO6nDkv1dMQxEKDyPMSYrTBqyV89QXrwTOBG74+rTo bfJIl8XEyTH4M0dmDhAjl4zC1veAHIZQfSk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2801 Add samples for all UnitTestLib macros including using UT_EXPECT_ASSERT_FAILURE() for positive test cases where an ASSERT() is triggered and detected correctly. Additional test cases are added that disable ASSERT()s and verify that UT_EXPECT_ASSERT_FAILURE() macros are skipped. Cc: Sean Brogan Cc: Bret Barkelew Cc: Jiewen Yao Signed-off-by: Michael D Kinney Reviewed-by: Bret Barkelew --- .../Sample/SampleUnitTest/SampleUnitTest.c | 510 ++++++++++++++++++ .../SampleUnitTest/SampleUnitTestDxe.inf | 3 + .../SampleUnitTest/SampleUnitTestHost.inf | 3 + .../SampleUnitTest/SampleUnitTestPei.inf | 3 + .../SampleUnitTest/SampleUnitTestSmm.inf | 3 + .../SampleUnitTestUefiShell.inf | 3 + .../Test/UnitTestFrameworkPkgHostTest.dsc | 3 + UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc | 3 + 8 files changed, 531 insertions(+) diff --git a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/Sampl= eUnitTest.c b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/Samp= leUnitTest.c index 37d5747bca..cb50f45391 100644 --- a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= st.c +++ b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= st.c @@ -181,6 +181,466 @@ GlobalPointerShouldBeChangeable ( return UNIT_TEST_PASSED; } =20 +/** + Unit-Test Test Suite Setup (before) function that enables ASSERT() macro= s. +**/ +VOID +EFIAPI +TestSuiteEnableAsserts ( + VOID + ) +{ + // + // Set BIT0 (DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) + // + PatchPcdSet8 (PcdDebugPropertyMask, PcdGet8 (PcdDebugPropertyMask) | BIT= 0); +} + +/** + Unit-Test Test Suite Setup (before) function that disables ASSERT() macr= os. +**/ +VOID +EFIAPI +TestSuiteDisableAsserts ( + VOID + ) +{ + // + // Clear BIT0 (DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) + // + PatchPcdSet8 (PcdDebugPropertyMask, PcdGet8 (PcdDebugPropertyMask) & (~B= IT0)); +} + +/** + Sample unit test using the UT_ASSERT_TRUE() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtAssertTrue ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINT64 Result; + + // + // This test passes because expression always evaluated to TRUE. + // + UT_ASSERT_TRUE (TRUE); + + // + // This test passes because expression always evaluates to TRUE. + // + Result =3D LShiftU64 (BIT0, 1); + UT_ASSERT_TRUE (Result =3D=3D BIT1); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_ASSERT_FALSE() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtAssertFalse ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINT64 Result; + + // + // This test passes because expression always evaluated to FALSE. + // + UT_ASSERT_FALSE (FALSE); + + // + // This test passes because expression always evaluates to FALSE. + // + Result =3D LShiftU64 (BIT0, 1); + UT_ASSERT_FALSE (Result =3D=3D BIT0); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_ASSERT_EQUAL() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtAssertEqual ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINT64 Result; + + // + // This test passes because both values are always equal. + // + UT_ASSERT_EQUAL (1, 1); + + // + // This test passes because both values are always equal. + // + Result =3D LShiftU64 (BIT0, 1); + UT_ASSERT_EQUAL (Result, BIT1); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_ASSERT_MEM_EQUAL() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtAssertMemEqual ( + IN UNIT_TEST_CONTEXT Context + ) +{ + CHAR8 *String1; + CHAR8 *String2; + UINTN Length; + + // + // This test passes because String1 and String2 are the same. + // + String1 =3D "Hello"; + String2 =3D "Hello"; + Length =3D sizeof ("Hello"); + UT_ASSERT_MEM_EQUAL (String1, String2, Length); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_ASSERT_NOT_EQUAL() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtAssertNotEqual ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINT64 Result; + + // + // This test passes because both values are never equal. + // + UT_ASSERT_NOT_EQUAL (0, 1); + + // + // This test passes because both values are never equal. + // + Result =3D LShiftU64 (BIT0, 1); + UT_ASSERT_NOT_EQUAL (Result, BIT0); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_ASSERT_NOT_EFI_ERROR() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtAssertNotEfiError ( + IN UNIT_TEST_CONTEXT Context + ) +{ + // + // This test passes because the status is not an EFI error. + // + UT_ASSERT_NOT_EFI_ERROR (EFI_SUCCESS); + + // + // This test passes because the status is not an EFI error. + // + UT_ASSERT_NOT_EFI_ERROR (EFI_WARN_BUFFER_TOO_SMALL); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_ASSERT_STATUS_EQUAL() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtAssertStatusEqual ( + IN UNIT_TEST_CONTEXT Context + ) +{ + // + // This test passes because the status value are always equal. + // + UT_ASSERT_STATUS_EQUAL (EFI_SUCCESS, EFI_SUCCESS); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_ASSERT_NOT_NULL() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtAssertNotNull ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINT64 Result; + + // + // This test passes because the pointer is never NULL. + // + UT_ASSERT_NOT_NULL (&Result); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_EXPECT_ASSERT_FAILURE() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtExpectAssertFailure ( + IN UNIT_TEST_CONTEXT Context + ) +{ + // + // This test passes because it directly triggers an ASSERT(). + // + UT_EXPECT_ASSERT_FAILURE (ASSERT (FALSE), NULL); + + // + // This test passes because DecimalToBcd() generates an ASSERT() if the + // value passed in is >=3D 100. The expected ASSERT() is caught by the = unit + // test framework and UT_EXPECT_ASSERT_FAILURE() returns without an erro= r. + // + UT_EXPECT_ASSERT_FAILURE (DecimalToBcd8 (101), NULL); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_LOG_ERROR() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtLogError ( + IN UNIT_TEST_CONTEXT Context + ) +{ + // + // Example of logging. + // + UT_LOG_ERROR ("UT_LOG_ERROR() message\n"); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_LOG_WARNING() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtLogWarning ( + IN UNIT_TEST_CONTEXT Context + ) +{ + // + // Example of logging. + // + UT_LOG_WARNING ("UT_LOG_WARNING() message\n"); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_LOG_INFO() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtLogInfo ( + IN UNIT_TEST_CONTEXT Context + ) +{ + // + // Example of logging. + // + UT_LOG_INFO ("UT_LOG_INFO() message\n"); + + return UNIT_TEST_PASSED; +} + +/** + Sample unit test using the UT_LOG_VERBOSE() macro. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +MacroUtLogVerbose ( + IN UNIT_TEST_CONTEXT Context + ) +{ + // + // Example of logging. + // + UT_LOG_VERBOSE ("UT_LOG_VERBOSE() message\n"); + + return UNIT_TEST_PASSED; +} + /** Initialize the unit test framework, suite, and unit tests for the sample unit tests and run the unit tests. @@ -199,6 +659,8 @@ UefiTestMain ( UNIT_TEST_FRAMEWORK_HANDLE Framework; UNIT_TEST_SUITE_HANDLE SimpleMathTests; UNIT_TEST_SUITE_HANDLE GlobalVarTests; + UNIT_TEST_SUITE_HANDLE MacroTestsAssertsEnabled; + UNIT_TEST_SUITE_HANDLE MacroTestsAssertsDisabled; =20 Framework =3D NULL; =20 @@ -236,6 +698,54 @@ UefiTestMain ( AddTestCase (GlobalVarTests, "You should be able to change a global BOOL= EAN", "Boolean", GlobalBooleanShouldBeChangeable, NULL, NULL, NULL); AddTestCase (GlobalVarTests, "You should be able to change a global poin= ter", "Pointer", GlobalPointerShouldBeChangeable, MakeSureThatPointerIsNull= , ClearThePointer, NULL); =20 + // + // Populate the Macro Tests with ASSERT() enabled + // + Status =3D CreateUnitTestSuite (&MacroTestsAssertsEnabled, Framework, "M= acro Tests with ASSERT() enabled", "Sample.MacroAssertsEnabled", TestSuiteE= nableAsserts, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for MacroTestsAsse= rtsEnabled\n")); + Status =3D EFI_OUT_OF_RESOURCES; + goto EXIT; + } + AddTestCase (MacroTestsAssertsEnabled, "Test UT_ASSERT_TRUE() macro", = "MacroUtAssertTrue", MacroUtAssertTrue, NULL, NUL= L, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_ASSERT_FALSE() macro", = "MacroUtAssertFalse", MacroUtAssertFalse, NULL, NUL= L, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_ASSERT_EQUAL() macro", = "MacroUtAssertEqual", MacroUtAssertEqual, NULL, NUL= L, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_ASSERT_MEM_EQUAL() macro= ", "MacroUtAssertMemEqual", MacroUtAssertMemEqual, NULL, NUL= L, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_ASSERT_NOT_EQUAL() macro= ", "MacroUtAssertNotEqual", MacroUtAssertNotEqual, NULL, NUL= L, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_ASSERT_NOT_EFI_ERROR() m= acro", "MacroUtAssertNotEfiError", MacroUtAssertNotEfiError, NULL, NUL= L, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_ASSERT_STATUS_EQUAL() ma= cro", "MacroUtAssertStatusEqual", MacroUtAssertStatusEqual, NULL, NUL= L, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_ASSERT_NOT_NULL() macro"= , "MacroUtAssertNotNull", MacroUtAssertNotNull, NULL, NUL= L, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_EXPECT_ASSERT_FAILURE() = macro", "MacroUtExpectAssertFailure", MacroUtExpectAssertFailure, NULL, NUL= L, NULL); + + AddTestCase (MacroTestsAssertsEnabled, "Test UT_LOG_ERROR() macro", "M= acroUtLogError", MacroUtLogError, NULL, NULL, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_LOG_WARNING() macro", "M= acroUtLogWarning", MacroUtLogWarning, NULL, NULL, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_LOG_INFO() macro", "M= acroUtLogInfo", MacroUtLogInfo, NULL, NULL, NULL); + AddTestCase (MacroTestsAssertsEnabled, "Test UT_LOG_VERBOSE() macro", "M= acroUtLogVerbose", MacroUtLogVerbose, NULL, NULL, NULL); + + // + // Populate the Macro Tests with ASSERT() disabled + // + Status =3D CreateUnitTestSuite (&MacroTestsAssertsDisabled, Framework, "= Macro Tests with ASSERT() disabled", "Sample.MacroAssertsDisables", TestSui= teDisableAsserts, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for MacroTestsAsse= rtsDisabled\n")); + Status =3D EFI_OUT_OF_RESOURCES; + goto EXIT; + } + AddTestCase (MacroTestsAssertsDisabled, "Test UT_ASSERT_TRUE() macro", = "MacroUtAssertTrue", MacroUtAssertTrue, NULL, NU= LL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_ASSERT_FALSE() macro", = "MacroUtAssertFalse", MacroUtAssertFalse, NULL, NU= LL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_ASSERT_EQUAL() macro", = "MacroUtAssertEqual", MacroUtAssertEqual, NULL, NU= LL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_ASSERT_MEM_EQUAL() macr= o", "MacroUtAssertMemEqual", MacroUtAssertMemEqual, NULL, NU= LL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_ASSERT_NOT_EQUAL() macr= o", "MacroUtAssertNotEqual", MacroUtAssertNotEqual, NULL, NU= LL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_ASSERT_NOT_EFI_ERROR() = macro", "MacroUtAssertNotEfiError", MacroUtAssertNotEfiError, NULL, NU= LL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_ASSERT_STATUS_EQUAL() m= acro", "MacroUtAssertStatusEqual", MacroUtAssertStatusEqual, NULL, NU= LL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_ASSERT_NOT_NULL() macro= ", "MacroUtAssertNotNull", MacroUtAssertNotNull, NULL, NU= LL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_EXPECT_ASSERT_FAILURE()= macro", "MacroUtExpectAssertFailure", MacroUtExpectAssertFailure, NULL, NU= LL, NULL); + + AddTestCase (MacroTestsAssertsDisabled, "Test UT_LOG_ERROR() macro", "= MacroUtLogError", MacroUtLogError, NULL, NULL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_LOG_WARNING() macro", "= MacroUtLogWarning", MacroUtLogWarning, NULL, NULL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_LOG_INFO() macro", "= MacroUtLogInfo", MacroUtLogInfo, NULL, NULL, NULL); + AddTestCase (MacroTestsAssertsDisabled, "Test UT_LOG_VERBOSE() macro", "= MacroUtLogVerbose", MacroUtLogVerbose, NULL, NULL, NULL); + // // Execute the tests. // diff --git a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/Sampl= eUnitTestDxe.inf b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest= /SampleUnitTestDxe.inf index e253cf6e16..a1b1e53789 100644 --- a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stDxe.inf +++ b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stDxe.inf @@ -32,5 +32,8 @@ [LibraryClasses] UnitTestLib PrintLib =20 +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask + [Depex] TRUE diff --git a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/Sampl= eUnitTestHost.inf b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTes= t/SampleUnitTestHost.inf index 59a367cc6e..681165da3b 100644 --- a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stHost.inf +++ b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stHost.inf @@ -28,3 +28,6 @@ [LibraryClasses] BaseLib DebugLib UnitTestLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask diff --git a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/Sampl= eUnitTestPei.inf b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest= /SampleUnitTestPei.inf index 60f5252c34..2565f764a0 100644 --- a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stPei.inf +++ b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stPei.inf @@ -32,5 +32,8 @@ [LibraryClasses] UnitTestLib PrintLib =20 +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask + [Depex] gEfiPeiMemoryDiscoveredPpiGuid diff --git a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/Sampl= eUnitTestSmm.inf b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest= /SampleUnitTestSmm.inf index 324ad2686e..f47bc87df3 100644 --- a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stSmm.inf +++ b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stSmm.inf @@ -33,5 +33,8 @@ [LibraryClasses] UnitTestLib PrintLib =20 +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask + [Depex] gEfiSmmCpuProtocolGuid diff --git a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/Sampl= eUnitTestUefiShell.inf b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUn= itTest/SampleUnitTestUefiShell.inf index 6e39c229d4..19534e7b1f 100644 --- a/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stUefiShell.inf +++ b/UnitTestFrameworkPkg/Test/UnitTest/Sample/SampleUnitTest/SampleUnitTe= stUefiShell.inf @@ -31,3 +31,6 @@ [LibraryClasses] DebugLib UnitTestLib PrintLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask diff --git a/UnitTestFrameworkPkg/Test/UnitTestFrameworkPkgHostTest.dsc b/U= nitTestFrameworkPkg/Test/UnitTestFrameworkPkgHostTest.dsc index 70affddead..184fdec87a 100644 --- a/UnitTestFrameworkPkg/Test/UnitTestFrameworkPkgHostTest.dsc +++ b/UnitTestFrameworkPkg/Test/UnitTestFrameworkPkgHostTest.dsc @@ -18,6 +18,9 @@ [Defines] =20 !include UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc =20 +[PcdsPatchableInModule] + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 + [Components] # # Build HOST_APPLICATION that tests the SampleUnitTest diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc b/UnitTestFramew= orkPkg/UnitTestFrameworkPkg.dsc index 0dfd98f2a8..2f0fbfc7cc 100644 --- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc +++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc @@ -20,6 +20,9 @@ [Defines] =20 !include UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc =20 +[PcdsPatchableInModule] + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 + [Components] UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLib.inf UnitTestFrameworkPkg/Library/UnitTestPersistenceLibNull/UnitTestPersiste= nceLibNull.inf --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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