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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,garrett.kirkendall@amd.com X-Gm-Message-State: HJoZveAjyySUK8NEk4G8jxAKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592831929; bh=9MM9U6Xjs2OeDXJjpFDaiFUrxyhmlcnku8UbL/n3tA4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=LprjsjTbLaTF6/23FULvvZDp8f2IIClcfCRRmSQEDH3xIGRC+sTNIUCltXQDA11oZlH i9AK6sSPWaTN2K21feihAs8rv7tcrvIXJfXCRpyWEDtyEMOvxbnVNGQ/huZcY1S9aSzvc 0Xi0U0y7wZYGB8v1zkTMNC78oBKWJQxoxrk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" AMD does not support MSR_IA32_MISC_ENABLE. Accessing that register causes and exception on AMD processors. If Execution Disable is supported, but if the processor is an AMD processor, skip manipulating MSR_IA32_MISC_ENABLE[34] XD Disable bit. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Garrett Kirkendall Reviewed-by: Eric Dong Reviewed-by: Laszlo Ersek Tested-by: Laszlo Ersek --- Notes: Tested on Intel hardware with Laszlo Ersek's help =20 (1) downloaded two Linux images from provided links. (2) Test using a 32-bit guest on an Intel host (standing in your edk2 t= ree, with the patches applied): =20 $ build -a IA32 -b DEBUG -p OvmfPkg/OvmfPkgIa32.dsc -t GCC5 -D SMM_REQU= IRE =20 $ qemu-system-i386 \ -cpu coreduo,-nx \ -machine q35,smm=3Don,accel=3Dkvm \ -m 4096 \ -smp 4 \ -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ -drive if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild= /OvmfIa32/DEBUG_GCC5/FV/OVMF_CODE.fd \ -drive if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild= /OvmfIa32/DEBUG_GCC5/FV/OVMF_VARS.fd \ -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfedor= a-30-efi-systemd-i686.qcow2 \ -device virtio-scsi-pci,id=3Dscsi0 \ -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 =20 (Once you get a login prompt, feel free to interrupt QEMU with Ctrl-C.) =20 (3) Test using a 64-bit guest on an Intel host: =20 $ build -a IA32 -a X64 -b DEBUG -p OvmfPkg/OvmfPkgIa32X64.dsc -t GCC5 -= D SMM_REQUIRE =20 $ qemu-system-x86_64 \ -cpu host \ -machine q35,smm=3Don,accel=3Dkvm \ -m 4096 \ -smp 4 \ -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ -drive if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild= /Ovmf3264/DEBUG_GCC5/FV/OVMF_CODE.fd \ -drive if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild= /Ovmf3264/DEBUG_GCC5/FV/OVMF_VARS.fd \ -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfedor= a-31-efi-grub2-x86_64.qcow2 \ -device virtio-scsi-pci,id=3Dscsi0 \ -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 =20 Tested on real AMD Hardware UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 3 +++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 9 ++++++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 19 +++++++++++++++++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 20 ++++++++++++++++++-- 4 files changed, 46 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/Pi= SmmCpuDxeSmm/SmmProfileInternal.h index 43f6935cf9dc..993360a8a8c1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -2,6 +2,7 @@ SMM profile internal header file. =20 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2020, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -13,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include =20 #include "SmmProfileArch.h" @@ -99,6 +101,7 @@ extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; extern UINTN gSmiExceptionHandlers[]; extern BOOLEAN mXdSupported; X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; +X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported; extern UINTN *mPFEntryCount; extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUN= T]; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index c47b5573e366..d7ed9ab7a770 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -2,7 +2,7 @@ Enable SMM profile. =20 Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
-Copyright (c) 2017, AMD Incorporated. All rights reserved.
+Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1015,6 +1015,13 @@ CheckFeatureSupported ( mXdSupported =3D FALSE; PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1); } + + if (StandardSignatureIsAuthenticAMD ()) { + // + // AMD processors do not support MSR_IA32_MISC_ENABLE + // + PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1); + } } =20 if (mBtsSupported) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index f96de9bdeb43..167f5e14dbd4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -59,6 +60,7 @@ global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) +global ASM_PFX(gPatchMsrIa32MiscEnableSupported) extern ASM_PFX(gSmiHandlerIdtr) =20 extern ASM_PFX(mCetSupported) @@ -153,17 +155,30 @@ ASM_PFX(gPatchSmiCr3): ASM_PFX(gPatchXdSupported): cmp al, 0 jz @SkipXd + +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit + mov al, strict byte 1 ; source operand may be patched +ASM_PFX(gPatchMsrIa32MiscEnableSupported): + cmp al, 1 + jz MsrIa32MiscEnableSupported + +; MSR_IA32_MISC_ENABLE not supported + xor edx, edx + push edx ; don't try to restore the XD Disa= ble bit just before RSM + jmp EnableNxe + ; ; Check XD disable bit ; +MsrIa32MiscEnableSupported: mov ecx, MSR_IA32_MISC_ENABLE rdmsr push edx ; save MSR_IA32_MISC_ENABLE[63-32] test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] - jz .5 + jz EnableNxe and dx, 0xFFFB ; clear XD Disable bit if it is set wrmsr -.5: +EnableNxe: mov ecx, MSR_EFER rdmsr or ax, MSR_EFER_XD ; enable NXE diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index 8bfba55b5d08..0e154e5db949 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -67,6 +68,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) +global ASM_PFX(gPatchMsrIa32MiscEnableSupported) global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmiCr3) global ASM_PFX(gPatch5LevelPagingNeeded) @@ -152,18 +154,32 @@ SkipEnable5LevelPaging: ASM_PFX(gPatchXdSupported): cmp al, 0 jz @SkipXd + +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit + mov al, strict byte 1 ; source operand may be patched +ASM_PFX(gPatchMsrIa32MiscEnableSupported): + cmp al, 1 + jz MsrIa32MiscEnableSupported + +; MSR_IA32_MISC_ENABLE not supported + sub esp, 4 + xor rdx, rdx + push rdx ; don't try to restore the XD Disa= ble bit just before RSM + jmp EnableNxe + ; ; Check XD disable bit ; +MsrIa32MiscEnableSupported: mov ecx, MSR_IA32_MISC_ENABLE rdmsr sub esp, 4 push rdx ; save MSR_IA32_MISC_ENABLE[63-32] test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] - jz .0 + jz EnableNxe and dx, 0xFFFB ; clear XD Disable bit if it is set wrmsr -.0: +EnableNxe: mov ecx, MSR_EFER rdmsr or ax, MSR_EFER_XD ; enable NXE --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61560): https://edk2.groups.io/g/devel/message/61560 Mute This Topic: https://groups.io/mt/75037839/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-