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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from SN1PR12MB2352.namprd12.prod.outlook.com (2603:10b6:802:25::13) by SA0PR12MB4461.namprd12.prod.outlook.com (2603:10b6:806:9c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22; Mon, 22 Jun 2020 13:18:41 +0000 X-Received: from SN1PR12MB2352.namprd12.prod.outlook.com ([fe80::156e:ce6d:a148:274e]) by SN1PR12MB2352.namprd12.prod.outlook.com ([fe80::156e:ce6d:a148:274e%7]) with mapi id 15.20.3109.027; Mon, 22 Jun 2020 13:18:41 +0000 From: "Kirkendall, Garrett" To: devel@edk2.groups.io CC: Ray Ni Subject: [edk2-devel] [PATCH v6 1/4] PcAtChipsetPkg: PcAtChipsetPkg.dsc add UefiCpuLib LibraryClass Date: Mon, 22 Jun 2020 08:18:22 -0500 Message-ID: <20200622131825.1352-2-Garrett.Kirkendall@amd.com> In-Reply-To: <20200622131825.1352-1-Garrett.Kirkendall@amd.com> References: <20200622131825.1352-1-Garrett.Kirkendall@amd.com> X-ClientProxiedBy: SN4PR0501CA0135.namprd05.prod.outlook.com (2603:10b6:803:2c::13) To SN1PR12MB2352.namprd12.prod.outlook.com (2603:10b6:802:25::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from biosdev-01.amd.com (165.204.78.2) by SN4PR0501CA0135.namprd05.prod.outlook.com (2603:10b6:803:2c::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.13 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,garrett.kirkendall@amd.com X-Gm-Message-State: 4ykZTfwt26WAejHtnwqpwOA5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592832253; bh=9KBhckWQZICVrwgyTb5Sw7BF7k3lf2VlPfnMWJJ9acg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=iPbLhNdIqdTaTi6xj0TDxOBeuviRg0CQ/pzYxVEzVBnN2qpyRaj6C0RUJJk4MweASxr IGAEHjzdNsYevinGdguo/L/BCRb1HwFKtx3bG15UmnuHxL1z1Ughxdy+CCVkuMt1KvpxF euE3q+fPdkAvJiNQC+P52kPILDzOEpUfetQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" In preparation for moving StandardSignatureIsAuthenticAMD to UefiCpuLib in UefiCpuPkg, PcAtChipset/PcAtChipsetPkg.dsc needs LibraryClass UefiCpuLib. LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf will need UefiCpuLib LibraryClass. Likely most "real" platforms will be using BaseX2XApicLib instance which already required UefiCpuLib. Cc: Ray Ni Signed-off-by: Garrett Kirkendall Reviewed-by: Chasel Chiu Reviewed-by: Ray Ni --- PcAtChipsetPkg/PcAtChipsetPkg.dsc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dsc b/PcAtChipsetPkg/PcAtChipset= Pkg.dsc index 01a3ee716a98..b61b7d1f528e 100644 --- a/PcAtChipsetPkg/PcAtChipsetPkg.dsc +++ b/PcAtChipsetPkg/PcAtChipsetPkg.dsc @@ -2,6 +2,7 @@ # PC/AT Chipset Package # # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2020, AMD Incorporated. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -39,6 +40,7 @@ [LibraryClasses] ResetSystemLib|PcAtChipsetPkg/Library/ResetSystemLib/ResetSystemLib.inf IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61557): https://edk2.groups.io/g/devel/message/61557 Mute This Topic: https://groups.io/mt/75037835/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 23:30:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+61558+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61558+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1592831929342384.21608247451945; Mon, 22 Jun 2020 06:18:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id YbiIYY1788612xPSaTrddMm8; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from SN1PR12MB2352.namprd12.prod.outlook.com (2603:10b6:802:25::13) by SA0PR12MB4461.namprd12.prod.outlook.com (2603:10b6:806:9c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22; Mon, 22 Jun 2020 13:18:41 +0000 X-Received: from SN1PR12MB2352.namprd12.prod.outlook.com ([fe80::156e:ce6d:a148:274e]) by SN1PR12MB2352.namprd12.prod.outlook.com ([fe80::156e:ce6d:a148:274e%7]) with mapi id 15.20.3109.027; Mon, 22 Jun 2020 13:18:41 +0000 From: "Kirkendall, Garrett" To: devel@edk2.groups.io CC: Hao A Wu Subject: [edk2-devel] [PATCH v6 2/4] SourceLevelDebugPkg: SourceLevelDebugPkg.dsc add UefiCpuLib LibraryClass Date: Mon, 22 Jun 2020 08:18:23 -0500 Message-ID: <20200622131825.1352-3-Garrett.Kirkendall@amd.com> In-Reply-To: <20200622131825.1352-1-Garrett.Kirkendall@amd.com> References: <20200622131825.1352-1-Garrett.Kirkendall@amd.com> X-ClientProxiedBy: SN4PR0501CA0135.namprd05.prod.outlook.com (2603:10b6:803:2c::13) To SN1PR12MB2352.namprd12.prod.outlook.com (2603:10b6:802:25::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from biosdev-01.amd.com (165.204.78.2) by SN4PR0501CA0135.namprd05.prod.outlook.com (2603:10b6:803:2c::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3131.13 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,garrett.kirkendall@amd.com X-Gm-Message-State: znUBmHz52tvv0wfAkhpLYeZRx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592831929; bh=03KaE1RIj5dH6+MY1HAHt6k6kb/3/Te1vqXLvv+0Exg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=SSkh559BR9zDBQz3Q7ppsDUyc5usk91Yp/TuLISIdtx5O3qE02CG6I0B3+5Wx87Iog8 Fqz03OpvZ4n8ncJPOR5QhMSaocn7bS+4qf9zej9QIuPFOv7zNY6wPRrgUPr6RtaZ06zCu yYAGvQSH/8/ruZ2q49L5BTwQGBClvMRXLGU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" In preparation for moving StandardSignatureIsAuthenticAMD to UefiCpuLib in UefiCpuPkg, SourceLevelDebugPkg/SourceLevelDebugPkg.dsc needs LibraryClass UefiCpuLib. LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf will need UefiCpuLib LibraryClass. Likely most "real" platforms will be using BaseX2XApicLib instance which already required UefiCpuLib. Cc: Hao A Wu Signed-off-by: Garrett Kirkendall Reviewed-by: Chasel Chiu Reviewed-by: Hao A Wu --- SourceLevelDebugPkg/SourceLevelDebugPkg.dsc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/SourceLevelDebugPkg/SourceLevelDebugPkg.dsc b/SourceLevelDebug= Pkg/SourceLevelDebugPkg.dsc index a1a1b81d03cb..20eb10ba07f8 100644 --- a/SourceLevelDebugPkg/SourceLevelDebugPkg.dsc +++ b/SourceLevelDebugPkg/SourceLevelDebugPkg.dsc @@ -2,6 +2,7 @@ # Source Level Debug Package. # # Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2020, AMD Incorporated. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,6 +33,7 @@ [LibraryClasses.common] IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort= Lib16550.inf PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61558): https://edk2.groups.io/g/devel/message/61558 Mute This Topic: https://groups.io/mt/75037837/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 23:30:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+61559+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61559+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1592831929362280.67899699447446; Mon, 22 Jun 2020 06:18:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4JBxYY1788612xk3VPjrXm3W; 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Mon, 22 Jun 2020 13:18:41 +0000 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: b6b664cd-4b0e-4241-75e6-08d816aec84a X-MS-TrafficTypeDiagnostic: SA0PR12MB4461: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: 3ONJ3tf7GwTEle/9maLucXJN9fLCvGwGk8Us7TLDZrs+T5GxncAxsg5T5MF0MMxFWG6obLPA7wR/oxh6Ld6pT3d5gQQNlmhJy2NWLRt9ZfNBKazJs2Mdh3rVcyfrnnfWR4L7u2Ykb08u58MT3uHU/AGzDwi/g31n8i3otofqiUyMyBYfmRGpukWiaXQ57P6Gqw1vQFrobaXTEacrMb5EEZt0sJZFHZKOMCZdVUjx6at+XhHtlQExP9BJ7HcdbWos+5hrnbE022TqMjHDW6SK1EHsAGDHm7deQXVAtozCbTDMvnUy0wcjLX8uAQUlo3kW3p84qbfOK//9ihYD+c5xbw== X-MS-Exchange-AntiSpam-MessageData: JVwyFu1PaGRq9mA9igUiK74rg6zL51OK1wdufndA/7M/KTPrscaqu17ps1Gh2jV73A9fj/9hZ+WWSI/aPTgj0r54sauF75KYwGqJ/QGOnRWB7x/Uf39IZxvUXFlN5+5Eic2QZJ4cNlArUIkc2RSWAMFp0PbjbqL7ua70mx2jMHq0l33plbMUEGfcM8QxtHTZwH4KFkj8g43e44CrW7HWnjIeXZyRi4Y30jDrQQlPZM1qQ5LJpRlNy7FVptXq9NCQyCG+j7q0bCuYPt2UJntcMnsWl/pJRp7exsTX9C6LqZAvjOkO3oZm6sj/JTjRb3UGhtLZ6BeaEk4B7Ubd2l/gQzpu64K3RGRwdbA/3wJrHVerg5GjSK857rYySFefAf7ZlWcxR05hJ8GEoGxAU0UG6QM979OUl9TeurgUYalDwwHB5nfEkcTLCAKUBNjgVm7ZbhgOGqRg94EjBS/lP2dDjlvC438sBT4PplnnawZs9ss= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6b664cd-4b0e-4241-75e6-08d816aec84a X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2020 13:18:41.5307 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hLVF7CmUDx3EGOedhZIP0VtoFuXkJmAfwkj+EP3wuTiuH3aXO4QRUxd3PPnxGK69SJUEufOq40XLfHtvXJ03Wg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4461 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,garrett.kirkendall@amd.com X-Gm-Message-State: vopRsHUYnAsF1hakwbkeMu3Ux1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592831929; bh=jKe1G6wLPXtXg0x2i7VY9hZ7cwPwSD5bWjowMwDRb14=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=CS8NDqjvKi3cPbMv1CRSm7HYIMnNI3BXa8A9m4GNkBfAE8L2WRZs2wij/EPn64aUh83 cAbAU6Dz7XSh3UE7EUQxWw6ire15MmuDazkyQFnilG10M9m1XYyxzf3TH0lgJeJanzeYg qB9nZhU8vUfIHfoqfr/s+AMZmPZwrYHQLQg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Refactor StandardSignatureIsAuthenticAMD into BaseUefiCpuLib from separate copies in BaseXApicLib, BaseXApicX2ApicLib, and MpInitLib. This allows for future use of StandarSignatureIsAuthinticAMD without creating more instances in other modules. This function allows IA32/X64 code to determine if it is running on an AMD brand processor. UefiCpuLib is already included directly or indirectly in all modified modules. Complete move is made in this change. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Garrett Kirkendall Reviewed-by: Laszlo Ersek Reviewed-by: Eric Dong Reviewed-by: Chasel Chiu --- UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 7 ++++ UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf | 2 ++ UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf | 2 ++ UefiCpuPkg/Include/Library/UefiCpuLib.h | 14 ++++++++ UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 38 ++++++++= ++++++++++++ UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 25 ++------= ----- UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 25 ++------= ----- UefiCpuPkg/Library/MpInitLib/MpLib.c | 23 --------= ---- 8 files changed, 67 insertions(+), 69 deletions(-) diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpu= Pkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf index 006b7acbf14e..34d3a7bb4303 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf @@ -4,6 +4,7 @@ # The library routines are UEFI specification compliant. # # Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2020, AMD Inc. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -29,6 +30,12 @@ [Sources.IA32] [Sources.X64] X64/InitializeFpu.nasm =20 +[Sources] + BaseUefiCpuLib.c + [Packages] MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf b/UefiCpuPkg/= Library/BaseXApicLib/BaseXApicLib.inf index bdb2ff372677..561baa44b0e6 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf @@ -5,6 +5,7 @@ # where local APIC is disabled. # # Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2020, AMD Inc. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -37,6 +38,7 @@ [LibraryClasses] TimerLib IoLib PcdLib + UefiCpuLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds ## SOMETIMES= _CONSUMES diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf b= /UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf index ac1e0a1c9896..1e2a4f8b790f 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf @@ -5,6 +5,7 @@ # where local APIC is disabled. # # Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2020, AMD Inc. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -37,6 +38,7 @@ [LibraryClasses] TimerLib IoLib PcdLib + UefiCpuLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds ## SOMETIMES= _CONSUMES diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/L= ibrary/UefiCpuLib.h index 82e53bab3a0f..5326e7246301 100644 --- a/UefiCpuPkg/Include/Library/UefiCpuLib.h +++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h @@ -5,6 +5,7 @@ to be UEFI specification compliant. =20 Copyright (c) 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -29,4 +30,17 @@ InitializeFloatingPointUnits ( VOID ); =20 +/** + Determine if the standard CPU signature is "AuthenticAMD". + + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. + +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ); + #endif diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPk= g/Library/BaseUefiCpuLib/BaseUefiCpuLib.c new file mode 100644 index 000000000000..c2cc3ff9a709 --- /dev/null +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c @@ -0,0 +1,38 @@ +/** @file + This library defines some routines that are generic for IA32 family CPU. + + The library routines are UEFI specification compliant. + + Copyright (c) 2020, AMD Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include +#include + +/** + Determine if the standard CPU signature is "AuthenticAMD". + + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. + +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ) +{ + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && + RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && + RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); +} diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index 33ea15ca2916..52bd90d33428 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -4,7 +4,7 @@ This local APIC library instance supports xAPIC mode only. =20 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
- Copyright (c) 2017, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -21,33 +21,12 @@ #include #include #include +#include =20 // // Library internal functions // =20 -/** - Determine if the standard CPU signature is "AuthenticAMD". - - @retval TRUE The CPU signature matches. - @retval FALSE The CPU signature does not match. - -**/ -BOOLEAN -StandardSignatureIsAuthenticAMD ( - VOID - ) -{ - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - - AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); - return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && - RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && - RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); -} - /** Determine if the CPU supports the Local APIC Base Address MSR. =20 diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index d0f92b33dc8c..cdcbca046191 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -5,7 +5,7 @@ which have xAPIC and x2APIC modes. =20 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
- Copyright (c) 2017, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -22,33 +22,12 @@ #include #include #include +#include =20 // // Library internal functions // =20 -/** - Determine if the standard CPU signature is "AuthenticAMD". - - @retval TRUE The CPU signature matches. - @retval FALSE The CPU signature does not match. - -**/ -BOOLEAN -StandardSignatureIsAuthenticAMD ( - VOID - ) -{ - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - - AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); - return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && - RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && - RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); -} - /** Determine if the CPU supports the Local APIC Base Address MSR. =20 diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index ab7a8ed6633a..9b0660a5d4ea 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -13,29 +13,6 @@ EFI_GUID mCpuInitMpLibHobGuid =3D CPU_INIT_MP_LIB_HOB_GUID; =20 =20 -/** - Determine if the standard CPU signature is "AuthenticAMD". - - @retval TRUE The CPU signature matches. - @retval FALSE The CPU signature does not match. - -**/ -STATIC -BOOLEAN -StandardSignatureIsAuthenticAMD ( - VOID - ) -{ - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - - AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); - return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && - RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && - RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); -} - /** The function will check if BSP Execute Disable is enabled. =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,garrett.kirkendall@amd.com X-Gm-Message-State: HJoZveAjyySUK8NEk4G8jxAKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592831929; bh=9MM9U6Xjs2OeDXJjpFDaiFUrxyhmlcnku8UbL/n3tA4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=LprjsjTbLaTF6/23FULvvZDp8f2IIClcfCRRmSQEDH3xIGRC+sTNIUCltXQDA11oZlH i9AK6sSPWaTN2K21feihAs8rv7tcrvIXJfXCRpyWEDtyEMOvxbnVNGQ/huZcY1S9aSzvc 0Xi0U0y7wZYGB8v1zkTMNC78oBKWJQxoxrk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" AMD does not support MSR_IA32_MISC_ENABLE. Accessing that register causes and exception on AMD processors. If Execution Disable is supported, but if the processor is an AMD processor, skip manipulating MSR_IA32_MISC_ENABLE[34] XD Disable bit. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Garrett Kirkendall Reviewed-by: Chasel Chiu Reviewed-by: Eric Dong Reviewed-by: Laszlo Ersek Tested-by: Laszlo Ersek --- Notes: Tested on Intel hardware with Laszlo Ersek's help =20 (1) downloaded two Linux images from provided links. (2) Test using a 32-bit guest on an Intel host (standing in your edk2 t= ree, with the patches applied): =20 $ build -a IA32 -b DEBUG -p OvmfPkg/OvmfPkgIa32.dsc -t GCC5 -D SMM_REQU= IRE =20 $ qemu-system-i386 \ -cpu coreduo,-nx \ -machine q35,smm=3Don,accel=3Dkvm \ -m 4096 \ -smp 4 \ -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ -drive if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild= /OvmfIa32/DEBUG_GCC5/FV/OVMF_CODE.fd \ -drive if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild= /OvmfIa32/DEBUG_GCC5/FV/OVMF_VARS.fd \ -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfedor= a-30-efi-systemd-i686.qcow2 \ -device virtio-scsi-pci,id=3Dscsi0 \ -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 =20 (Once you get a login prompt, feel free to interrupt QEMU with Ctrl-C.) =20 (3) Test using a 64-bit guest on an Intel host: =20 $ build -a IA32 -a X64 -b DEBUG -p OvmfPkg/OvmfPkgIa32X64.dsc -t GCC5 -= D SMM_REQUIRE =20 $ qemu-system-x86_64 \ -cpu host \ -machine q35,smm=3Don,accel=3Dkvm \ -m 4096 \ -smp 4 \ -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ -drive if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild= /Ovmf3264/DEBUG_GCC5/FV/OVMF_CODE.fd \ -drive if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild= /Ovmf3264/DEBUG_GCC5/FV/OVMF_VARS.fd \ -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfedor= a-31-efi-grub2-x86_64.qcow2 \ -device virtio-scsi-pci,id=3Dscsi0 \ -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 =20 Tested on real AMD Hardware UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 3 +++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 9 ++++++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 19 +++++++++++++++++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 20 ++++++++++++++++++-- 4 files changed, 46 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/Pi= SmmCpuDxeSmm/SmmProfileInternal.h index 43f6935cf9dc..993360a8a8c1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -2,6 +2,7 @@ SMM profile internal header file. =20 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2020, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -13,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include =20 #include "SmmProfileArch.h" @@ -99,6 +101,7 @@ extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; extern UINTN gSmiExceptionHandlers[]; extern BOOLEAN mXdSupported; X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; +X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported; extern UINTN *mPFEntryCount; extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUN= T]; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index c47b5573e366..d7ed9ab7a770 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -2,7 +2,7 @@ Enable SMM profile. =20 Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
-Copyright (c) 2017, AMD Incorporated. All rights reserved.
+Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1015,6 +1015,13 @@ CheckFeatureSupported ( mXdSupported =3D FALSE; PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1); } + + if (StandardSignatureIsAuthenticAMD ()) { + // + // AMD processors do not support MSR_IA32_MISC_ENABLE + // + PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1); + } } =20 if (mBtsSupported) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index f96de9bdeb43..167f5e14dbd4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -59,6 +60,7 @@ global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) +global ASM_PFX(gPatchMsrIa32MiscEnableSupported) extern ASM_PFX(gSmiHandlerIdtr) =20 extern ASM_PFX(mCetSupported) @@ -153,17 +155,30 @@ ASM_PFX(gPatchSmiCr3): ASM_PFX(gPatchXdSupported): cmp al, 0 jz @SkipXd + +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit + mov al, strict byte 1 ; source operand may be patched +ASM_PFX(gPatchMsrIa32MiscEnableSupported): + cmp al, 1 + jz MsrIa32MiscEnableSupported + +; MSR_IA32_MISC_ENABLE not supported + xor edx, edx + push edx ; don't try to restore the XD Disa= ble bit just before RSM + jmp EnableNxe + ; ; Check XD disable bit ; +MsrIa32MiscEnableSupported: mov ecx, MSR_IA32_MISC_ENABLE rdmsr push edx ; save MSR_IA32_MISC_ENABLE[63-32] test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] - jz .5 + jz EnableNxe and dx, 0xFFFB ; clear XD Disable bit if it is set wrmsr -.5: +EnableNxe: mov ecx, MSR_EFER rdmsr or ax, MSR_EFER_XD ; enable NXE diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index 8bfba55b5d08..0e154e5db949 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -67,6 +68,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) +global ASM_PFX(gPatchMsrIa32MiscEnableSupported) global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmiCr3) global ASM_PFX(gPatch5LevelPagingNeeded) @@ -152,18 +154,32 @@ SkipEnable5LevelPaging: ASM_PFX(gPatchXdSupported): cmp al, 0 jz @SkipXd + +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit + mov al, strict byte 1 ; source operand may be patched +ASM_PFX(gPatchMsrIa32MiscEnableSupported): + cmp al, 1 + jz MsrIa32MiscEnableSupported + +; MSR_IA32_MISC_ENABLE not supported + sub esp, 4 + xor rdx, rdx + push rdx ; don't try to restore the XD Disa= ble bit just before RSM + jmp EnableNxe + ; ; Check XD disable bit ; +MsrIa32MiscEnableSupported: mov ecx, MSR_IA32_MISC_ENABLE rdmsr sub esp, 4 push rdx ; save MSR_IA32_MISC_ENABLE[63-32] test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] - jz .0 + jz EnableNxe and dx, 0xFFFB ; clear XD Disable bit if it is set wrmsr -.0: +EnableNxe: mov ecx, MSR_EFER rdmsr or ax, MSR_EFER_XD ; enable NXE --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61560): https://edk2.groups.io/g/devel/message/61560 Mute This Topic: https://groups.io/mt/75037839/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-