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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,garrett.kirkendall@amd.com X-Gm-Message-State: qGCyBlEyIKxUzLFA45K85uG7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592493786; bh=UJfWjlJ8yJju4bRJSUhTKSjamWmonsh/7W+m2PDTN7w=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=J1p3QGzNFRjWfc2OxpdhEo6AveOzXcphCDO1S4U7sOdCzgLSDgj5wx3Rj8w2JX70DPV mmLLBhqKfmod4V2bGDJSjSfiL1ETHtvqJz/UJyvVbYAE0ZJQmJWeNFSvqDDsAKWCxiTGu TlHC70rRagooKcki/N93wEo3Ym8hbW5ZN5c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Refactor StandardSignatureIsAuthenticAMD into BaseUefiCpuLib from separate copies in BaseXApicLib, BaseXApicX2ApicLib, and MpInitLib. This allows for future use of StandarSignatureIsAuthinticAMD without creating more instances in other modules. This function allows IA32/X64 code to determine if it is running on an AMD brand processor. UefiCpuLib is already included directly or indirectly in all modified modules. Complete move is made in this change. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Garrett Kirkendall Reviewed-by: Laszlo Ersek Reviewed-by: Eric Dong --- UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 7 ++++ UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf | 2 ++ UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf | 2 ++ UefiCpuPkg/Include/Library/UefiCpuLib.h | 14 ++++++++ UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 38 ++++++++= ++++++++++++ UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 25 ++------= ----- UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 25 ++------= ----- UefiCpuPkg/Library/MpInitLib/MpLib.c | 23 --------= ---- 8 files changed, 67 insertions(+), 69 deletions(-) diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpu= Pkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf index 006b7acbf14e..34d3a7bb4303 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf @@ -4,6 +4,7 @@ # The library routines are UEFI specification compliant. # # Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2020, AMD Inc. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -29,6 +30,12 @@ [Sources.IA32] [Sources.X64] X64/InitializeFpu.nasm =20 +[Sources] + BaseUefiCpuLib.c + [Packages] MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf b/UefiCpuPkg/= Library/BaseXApicLib/BaseXApicLib.inf index bdb2ff372677..561baa44b0e6 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf @@ -5,6 +5,7 @@ # where local APIC is disabled. # # Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2020, AMD Inc. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -37,6 +38,7 @@ [LibraryClasses] TimerLib IoLib PcdLib + UefiCpuLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds ## SOMETIMES= _CONSUMES diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf b= /UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf index ac1e0a1c9896..1e2a4f8b790f 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf @@ -5,6 +5,7 @@ # where local APIC is disabled. # # Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2020, AMD Inc. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -37,6 +38,7 @@ [LibraryClasses] TimerLib IoLib PcdLib + UefiCpuLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds ## SOMETIMES= _CONSUMES diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/L= ibrary/UefiCpuLib.h index 82e53bab3a0f..5326e7246301 100644 --- a/UefiCpuPkg/Include/Library/UefiCpuLib.h +++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h @@ -5,6 +5,7 @@ to be UEFI specification compliant. =20 Copyright (c) 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -29,4 +30,17 @@ InitializeFloatingPointUnits ( VOID ); =20 +/** + Determine if the standard CPU signature is "AuthenticAMD". + + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. + +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ); + #endif diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPk= g/Library/BaseUefiCpuLib/BaseUefiCpuLib.c new file mode 100644 index 000000000000..c2cc3ff9a709 --- /dev/null +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c @@ -0,0 +1,38 @@ +/** @file + This library defines some routines that are generic for IA32 family CPU. + + The library routines are UEFI specification compliant. + + Copyright (c) 2020, AMD Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include +#include + +/** + Determine if the standard CPU signature is "AuthenticAMD". + + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. + +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ) +{ + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && + RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && + RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); +} diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index 33ea15ca2916..52bd90d33428 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -4,7 +4,7 @@ This local APIC library instance supports xAPIC mode only. =20 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
- Copyright (c) 2017, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -21,33 +21,12 @@ #include #include #include +#include =20 // // Library internal functions // =20 -/** - Determine if the standard CPU signature is "AuthenticAMD". - - @retval TRUE The CPU signature matches. - @retval FALSE The CPU signature does not match. - -**/ -BOOLEAN -StandardSignatureIsAuthenticAMD ( - VOID - ) -{ - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - - AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); - return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && - RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && - RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); -} - /** Determine if the CPU supports the Local APIC Base Address MSR. =20 diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index d0f92b33dc8c..cdcbca046191 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -5,7 +5,7 @@ which have xAPIC and x2APIC modes. =20 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
- Copyright (c) 2017, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -22,33 +22,12 @@ #include #include #include +#include =20 // // Library internal functions // =20 -/** - Determine if the standard CPU signature is "AuthenticAMD". - - @retval TRUE The CPU signature matches. - @retval FALSE The CPU signature does not match. - -**/ -BOOLEAN -StandardSignatureIsAuthenticAMD ( - VOID - ) -{ - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - - AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); - return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && - RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && - RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); -} - /** Determine if the CPU supports the Local APIC Base Address MSR. =20 diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index ab7a8ed6633a..9b0660a5d4ea 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -13,29 +13,6 @@ EFI_GUID mCpuInitMpLibHobGuid =3D CPU_INIT_MP_LIB_HOB_GUID; =20 =20 -/** - Determine if the standard CPU signature is "AuthenticAMD". - - @retval TRUE The CPU signature matches. - @retval FALSE The CPU signature does not match. - -**/ -STATIC -BOOLEAN -StandardSignatureIsAuthenticAMD ( - VOID - ) -{ - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - - AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); - return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && - RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && - RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); -} - /** The function will check if BSP Execute Disable is enabled. =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 18 Jun 2020 15:23:03 +0000 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: b5917eb7-f9aa-4877-7cdf-08d8139b7edd X-MS-TrafficTypeDiagnostic: SN1PR12MB2573: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: vGP2Gbe+bWJPvVKm1XHh/1h51hP2P6OOWPsCfvr5kWPcA4WXrbbWkpG7xSCq/CJhII/K3Pen9aa3yNl56astJpwhKFAL0NXc5P4kjNdwYPNAFLOL1WYX5JnKnOVVbONPunmFAuvkzrC6f2AdjhdFSd6f6JNhuT68ZYz8mjyHsRaz/iAYapLcDiZmNdVmwNL6P2EBuCWALJOMFb+R122HEiFnrbPXrOJqBHHze9OjLsNWjfibr/fHIpJZ1eYml4k1/tMaU2rGfIQNAIA/EtsFOVoaWljDL/iR6WUVtbGhQUyzHXdVC/l8KWZSjlOGOcd8oogzSwPpMnp0il7SumGLTw== X-MS-Exchange-AntiSpam-MessageData: fRi078Mi2nu+VSXrGDMdh6XhRsBRilBuV18cnrmyCb2LNOwWh3dcKZMg8xHF1OIqE62wm4E0I37H2u35fJuG2XFrwhh5P6ivl+Ir84hJyF1FbA/AqqYVIZAioY7G3ZxT1BNR5a/W2Fd9ER3BTqJWwgRsmZvP+w7C7d8sBTekPLAOb6J+PKujRYedyynjHBgc0d8DTNQuwr8sBpQjU3yLbVj8bYjxlTblWEwnOiUZqmvJmXwdx9D4OHbgEa8pRtw2PwxNv7MdNcae4zBHoIUSnIbaLLV75d4p0q3p8nXI1xgu635hTQ4BBmM8lYbXVPi3Nbd8N8udvOa9/Ryag0WZhgjhTT0cSkOk5dD9WmJj9cL0kPIZE2gIrR+NsgJmsh1UIMSrh4xS1YABHV9HWUBeO9LztelIKv9K+X2uDxss2YVZLxVZNOCJ6eeFXWb+IZ14AAuOCFTPjS32a9NyEHMjqarI6SDlJhh/fZagn+jt5Gs= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b5917eb7-f9aa-4877-7cdf-08d8139b7edd X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2020 15:23:04.3837 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iBcXgQpi3Ly3vhnC1e9YgENI+22ETdMzwRA66OcTwRAugPfEZwPKxu0jZYF30tWHKZZHbOFaY1z4uQpLZeHqbg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2573 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,garrett.kirkendall@amd.com X-Gm-Message-State: pqsjeOzakQvhuaarj0XBcs4Zx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592493787; bh=Dbe/AXsCRWRkDaEDEQvtyany7WrO9z9cWkfgJzW9kz4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=oKQwlmXUqKJlnSEQ5nplCafqC9k86FGMHbvJhmrV9s3rmSLZ400GRa6pJOaaIn43RjG kilDkKRNOl0zbz78z1jHRBcYSNu9aYvNbXN8jFfI14edht0Q2/br0TM3NsUJrMUN0b0hE Zz/Qr8VKYs5bOJxKjE1b42uuV2XeUC9UmIQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" AMD does not support MSR_IA32_MISC_ENABLE. Accessing that register causes and exception on AMD processors. If Execution Disable is supported, but if the processor is an AMD processor, skip manipulating MSR_IA32_MISC_ENABLE[34] XD Disable bit. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Garrett Kirkendall Reviewed-by: Laszlo Ersek --- Notes: Tested on Intel hardware with Laszlo Ersek's help =20 (1) downloaded two Linux images from provided links. (2) Test using a 32-bit guest on an Intel host (standing in your edk2 t= ree, with the patches applied): =20 $ build -a IA32 -b DEBUG -p OvmfPkg/OvmfPkgIa32.dsc -t GCC5 -D SMM_REQU= IRE =20 $ qemu-system-i386 \ -cpu coreduo,-nx \ -machine q35,smm=3Don,accel=3Dkvm \ -m 4096 \ -smp 4 \ -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ -drive if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild= /OvmfIa32/DEBUG_GCC5/FV/OVMF_CODE.fd \ -drive if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild= /OvmfIa32/DEBUG_GCC5/FV/OVMF_VARS.fd \ -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfedor= a-30-efi-systemd-i686.qcow2 \ -device virtio-scsi-pci,id=3Dscsi0 \ -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 =20 (Once you get a login prompt, feel free to interrupt QEMU with Ctrl-C.) =20 (3) Test using a 64-bit guest on an Intel host: =20 $ build -a IA32 -a X64 -b DEBUG -p OvmfPkg/OvmfPkgIa32X64.dsc -t GCC5 -= D SMM_REQUIRE =20 $ qemu-system-x86_64 \ -cpu host \ -machine q35,smm=3Don,accel=3Dkvm \ -m 4096 \ -smp 4 \ -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ -drive if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild= /Ovmf3264/DEBUG_GCC5/FV/OVMF_CODE.fd \ -drive if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild= /Ovmf3264/DEBUG_GCC5/FV/OVMF_VARS.fd \ -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfedor= a-31-efi-grub2-x86_64.qcow2 \ -device virtio-scsi-pci,id=3Dscsi0 \ -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 =20 Tested on real AMD Hardware UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 3 +++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 9 ++++++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 19 +++++++++++++++++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 20 ++++++++++++++++++-- 4 files changed, 46 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/Pi= SmmCpuDxeSmm/SmmProfileInternal.h index 43f6935cf9dc..993360a8a8c1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -2,6 +2,7 @@ SMM profile internal header file. =20 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2020, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -13,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include =20 #include "SmmProfileArch.h" @@ -99,6 +101,7 @@ extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; extern UINTN gSmiExceptionHandlers[]; extern BOOLEAN mXdSupported; X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; +X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported; extern UINTN *mPFEntryCount; extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUN= T]; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index c47b5573e366..d7ed9ab7a770 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -2,7 +2,7 @@ Enable SMM profile. =20 Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
-Copyright (c) 2017, AMD Incorporated. All rights reserved.
+Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1015,6 +1015,13 @@ CheckFeatureSupported ( mXdSupported =3D FALSE; PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1); } + + if (StandardSignatureIsAuthenticAMD ()) { + // + // AMD processors do not support MSR_IA32_MISC_ENABLE + // + PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1); + } } =20 if (mBtsSupported) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index f96de9bdeb43..167f5e14dbd4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -59,6 +60,7 @@ global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) +global ASM_PFX(gPatchMsrIa32MiscEnableSupported) extern ASM_PFX(gSmiHandlerIdtr) =20 extern ASM_PFX(mCetSupported) @@ -153,17 +155,30 @@ ASM_PFX(gPatchSmiCr3): ASM_PFX(gPatchXdSupported): cmp al, 0 jz @SkipXd + +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit + mov al, strict byte 1 ; source operand may be patched +ASM_PFX(gPatchMsrIa32MiscEnableSupported): + cmp al, 1 + jz MsrIa32MiscEnableSupported + +; MSR_IA32_MISC_ENABLE not supported + xor edx, edx + push edx ; don't try to restore the XD Disa= ble bit just before RSM + jmp EnableNxe + ; ; Check XD disable bit ; +MsrIa32MiscEnableSupported: mov ecx, MSR_IA32_MISC_ENABLE rdmsr push edx ; save MSR_IA32_MISC_ENABLE[63-32] test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] - jz .5 + jz EnableNxe and dx, 0xFFFB ; clear XD Disable bit if it is set wrmsr -.5: +EnableNxe: mov ecx, MSR_EFER rdmsr or ax, MSR_EFER_XD ; enable NXE diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index 8bfba55b5d08..0e154e5db949 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -67,6 +68,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) +global ASM_PFX(gPatchMsrIa32MiscEnableSupported) global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmiCr3) global ASM_PFX(gPatch5LevelPagingNeeded) @@ -152,18 +154,32 @@ SkipEnable5LevelPaging: ASM_PFX(gPatchXdSupported): cmp al, 0 jz @SkipXd + +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit + mov al, strict byte 1 ; source operand may be patched +ASM_PFX(gPatchMsrIa32MiscEnableSupported): + cmp al, 1 + jz MsrIa32MiscEnableSupported + +; MSR_IA32_MISC_ENABLE not supported + sub esp, 4 + xor rdx, rdx + push rdx ; don't try to restore the XD Disa= ble bit just before RSM + jmp EnableNxe + ; ; Check XD disable bit ; +MsrIa32MiscEnableSupported: mov ecx, MSR_IA32_MISC_ENABLE rdmsr sub esp, 4 push rdx ; save MSR_IA32_MISC_ENABLE[63-32] test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] - jz .0 + jz EnableNxe and dx, 0xFFFB ; clear XD Disable bit if it is set wrmsr -.0: +EnableNxe: mov ecx, MSR_EFER rdmsr or ax, MSR_EFER_XD ; enable NXE --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61499): https://edk2.groups.io/g/devel/message/61499 Mute This Topic: https://groups.io/mt/74960777/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-