From nobody Sat Apr 27 01:26:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+61484+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61484+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1592486906; cv=none; d=zohomail.com; s=zohoarc; b=L0CnAnzjuNtpYtu1/8fbwKOsSFZkxn/+SrNrPjcuaMBOufRcv0VOTwO82kpsloe0gIS7iyKalbI8qbBpbDyBLh7Y+0rb1PGPl4aNfycjy5gWYffmcBJHm4Od1BJ1YUr8+rMtp/GmYGvvhtPb1RKmYuszWWJJgzedVqWvtUnOUAg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592486906; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=8+VVq+9jgZ1WSVfcwyfZ+mQPlamdpwI07xu9cF1t3xI=; b=WzZOCBzyhw1WK0r7npamyn0bHSb6Y1aBU4tx+pQJh6xwHGjwAbfAy7qXI0ihYQ+HhoR/fdhqaNLCRmFEOdmj37j89N6/zvWOaQ2CPnqPmeRRMbCdqJw95K6M48mqiZIDaWECWqIoaTC19gZ5776JB5ME1kY/K5URgA4f4Yz2tFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61484+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1592486906320675.8754716321012; Thu, 18 Jun 2020 06:28:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cA9OYY1788612xxCHee1MV4T; Thu, 18 Jun 2020 06:28:25 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.7476.1592486904777453868 for ; Thu, 18 Jun 2020 06:28:24 -0700 IronPort-SDR: AKe+a3pnC248PJDWADOedLnuU94N61wtD8JjLrEbfcJbaYSqMTN5J7016fsBpTrpHX2lY/M0H3 XeXb8Msh3lVA== X-IronPort-AV: E=McAfee;i="6000,8403,9655"; a="140910907" X-IronPort-AV: E=Sophos;i="5.73,526,1583222400"; d="scan'208";a="140910907" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2020 06:28:10 -0700 IronPort-SDR: PNYDxZH07LeuNITaBDk0+84lwIpn7T2d0+C95JcMuNq8JAM5qMS385L8nw5QkbRpty17+E3AFx kRMM8kbwA9cA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,526,1583222400"; d="scan'208";a="477193864" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.252.130.131]) by fmsmga006.fm.intel.com with ESMTP; 18 Jun 2020 06:28:07 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Maurice Ma , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH v2 1/2] IntelFsp2Pkg: Add FSP*_ARCH_UPD. Date: Thu, 18 Jun 2020 21:27:43 +0800 Message-Id: <20200618132744.12856-2-chasel.chiu@intel.com> In-Reply-To: <20200618132744.12856-1-chasel.chiu@intel.com> References: <20200618132744.12856-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: sQarViML2y9KLsoDOcji5gTfx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592486905; bh=c6sk49pii78xvMv4w/CnTbWka9l/D7AT/5D+P2fnDU8=; h=Cc:Date:From:Reply-To:Subject:To; b=mOWS2uypbe3QeykjVT2Z/+scf5fWiabMlwUGgwREOOaFFcLURNBEznLfUJajo9qd75X yFwyvFm7LsZ8SfygnqbpmMVQAC9bLIyu/PSmfhiMwLLVnIaqhgfnnbWbSOfLKCEK1zZAR 92CAe+b8kGJG9+qU5nzrNQ/32APKgUuaHa0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2781 Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events and multi-phase silicon initialization. For backward compatibility the original structures are kept and new ARCH_UPD structures will be included only when UPD header revision equal or greater than 2. GenCfgOpt script also updated to prevent from generating duplicate FSPT_ARCH_UPD and FSPS_ARCH_UPD typedef structures. Cc: Maurice Ma Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 78 ++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++----- IntelFsp2Pkg/Include/FspEas/FspApi.h | 81 ++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- IntelFsp2Pkg/Tools/GenCfgOpt.py | 6 +++--- 3 files changed, 156 insertions(+), 9 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index e354870a1d..7934eab6d7 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -1,7 +1,7 @@ ;; @file ; Provide FSP API entry points. ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ;; =20 @@ -78,6 +78,23 @@ struc LoadMicrocodeParams .size: endstruc =20 +struc LoadMicrocodeParamsFsp22 + ; FSP_UPD_HEADER { + .FspUpdHeaderSignature: resd 2 + .FspUpdHeaderRevision: resb 1 + .FspUpdHeaderReserved: resb 23 + ; } + ; FSPT_ARCH_UPD{ + .FsptArchUpd: resd 8 + ; } + ; FSPT_CORE_UPD { + .MicrocodeCodeAddr: resd 1 + .MicrocodeCodeSize: resd 1 + .CodeRegionBase: resd 1 + .CodeRegionSize: resd 1 + ; } + .size: +endstruc =20 ; ; Define SSE macros @@ -169,6 +186,11 @@ ASM_PFX(LoadMicrocodeDefault): =20 ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k + ; first check UPD header revision + cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 + jae Fsp22UpdHeader + + ; UPD structure is compliant with FSP spec 2.0/2.1 mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize] cmp eax, 0 jz Exit2 @@ -178,6 +200,19 @@ ASM_PFX(LoadMicrocodeDefault): mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr] cmp esi, 0 jnz CheckMainHeader + jmp ParamError + +Fsp22UpdHeader: + ; UPD structure is compliant with FSP spec 2.2 + mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] + cmp eax, 0 + jz Exit2 + cmp eax, 0800h + jl ParamError + + mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] + cmp esi, 0 + jnz CheckMainHeader =20 ParamError: mov eax, 080000002h @@ -276,6 +311,11 @@ CheckAddress: cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh jz Done =20 + ; Check UPD header revision + cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 + jae Fsp22UpdHeader1 + + ; UPD structure is compliant with FSP spec 2.0/2.1 ; Is automatic size detection ? mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize] cmp eax, 0ffffffffh @@ -287,6 +327,19 @@ CheckAddress: jae Done ;Jif address is outside of microcode region jmp CheckMainHeader =20 +Fsp22UpdHeader1: + ; UPD structure is compliant with FSP spec 2.2 + ; Is automatic size detection ? + mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] + cmp eax, 0ffffffffh + jz LoadMicrocodeDefault4 + + ; Address >=3D microcode region address + microcode region size? + add eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] + cmp esi, eax + jae Done ;Jif address is outside of microcode region + jmp CheckMainHeader + LoadMicrocodeDefault4: LoadCheck: ; Get the revision of the current microcode update loaded @@ -349,11 +402,26 @@ ASM_PFX(EstablishStackFsp): =20 push DATA_LEN_OF_MCUD ; Size of the data region push 4455434Dh ; Signature of the data region 'MCUD' - push dword [edx + 2Ch] ; Code size sizeof(FSPT_UPD_COMMON)= + 12 - push dword [edx + 28h] ; Code base sizeof(FSPT_UPD_COMMON)= + 8 - push dword [edx + 24h] ; Microcode size sizeof(FSPT_UPD_COMMON)= + 4 - push dword [edx + 20h] ; Microcode base sizeof(FSPT_UPD_COMMON)= + 0 =20 + ; check UPD structure revision (edx + 8) + cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 + jae Fsp22UpdHeader2 + + ; UPD structure is compliant with FSP spec 2.0/2.1 + push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code si= ze sizeof(FSPT_UPD_COMMON) + 12 + push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code ba= se sizeof(FSPT_UPD_COMMON) + 8 + push dword [edx + LoadMicrocodeParams.MicrocodeCodeSize] ; Microco= de size sizeof(FSPT_UPD_COMMON) + 4 + push dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr] ; Microco= de base sizeof(FSPT_UPD_COMMON) + 0 + jmp ContinueAfterUpdPush + +Fsp22UpdHeader2: + ; UPD structure is compliant with FSP spec 2.2 + push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize] ; Co= de size sizeof(FSPT_UPD_COMMON) + 12 + push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Co= de base sizeof(FSPT_UPD_COMMON) + 8 + push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Mi= crocode size sizeof(FSPT_UPD_COMMON) + 4 + push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Mi= crocode base sizeof(FSPT_UPD_COMMON) + 0 + +ContinueAfterUpdPush: ; ; Save API entry/exit timestamp into stack ; diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index ed40f9538c..5e488c452a 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -99,13 +99,36 @@ typedef struct { /// UINT64 Signature; /// - /// Revision of the Data structure. For FSP v2.0 value is 1. + /// Revision of the Data structure. + /// For FSP spec 2.0/2.1 value is 1. + /// For FSP spec 2.2 value is 2. /// UINT8 Revision; UINT8 Reserved[23]; } FSP_UPD_HEADER; =20 /// +/// FSPT_ARCH_UPD Configuration. +/// +typedef struct { + /// + /// Revision Revision of the structure is 1 for this version of the spec= ification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length Length of the structure in bytes. The current value for this = field is 32. + /// + UINT32 Length; + /// + /// FspDebugHandler Optional debug handler for the bootloader to receive= debug messages + /// occurring during FSP execution. + /// + FSP_DEBUG_HANDLER FspDebugHandler; + UINT8 Reserved1[20]; +} FSPT_ARCH_UPD; + +/// /// FSPM_ARCH_UPD Configuration. /// typedef struct { @@ -146,6 +169,32 @@ typedef struct { UINT8 Reserved1[4]; } FSPM_ARCH_UPD; =20 +typedef struct { + /// + /// Revision Revision of the structure is 1 for this version of the spec= ification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length Length of the structure in bytes. The current value for this = field is 32. + /// + UINT32 Length; + /// + /// FspEventHandler Optional event handler for the bootloader to be info= rmed of events + /// occurring during FSP execution. + /// + FSP_EVENT_HANDLER FspEventHandler; + /// + /// A FSP binary may optionally implement multi-phase silicon initializa= tion, + /// This is only supported if the FspMultiPhaseSiInitEntryOffset field i= n FSP_INFO_HEADER + /// is non-zero. + /// To enable multi-phase silicon initialization, the bootloader must set + /// EnableMultiPhaseSiliconInit to a non-zero value. + /// + UINT8 EnableMultiPhaseSiliconInit; + UINT8 Reserved1[19]; +} FSPS_ARCH_UPD; + /// /// FSPT_UPD_COMMON Configuration. /// @@ -157,6 +206,21 @@ typedef struct { } FSPT_UPD_COMMON; =20 /// +/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPT_ARCH_UPD Configuration. + /// + FSPT_ARCH_UPD FsptArchUpd; +} FSPT_UPD_COMMON_FSP22; + +/// /// FSPM_UPD_COMMON Configuration. /// typedef struct { @@ -181,6 +245,21 @@ typedef struct { } FSPS_UPD_COMMON; =20 /// +/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPS_ARCH_UPD Configuration. + /// + FSPS_ARCH_UPD FspsArchUpd; +} FSPS_UPD_COMMON_FSP22; + +/// /// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE. /// typedef enum { diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt= .py index d1d6901bc3..e6c15108f5 100644 --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py @@ -1175,7 +1175,7 @@ EndList UpdRegionCheck =3D ['FSPT', 'FSPM', 'FSPS'] # FSPX_UPD_REGION UpdConfigCheck =3D ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FS= P_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG UpdSignatureCheck =3D ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE',= 'FSPS_UPD_SIGNATURE'] - ExcludedSpecificUpd =3D 'FSPM_ARCH_UPD' + ExcludedSpecificUpd =3D ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_A= RCH_UPD'] =20 if InputHeaderFile !=3D '': if not os.path.exists(InputHeaderFile): @@ -1229,7 +1229,7 @@ EndList if Match: StartIndex =3D Index - 1 Match =3D re.match("}\s([_A-Z0-9]+);", Line) - if Match and (UpdRegionCheck[item] in Match.group(1) or Up= dConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd not in Match= .group(1)): + if Match and (UpdRegionCheck[item] in Match.group(1) or Up= dConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd[item] not in= Match.group(1)): EndIndex =3D Index StructStart.append(StartIndex) StructEnd.append(EndIndex) @@ -1466,7 +1466,7 @@ EndList =20 =20 def Usage(): - print ("GenCfgOpt Version 0.54") + print ("GenCfgOpt Version 0.55") print ("Usage:") print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir = [-D Macros]") print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile = [-D Macros]") --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61484): https://edk2.groups.io/g/devel/message/61484 Mute This Topic: https://groups.io/mt/74958113/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 01:26:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+61485+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61485+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1592486907; cv=none; d=zohomail.com; s=zohoarc; b=CEOJ0lLT0FTcF18zq3NQsThWnCmfkMFrMxLhNEC6kbGn3rzX+klh4L4DqV0MviTChQ29u1HBvlEG+/9LPvr+n9ePLTZBQ7T8abKdv9EQ30XCI885uX63Se0j7CDQLBWPoeSKEbI6zbhGaR59MY9X7SKOckl6kD4nq2kGXowM2f4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1592486907; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=wynbR+OyuhfNLcYRr1RbvSWWR7Gjc3I3Ic0wwMX1WqA=; b=iNPibmr8EZi4U/AwuhqijsVTip068hPl/4qPkkVKCK7/Dl5JVcHylk+GaRQZv4ufgx65SJ+jnkOmqYoLixRM/pNz6HyOaruDHhtKvprF16+6WOSvTCR8FQJFNE6Or/Yi7UQlTcRm+FoHe7xK5NtVQm6GdKripiH8h61f7+4q4QE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+61485+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1592486906896190.66536138731044; Thu, 18 Jun 2020 06:28:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id z5XYYY1788612xkhpqTC5RVs; Thu, 18 Jun 2020 06:28:26 -0700 X-Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web12.7476.1592486904777453868 for ; Thu, 18 Jun 2020 06:28:25 -0700 IronPort-SDR: sCp56zKg3INDmNizNe4R8kDwsgQhifaLOeQ27xaEtryDYpQMrZaXAYw6ONrMSjicgJxtoCocqi qoOvu4N4OKkg== X-IronPort-AV: E=McAfee;i="6000,8403,9655"; a="140910918" X-IronPort-AV: E=Sophos;i="5.73,526,1583222400"; d="scan'208";a="140910918" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2020 06:28:11 -0700 IronPort-SDR: XmuF0XucM4P31OPXp62dJXDu/FfSSR0zs8XByhP1z+xOgwz5I/641RiTfjc2LgUV3ecUK055V3 JCl2WQSlNtqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,526,1583222400"; d="scan'208";a="477193869" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.252.130.131]) by fmsmga006.fm.intel.com with ESMTP; 18 Jun 2020 06:28:10 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Maurice Ma , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH v2 2/2] IntelFsp2WrapperPkg: Add FSP*_ARCH_UPD. Date: Thu, 18 Jun 2020 21:27:44 +0800 Message-Id: <20200618132744.12856-3-chasel.chiu@intel.com> In-Reply-To: <20200618132744.12856-1-chasel.chiu@intel.com> References: <20200618132744.12856-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: jns7ib93ZnmrBcoeu6OMG8c4x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592486906; bh=0pF0iBTq0WZrzmGEioW/XdOVGcoQZ1prZtc8bpF7RI8=; h=Cc:Date:From:Reply-To:Subject:To; b=Mgbxads6zcPGM5lVzHxqZ/WvQRqjKLxgKv1A8s+2vvGdm1LC5mIEWvNbz3VeH046sCL Ls0oPDBgZF913UVnKJx/Mokysz3bv2FIHs2h821aPcXlxrJGftLiJ2D7G3C55QlM1pZ2T s/PvkF/ynUM9XF7Yf/hkeu3nQKIrntNC/JM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2781 Provides sample code to include FSPT_ARCH_UPD initial values with UPD header revision set to 2. Cc: Maurice Ma Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitDa= ta.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecRamInitData.c b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibS= ample/SecRamInitData.c index 2d1368c3ed..96b47e23da 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c @@ -1,7 +1,7 @@ /** @file Sample to provide TempRamInitParams data. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -18,17 +18,39 @@ typedef struct { =20 typedef struct { FSP_UPD_HEADER FspUpdHeader; + // + // If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD struct= ure. + // + FSPT_ARCH_UPD FsptArchUpd; FSPT_CORE_UPD FsptCoreUpd; } FSPT_UPD_CORE_DATA; =20 GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr =3D { { 0x4450555F54505346, - 0x00, + // + // UPD header revision must be equal or greater than 2 when the struct= ure is compliant with FSP spec 2.2. + // + 0x02, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + // + // If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD struct= ure. + // + { + 0x01, + { + 0x00, 0x00, 0x00 + }, + 0x00000020, + 0x00000000, + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }, { ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (= PcdFlashMicrocodeOffset)), ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet3= 2 (PcdFlashMicrocodeOffset)), --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61485): https://edk2.groups.io/g/devel/message/61485 Mute This Topic: https://groups.io/mt/74958115/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-