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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,garrett.kirkendall@amd.com X-Gm-Message-State: T5O81qoe9MyxVSf0PCzIozVNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1592245854; bh=CgqAHgd0gpUSEqMPMylWWZZRyhNSGjFfGZ6YWWy+hi4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ekSnBNA9tsT/x6b1snPtP4rQxyccAojj6SNlo4Cgml3nb6O3JvmYZwFgkC/lA9Vim5i De5g9ZMI4oRPlrj/VHRYQWuFcAIpexBAN/wYRd3S4/vq9LfYAg0tSUBGqHMBjnXfpqnp6 1481e+zu68s5S7fHjc/LumWoHPVIcT6ndYA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" AMD does not support MSR_IA32_MISC_ENABLE. Accessing that register causes and exception on AMD processors. If Execution Disable is supported, and if the processor is an AMD processor skip manipulating MSR_IA32_MISC_ENABLE[34] XD Disable bit. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Garrett Kirkendall --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 3 +++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 9 ++++++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 19 +++++++++++++++++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 20 ++++++++++++++++++-- 4 files changed, 46 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/Pi= SmmCpuDxeSmm/SmmProfileInternal.h index 43f6935cf9dc..0f6e0c9c98ad 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -2,6 +2,7 @@ SMM profile internal header file. =20 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2020, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -13,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include =20 #include "SmmProfileArch.h" @@ -99,6 +101,7 @@ extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; extern UINTN gSmiExceptionHandlers[]; extern BOOLEAN mXdSupported; X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; +X86_ASSEMBLY_PATCH_LABEL gPatchMsrIA32MiscEnableSupported; extern UINTN *mPFEntryCount; extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUN= T]; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index c47b5573e366..146600e6c3b4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -2,7 +2,7 @@ Enable SMM profile. =20 Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
-Copyright (c) 2017, AMD Incorporated. All rights reserved.
+Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1015,6 +1015,13 @@ CheckFeatureSupported ( mXdSupported =3D FALSE; PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1); } + + if (StandardSignatureIsAuthenticAMD()) { + // + // AMD processors do not support MSR_IA32_MISC_ENABLE + // + PatchInstructionX86 (gPatchMsrIA32MiscEnableSupported, FALSE, 1); + } } =20 if (mBtsSupported) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index f96de9bdeb43..e4ef5899f274 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -59,6 +60,7 @@ global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) +global ASM_PFX(gPatchMsrIA32MiscEnableSupported) extern ASM_PFX(gSmiHandlerIdtr) =20 extern ASM_PFX(mCetSupported) @@ -153,17 +155,30 @@ ASM_PFX(gPatchSmiCr3): ASM_PFX(gPatchXdSupported): cmp al, 0 jz @SkipXd + +; Clear XD Disable bit if supported + mov al, strict byte 1 ; source operand may be patched +ASM_PFX(gPatchMsrIA32MiscEnableSupported): + cmp al, 1 + jz MsrIA32MiscEnableSupported + +; MSR_IA32_MISC_ENABLE not supported + xor edx, edx + push edx + jmp EnableNxe + ; ; Check XD disable bit ; +MsrIA32MiscEnableSupported: mov ecx, MSR_IA32_MISC_ENABLE rdmsr push edx ; save MSR_IA32_MISC_ENABLE[63-32] test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] - jz .5 + jz EnableNxe and dx, 0xFFFB ; clear XD Disable bit if it is set wrmsr -.5: +EnableNxe: mov ecx, MSR_EFER rdmsr or ax, MSR_EFER_XD ; enable NXE diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index 8bfba55b5d08..5a4678c7aa63 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -67,6 +68,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) +global ASM_PFX(gPatchMsrIA32MiscEnableSupported) global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmiCr3) global ASM_PFX(gPatch5LevelPagingNeeded) @@ -152,18 +154,32 @@ SkipEnable5LevelPaging: ASM_PFX(gPatchXdSupported): cmp al, 0 jz @SkipXd + +; Clear XD Disable bit if supported + mov al, strict byte 1 ; source operand may be patched +ASM_PFX(gPatchMsrIA32MiscEnableSupported): + cmp al, 1 + jz MsrIA32MiscEnableSupported + +; MSR_IA32_MISC_ENABLE not supported + sub esp, 4 + xor rdx, rdx + push rdx + jmp EnableNxe + ; ; Check XD disable bit ; +MsrIA32MiscEnableSupported: mov ecx, MSR_IA32_MISC_ENABLE rdmsr sub esp, 4 push rdx ; save MSR_IA32_MISC_ENABLE[63-32] test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] - jz .0 + jz EnableNxe and dx, 0xFFFB ; clear XD Disable bit if it is set wrmsr -.0: +EnableNxe: mov ecx, MSR_EFER rdmsr or ax, MSR_EFER_XD ; enable NXE --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#61307): https://edk2.groups.io/g/devel/message/61307 Mute This Topic: https://groups.io/mt/74901070/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-