From nobody Sun May 5 02:26:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+60551+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60551+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1591055375; cv=none; d=zohomail.com; s=zohoarc; b=SCjjWMeo80Lf/Yqs0mHQfhA4XEbEUJbLTJK7kxvYCYdrG3vfW+IbRLE9CLB3lDSkiY7EvY8Z05Z+KBI33gV4t11FvNzqZGHhhJU8KnnXcRzzpJOqRPFvlsOkNR6vCbNtgL/ifomnklPFw+sFhd+AafJGKH2jGq3fPLh2b59Y2hc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591055375; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=AuLIi5GBhmZW/K6COR1sZ80IlzYh6YxJEaOGayPkZFM=; b=DhgrHLlGB5m+O1XtgE8v25H//tXWiQXKNKeMDDqRRaPYa3ixCXGUWePCiIhpIhpmrOE2DUj97WMVRusoddMT7Sq1vSyKlfTpRhigK9qg+Sme2vKIfQ/9FV8uwcNQclRgx66x8JNdGOPLbvrLuMTWXKIIs8h3qNnV5TUF8EycwWg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+60551+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 159105537540979.28331493860333; Mon, 1 Jun 2020 16:49:35 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id WczIYY1788612xHCMFUmzcDS; Mon, 01 Jun 2020 16:49:35 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web10.1876.1591055374297572877 for ; Mon, 01 Jun 2020 16:49:34 -0700 IronPort-SDR: r70WP85xgzGWs2ZCQImFbHNfKfgo2c2Btt7FHnDuZOXUjLsXf3jNwpudSwgFpsX9Xa6bm922GV l0+ZmlhW2vpg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2020 16:49:33 -0700 IronPort-SDR: xlz+Y96kZTOG2dgDUMBvq/lyORQN2lCAUHDrkrLjjNu6O0XvO4VYomkynvqmZO0uXQnY15l+R4 x9xo7X5WosVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,462,1583222400"; d="scan'208";a="347213748" X-Received: from iwenevel-dev01.amr.corp.intel.com ([10.9.70.66]) by orsmga001.jf.intel.com with ESMTP; 01 Jun 2020 16:49:33 -0700 From: "Evelyn Wang" To: devel@edk2.groups.io Cc: Jenny Huang , More Shih , Ray Ni , Rangasai V Chaganty , Jiewen Yao , W Sheng Subject: [edk2-devel] [PATCH] IntelSiliconPkg-Vtd: Set all IOMMU PMR to same range Date: Mon, 1 Jun 2020 16:49:25 -0700 Message-Id: <20200601234925.11108-1-iwen.evelyn.wang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,iwen.evelyn.wang@intel.com X-Gm-Message-State: i5gUCPSwnnt9HKXVsYufGtIFx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1591055375; bh=r6q3VEEXYFZPqt/S417xIT+YS4s00Xqw7r238NonF7o=; h=Cc:Date:From:Reply-To:Subject:To; b=qav1OIlchrnRaXJVPAy2FUspjqKDCEebD1NVb4tDePYTE4yV8n5lgwD0GRXX3Lu3xZJ GF/DsMhsR3jQNDJXVt9s8XIdY1IeP3nbnOsK8nyqundr9NxQ3sfKYU6ibedqI8nAJRTF6 dvw6Sb3x9aDWOsYenMdpAdQCwKjrY5hpPH0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2775 Signed-off-by: Evelyn Wang Cc: Jenny Huang Cc: More Shih Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jiewen Yao Cc: W Sheng --- .../Feature/VTd/IntelVTdPmrPei/DmarTable.c | 38 +++++++++++++++---= ---- 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarT= able.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable= .c index d920d136f1..fd64051032 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -13,7 +13,7 @@ #include #include #include - +#include #include "IntelVTdPmrPei.h" =20 /** @@ -502,19 +502,17 @@ ProcessRmrr ( UINT64 RmrrMask; UINTN LowBottom; UINTN LowTop; - UINTN HighBottom; + UINT64 HighBottom; UINT64 HighTop; EFI_ACPI_DMAR_HEADER *AcpiDmarTable; + VTD_PMR_INFO_HOB *VtdPmrHob; + VOID *VtdPmrHobPtr; =20 + VtdPmrHobPtr =3D GetFirstGuidHob (&gVtdPmrInfoDataHobGuid); AcpiDmarTable =3D VTdInfo->AcpiDmarTable; =20 DEBUG ((DEBUG_INFO," RMRR (Base 0x%016lx, Limit 0x%016lx)\n", DmarRmrr-= >ReservedMemoryRegionBaseAddress, DmarRmrr->ReservedMemoryRegionLimitAddres= s)); =20 - if ((DmarRmrr->ReservedMemoryRegionBaseAddress =3D=3D 0) || - (DmarRmrr->ReservedMemoryRegionLimitAddress =3D=3D 0)) { - return ; - } - DmarDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)((U= INTN)(DmarRmrr + 1)); while ((UINTN)DmarDevScopeEntry < (UINTN)DmarRmrr + DmarRmrr->Header.Len= gth) { ASSERT (DmarDevScopeEntry->Type =3D=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYP= E_PCI_ENDPOINT); @@ -523,10 +521,26 @@ ProcessRmrr ( if (VTdIndex !=3D (UINTN)-1) { RmrrMask =3D LShiftU64 (1, VTdIndex); =20 - LowBottom =3D 0; - LowTop =3D (UINTN)DmarRmrr->ReservedMemoryRegionBaseAddress; - HighBottom =3D (UINTN)DmarRmrr->ReservedMemoryRegionLimitAddress + 1; - HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); + if (VtdPmrHobPtr =3D=3D NULL) { + LowBottom =3D 0; + LowTop =3D (UINTN)DmarRmrr->ReservedMemoryRegionBaseAddress; + HighBottom =3D DmarRmrr->ReservedMemoryRegionLimitAddress + 1; + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); + } else { + /** + When gVtdPmrInfoDataHobGuid exists, it means: + 1. Dma buffer is reserved by memory initialize code + 2. PeiGetVtdPmrAlignmentLib is used to get alignment + 3. PMR ranges are determined by the system memory map + 4. PMR ranges will be conveyed through VTD_PMR_INFO_HOB + 5. All IOMMU PMR should have the same ranges + **/ + VtdPmrHob =3D GET_GUID_HOB_DATA (VtdPmrHobPtr); + LowBottom =3D VtdPmrHob->ProtectedLowBase; + LowTop =3D VtdPmrHob->ProtectedLowLimit; + HighBottom =3D VtdPmrHob->ProtectedHighBase; + HighTop =3D VtdPmrHob->ProtectedHighLimit; + } =20 SetDmaProtectedRange ( VTdInfo, --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60551): https://edk2.groups.io/g/devel/message/60551 Mute This Topic: https://groups.io/mt/74618024/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-