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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: kH8oaLqkFxtiTvXHiDMLcRgJx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731591; bh=dVDrSllLDhzavU4UGMucKu/5rwdwH7FMJ/uJ2Y8cydI=; h=Content-Type:Date:From:Reply-To:Subject:To; b=cHBTSMu2VBmFoTpCnJkLL0sNQkAfsEkcbZ+diz9AKola7cpgFsQf1VaQKGatt6qM5Pl QLKzxCVvV9uBi7/H1B4g2n/sZtgQHkTyI4YwDlWWDaJI+b77ONkjXbrXzYaX7P1I60Zvz D0oGMpr5O5amfiA65b09pAW/d4YNdKwUqG0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal There are two implementations of Metronome protocol. EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf MdeModulePkg/Universal/Metronome/Metronome.inf Although nowhere it has been specified, which one to use, but we are going by the general practice of preferring MdeModulePkg/MdePkg over EmbeddedPkg. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - No change =20 V2: - No change Silicon/NXP/NxpQoriqLs.dsc.inc | 4 +--- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc index 03759c7cee7c..54236e19531c 100644 --- a/Silicon/NXP/NxpQoriqLs.dsc.inc +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc @@ -218,8 +218,6 @@ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|10 =20 [PcdsFixedAtBuild.common] - gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 - gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units,= 100,000 x 100 ns =3D 10,000,000 ns =3D 10 ms gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE @@ -348,7 +346,7 @@ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf MdeModulePkg/Universal/SerialDxe/SerialDxe.inf MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPkg/Drivers/ArmGic/ArmGicDxe.inf EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf index 1c160e349eb9..95bbb54cc420 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -117,7 +117,7 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf =20 - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf =20 # --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 29 May 2020 05:53:12 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 02/10] Platform/NXP: Use Monotonic counter from MdeModulePkg Date: Fri, 29 May 2020 11:21:41 +0530 Message-ID: <20200529055149.30953-3-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: XeHZPdguVaRTqBkA5Bvw8Cl8x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731596; bh=aKdCEF+tMBjCkPJI9cwcXTkFHKkNiQifzO4g2ULX/cc=; h=Content-Type:Date:From:Reply-To:Subject:To; b=VX+eqURjuOBNo7X5PeYXMLu81IghsJapjubcM3AHbr0RnB0lY+5SsheKmW3gCjQ91Ps PpYrfqj8S8zXTUgsnzGkB27QPW2viBCBIF99FrupVZdWk/SfwTvJqTWA7ouCliU4HtnkE oUBGSV40GBrkRP0Ev28bQVdL84woIQca7GY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Monotonic counter module from EmbeddedPkg doesn't treat the high 32 bit as non volatile, which is needed as per spec. Therefore, use Monotonic counter module from MdeModulePkg Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - No change =20 V2: - No change Silicon/NXP/NxpQoriqLs.dsc.inc | 2 +- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc index 54236e19531c..12e2b89fac58 100644 --- a/Silicon/NXP/NxpQoriqLs.dsc.inc +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc @@ -337,7 +337,7 @@ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf =20 # FDT installation MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf index 95bbb54cc420..dd31b45b4d78 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -100,7 +100,7 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 29 May 2020 05:53:15 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 03/10] Silicon/NXP/PciHostBridgeLib: Fix compilation with MDEPKG_NDEBUG flag Date: Fri, 29 May 2020 11:21:42 +0530 Message-ID: <20200529055149.30953-4-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: z1BPwHdHBgAaHMEi2LQOQAYMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731598; bh=9jGbS/ZZOXUW2N1EO052kbZg4XVxnArsCxVqPhSSL6Q=; h=Content-Type:Date:From:Reply-To:Subject:To; b=gxKWfNN0Pr1l1k1FceG+1z0uLsSc8OVj4zmb7F+o2SR8V8PFVYlmgggxqGK2Ruk4Ssw zQ1Z72bs218djf6ZOUNmeqHOSkscyl24oFj9nKWp6kBk6jiXa8QZtqBhyke+kojOIpg1S zj8UM5sJDh6bzXVvNrdzeQ6YRqPYwMow47Q= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal when MDEPKG_NDEBUG flag is enabled, RELEASE build fails with this error: error: mPciHostBridgeLibAcpiAddressSpaceTypeStr defined but not used [-Werror=3Dunused-variable] Fix this error by protecting mPciHostBridgeLibAcpiAddressSpaceTypeStr with MDEPKG_NDEBUG macro. Suggested-by: Leif Lindholm Signed-off-by: Pankaj Bansal --- Notes: V3: - New commit Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index 549f4fa133fb..e5309a4f4248 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -167,11 +167,13 @@ STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciR= ootBridgeDevicePath[] =3D { } }; =20 +#ifndef MDEPKG_NDEBUG STATIC GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D { L"Mem", L"I/O", L"Bus" }; +#endif =20 #define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PM= EM | \ EFI_PCI_HOST_BRIDGE_MEM64_DECODE --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 29 May 2020 05:53:18 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 04/10] Silicon/NXP: Use edk2 recommended compilation flags Date: Fri, 29 May 2020 11:21:43 +0530 Message-ID: <20200529055149.30953-5-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: tlnjf6Y4Sq7vtRyuKAebmogfx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731603; bh=ST8sYD7/VabAHZgLsj7dqzHTB8rOuW0FHTeXRKb97sg=; h=Content-Type:Date:From:Reply-To:Subject:To; b=YWPnKMPlI6OUE4CSZYbKBaImrgumTbt5jnC0Qv+EgEcz7IpeRwlLGWZDhIvamRJTiSJ GXiLPZ9H7jAeQpBZ/WtTr8OD7l+YM0RgnTYel3IXFvupC33ULF8kHBYCv2DNdwKOTdkNL hA0G+H57W4EOnCS4lQoFcO8u0srnvhaMm1A= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal edk2 recommends to use MDEPKG_NDEBUG for release builds and to use DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms. Therefore, enable these flags for NXP platforms as well Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - No change =20 V2: - No change Silicon/NXP/NxpQoriqLs.dsc.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc index 12e2b89fac58..ee639d552483 100644 --- a/Silicon/NXP/NxpQoriqLs.dsc.inc +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc @@ -173,7 +173,12 @@ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf =20 [BuildOptions] - RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu cortex-a9 + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + + # + # Disable deprecated APIs. + # + GCC:*_*_*_CC_FLAGS =3D -DDISABLE_NEW_DEPRECATED_INTERFACES =20 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_ARM_DLINK_FLAGS =3D -z common-page-size=3D0x1000 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 29 May 2020 05:53:21 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 05/10] Platform/NXP/LX2160ARDB: Add ArmPlatformLib Date: Fri, 29 May 2020 11:21:44 +0530 Message-ID: <20200529055149.30953-6-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: G6cSOH4VELGJ8hAhxvJadAo7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731604; bh=1GeJs8bAiWAspvWzA8yADhoyni+rDHJHCjm80B5F+AI=; h=Content-Type:Date:From:Reply-To:Subject:To; b=M234rysLIZnfm/lT7YV1o1m75Kpbsi5rj2vZtE9+qkviTxKkiGMw9fSm7lCeyB51BQ7 392k3yQO0UKwkVGBGf9DAB8h+dezON8V+0uhkshuCJ8Uj3dAC0ALykj5MDaw2gWNMrm3Z VXAFckGAG2Zfwojz+noejudlIJdn52OcHYY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Add ArmPlatformLib for LX2160ARDB platform that is based on ArmPlatformPkg/Library/ArmPlatformLibNull. Apart from the the interfaces exposed by ArmPlatformLibNull, this library also implements gPlatformGetClockPpi, which is specific to NXP SOCs' based platforms. Refer edk2-platforms/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h for the details. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - No change =20 V2: - New commit - split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts part containing gPlatformGetClockPpi is put before PL011UartClockLib implementation. Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf = | 39 ++++++ Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c = | 145 ++++++++++++++++++++ Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c = | 28 ++++ Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelpe= r.S | 45 ++++++ 4 files changed, 257 insertions(+) diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.inf b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.i= nf new file mode 100644 index 000000000000..743836e57141 --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -0,0 +1,39 @@ +#/* @file +# Copyright 2018, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformLib + FILE_GUID =3D d1361285-8a47-421c-9efd-6b262c9093fc + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ArmLib + DebugLib + +[Sources.common] + ArmPlatformLib.c + ArmPlatformLibMem.c + +[Sources.AArch64] + AArch64/ArmPlatformHelper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c new file mode 100644 index 000000000000..806cfd180bee --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -0,0 +1,145 @@ +/** @file +* +* Copyright 2018-2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include + +#include +#include + +ARM_CORE_INFO mLX2160aMpCoreInfoTable[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + } +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs + + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] ... Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. + if ClockType is NXP_CORE_CLOCK, then second argum= ent + is interpreted as cluster number and third argume= nt is + interpreted as core number (within the cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +EFIAPI +NxpPlatformGetClock( + IN UINT32 ClockType, + ... + ) +{ + UINT64 Clock; + VA_LIST Args; + + Clock =3D 0; + + VA_START (Args, ClockType); + + switch (ClockType) { + case NXP_SYSTEM_CLOCK: + Clock =3D 100 * 1000 * 1000; // 100 MHz + break; + case NXP_I2C_CLOCK: + case NXP_UART_CLOCK: + Clock =3D NxpPlatformGetClock (NXP_SYSTEM_CLOCK); + break; + default: + break; + } + + VA_END (Args); + + return Clock; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/Pl= atformPei + in the PEI phase. + +**/ +EFI_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + //TODO: Implement me + + return EFI_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + if (ArmIsMpCore()) { + *CoreCount =3D sizeof(mLX2160aMpCoreInfoTable) / sizeof(ARM_CORE_IN= FO); + *ArmCoreTable =3D mLX2160aMpCoreInfoTable; + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi =3D { NxpPlatformGetClock = }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + if (ArmIsMpCore()) { + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; + } else { + *PpiListSize =3D 0; + *PpiList =3D NULL; + } +} diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ibMem.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibM= em.c new file mode 100644 index 000000000000..ad6862dd81eb --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c @@ -0,0 +1,28 @@ +/** @file +* +* Copyright 2018, 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ASSERT(0); +} diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmP= latformHelper.S b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64= /ArmPlatformHelper.S new file mode 100644 index 000000000000..b7c6dbdc2e61 --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatform= Helper.S @@ -0,0 +1,45 @@ +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// + +#include +#include + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore)) + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq + ret --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 29 May 2020 05:53:24 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 06/10] Silicon/NXP: Implement PL011UartClockLib for NXP platforms Date: Fri, 29 May 2020 11:21:45 +0530 Message-ID: <20200529055149.30953-7-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: LjUeE4SpXOILFnDolKrHcnO7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731608; bh=7gZhKeNtBS607zmgd0pTgSIfUl9xK/lQGJ9l+kuiIFk=; h=Content-Type:Date:From:Reply-To:Subject:To; b=DpWP7j3+G11G3wFU0fIpr9lIkdCyDDum5aIFyvXOXQmSwVxJiWd2PyK1rjcE2ELo0Jv 0pmBiMsVH/duAFw1LW+zvKGnDOuagR0UaaDPcm7ckYlaV2Ycwai0WLMX94zbVlPmta7Jb 1Vs1lhH6Fm1/swrxzjQdMIQsit/B5LxWjVM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal In NXP SOCs the UART clock is derived from System clock after PLL multiplication. Therefore, add the PL011UartClockLib implementation for NXP platforms. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - No change =20 V2: - No change Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf | 24 +++++++++= +++++++++++ Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c | 22 +++++++++= +++++++++ 2 files changed, 46 insertions(+) diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf b/= Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf new file mode 100644 index 000000000000..b771dba7697f --- /dev/null +++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf @@ -0,0 +1,24 @@ +#/* @file +# Copyright 2018, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PL011UartClockLib + FILE_GUID =3D af8fef24-afbb-472a-b8b7-13101a79703c + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PL011UartClockLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[Sources.common] + PL011UartClockLib.c + +[LibraryClasses] + ArmPlatformLib diff --git a/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c b/Si= licon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c new file mode 100644 index 000000000000..3814685585eb --- /dev/null +++ b/Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c @@ -0,0 +1,22 @@ +/** @file +* +* Copyright 2018, 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include + +/** + Return clock in for PL011 Uart IP +**/ +UINT32 +EFIAPI +PL011UartClockGetFreq ( + VOID + ) +{ + return gPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0); +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 29 May 2020 05:53:27 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 07/10] Silicon/NXP: Add Chassis3V2 Package Date: Fri, 29 May 2020 11:21:46 +0530 Message-ID: <20200529055149.30953-8-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: F9C0fGc5L2zuj9I2AbIVEBerx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731610; bh=VMol2I87pqJOmdpi9iHN05JGieKD9oiYVaeNngrzK7U=; h=Content-Type:Date:From:Reply-To:Subject:To; b=YxmdqqHdUhJTHtWkhkv7OIoMbnIKGIQvka2PToBYr3gPKQJ9fGU9ygiyVu+ojCEJNeg G7JcfhmlEVKGTHDFxT6NbFcKTDeCLuO2egsSW2vZe+hNMQzFP2hBWW1UEu+UFw1CUGgT6 tGdzewClJWlBY6t6gN2zQR189W8DOy/HjeU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs are based. Add the Chassis3V2 package. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - No change =20 V2: - No change Silicon/NXP/Chassis3V2/Chassis3V2.dec | 22 ++++++ Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 +++ Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf | 33 +++++++++ Silicon/NXP/Chassis3V2/Include/Chassis.h | 26 +++++++ Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c | 71 ++++++++++++= ++++++++ 5 files changed, 162 insertions(+) diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec b/Silicon/NXP/Chassis3V2= /Chassis3V2.dec new file mode 100644 index 000000000000..f7269e6bf6de --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec @@ -0,0 +1,22 @@ +# @file +# NXP Layerscape processor package. +# +# Copyright 2017, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEC_SPECIFICATION =3D 1.27 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc b/Silicon/NXP/Chassi= s3V2/Chassis3V2.dsc.inc new file mode 100644 index 000000000000..b9f388a59f2a --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc @@ -0,0 +1,10 @@ +# @file +# +# Copyright 2018-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[LibraryClasses.common] + ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf b/Sil= icon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf new file mode 100644 index 000000000000..75b68cc4ca2d --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf @@ -0,0 +1,33 @@ +# @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION =3D 1.27 + BASE_NAME =3D Chassis3V2Lib + FILE_GUID =3D fae0d077-5fc2-494f-b8e1-c51a3023ee3e + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ChassisLib + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/Chassis3V2/Chassis3V2.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + IoAccessLib + IoLib + PcdLib + SerialPortLib + +[Sources.common] + ChassisLib.c + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h b/Silicon/NXP/Chassis= 3V2/Include/Chassis.h new file mode 100644 index 000000000000..0fd70132d897 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h @@ -0,0 +1,26 @@ +/** @file + + Copyright 2018-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef CHASSIS_H__ +#define CHASSIS_H__ + +#include + +#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000 + +/** + The Device Configuration Unit provides general purpose configuration and + status for the device. These registers only support 32-bit accesses. +**/ +#pragma pack(1) +typedef struct { + UINT8 Reserved0[0x100 - 0x0]; + UINT32 RcwSr[32]; // Reset Control Word Status Register +} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG; +#pragma pack() + +#endif // CHASSIS_H__ diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c b/Silic= on/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c new file mode 100644 index 000000000000..30f8f945b233 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c @@ -0,0 +1,71 @@ +/** @file + Chassis specific functions common to all SOCs based on a specific Chessis + + Copyright 2018-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Read Dcfg register + + @param Address The MMIO register to read. + + @return The value read. +**/ +UINT32 +EFIAPI +DcfgRead32 ( + IN UINTN Address + ) +{ + MMIO_OPERATIONS *DcfgOps; + + DcfgOps =3D GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian)); + + return DcfgOps->Read32 (Address); +} + +/** + Write Dcfg register + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. +**/ +UINT32 +EFIAPI +DcfgWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + MMIO_OPERATIONS *DcfgOps; + + DcfgOps =3D GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian)); + + return DcfgOps->Write32 (Address, Value); +} + +/** + Function to initialize Chassis Specific functions + **/ +VOID +ChassisInit ( + VOID + ) +{ + // + // Early init serial Port to get board information. + // + SerialPortInitialize (); +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 29 May 2020 05:53:30 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 08/10] Silicon/NXP: Add LX2160A Soc package Date: Fri, 29 May 2020 11:21:47 +0530 Message-ID: <20200529055149.30953-9-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: twmPQjGkx8E8kOqnxTrwv1Ryx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731620; bh=/7UVvYA2pfahSpdyqTIKeSwBSB5EelF7/8+Smrw5QMM=; h=Content-Type:Date:From:Reply-To:Subject:To; b=ci3in2Oj56ofLS6a29EgGNd2XF4Bf7qJLm56Byw5mUuTNCTvkMwUT7GuSa0e3N6TmFV rzJppZVm5Fw4sD6bnCtiraqu03uOc16DEwpMllB6M9Vrxzc7yGL3lUC8dzUn3IFZT6LGe WymT8uKRtzHHRbMhzU8vmKwv+xodUe7JYGg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal LX2160A is QorIq Layerscape multicore communications processor with sixteen Arm Cortex-A72 cores. This SOC is based on Layerscape Chassis v3.2. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - No change =20 V2: - No change Silicon/NXP/LX2160A/LX2160A.dec | 13 ++++ Silicon/NXP/LX2160A/LX2160A.dsc.inc | 50 ++++++++++++ Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf | 27 +++++++ Silicon/NXP/LX2160A/Include/Soc.h | 38 ++++++++++ Silicon/NXP/LX2160A/Library/SocLib/SocLib.c | 80 ++++++++++++++++++++ 5 files changed, 208 insertions(+) diff --git a/Silicon/NXP/LX2160A/LX2160A.dec b/Silicon/NXP/LX2160A/LX2160A.= dec new file mode 100644 index 000000000000..50481c0f2ebd --- /dev/null +++ b/Silicon/NXP/LX2160A/LX2160A.dec @@ -0,0 +1,13 @@ +# LX2160A.dec +# +# Copyright 2018, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + +[Includes] + Include diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/LX2160A/LX21= 60A.dsc.inc new file mode 100644 index 000000000000..af22b4dd973c --- /dev/null +++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc @@ -0,0 +1,50 @@ +# LX2160A.dsc +# LX2160A Soc package. +# +# Copyright 2018-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc + +[LibraryClasses.common] + SocLib|Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf + + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL= ib.inf + PL011UartClockLib|Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLi= b.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsDynamicDefault.common] + # + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6200000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xC0C0000 + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x23A0000 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2390000 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|91 + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21C0000 + +[PcdsFeatureFlag] + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + +## diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf b/Silicon/NXP/LX= 2160A/Library/SocLib/SocLib.inf new file mode 100644 index 000000000000..421072b88019 --- /dev/null +++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf @@ -0,0 +1,27 @@ +# @file +# +# Copyright 2018-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocLib + FILE_GUID =3D 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SocLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/Chassis3V2/Chassis3V2.dec + Silicon/NXP/LX2160A/LX2160A.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ChassisLib + DebugLib + +[Sources.common] + SocLib.c diff --git a/Silicon/NXP/LX2160A/Include/Soc.h b/Silicon/NXP/LX2160A/Includ= e/Soc.h new file mode 100644 index 000000000000..52674ee5f32c --- /dev/null +++ b/Silicon/NXP/LX2160A/Include/Soc.h @@ -0,0 +1,38 @@ +/** @file + + Copyright 2018-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SOC_H__ +#define SOC_H__ + +#include + +/** + Soc Memory Map +**/ +#define LX2160A_DRAM0_PHYS_ADDRESS (BASE_2GB) +#define LX2160A_DRAM0_SIZE (SIZE_2GB) +#define LX2160A_DRAM1_PHYS_ADDRESS (BASE_128GB + BASE_2GB) +#define LX2160A_DRAM1_SIZE (SIZE_128GB - SIZE_2GB) // 126 GB +#define LX2160A_DRAM2_PHYS_ADDRESS (BASE_256GB + BASE_128GB) +#define LX2160A_DRAM2_SIZE (SIZE_128GB) + +#define LX2160A_CCSR_PHYS_ADDRESS (BASE_16MB) +#define LX2160A_CCSR_SIZE (SIZE_256MB - SIZE_16MB) // 240MB + +#define LX2160A_FSPI0_PHYS_ADDRESS (BASE_512MB) +#define LX2160A_FSPI0_SIZE (SIZE_256MB) + +#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS + +/** + Reset Control Word (RCW) Bits +**/ +#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 + +typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG; + +#endif // SOC_H__ diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.c b/Silicon/NXP/LX21= 60A/Library/SocLib/SocLib.c new file mode 100644 index 000000000000..6f774eb7dc6c --- /dev/null +++ b/Silicon/NXP/LX2160A/Library/SocLib/SocLib.c @@ -0,0 +1,80 @@ +/** @Soc.c + SoC specific Library containg functions to initialize various SoC compon= ents + + Copyright 2018-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Return the input clock frequency to an IP Module. + This function reads the RCW bits and calculates the PLL multiplier/divi= der + values to be applied to various IP modules. + If a module is disabled or doesn't exist on platform, then return zero. + + @param[in] BaseClock Base clock to which PLL multiplier/divider values= is + to be applied. + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] Args Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within the + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +SocGetClock ( + IN UINT64 BaseClock, + IN NXP_IP_CLOCK ClockType, + IN VA_LIST Args + ) +{ + LX2160A_DEVICE_CONFIG *Dcfg; + UINT32 RcwSr; + UINT64 ReturnValue; + + ReturnValue =3D 0; + Dcfg =3D (LX2160A_DEVICE_CONFIG *)LX2160A_DCFG_ADDRESS; + + switch (ClockType) { + case NXP_UART_CLOCK: + RcwSr =3D DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]); + ReturnValue =3D (BaseClock * SYS_PLL_RAT (RcwSr)) >> 3; + break; + case NXP_I2C_CLOCK: + RcwSr =3D DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]); + ReturnValue =3D (BaseClock * SYS_PLL_RAT (RcwSr)) >> 4; + break; + default: + break; + } + + return ReturnValue; +} + +/** + Function to initialize SoC specific constructs + **/ +VOID +SocInit ( + VOID + ) +{ + ChassisInit (); + + return; +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 29 May 2020 05:53:33 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 09/10] Platform/NXP: Add LX2160ARDB Platform Date: Fri, 29 May 2020 11:21:48 +0530 Message-ID: <20200529055149.30953-10-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: T0FrVzrgUEHMBFFD7k7tl5znx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731619; bh=C8B8X8efcCI1s8T22ZGVsZOGsauSIPuGqzDxr9eEhEg=; h=Content-Type:Date:From:Reply-To:Subject:To; b=iCaUBJ/DzRx0MNyW327D5DJvQsg++ILu1fRK8AJq7DNESMBobH5C8eQ5HCbqgkgwfq8 /p2WvNL5Umlen8LIgAJoHE1mEZHTbXW6ly5KiRRmXy0Cx2MtE+rOxbpojf3k7sTEX/yqc Tz/yKaGfSi6C4fvPJySan6QjsQqV20gyYpw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal LX2160A Reference Design Board (RDB) is a high-performance development platform that supports the QorIQ LX2160A Layerscape Architecture SOCs. Signed-off-by: Pankaj Bansal --- Notes: V3: - Alphabetically sorted LibraryClasses in Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf =20 V2: - split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts part containing gPlatformGetClockPpi is put before PL011UartClockLib implementation. Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec | 2= 3 +++ Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 4= 6 ++++++ Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 16= 8 ++++++++++++++++++++ Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | = 3 + Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | = 4 +- Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 5= 4 ++++++- 6 files changed, 296 insertions(+), 2 deletions(-) diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.dec new file mode 100644 index 000000000000..03996b07fcb9 --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec @@ -0,0 +1,23 @@ +# LX2160aRdbPkg.dec +# LX2160a board package. +# +# Copyright 2018, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + PACKAGE_NAME =3D LX2160aRdbPkg + PACKAGE_GUID =3D 474e0c59-5f77-4060-82dd-9025ee4f4939 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.dsc new file mode 100644 index 000000000000..9b3e0386c13e --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc @@ -0,0 +1,46 @@ +# LX2160aRdbPkg.dsc +# +# LX2160ARDB Board package. +# +# Copyright 2018-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_NAME =3D LX2160aRdbPkg + PLATFORM_GUID =3D be06d8bc-05eb-44d6-b39f-191e93617ebd + OUTPUT_DIRECTORY =3D Build/LX2160aRdbPkg + FLASH_DEFINITION =3D Platform/NXP/LX2160aRdbPkg/LX2160aRdb= Pkg.fdf + +!include Silicon/NXP/NxpQoriqLs.dsc.inc +!include Silicon/NXP/LX2160A/LX2160A.dsc.inc + +[LibraryClasses.common] + ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlat= formLib.inf + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal= TimeClockLib.inf + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # Architectural Protocols + # + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + } + + ## diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.fdf new file mode 100644 index 000000000000..19d2ca9bbe58 --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf @@ -0,0 +1,168 @@ +# LX2160aRdbPkg.fdf +# +# FLASH layout file for LX2160a board. +# +# Copyright 2018-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.LX2160ARDB_EFI] +BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. +Size =3D 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x10000 +NumBlocks =3D 0x14 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### +0x00000000|0x00140000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +!include Platform/NXP/FVRules.fdf.inc +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 1037c42b-8452-4c41-aac7-41e6c31468da +BlockSize =3D 0x1 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.i= nf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.inf b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.i= nf index 743836e57141..6780ee883c8c 100644 --- a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -19,10 +19,13 @@ ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis3V2/Chassis3V2.dec + Silicon/NXP/LX2160A/LX2160A.dec =20 [LibraryClasses] ArmLib DebugLib + SocLib =20 [Sources.common] ArmPlatformLib.c diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c index 806cfd180bee..f3f1e5b3f220 100644 --- a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 #include #include @@ -76,6 +77,7 @@ NxpPlatformGetClock( case NXP_I2C_CLOCK: case NXP_UART_CLOCK: Clock =3D NxpPlatformGetClock (NXP_SYSTEM_CLOCK); + Clock =3D SocGetClock (Clock, ClockType, Args); break; default: break; @@ -98,7 +100,7 @@ ArmPlatformInitialize ( IN UINTN MpId ) { - //TODO: Implement me + SocInit (); =20 return EFI_SUCCESS; } diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ibMem.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibM= em.c index ad6862dd81eb..391dab265ad7 100644 --- a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c @@ -7,7 +7,12 @@ **/ =20 #include +#include #include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 =20 /** Return the Virtual Memory Map of your platform @@ -24,5 +29,52 @@ ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap ) { - ASSERT(0); + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + Index =3D 0; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTO= R) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + if (VirtualMemoryTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION_= _)); + return; + } + + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_DRAM0_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_DRAM1_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_DRAM2_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_DRAM2_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_DRAM2_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK; + + // CCSR Space + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_CCSR_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // FlexSPI + VirtualMemoryTable[Index].PhysicalBase =3D LX2160A_FSPI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LX2160A_FSPI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LX2160A_FSPI0_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // End of Table + ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTO= R)); + + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; } --=20 2.17.1 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Fri, 29 May 2020 05:53:36 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v3 10/10] Platform/NXP/LX2160aRdbPkg: Add VarStore Date: Fri, 29 May 2020 11:21:49 +0530 Message-ID: <20200529055149.30953-11-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> References: <20200529055149.30953-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0112.apcprd01.prod.exchangelabs.com (2603:1096:4:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: jSByFzZv5anFNQRxouTcG84Px1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1590731620; bh=ZRwOcOyZ4pU71Q/693uB2CR3UEngSrT46VPAwC/9CNQ=; h=Content-Type:Date:From:Reply-To:Subject:To; b=DAadJRRUZ3BU3QhMIYqI6fPiONcJCz++l49Fr7Tg+nlMftb7BYlmW3vnLFj27F1w6Jf SqxK+P9QlXlp4MlZQAoyFbWNJ5ZX5WQ2MXo+KCVoT2i2u5NVzgFNKkNOVNSpLfsbiFNLi qYNcxB2XlAvJ8aNL4uv/2Cx+wOD0/1XAtK0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Add VarStore Fd. This Fd is used to store non volatile variables in flash. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V3: - No change =20 V2: - No change Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 1 + Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc | 91 ++++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf b/Platform/NXP/LX= 2160aRdbPkg/LX2160aRdbPkg.fdf index 19d2ca9bbe58..eec1c0774a86 100644 --- a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf @@ -48,6 +48,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.Pc= dFvSize FV =3D FVMAIN_COMPACT =20 !include Platform/NXP/FVRules.fdf.inc +!include VarStore.fdf.inc ##########################################################################= ###### # # FV Section diff --git a/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LX2= 160aRdbPkg/VarStore.fdf.inc new file mode 100644 index 000000000000..799eee87193f --- /dev/null +++ b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc @@ -0,0 +1,91 @@ +## @file +# FDF include file with FD definition that defines an empty variable stor= e. +# +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved. +# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2016, Linaro, Ltd. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved. +# Copyright 2017-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[FD.LX2160aRdbNv_EFI] +BaseAddress =3D 0x20500000 #The base address of the FLASH device +Size =3D 0x000C0000 #The size in bytes of the FLASH device +ErasePolarity =3D 1 +BlockSize =3D 0x1000 +NumBlocks =3D 0xC0 + +# +# Place NV Storage just above Platform Data Base +# +DEFINE NVRAM_AREA_VARIABLE_BASE =3D 0x00000000 +DEFINE NVRAM_AREA_VARIABLE_SIZE =3D 0x00040000 +DEFINE FTW_WORKING_BASE =3D $(NVRAM_AREA_VARIABLE_B= ASE) + $(NVRAM_AREA_VARIABLE_SIZE) +DEFINE FTW_WORKING_SIZE =3D 0x00040000 +DEFINE FTW_SPARE_BASE =3D $(FTW_WORKING_BASE) + $= (FTW_WORKING_SIZE) +DEFINE FTW_SPARE_SIZE =3D 0x00040000 + +##########################################################################= ### +# LX2160ARDB NVRAM Area +# LX2160ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare +##########################################################################= ### + + +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: Flash Size : 0x4000000 + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block =3D SIZE_64MB + 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + # It is compatible with SECURE_BOOT_ENABLE =3D=3D FALSE as well. + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3ffb8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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