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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,daniel.schaefer@hpe.com X-Gm-Message-State: zELvcd2MQsdJ8d74m0sPjgrYx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589549996; bh=ldFJZK3e8vwJEa5DYVIX4JYzP5gJO8ZdyrdpZ7WloIs=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=iv3dAke7HkKHv1MXyPOQOsazQpOk0OZRqb7EHCQZ+oxnMP+0qIa/3X26ER+PvvdbNGG GLnGCE4beTf2/1K+Z2apLVGIgSpEexV/695oTJk0lyxpKFkWLft/00MTK6XNyzfQQZlyc 0lbqaU1YbHTAi1vmKh2MGSAYhmH1fTLw8Oc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add submodule opensbi under Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbLlib. The current supported opensbi version for RISC-V edk2 port is tags/v0.6. Signed-off-by: Daniel Schaefer Co-authored-by: Gilbert Chen Co-authored-by: Abner Chang Cc: Abner Chang Cc: Gilbert Chen Cc: Michael D Kinney Cc: Leif Lindholm Reviewed-by: Leif Lindholm --- .gitmodules | 3 ++ Readme.md | 36 +++++++++= +++++++++++ Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi | 1 + 3 files changed, 40 insertions(+) diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 000000000000..88aafaf15820 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi"] + path =3D Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi + url =3D https://github.com/riscv/opensbi diff --git a/Readme.md b/Readme.md index 8f9522659d7b..8f7317e6b029 100644 --- a/Readme.md +++ b/Readme.md @@ -10,6 +10,10 @@ The majority of the content in the EDK II open source pr= oject uses a [BSD-2-Clause Plus Patent License](License.txt). Additional details on ED= K II open source project code contributions can be found in the edk2 repository [Readme.md](https://github.com/tianocore/edk2/blob/master/Readme.md). +The EDK II Platforms open source project contains the following components= that +are covered by additional licenses: + +- [`Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi`](https://= github.com/riscv/opensbi/blob/master/COPYING.BSD) =20 # INDEX * [Overview](#overview) @@ -260,3 +264,35 @@ For more information, see the # Maintainers =20 See [Maintainers.txt](Maintainers.txt). + +# Submodules + +Submodule in EDK II Platforms is allowed but submodule chain should be avo= ided +as possible as we can. Currently EDK II Platforms contains the following +submodules + +- Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi + +To get a full, buildable EDK II repository, use following steps of git com= mand + +```bash + git clone https://github.com/tianocore/edk2-platforms.git + cd edk2-platforms + git submodule update --init + cd .. +``` + +If there's update for submodules, use following git commands to get the la= test +submodules code. + +```bash + cd edk2-platforms + git pull + git submodule update +``` + +Note: When cloning submodule repos, '--recursive' option is not recommende= d. +EDK II Platforms itself will not use any code/feature from submodules in a= bove +submodules. So using '--recursive' adds a dependency on being able to reach +servers we do not actually want any code from, as well as needlessly +downloading code we will not use. diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi b/= Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi new file mode 160000 index 000000000000..ac5e821d50be --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi @@ -0,0 +1 @@ +Subproject commit ac5e821d50be631f26274765a59bc1b444ffd862 --=20 2.26.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 15 May 2020 13:39:54 +0000 From: "Daniel Schaefer" To: CC: Gilbert Chen , Leif Lindholm , Abner Chang , Michael D Kinney , Leif Lindholm Subject: [edk2-devel] [PATCH v2 2/3] ProcessorPkg/Library: Add RiscVOpensbiLib Date: Fri, 15 May 2020 15:39:36 +0200 Message-ID: <20200515133937.29909-3-daniel.schaefer@hpe.com> In-Reply-To: <20200515133937.29909-1-daniel.schaefer@hpe.com> References: <20200515133937.29909-1-daniel.schaefer@hpe.com> X-ClientProxiedBy: AM0P190CA0007.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::17) To CS1PR8401MB0726.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:750c::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from x360-nix.fritz.box (93.215.201.203) by AM0P190CA0007.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.20 via Frontend Transport; Fri, 15 May 2020 13:39:52 +0000 X-Originating-IP: [93.215.201.203] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 40f2c80e-b22f-422f-c117-08d7f8d572fd X-MS-TrafficTypeDiagnostic: CS1PR8401MB0726: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,daniel.schaefer@hpe.com X-Gm-Message-State: HQ603Pl4WvGmIzRHsxe7fWjwx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589550000; bh=DfecZHn++MShKgRfPaJEDt74aj2QkS+ZFO4ruYwfWW8=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=uWKsE+t2A2sON5SQNd4hpSSyLnsw1UvgjEpq4iJ344dfbABixOEA8XQkde5l2xlxtLi DaBapuoETLeqAx2TYya2C7nbw0PS3Alspf22++VX/gJOjkXDBUQ/ZS4FNCoSXmHvvM1nW GafwG+xS6cknZFT0UTQ9M+kbMLxzxWVQUf0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Abner Chang EDK2 RISC-V OpenSBI library which pull in external source files under RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi to the build process. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Abner Chang Cc: Gilbert Chen Cc: Michael D Kinney Cc: Leif Lindholm --- Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | = 60 +++++++++++++++ Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h | = 79 ++++++++++++++++++++ Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h | = 73 ++++++++++++++++++ 3 files changed, 212 insertions(+) diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpens= biLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensb= iLib.inf new file mode 100644 index 000000000000..59dbd67d8e03 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.i= nf @@ -0,0 +1,60 @@ +## @file +# RISC-V Opensbi Library Instance. +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVOpensbiLib + FILE_GUID =3D 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVOpensbiLib + +[Sources] + opensbi/lib/sbi/riscv_asm.c + opensbi/lib/sbi/riscv_atomic.c + opensbi/lib/sbi/riscv_hardfp.S + opensbi/lib/sbi/riscv_locks.c + opensbi/lib/sbi/sbi_console.c + opensbi/lib/sbi/sbi_ecall.c + opensbi/lib/sbi/sbi_ecall_vendor.c + opensbi/lib/sbi/sbi_ecall_replace.c + opensbi/lib/sbi/sbi_ecall_legacy.c + opensbi/lib/sbi/sbi_ecall_base.c + opensbi/lib/sbi/sbi_emulate_csr.c + opensbi/lib/sbi/sbi_fifo.c + opensbi/lib/sbi/sbi_hart.c + opensbi/lib/sbi/sbi_hfence.S + opensbi/lib/sbi/sbi_illegal_insn.c + opensbi/lib/sbi/sbi_init.c + opensbi/lib/sbi/sbi_ipi.c + opensbi/lib/sbi/sbi_misaligned_ldst.c + opensbi/lib/sbi/sbi_scratch.c + opensbi/lib/sbi/sbi_string.c + opensbi/lib/sbi/sbi_system.c + opensbi/lib/sbi/sbi_timer.c + opensbi/lib/sbi/sbi_tlb.c + opensbi/lib/sbi/sbi_trap.c + opensbi/lib/sbi/sbi_unpriv.c + opensbi/lib/utils/sys/clint.c + opensbi/lib/utils/irqchip/plic.c + opensbi/lib/utils/serial/sifive-uart.c + opensbi/lib/utils/serial/uart8250.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec # For libfdt. + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + RiscVCpuLib + + + diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen= sbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h new file mode 100644 index 000000000000..c5c0bd6d9b01 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h @@ -0,0 +1,79 @@ +/** @file + SBI inline function calls. + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef EDK2_SBI_H_ +#define EDK2_SBI_H_ + +#include // Reference to header file in opensbi +#include +#include // Reference to header file wrapper + +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILED -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 + +#define SBI_BASE_EXT 0x10 +#define SBI_HSM_EXT 0x48534D +#define SBI_TIME_EXT 0x54494D45 +#define SBI_IPI_EXT 0x735049 +#define SBI_RFNC_EXT 0x52464E43 + +// +// Below two definitions should be defined in OpenSBI. +// +#define SBI_EXT_FIRMWARE_CODE_BASE_START 0x0A000000 +#define SBI_EXT_FIRMWARE_CODE_BASE_END 0x0AFFFFFF + +#define SBI_GET_SPEC_VERSION_FUNC 0 +#define SBI_GET_IMPL_ID_FUNC 1 +#define SBI_GET_IMPL_VERSION_FUNC 2 +#define SBI_PROBE_EXTENSION_FUNC 3 +#define SBI_GET_MVENDORID_FUNC 4 +#define SBI_GET_MARCHID_FUNC 5 +#define SBI_GET_MIMPID_FUNC 6 + +#define SBI_HART_START_FUNC 0 +#define SBI_HART_STOP_FUNC 1 +#define SBI_HART_GET_STATUS_FUNC 2 + +#define RISC_V_MAX_HART_SUPPORTED 16 + +typedef +VOID +(EFIAPI *RISCV_HART_SWITCH_MODE)( + IN UINTN FuncArg0, + IN UINTN FuncArg1, + IN UINTN NextAddr, + IN UINTN NextMode, + IN BOOLEAN NextVirt + ); + +// +// Keep the structure member in 64-bit alignment. +// +typedef struct { + UINT64 IsaExtensionSupported; // The ISA extension th= is core supported. + RISCV_UINT128 MachineVendorId; // Machine vendor ID + RISCV_UINT128 MachineArchId; // Machine Architecture= ID + RISCV_UINT128 MachineImplId; // Machine Implementati= on ID + RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function t= o switch the mode of a hart +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC; +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size = of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC + // structure. Referr= ed by both C code and assembly code. + +typedef struct { + VOID *PeiServiceTable; // PEI Service table + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_= SUPPORTED]; +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; + +#endif diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/R= ISC-V/ProcessorPkg/Include/OpensbiTypes.h new file mode 100644 index 000000000000..5f3278e8461f --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h @@ -0,0 +1,73 @@ +/** @file + RISC-V OpesbSBI header file reference. + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef EDK2_SBI_TYPES_H_ +#define EDK2_SBI_TYPES_H_ + +#include + +typedef INT8 s8; +typedef UINT8 u8; +typedef UINT8 uint8_t; + +typedef INT16 s16; +typedef UINT16 u16; +typedef INT16 int16_t; +typedef UINT16 uint16_t; + +typedef INT32 s32; +typedef UINT32 u32; +typedef INT32 int32_t; +typedef UINT32 uint32_t; + +typedef INT64 s64; +typedef UINT64 u64; +typedef INT64 int64_t; +typedef UINT64 uint64_t; + +#define PRILX "016lx" + +typedef BOOLEAN bool; +typedef unsigned long ulong; +typedef UINT64 uintptr_t; +typedef UINT64 size_t; +typedef INT64 ssize_t; +typedef UINT64 virtual_addr_t; +typedef UINT64 virtual_size_t; +typedef UINT64 physical_addr_t; +typedef UINT64 physical_size_t; + +#define __packed __attribute__((packed)) +#define __noreturn __attribute__((noreturn)) + +#if defined(__GNUC__) || defined(__clang__) + #define likely(x) __builtin_expect((x), 1) + #define unlikely(x) __builtin_expect((x), 0) +#else + #define likely(x) (x) + #define unlikely(x) (x) +#endif + +#undef offsetof +#ifdef __compiler_offsetof +#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER) +#else +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#endif + +#define container_of(ptr, type, member) ({ \ + const typeof(((type *)0)->member) * __mptr =3D (ptr); \ + (type *)((char *)__mptr - offsetof(type, member)); }) + +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) +#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) +#define ROUNDDOWN(a, b) ((a) / (b) * (b)) + +/* clang-format on */ + +#endif --=20 2.26.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 15 May 2020 13:39:56 +0000 From: "Daniel Schaefer" To: CC: Abner Chang , Gilbert Chen , Michael D Kinney , Leif Lindholm Subject: [edk2-devel] [PATCH v2 3/3] ProcessorPkg/Library: Add RiscVEdk2SbiLib Date: Fri, 15 May 2020 15:39:37 +0200 Message-ID: <20200515133937.29909-4-daniel.schaefer@hpe.com> In-Reply-To: <20200515133937.29909-1-daniel.schaefer@hpe.com> References: <20200515133937.29909-1-daniel.schaefer@hpe.com> X-ClientProxiedBy: AM0P190CA0007.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::17) To CS1PR8401MB0726.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:750c::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from x360-nix.fritz.box (93.215.201.203) by AM0P190CA0007.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.20 via Frontend Transport; Fri, 15 May 2020 13:39:54 +0000 X-Originating-IP: [93.215.201.203] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 2842a954-5da3-4c28-4931-08d7f8d57419 X-MS-TrafficTypeDiagnostic: CS1PR8401MB0726: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,daniel.schaefer@hpe.com X-Gm-Message-State: tAm09kq3j2iurCWOZv9CS5X9x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589550002; bh=bILerFLfF3yfnfKuWG/JsRK6rkTwtraL7pvtcaHCII4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=RHYvJwQOkX0ciEpaSPFFh04vfBbbRxsFr0Oo3vIOcA9DlOfXJXq2IkXO3jP+ByP+vB3 Dpxgsvr2vDwx94ZtKmuy72FCTvFlaTdwwj1tviSqfhQ/WGC78zP0BGFUa06Ronhz+PDCq fu5H4rtMSbF/Boh6XFKrjavnYu5TQpSZp2c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Library provides interfaces to invoke SBI extensions. Signed-off-by: Daniel Schaefer Cc: Abner Chang Cc: Gilbert Chen Cc: Michael D Kinney Cc: Leif Lindholm --- Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf | = 28 + Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h | = 43 +- Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h | = 631 ++++++++++++++++ Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | = 789 ++++++++++++++++++++ 4 files changed, 1466 insertions(+), 25 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2S= biLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2Sb= iLib.inf new file mode 100644 index 000000000000..665dcbf40e01 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.i= nf @@ -0,0 +1,28 @@ +## @file +# RISC-V Library to call SBI ecalls +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVEdk2SbiLib + FILE_GUID =3D 0DF1BBBD-F7E5-4E8A-BCF1-9D63D2DD9FDD + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVEdk2SbiLib + +[Sources] + RiscVEdk2SbiLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + RiscVOpensbiLib diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen= sbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h index c5c0bd6d9b01..18a85e2238d2 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h @@ -10,42 +10,35 @@ #ifndef EDK2_SBI_H_ #define EDK2_SBI_H_ =20 -#include // Reference to header file in opensbi #include +#include // Reference to header file in opensbi +#include +#include #include // Reference to header file wrapper =20 -#define SBI_SUCCESS 0 -#define SBI_ERR_FAILED -1 -#define SBI_ERR_NOT_SUPPORTED -2 -#define SBI_ERR_INVALID_PARAM -3 -#define SBI_ERR_DENIED -4 -#define SBI_ERR_INVALID_ADDRESS -5 -#define SBI_ERR_ALREADY_AVAILABLE -6 +// Translation from OpenSBI constants to SBI names +#define SBI_SUCCESS SBI_OK +#define SBI_ERR_FAILED SBI_EFAIL +#define SBI_ERR_NOT_SUPPORTED SBI_ENOTSUPP +#define SBI_ERR_INVALID_PARAM SBI_EINVAL +#define SBI_ERR_DENIED SBI_DENIED +#define SBI_ERR_INVALID_ADDRESS SBI_INVALID_ADDR +#define SBI_ERR_ALREADY_AVAILABLE -6 =20 -#define SBI_BASE_EXT 0x10 -#define SBI_HSM_EXT 0x48534D -#define SBI_TIME_EXT 0x54494D45 -#define SBI_IPI_EXT 0x735049 -#define SBI_RFNC_EXT 0x52464E43 +// Included in OpenSBI 0.7 +// Can be removed, once we upgrade +#define SBI_EXT_HSM 0x48534D +#define SBI_EXT_HSM_HART_START 0x0 +#define SBI_EXT_HSM_HART_STOP 0x1 +#define SBI_EXT_HSM_HART_GET_STATUS 0x2 =20 // // Below two definitions should be defined in OpenSBI. +// Submitted to upstream, waiting for merge and release. // #define SBI_EXT_FIRMWARE_CODE_BASE_START 0x0A000000 #define SBI_EXT_FIRMWARE_CODE_BASE_END 0x0AFFFFFF =20 -#define SBI_GET_SPEC_VERSION_FUNC 0 -#define SBI_GET_IMPL_ID_FUNC 1 -#define SBI_GET_IMPL_VERSION_FUNC 2 -#define SBI_PROBE_EXTENSION_FUNC 3 -#define SBI_GET_MVENDORID_FUNC 4 -#define SBI_GET_MARCHID_FUNC 5 -#define SBI_GET_MIMPID_FUNC 6 - -#define SBI_HART_START_FUNC 0 -#define SBI_HART_STOP_FUNC 1 -#define SBI_HART_GET_STATUS_FUNC 2 - #define RISC_V_MAX_HART_SUPPORTED 16 =20 typedef diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h = b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h new file mode 100644 index 000000000000..cf77814e3bbc --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h @@ -0,0 +1,631 @@ +/** @file Defines the PPIs to let PEIMs call SBI + +Copyright (c) 2020, Hewlett Packard Development LP. All rights reserved. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_SBI_LIB_H_ +#define RISCV_SBI_LIB_H_ + +#include +#include +#include +#include + +// +// EDK2 OpenSBI Firmware extension. +// +#define SBI_EDK2_FW_EXT (SBI_EXT_FIRMWARE_CODE_BASE_START | SBI_OPENSBI_IM= PID) +// +// EDK2 OpenSBI Firmware extension functions. +// +#define SBI_EXT_FW_MSCRATCH_FUNC 0 +#define SBI_EXT_FW_MSCRATCH_HARTID_FUNC 1 + +// +// EDK2 OpenSBI firmware extension return status. +// +struct sbiret { + long error; ///< SBI status code + long value; ///< Value returned +}; + +#define SbiCall0(ext_id, func_id) \ + SbiCall(ext_id, func_id, 0, 0, 0, 0, 0, 0) +#define SbiCall1(ext_id, func_id, arg0) \ + SbiCall(ext_id, func_id, arg0, 0, 0, 0, 0, 0) +#define SbiCall2(ext_id, func_id, arg0, arg1) \ + SbiCall(ext_id, func_id, arg0, arg1, 0, 0, 0, 0) +#define SbiCall3(ext_id, func_id, arg0, arg1, arg2) \ + SbiCall(ext_id, func_id, arg0, arg1, arg2, 0, 0, 0) +#define SbiCall4(ext_id, func_id, arg0, arg1, arg2, arg3) \ + SbiCall(ext_id, func_id, arg0, arg1, arg2, arg3, 0, 0) +#define SbiCall5(ext_id, func_id, arg0, arg1, arg2, arg3, arg4) \ + SbiCall(ext_id, func_id, arg0, arg1, arg2, arg3, arg4, 0) +#define SbiCall6(ext_id, func_id, arg0, arg1, arg2, arg3, arg4, arg5) \ + SbiCall(ext_id, func_id, arg0, arg1, arg2, arg3, arg4, arg5) + +/** + EDK2 SbiCall to invoke SBI extensions. + + @param[in] ext_id Sbi extension ID. + @param[in] func_id Sbi functions ID. + @param[in] arg0 Arg0 to function. + @param[in] arg1 Arg1 to function. + @param[in] arg2 Arg2 to function. + @param[in] arg3 Arg3 to function. + @param[in] arg4 Arg4 to function. + @param[in] arg5 Arg5 to function. + + @retval Returns sbiret structure. + +**/ +inline +EFIAPI +struct sbiret SbiCall(UINTN ext_id, UINTN func_id, UINTN arg0, UINTN arg1, + UINTN arg2, UINTN arg3, UINTN arg4, UINTN arg5) +__attribute__((always_inline)); + +/** + EDK2 SbiCall to invoke SBI extensions. + + @param[in] ext_id Sbi extension ID. + @param[in] func_id Sbi functions ID. + @param[in] arg0 Arg0 to function. + @param[in] arg1 Arg1 to function. + @param[in] arg2 Arg2 to function. + @param[in] arg3 Arg3 to function. + @param[in] arg4 Arg4 to function. + @param[in] arg5 Arg5 to function. + + @retval Returns sbiret structure. + +**/ +inline +EFIAPI +struct sbiret SbiCall(UINTN ext_id, UINTN func_id, UINTN arg0, UINTN arg1, + UINTN arg2, UINTN arg3, UINTN arg4, UINTN arg5)= { + register uintptr_t a0 asm ("a0") =3D (uintptr_t)(arg0); + register uintptr_t a1 asm ("a1") =3D (uintptr_t)(arg1); + register uintptr_t a2 asm ("a2") =3D (uintptr_t)(arg2); + register uintptr_t a3 asm ("a3") =3D (uintptr_t)(arg3); + register uintptr_t a4 asm ("a4") =3D (uintptr_t)(arg4); + register uintptr_t a5 asm ("a5") =3D (uintptr_t)(arg5); + register uintptr_t a6 asm ("a6") =3D (uintptr_t)(func_id); + register uintptr_t a7 asm ("a7") =3D (uintptr_t)(ext_id); + asm volatile ("ecall" \ + : "+r" (a0) \ + : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r"= (a7) \ + : "memory"); \ + struct sbiret ret =3D { a0, a1 }; + return ret; +} + +/** + Get the implemented SBI specification version + + The minor number of the SBI specification is encoded in the low 24 bits, + with the major number encoded in the next 7 bits. Bit 32 must be 0 and = is + reserved for future expansion. + + @param[out] SpecVersion The Version of the SBI specification. +**/ +VOID +EFIAPI +SbiGetSpecVersion ( + OUT UINTN *SpecVersion + ); + +/** + Get the SBI implementation ID + + This ID is used to idenetify a specific SBI implementation in order to w= ork + around any quirks it might have. + + @param[out] ImplId The ID of the SBI implementation. +**/ +VOID +EFIAPI +SbiGetImplId ( + OUT UINTN *ImplId + ); + +/** + Get the SBI implementation version + + The version of this SBI implementation. + The encoding of this number is determined by the specific SBI implementa= tion. + + @param[out] ImplVersion The version of the SBI implementation. +**/ +VOID +EFIAPI +SbiGetImplversion ( + OUT UINTN *ImplVersion + ); + +/** + Probe whether an SBI extension is available + + ProbeResult is set to 0 if the extension is not available or to an exten= sion + specified value if it is available. + + @param[in] ExtensionId The extension ID. + @param[out] ProbeResult The return value of the probe. +**/ +VOID +EFIAPI +SbiProbeExtension ( + IN INTN ExtensionId, + OUT INTN *ProbeResult + ); + +/** + Get the CPU's vendor ID + + Reads the mvendorid CSR. + + @param[out] MvendorId The CPU's vendor ID. +**/ +VOID +EFIAPI +SbiGetMvendorId ( + OUT UINTN *MvendorId + ); + +/** + Get the CPU's architecture ID + + Reads the marchid CSR. + + @param[out] MarchId The CPU's architecture ID. +**/ +VOID +EFIAPI +SbiGetMarchId ( + OUT UINTN *MarchId + ); + +/** + Get the CPU's implementation ID + + Reads the mimpid CSR. + + @param[out] MimpId The CPU's implementation ID. +**/ +VOID +EFIAPI +SbiGetMimpId ( + OUT UINTN *Mimpid + ); + +/** + Politely ask the SBI to start a given hart. + + This call may return before the hart has actually started executing, if = the + SBI implementation can guarantee that the hart is actually going to star= t. + + Before the hart jumps to StartAddr, the hart MUST configure PMP if prese= nt + and switch to S-mode. + + @param[in] HartId The id of the hart to start. + @param[in] StartAddr The physical address, where the hart st= arts + executing from. + @param[in] Priv An XLEN-bit value, which will be in reg= ister + a1 when the hart starts. + @retval EFI_SUCCESS Hart was stopped and will start executi= ng from StartAddr. + @retval EFI_LOAD_ERROR StartAddr is not valid, possibly due to= following reasons: + - It is not a valid physical address. + - The address is prohibited by PMP to = run in + supervisor mode. + @retval EFI_INVALID_PARAMETER HartId is not a valid hart id + @retval EFI_ALREADY_STARTED The hart is already running. + @retval other The start request failed for unknown re= asons. +**/ +EFI_STATUS +EFIAPI +SbiHartStart ( + IN UINTN HartId, + IN UINTN StartAddr, + IN UINTN Priv + ); + +/** + Return execution of the calling hart to SBI. + + MUST be called in S-Mode with user interrupts disabled. + This call is not expected to return, unless a failure occurs. + + @retval EFI_SUCCESS Never occurs. When successful, the call= does not return. + @retval other Failed to stop hard for an unknown reas= on. +**/ +EFI_STATUS +EFIAPI +SbiHartStop ( + ); + +/** + Get the current status of a hart. + + Since harts can transition between states at any time, the status retrie= ved + by this function may already be out of date, once it returns. + + Possible values for HartStatus are: + 0: STARTED + 1: STOPPED + 2: START_REQUEST_PENDING + 3: STOP_REQUEST_PENDING + + @param[out] HartStatus The pointer in which the hart's status = is + stored. + @retval EFI_SUCCESS The operation succeeds. + @retval EFI_INVALID_PARAMETER A parameter is invalid. +**/ +EFI_STATUS +EFIAPI +SbiHartGetStatus ( + IN UINTN HartId, + OUT UINTN *HartStatus + ); + +/// +/// Timer extension +/// + +/** + Clear pending timer interrupt bit and set timer for next event after Sti= meValue. + + To clear the timer without scheduling a timer event, set StimeValue to a + practically infinite value or mask the timer interrupt by clearing sie.S= TIE. + + @param[in] StimeValue The time offset to the next scheduled t= imer interrupt. +**/ +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 StimeValue + ); + +/// +/// IPI extension +/// + +/** + Send IPI to all harts specified in the mask. + + The interrupts are registered as supervisor software interrupts at the + receiving hart. + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiSendIpi ( + IN UINTN *HartMask, + IN UINTN HartMaskBase + ); + +/// +/// Remote fence extension +/// + +/** + Instructs remote harts to execute a FENCE.I instruction. + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteFenceI ( + IN UINTN *HartMask, + IN UINTN HartMaskBase + ); + +/** + Instructs the remote harts to execute one or more SFENCE.VMA instruction= s. + + The SFENCE.VMA covers the range of virtual addresses between StartAaddr = and Size. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteSfenceVma ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size + ); + +/** + Instructs the remote harts to execute one or more SFENCE.VMA instruction= s. + + The SFENCE.VMA covers the range of virtual addresses between StartAaddr = and Size. + Covers only the given ASID. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteSfenceVmaAsid ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size, + IN UINTN Asid + ); + +/** + Instructs the remote harts to execute one or more SFENCE.GVMA instructio= ns. + + The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size. + Covers only the given VMID. + This function call is only valid for harts implementing the hypervisor e= xtension. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_UNSUPPORTED SBI does not implement this function or= one + of the target harts does not support the + hypervisor extension. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteHfenceGvmaVmid ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size, + IN UINTN Vmid + ); + +/** + Instructs the remote harts to execute one or more SFENCE.GVMA instructio= ns. + + The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size. + This function call is only valid for harts implementing the hypervisor e= xtension. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_UNSUPPORTED SBI does not implement this function or= one + of the target harts does not support the + hypervisor extension. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteHfenceGvma ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size + ); + +/** + Instructs the remote harts to execute one or more SFENCE.VVMA instructio= ns. + + The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size. + Covers only the given ASID. + This function call is only valid for harts implementing the hypervisor e= xtension. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_UNSUPPORTED SBI does not implement this function or= one + of the target harts does not support the + hypervisor extension. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteHfenceVvmaAsid ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size, + IN UINTN Asid + ); + +/** + Instructs the remote harts to execute one or more SFENCE.VVMA instructio= ns. + + The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size. + This function call is only valid for harts implementing the hypervisor e= xtension. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_UNSUPPORTED SBI does not implement this function or= one + of the target harts does not support the + hypervisor extension. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteHfenceVvma ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size + ); + +/// +/// Vendor Specific extension space: Extension Ids 0x09000000 through 0x09= FFFFFF +/// + +/** + Call a function in a vendor defined SBI extension + + ASSERT() if the ExtensionId is not in the designated SBI Vendor Extension + Space. + + @param[in] ExtensionId The SBI vendor extension ID. + @param[in] FunctionId The function ID to call in this extensi= on. + @param[in] NumArgs How many arguments are passed. + @param[in] ... Actual Arguments to the function. + @retval EFI_SUCCESS if the SBI function was called and it was successful + @retval EFI_INVALID_PARAMETER if NumArgs exceeds 6 + @retval others if the called SBI function returns an error +**/ +EFI_STATUS +EFIAPI +SbiVendorCall ( + IN UINTN ExtensionId, + IN UINTN FunctionId, + IN UINTN NumArgs, + ... + ); + +/// +/// Firmware SBI Extension +/// +/// This SBI Extension is defined and used by EDK2 only in order to be abl= e to +/// run PI and DXE phase in S-Mode. +/// + +/** + Get scratch space of the current hart. + + Please consider using the wrapper SbiGetFirmwareContext if you only need= to + access the firmware context. + + @param[out] ScratchSpace The scratch space pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +EFI_STATUS +EFIAPI +SbiGetMscratch ( + OUT struct sbi_scratch **ScratchSpace + ); + +/** + Get scratch space of the given hart id. + + @param[in] HartId The hart id. + @param[out] ScratchSpace The scratch space pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +EFI_STATUS +EFIAPI +SbiGetMscratchHartid ( + IN UINTN HartId, + OUT struct sbi_scratch **ScratchSpace + ); + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +EFI_STATUS +EFIAPI +SbiGetFirmwareContext ( + OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext + ); + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +EFI_STATUS +EFIAPI +SbiSetFirmwareContext ( + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext + ); + +#endif diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2S= biLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiL= ib.c new file mode 100644 index 000000000000..bbe006a78af8 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c @@ -0,0 +1,789 @@ +/** @file + Instance of the SBI ecall library. + + It allows calling an SBI function via an ecall from S-Mode. + + The legacy extensions are not included because they are not necessary. + They would be: + - SbiLegacySetTimer -> Use SbiSetTimer + - SbiLegacyConsolePutChar -> No replacement - Use regular UEFI func= tions + - SbiLegacyConsoleGetChar -> No replacement - Use regular UEFI func= tions + - SbiLegacyClearIpi -> Write 0 to SSIP + - SbiLegacySendIpi -> Use SbiSendIpi + - SbiLegacyRemoteFenceI -> Use SbiRemoteFenceI + - SbiLegacyRemoteSfenceVma -> Use SbiRemoteSfenceVma + - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid + - SbiLegacyShutdown -> Wait for new System Reset extension + + Copyright (c) 2020, Hewlett Packard Development LP. All rights reserved.=
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Translate SBI error code to EFI status. + + @param[in] SbiError SBI error code + @retval EFI_STATUS +**/ + +EFI_STATUS +EFIAPI +TranslateError( + IN UINTN SbiError + ) { + switch (SbiError) { + case SBI_SUCCESS: + return EFI_SUCCESS; + case SBI_ERR_FAILED: + return EFI_DEVICE_ERROR; + break; + case SBI_ERR_NOT_SUPPORTED: + return EFI_UNSUPPORTED; + break; + case SBI_ERR_INVALID_PARAM: + return EFI_INVALID_PARAMETER; + break; + case SBI_ERR_DENIED: + return EFI_ACCESS_DENIED; + break; + case SBI_ERR_INVALID_ADDRESS: + return EFI_LOAD_ERROR; + break; + case SBI_ERR_ALREADY_AVAILABLE: + return EFI_ALREADY_STARTED; + break; + default: + // + // Reaches here only if SBI has defined a new error type + // + ASSERT (FALSE); + return EFI_UNSUPPORTED; + break; + } +} + +// +// OpenSBI libraary interface function for the base extension +// + +/** + Get the implemented SBI specification version + + The minor number of the SBI specification is encoded in the low 24 bits, + with the major number encoded in the next 7 bits. Bit 32 must be 0 and = is + reserved for future expansion. + + @param[out] SpecVersion The Version of the SBI specification. +**/ +VOID +EFIAPI +SbiGetSpecVersion ( + OUT UINTN *SpecVersion + ) +{ + struct sbiret ret =3D SbiCall0 (SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERS= ION); + + if (!ret.error) { + *SpecVersion =3D (UINTN) ret.value; + } + + //return TranslateError(ret.error); +} + +/** + Get the SBI implementation ID + + This ID is used to idenetify a specific SBI implementation in order to w= ork + around any quirks it might have. + + @param[out] ImplId The ID of the SBI implementation. +**/ +VOID +EFIAPI +SbiGetImplId ( + OUT UINTN *ImplId + ) +{ + struct sbiret ret =3D SbiCall0 (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID); + *ImplId =3D (UINTN) ret.value; +} + +/** + Get the SBI implementation version + + The version of this SBI implementation. + The encoding of this number is determined by the specific SBI implementa= tion. + + @param[out] ImplVersion The version of the SBI implementation. +**/ +VOID +EFIAPI +SbiGetImplVersion ( + OUT UINTN *ImplVersion + ) +{ + struct sbiret ret =3D SbiCall0 (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSI= ON); + *ImplVersion =3D (UINTN) ret.value; +} + +/** + Probe whether an SBI extension is available + + ProbeResult is set to 0 if the extension is not available or to an exten= sion + specified value if it is available. + + @param[in] ExtensionId The extension ID. + @param[out] ProbeResult The return value of the probe. +**/ +VOID +EFIAPI +SbiProbeExtension ( + IN INTN ExtensionId, + OUT INTN *ProbeResult + ) +{ + struct sbiret ret =3D SbiCall0 (SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT); + *ProbeResult =3D (UINTN) ret.value; +} + +/** + Get the CPU's vendor ID + + Reads the mvendorid CSR. + + @param[out] MvendorId The CPU's vendor ID. +**/ +VOID +EFIAPI +SbiGetMvendorId ( + OUT UINTN *MvendorId + ) +{ + struct sbiret ret =3D SbiCall0 (SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID= ); + *MvendorId =3D (UINTN) ret.value; +} + +/** + Get the CPU's vendor ID + + Reads the mvendorid CSR. + + @param[out] MvendorId The CPU's vendor ID. +**/ +VOID +EFIAPI +SbiGetMarchId ( + OUT UINTN *MarchId + ) +{ + struct sbiret ret =3D SbiCall0 (SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID); + *MarchId =3D (UINTN) ret.value; +} + +/** + Get the CPU's architecture ID + + Reads the marchid CSR. + + @param[out] MarchId The CPU's architecture ID. +**/ +VOID +EFIAPI +SbiGetMimpId ( + OUT UINTN *MimpId + ) +{ + struct sbiret ret =3D SbiCall0 (SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID); + *MimpId =3D (UINTN) ret.value; +} + +// +// SBI interface function for the hart state management extension +// + +/** + Politely ask the SBI to start a given hart. + + This call may return before the hart has actually started executing, if = the + SBI implementation can guarantee that the hart is actually going to star= t. + + Before the hart jumps to StartAddr, the hart MUST configure PMP if prese= nt + and switch to S-mode. + + @param[in] HartId The id of the hart to start. + @param[in] StartAddr The physical address, where the hart st= arts + executing from. + @param[in] Priv An XLEN-bit value, which will be in reg= ister + a1 when the hart starts. + @retval EFI_SUCCESS Hart was stopped and will start executi= ng from StartAddr. + @retval EFI_LOAD_ERROR StartAddr is not valid, possibly due to= following reasons: + - It is not a valid physical address. + - The address is prohibited by PMP to= run in + supervisor mode. + @retval EFI_INVALID_PARAMETER HartId is not a valid hart id + @retval EFI_ALREADY_STARTED The hart is already running. + @retval other The start request failed for unknown re= asons. +**/ +EFI_STATUS +EFIAPI +SbiHartStart ( + IN UINTN HartId, + IN UINTN StartAddr, + IN UINTN Priv + ) +{ + struct sbiret ret =3D SbiCall3 (SBI_EXT_HSM, + SBI_EXT_HSM_HART_START, + HartId, + StartAddr, + Priv); + return TranslateError(ret.error); +} + +/** + Return execution of the calling hart to SBI. + + MUST be called in S-Mode with user interrupts disabled. + This call is not expected to return, unless a failure occurs. + + @retval EFI_SUCCESS Never occurs. When successful, the call= does not return. + @retval other Failed to stop hard for an unknown reas= on. +**/ +EFI_STATUS +EFIAPI +SbiHartStop ( + ) +{ + struct sbiret Ret =3D SbiCall0 (SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP); + return TranslateError(Ret.error); +} + +/** + Get the current status of a hart. + + Since harts can transition between states at any time, the status retrie= ved + by this function may already be out of date, once it returns. + + Possible values for HartStatus are: + 0: STARTED + 1: STOPPED + 2: START_REQUEST_PENDING + 3: STOP_REQUEST_PENDING + + @param[out] HartStatus The pointer in which the hart's status = is + stored. + @retval EFI_SUCCESS The operation succeeds. + @retval EFI_INVALID_PARAMETER A parameter is invalid. +**/ +EFI_STATUS +EFIAPI +SbiHartGetStatus ( + IN UINTN HartId, + OUT UINTN *HartStatus + ) +{ + struct sbiret ret =3D SbiCall1 (SBI_EXT_HSM, SBI_EXT_HSM_HART_GET_STATUS= , HartId); + + if (!ret.error) { + *HartStatus =3D (UINTN) ret.value; + } + + return TranslateError(ret.error); +} + +/** + Clear pending timer interrupt bit and set timer for next event after Sti= meValue. + + To clear the timer without scheduling a timer event, set StimeValue to a + practically infinite value or mask the timer interrupt by clearing sie.S= TIE. + + @param[in] StimeValue The time offset to the next scheduled t= imer interrupt. +**/ +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 StimeValue + ) +{ + SbiCall1 (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, StimeValue); +} + +EFI_STATUS +EFIAPI +SbiSendIpi ( + IN UINTN *HartMask, + IN UINTN HartMaskBase + ) +{ + struct sbiret ret =3D SbiCall2 (SBI_EXT_IPI, + SBI_EXT_IPI_SEND_IPI, + (UINTN) HartMask, + HartMaskBase); + return TranslateError(ret.error); +} + +/** + Instructs remote harts to execute a FENCE.I instruction. + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteFenceI ( + IN UINTN *HartMask, + IN UINTN HartMaskBase + ) +{ + struct sbiret ret =3D SbiCall2 (SBI_EXT_RFENCE, + SBI_EXT_RFENCE_REMOTE_FENCE_I, + (UINTN) HartMask, + HartMaskBase); + return TranslateError(ret.error); +} + +/** + Instructs the remote harts to execute one or more SFENCE.VMA instruction= s. + + The SFENCE.VMA covers the range of virtual addresses between StartAaddr = and Size. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteSfenceVma ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size + ) +{ + struct sbiret ret =3D SbiCall4 (SBI_EXT_RFENCE, + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, + (UINTN) HartMask, + HartMaskBase, + StartAddr, + Size); + return TranslateError(ret.error); +} + +/** + Instructs the remote harts to execute one or more SFENCE.VMA instruction= s. + + The SFENCE.VMA covers the range of virtual addresses between StartAaddr = and Size. + Covers only the given ASID. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteSfenceVmaAsid ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size, + IN UINTN Asid + ) +{ + struct sbiret ret =3D SbiCall5 (SBI_EXT_RFENCE, + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, + (UINTN) HartMask, + HartMaskBase, + StartAddr, + Size, + Asid); + return TranslateError(ret.error); +} + +/** + Instructs the remote harts to execute one or more SFENCE.GVMA instructio= ns. + + The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size. + Covers only the given VMID. + This function call is only valid for harts implementing the hypervisor e= xtension. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_UNSUPPORTED SBI does not implement this function or= one + of the target harts does not support the + hypervisor extension. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteHFenceGvmaVmid ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size, + IN UINTN Vmid + ) +{ + struct sbiret ret =3D SbiCall5 (SBI_EXT_RFENCE, + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, + (UINTN) HartMask, + HartMaskBase, + StartAddr, + Size, + Vmid); + return TranslateError(ret.error); +} + +/** + Instructs the remote harts to execute one or more SFENCE.GVMA instructio= ns. + + The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size. + This function call is only valid for harts implementing the hypervisor e= xtension. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_UNSUPPORTED SBI does not implement this function or= one + of the target harts does not support the + hypervisor extension. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteHFenceGvma ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size + ) +{ + struct sbiret ret =3D SbiCall4 (SBI_EXT_RFENCE, + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, + (UINTN) HartMask, + HartMaskBase, + StartAddr, + Size); + return TranslateError(ret.error); +} + +/** + Instructs the remote harts to execute one or more SFENCE.VVMA instructio= ns. + + The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size. + Covers only the given ASID. + This function call is only valid for harts implementing the hypervisor e= xtension. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_UNSUPPORTED SBI does not implement this function or= one + of the target harts does not support the + hypervisor extension. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteHFenceVvmaAsid ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size, + IN UINTN Asid + ) +{ + struct sbiret ret =3D SbiCall5 (SBI_EXT_RFENCE, + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, + (UINTN) HartMask, + HartMaskBase, + StartAddr, + Size, + Asid); + return TranslateError(ret.error); +} + +/** + Instructs the remote harts to execute one or more SFENCE.VVMA instructio= ns. + + The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size. + This function call is only valid for harts implementing the hypervisor e= xtension. + + The remote fence function acts as a full tlb flush if * StartAddr and si= ze + are both 0 * size is equal to 2^XLEN-1 + + @param[in] HartMask Scalar bit-vector containing hart ids + @param[in] HartMaskBase The starting hartid from which the bit-= vector + must be computed. If set to -1, HartMas= k is + ignored and all harts are considered. + @param[in] StartAddr The first address of the affected range. + @param[in] Size How many addresses are affected. + @retval EFI_SUCCESS IPI was sent to all the targeted harts. + @retval EFI_LOAD_ERROR StartAddr or Size is not valid. + @retval EFI_UNSUPPORTED SBI does not implement this function or= one + of the target harts does not support the + hypervisor extension. + @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the har= tid + from hart_mask is not valid i.e. either= the + hartid is not enabled by the platform o= r is + not available to the supervisor. +**/ +EFI_STATUS +EFIAPI +SbiRemoteHFenceVvma ( + IN UINTN *HartMask, + IN UINTN HartMaskBase, + IN UINTN StartAddr, + IN UINTN Size + ) +{ + struct sbiret ret =3D SbiCall4 (SBI_EXT_RFENCE, + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, + (UINTN) HartMask, + HartMaskBase, + StartAddr, + Size); + return TranslateError(ret.error); +} + +// +// SBI interface function for the vendor extension +// + +/** + Call a function in a vendor defined SBI extension + + ASSERT() if the ExtensionId is not in the designated SBI Vendor Extension + Space. + + @param[in] ExtensionId The SBI vendor extension ID. + @param[in] FunctionId The function ID to call in this extensi= on. + @param[in] NumArgs How many arguments are passed. + @param[in] ... Actual Arguments to the function. + @retval EFI_SUCCESS if the SBI function was called and it was successful + @retval EFI_INVALID_PARAMETER if NumArgs exceeds 6 + @retval others if the called SBI function returns an error +**/ +EFI_STATUS +EFIAPI +SbiVendorCall ( + IN UINTN ExtensionId, + IN UINTN FunctionId, + IN UINTN NumArgs, + ... + ) +{ + struct sbiret ret; + VA_LIST Args; + VA_START(Args, NumArgs); + + ASSERT (ExtensionId >=3D 0x09000000 && ExtensionId <=3D 0x09FFFFFF); + + switch (NumArgs) { + case 0: + ret =3D SbiCall0 (ExtensionId, FunctionId); + break; + case 1: + ret =3D SbiCall1 (ExtensionId, FunctionId, VA_ARG(Args, UINTN)); + break; + case 2: + ret =3D SbiCall2 (ExtensionId, FunctionId, VA_ARG(Args, UINTN), VA= _ARG(Args, UINTN)); + break; + case 3: + ret =3D SbiCall3 (ExtensionId, FunctionId, VA_ARG(Args, UINTN), VA= _ARG(Args, UINTN), VA_ARG(Args, UINTN)); + break; + case 4: + ret =3D SbiCall4 (ExtensionId, FunctionId, VA_ARG(Args, UINTN), VA= _ARG(Args, UINTN), VA_ARG(Args, UINTN), VA_ARG(Args, UINTN)); + break; + case 5: + ret =3D SbiCall5 (ExtensionId, FunctionId, VA_ARG(Args, UINTN), VA= _ARG(Args, UINTN), VA_ARG(Args, UINTN), VA_ARG(Args, UINTN), VA_ARG(Args, U= INTN)); + break; + case 6: + ret =3D SbiCall6 (ExtensionId, FunctionId, VA_ARG(Args, UINTN), VA= _ARG(Args, UINTN), VA_ARG(Args, UINTN), VA_ARG(Args, UINTN), VA_ARG(Args, U= INTN), VA_ARG(Args, UINTN)); + break; + default: + // Too many args. In theory SBI can handle more arguments when the= y are + // passed on the stack but no SBI extension uses this, therefore i= t's + // not yet implemented here. + return EFI_INVALID_PARAMETER; + } + + VA_END(Args); + return TranslateError(ret.error); +} + +// +// SBI Firmware extension +// + +/** + Get scratch space of the current hart. + + Please consider using the wrapper SbiGetFirmwareContext if you only need= to + access the firmware context. + + @param[out] ScratchSpace The scratch space pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +EFI_STATUS +EFIAPI +SbiGetMscratch ( + OUT struct sbi_scratch **ScratchSpace + ) +{ + struct sbiret ret =3D SbiCall0 (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUN= C); + + if (!ret.error) { + *ScratchSpace =3D (struct sbi_scratch *) ret.value; + } + + return EFI_SUCCESS; +} + +/** + Get scratch space of the given hart id. + + @param[in] HartId The hart id. + @param[out] ScratchSpace The scratch space pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +EFI_STATUS +EFIAPI +SbiGetMscratchHartid ( + IN UINTN HartId, + OUT struct sbi_scratch **ScratchSpace + ) +{ + struct sbiret ret =3D SbiCall1 (SBI_EDK2_FW_EXT, + SBI_EXT_FW_MSCRATCH_HARTID_FUNC, + HartId); + + if (!ret.error) { + *ScratchSpace =3D (struct sbi_scratch *) ret.value; + } + + return EFI_SUCCESS; +} + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +EFI_STATUS +EFIAPI +SbiGetFirmwareContext ( + OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext + ) +{ + struct sbi_scratch *ScratchSpace; + struct sbi_platform *SbiPlatform; + struct sbiret ret =3D SbiCall0 (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUN= C); + + if (!ret.error) { + ScratchSpace =3D (struct sbi_scratch *) ret.value; + SbiPlatform =3D (struct sbi_platform *) sbi_platform_ptr(ScratchSpace); + *FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *) SbiPlatfor= m->firmware_context; + } + + return EFI_SUCCESS; +} + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +EFI_STATUS +EFIAPI +SbiSetFirmwareContext ( + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext + ) +{ + struct sbi_scratch *ScratchSpace; + struct sbi_platform *SbiPlatform; + struct sbiret ret =3D SbiCall0 (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUN= C); + + if (!ret.error) { + ScratchSpace =3D (struct sbi_scratch *) ret.value; + SbiPlatform =3D (struct sbi_platform *) sbi_platform_ptr(ScratchSpace); + SbiPlatform->firmware_context =3D (long unsigned int) FirmwareContext; + } + + return EFI_SUCCESS; +} --=20 2.26.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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