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Thu, 14 May 2020 08:44:10 +0000 X-Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1415.2; Thu, 14 May 2020 08:40:20 +0000 X-Received: from E107187.Arm.com (10.57.42.179) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 14 May 2020 08:40:20 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , Subject: [edk2-devel] [PATCH v2 01/11] PcAtChipsetPkg: Add MMIO Support to RTC driver Date: Thu, 14 May 2020 09:40:09 +0100 Message-ID: <20200514084019.71368-2-sami.mujawar@arm.com> In-Reply-To: <20200514084019.71368-1-sami.mujawar@arm.com> References: <20200514084019.71368-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(6029001)(4636009)(136003)(376002)(346002)(39860400002)(396003)(46966005)(356005)(70206006)(70586007)(8936002)(5660300002)(82740400003)(336012)(2616005)(36756003)(426003)(47076004)(8676002)(86362001)(54906003)(7696005)(2906002)(966005)(82310400002)(81166007)(4326008)(1076003)(30864003)(6666004)(478600001)(186003)(26005)(316002)(44832011)(6916009);DIR:OUT;SFP:1101; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: sOwbRfLATJzO7WVDQhvKtVHnx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445875; bh=yEHjmR5LTwYUGEmVpWcgRkeQv4umyddBMKpQsOxf2eA=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=tCONVo+28QiLs5GdQqoGm99L9rYUa8y2Fj5rHZeLAmzkHZwrTaNJ59q/Ha5TYtHUEJN e837JUfU8ER35WGrDcs1hcLtvsFgxGGL/iO29B0L9+HcVjO8ISrQu2bRqr5wCeMpi/0Mv z+/dvbG38YyO8a+kMRcB3+OR2oeaQKaNXHg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some virtual machine managers like kvmtool emulate the MC146818 RTC controller in the MMIO space so that architectures that do not support I/O Mapped I/O can use the RTC. This patch adds MMIO support to the RTC controller driver. The PCD PcdRtcUseMmio has been added to select I/O or MMIO support. If PcdRtcUseMmio is: TRUE - Indicates the RTC port registers are in MMIO space. FALSE - Indicates the RTC port registers are in I/O space. Default is I/O space. When MMIO support is selected (PcdRtcUseMmio =3D=3D TRUE) the driver maps the MMIO region used by the RTC as runtime memory so that the RTC registers are accessible post ExitBootServices. Signed-off-by: Sami Mujawar Acked-by: Ard Biesheuvel --- Notes: v2: - Code review comments incorporated. [Sa= mi] =20 v1: - Add support to read/write from RTC registers using MMIO access [Sa= mi] - Use wrapper functions for RtcRead/Write accessors [Le= if] Ref: https://edk2.groups.io/g/devel/topic/30915281#30695 PcAtChipsetPkg/PcAtChipsetPkg.dec = | 8 ++ PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c = | 117 ++++++++++++++++-- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h = | 31 +++++ PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c = | 130 +++++++++++++++++++- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf= | 8 ++ 5 files changed, 280 insertions(+), 14 deletions(-) diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec b/PcAtChipsetPkg/PcAtChipset= Pkg.dec index 88de5cceea593176c3a2425a5963b66b789f2b9e..76d0c7eda69bb505914ba904e09= c89de170f69ae 100644 --- a/PcAtChipsetPkg/PcAtChipsetPkg.dec +++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec @@ -6,6 +6,7 @@ # # Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Inc. All rights reserved.
+# Copyright (c) 2018, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -142,5 +143,12 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] # @Prompt RTC Update Timeout Value. gPcAtChipsetPkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|100000|UINT3= 2|0x00000020 =20 + ## Indicates the RTC port registers are in MMIO space, or in I/O space. + # Default is I/O space.

+ # TRUE - RTC port registers are in MMIO space.
+ # FALSE - RTC port registers are in I/O space.
+ # @Prompt RTC port registers use MMIO. + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcUseMmio|FALSE|BOOLEAN|0x00000021 + [UserExtensions.TianoCore."ExtraFiles"] PcAtChipsetPkgExtra.uni diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChips= etPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c index 52af17941786ef81c3911512ee64551724e67209..df8dea83ab27bbba12351096d1b= fd9ea31accb60 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c @@ -3,6 +3,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Inc. All rights reserved.
+Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -10,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #include "PcRtc.h" =20 +extern EFI_PHYSICAL_ADDRESS mRtcRegisterBase; + // // Days of month. // @@ -21,6 +24,28 @@ UINTN mDayOfMonth[] =3D { 31, 29, 31, 30, 31, 30, 31, 31= , 30, 31, 30, 31 }; CHAR16 mTimeZoneVariableName[] =3D L"RTC"; =20 /** + A function pointer that evaluates to a function that reads the RTC conte= nt + through its registers either using IO or MMIO access. + + @param Address Address offset of RTC. It is recommended to use + macros such as RTC_ADDRESS_SECONDS. + + @return The data of UINT8 type read from RTC. +**/ +RTC_READ RtcRead; + +/** + A function pointer that evaluates to a function that reads the RTC conte= nt + through its registers either using IO or MMIO access. + + @param Address Address offset of RTC. It is recommended to use + macros such as RTC_ADDRESS_SECONDS. + + @return The data of UINT8 type read from RTC. +**/ +RTC_WRITE RtcWrite; + +/** Compare the Hour, Minute and Second of the From time and the To time. =20 Only compare H/M/S in EFI_TIME and ignore other fields here. @@ -54,41 +79,99 @@ IsWithinOneDay ( ); =20 /** - Read RTC content through its registers. + Read RTC content through its registers using IO access. =20 - @param Address Address offset of RTC. It is recommended to use macros = such as - RTC_ADDRESS_SECONDS. + @param Address Address offset of RTC. It is recommended to use + macros such as RTC_ADDRESS_SECONDS. =20 @return The data of UINT8 type read from RTC. **/ +STATIC UINT8 -RtcRead ( +IoRtcRead ( IN UINT8 Address ) { - IoWrite8 (PcdGet8 (PcdRtcIndexRegister), (UINT8) (Address | (UINT8) (IoR= ead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x80))); + IoWrite8 ( + PcdGet8 (PcdRtcIndexRegister), + (UINT8)(Address | (UINT8)(IoRead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x= 80)) + ); return IoRead8 (PcdGet8 (PcdRtcTargetRegister)); } =20 /** - Write RTC through its registers. + Write RTC through its registers using IO access. =20 - @param Address Address offset of RTC. It is recommended to use macros = such as - RTC_ADDRESS_SECONDS. - @param Data The content you want to write into RTC. + @param Address Address offset of RTC. It is recommended to use + macros such as RTC_ADDRESS_SECONDS. + @param Data The content you want to write into RTC. =20 **/ +STATIC VOID -RtcWrite ( +IoRtcWrite ( IN UINT8 Address, IN UINT8 Data ) { - IoWrite8 (PcdGet8 (PcdRtcIndexRegister), (UINT8) (Address | (UINT8) (IoR= ead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x80))); + IoWrite8 ( + PcdGet8 (PcdRtcIndexRegister), + (UINT8)(Address | (UINT8)(IoRead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x= 80)) + ); IoWrite8 (PcdGet8 (PcdRtcTargetRegister), Data); } =20 /** + Read RTC content through its registers using MMIO access. + + @param Address Address offset of RTC. It is recommended to use + macros such as RTC_ADDRESS_SECONDS. + + @return The data of UINT8 type read from RTC. +**/ +STATIC +UINT8 +MmioRtcRead ( + IN UINT8 Address + ) +{ + MmioWrite8 ( + mRtcRegisterBase, + (UINT8)(Address | (UINT8)(MmioRead8 (mRtcRegisterBase) & 0x80)) + ); + return MmioRead8 ( + mRtcRegisterBase + (PcdGet8 (PcdRtcTargetRegister) - + PcdGet8 (PcdRtcIndexRegister)) + ); +} + +/** + Write RTC through its registers using MMIO access. + + @param Address Address offset of RTC. It is recommended to use + macros such as RTC_ADDRESS_SECONDS. + @param Data The content you want to write into RTC. + +**/ +STATIC +VOID +MmioRtcWrite ( + IN UINT8 Address, + IN UINT8 Data + ) +{ + MmioWrite8 ( + mRtcRegisterBase, + (UINT8)(Address | (UINT8)(MmioRead8 (mRtcRegisterBase) & 0x80)) + ); + MmioWrite8 ( + mRtcRegisterBase + (PcdGet8 (PcdRtcTargetRegister) - + PcdGet8 (PcdRtcIndexRegister)), + Data + ); +} + +/** Initialize RTC. =20 @param Global For global use inside this module. @@ -113,6 +196,18 @@ PcRtcInit ( BOOLEAN Pending; =20 // + // Initialize the RtcRead and RtcWrite functions + // based on the chosen IO/MMIO access. + // + if (FixedPcdGetBool (PcdRtcUseMmio)) { + RtcRead =3D MmioRtcRead; + RtcWrite =3D MmioRtcWrite; + } else { + RtcRead =3D IoRtcRead; + RtcWrite =3D IoRtcWrite; + } + + // // Acquire RTC Lock to make access to RTC atomic // if (!EfiAtRuntime ()) { diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChips= etPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h index 47293ce44c5a1f4792892892f7da40d7f0a5a001..e64dbbea48f7f0d2f317c65c2e4= b93e7b1888efc 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h @@ -3,6 +3,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Inc. All rights reserved.
+Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -371,4 +372,34 @@ PcRtcAcpiTableChangeCallback ( IN EFI_EVENT Event, IN VOID *Context ); + +/** + Function pointer to Read RTC content through its registers. + + @param Address Address offset of RTC. It is recommended to use + macros such as RTC_ADDRESS_SECONDS. + + @return The data of UINT8 type read from RTC. +**/ +typedef +UINT8 +(EFIAPI *RTC_READ) ( + IN UINT8 Address + ); + +/** + Function pointer to Write RTC through its registers. + + @param Address Address offset of RTC. It is recommended to use + macros such as RTC_ADDRESS_SECONDS. + @param Data The content you want to write into RTC. + +**/ +typedef +VOID +(EFIAPI *RTC_WRITE) ( + IN UINT8 Address, + IN UINT8 Data + ); + #endif diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c b/PcAt= ChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c index ccda6331373bfe4069b0a59495b5e5cc731c8fc8..5d5dbeaf970ca8eb291c1e094fd= 764d201f9071e 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c @@ -2,16 +2,32 @@ Provides Set/Get time operations. =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 +#include #include "PcRtc.h" =20 PC_RTC_MODULE_GLOBALS mModuleGlobal; =20 EFI_HANDLE mHandle =3D NULL; =20 +STATIC EFI_EVENT mVirtualAddrChangeEvent; + +EFI_PHYSICAL_ADDRESS mRtcRegisterBase; + +// +// Function pointer for the Rtc Read interface function +// +extern RTC_READ RtcRead; + +// +// Function pointer for the Rtc Write interface function +// +extern RTC_WRITE RtcWrite; + /** Returns the current time and date information, and the time-keeping capa= bilities of the hardware platform. @@ -106,6 +122,33 @@ PcRtcEfiSetWakeupTime ( } =20 /** + Fixup internal data so that EFI can be called in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // Only needed if you are going to support the OS calling RTC functions = in + // virtual mode. You will need to call EfiConvertPointer (). To convert = any + // stored physical addresses to virtual address. After the OS transition= s to + // calling in virtual mode, all future runtime calls will be made in vir= tual + // mode. + EfiConvertPointer (0x0, (VOID**)&mRtcRegisterBase); + + // Convert the RtcRead and RtcWrite pointers for runtime use. + EfiConvertPointer (0x0, (VOID**)&RtcRead); + EfiConvertPointer (0x0, (VOID**)&RtcWrite); +} + +/** The user Entry Point for PcRTC module. =20 This is the entry point for PcRTC module. It installs the UEFI runtime s= ervice @@ -125,12 +168,77 @@ InitializePcRtc ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; - EFI_EVENT Event; + EFI_STATUS Status; + EFI_EVENT Event; + EFI_PHYSICAL_ADDRESS RtcPageBase; =20 EfiInitializeLock (&mModuleGlobal.RtcLock, TPL_CALLBACK); mModuleGlobal.CenturyRtcAddress =3D GetCenturyRtcAddress (); =20 + if (FixedPcdGetBool (PcdRtcUseMmio)) { + mRtcRegisterBase =3D PcdGet8 (PcdRtcIndexRegister); + RtcPageBase =3D mRtcRegisterBase & ~(EFI_PAGE_SIZE - 1); + + // Declare the controller as EFI_MEMORY_RUNTIME + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + RtcPageBase, + EFI_PAGE_SIZE, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, "Failed to add memory space. Status =3D %r\n", + Status + )); + return Status; + } + + Status =3D gDS->AllocateMemorySpace ( + EfiGcdAllocateAddress, + EfiGcdMemoryTypeMemoryMappedIo, + 0, + EFI_PAGE_SIZE, + &RtcPageBase, + ImageHandle, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Failed to allocate memory space. Status =3D %r\n", + Status + )); + gDS->RemoveMemorySpace ( + RtcPageBase, + EFI_PAGE_SIZE + ); + return Status; + } + + Status =3D gDS->SetMemorySpaceAttributes ( + RtcPageBase, + EFI_PAGE_SIZE, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Failed to set memory attributes. Status =3D %r\n", + Status + )); + gDS->FreeMemorySpace ( + RtcPageBase, + EFI_PAGE_SIZE + ); + gDS->RemoveMemorySpace ( + RtcPageBase, + EFI_PAGE_SIZE + ); + return Status; + } + } + Status =3D PcRtcInit (&mModuleGlobal); ASSERT_EFI_ERROR (Status); =20 @@ -165,7 +273,23 @@ InitializePcRtc ( NULL, NULL ); - ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (FixedPcdGetBool (PcdRtcUseMmio)) { + // Register for the virtual address change event + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + LibRtcVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + } =20 return Status; } diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRu= ntimeDxe.inf b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClock= RuntimeDxe.inf index c73ee98105e510f9e4e23c1a6c1e5c505325d2c9..3a373d11f8bfc7df0e4d00be8b4= 3e90bfa06b192 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDx= e.inf +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDx= e.inf @@ -6,6 +6,7 @@ # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Inc. All rights reserved.
+# Copyright (c) 2018, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -48,6 +49,7 @@ [LibraryClasses] BaseLib PcdLib ReportStatusCodeLib + DxeServicesTableLib =20 [Protocols] gEfiRealTimeClockArchProtocolGuid ## PRODUCES @@ -61,10 +63,13 @@ [Guids] ## SOMETIMES_CONSUMES ## SystemTable gEfiAcpiTableGuid =20 + gEfiEventVirtualAddressChangeGuid + [FixedPcd] gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA ## CONSUMES gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB ## CONSUMES gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD ## CONSUMES + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcUseMmio ## CONSUMES =20 [Pcd] gPcAtChipsetPkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout ## CONSUMES @@ -76,5 +81,8 @@ [Pcd] [Depex] gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid =20 +[Depex.common.DXE_RUNTIME_DRIVER] + gEfiCpuArchProtocolGuid + [UserExtensions.TianoCore."ExtraFiles"] PcRtcExtra.uni --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 14 May 2020 08:40:48 +0000 X-Received: from AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1415.2; Thu, 14 May 2020 08:40:23 +0000 X-Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1779.2; Thu, 14 May 2020 08:40:21 +0000 X-Received: from E107187.Arm.com (10.57.42.179) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 14 May 2020 08:40:21 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , , Subject: [edk2-devel] [PATCH v1 02/11] MdePkg: Add NULL implementation for PCILib Date: Thu, 14 May 2020 09:40:10 +0100 Message-ID: <20200514084019.71368-3-sami.mujawar@arm.com> In-Reply-To: <20200514084019.71368-1-sami.mujawar@arm.com> References: <20200514084019.71368-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(4636009)(346002)(39860400002)(376002)(136003)(396003)(46966005)(356005)(8936002)(70586007)(47076004)(70206006)(4326008)(2616005)(86362001)(82740400003)(316002)(81166007)(426003)(5660300002)(336012)(44832011)(54906003)(186003)(2906002)(82310400002)(478600001)(30864003)(7696005)(6916009)(8676002)(36756003)(26005)(6666004)(1076003)(579004);DIR:OUT;SFP:1101; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: nkY8wTiHXdS4VmDmDMHOGD3Kx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445662; bh=8SJNkA0m6d5CRXr+z6eFAFw8C+mWiGPm9VTeHY4lI/s=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=VLQKd3iH3m7m9s/+iREoKv9dkId8GM//9K/uNOdtigdXcrml44S8XY9WrEGtA73Hw+4 HcbMpo1vzky5lMlb9oRTA/WM+/e9YNAeFknnyIl5FRseXNUykEKCKkqa1Zpv8stD83r7S euxBWE93osNlW87Km7UPGcwrcbPjUqZmxgg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On some platforms the Serial 16550 UART is interfaced over PCI. To support such platforms the Serial 16550 driver links with PciLib. For platforms that do not interface the Serial 16550 UART over PCI, the driver still needs to link with a PciLib library. Linking to the full implementation of the PCI library may not be possible during the early firmware boot stage. To facilitate early firmware logs over the serial port this patch introduces a NULL PCI library implementation. Signed-off-by: Sami Mujawar Acked-by: Ard Biesheuvel --- MdePkg/Library/PciLibNull/PciLibNull.c | 1213 ++++++++++++++++++++ MdePkg/Library/PciLibNull/PciLibNull.inf | 25 + 2 files changed, 1238 insertions(+) diff --git a/MdePkg/Library/PciLibNull/PciLibNull.c b/MdePkg/Library/PciLib= Null/PciLibNull.c new file mode 100644 index 0000000000000000000000000000000000000000..c186ca9f86e5a0c860472b80209= aae9b958a95d7 --- /dev/null +++ b/MdePkg/Library/PciLibNull/PciLibNull.c @@ -0,0 +1,1213 @@ +/** @file + Provides a NULL implementation of PCI services used to access + PCI Configuration Space. + + Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Registers a PCI device so PCI configuration registers may be accessed af= ter + SetVirtualAddressMap(). + + Registers the PCI device specified by Address so all the PCI configurati= on + registers associated with that PCI device may be accessed after + SetVirtualAddressMap() is called. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runti= me + access. + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PCI + device at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return RETURN_UNSUPPORTED; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Addr= ess. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciRead8 ( + IN UINTN Address + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciOr8 ( + IN UINTN Address, + IN UINT8 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit + value. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit + value, followed by a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT8 +EFIAPI +PciBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 8-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciRead16 ( + IN UINTN Address + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with t= he + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciOr16 ( + IN UINTN Address, + IN UINT16 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit + value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT16 +EFIAPI +PciBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 16-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 16-bit register. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciRead32 ( + IN UINTN Address + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with t= he + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit + value. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit + value, followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT32 +EFIAPI +PciBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 32-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 32-bit register. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by + StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Reads a range of PCI configuration registers into a caller supplied buff= er. + + Reads the range of PCI configuration registers specified by StartAddress= and + Size into the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to= read + from StartAdress to StartAddress + Size. Due to alignment restrictions, = 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning an= d the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddres= s and + Size from the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrict= ions, + 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer containing the data to write. + + @return Size written to StartAddress. + +**/ +UINTN +EFIAPI +PciWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__= )); + ASSERT (FALSE); + return 0; +} diff --git a/MdePkg/Library/PciLibNull/PciLibNull.inf b/MdePkg/Library/PciL= ibNull/PciLibNull.inf new file mode 100644 index 0000000000000000000000000000000000000000..1778b4025e550939a6d13c5cc46= 6567ce99ebaa5 --- /dev/null +++ b/MdePkg/Library/PciLibNull/PciLibNull.inf @@ -0,0 +1,25 @@ +#/** @file +# +# Null implementation of Pcilib +# +# Copyright (c) 2019, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PciLibNull + FILE_GUID =3D C2E95ECC-9A39-4293-9F52-4C82BA370952 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciLib + + +[Sources] + PciLibNull.c + +[Packages] + MdePkg/MdePkg.dec + --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: DczwIvSAFerX1rMXl2MmuUe2x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445875; bh=rq2vy/irTrOvsU2sL9PhpQA89MbI2A+dHzepQ1WtUOs=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=smV5ou+WqjZsQEUG02e7zgNuHExBBrjRnc7x2wT28XbMQEZLxValhDXB2W+mz+1lR7m oxo17UtQp7bySKLyFWg3ZIPk3NffYw8BwvRfhHKCPnG9ot3ITedcwquHD11LIWbVLHJRw SRm+E8sBikdXhduiSC3sLALCSuYuoRKlHvc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some device drivers perform copy operations on device memory, e.g. device drivers for a Flash device. On some architectures unaligned access to device memory regions is not permitted. To add to this if the device is virtualised then there are further restrictions on the type of load/store operations that can be performed on the device memory regions, e.g. on AARCH64, Pre/Post index or LDP operations cannot be used, as a trap to EL2 does not provide the syndrome information to the hypervisor. To address these issues this patch introduces BaseMemoryLibMmio library which provides an implementation of Base memory library that uses aligned MMIO accesses. Signed-off-by: Sami Mujawar --- MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.inf | 50 ++++ MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.uni | 15 + MdePkg/Library/BaseMemoryLibMmio/CompareMemWrapper.c | 62 ++++ MdePkg/Library/BaseMemoryLibMmio/CopyMem.c | 149 ++++++++++ MdePkg/Library/BaseMemoryLibMmio/CopyMemWrapper.c | 59 ++++ MdePkg/Library/BaseMemoryLibMmio/IsZeroBufferWrapper.c | 50 ++++ MdePkg/Library/BaseMemoryLibMmio/MemLibGeneric.c | 304 +++++++++++++= +++++++ MdePkg/Library/BaseMemoryLibMmio/MemLibGuid.c | 143 +++++++++ MdePkg/Library/BaseMemoryLibMmio/MemLibInternals.h | 248 +++++++++++++= +++ MdePkg/Library/BaseMemoryLibMmio/ScanMem16Wrapper.c | 63 ++++ MdePkg/Library/BaseMemoryLibMmio/ScanMem32Wrapper.c | 62 ++++ MdePkg/Library/BaseMemoryLibMmio/ScanMem64Wrapper.c | 63 ++++ MdePkg/Library/BaseMemoryLibMmio/ScanMem8Wrapper.c | 95 ++++++ MdePkg/Library/BaseMemoryLibMmio/SetMem.c | 83 ++++++ MdePkg/Library/BaseMemoryLibMmio/SetMem16Wrapper.c | 60 ++++ MdePkg/Library/BaseMemoryLibMmio/SetMem32Wrapper.c | 60 ++++ MdePkg/Library/BaseMemoryLibMmio/SetMem64Wrapper.c | 60 ++++ MdePkg/Library/BaseMemoryLibMmio/SetMemWrapper.c | 87 ++++++ MdePkg/Library/BaseMemoryLibMmio/ZeroMemWrapper.c | 52 ++++ 19 files changed, 1765 insertions(+) diff --git a/MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.inf b/MdePk= g/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.inf new file mode 100644 index 0000000000000000000000000000000000000000..3a61cb985a242a4ce7a2446c4ef= b9b78fb1d7b5d --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.inf @@ -0,0 +1,50 @@ +## @file +# Instance of Base Memory Library using Mmio operations. +# +# +# Copyright (c) 2020, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D BaseMemoryLibMmio + MODULE_UNI_FILE =3D BaseMemoryLibMmio.uni + FILE_GUID =3D 5724063D-9855-4B3A-8DEE-1F80ED07E096 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BaseMemoryLib + +# +# VALID_ARCHITECTURES =3D ARM AARCH64 +# + +[Sources] + SetMem.c + ScanMem64Wrapper.c + ScanMem32Wrapper.c + ScanMem16Wrapper.c + ScanMem8Wrapper.c + ZeroMemWrapper.c + CompareMemWrapper.c + SetMem64Wrapper.c + SetMem32Wrapper.c + SetMem16Wrapper.c + SetMemWrapper.c + CopyMemWrapper.c + IsZeroBufferWrapper.c + MemLibGeneric.c + MemLibGuid.c + CopyMem.c + MemLibInternals.h + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + BaseLib + IoLib + diff --git a/MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.uni b/MdePk= g/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.uni new file mode 100644 index 0000000000000000000000000000000000000000..3dc99103e9a673902abcefe824d= 5cf5c19b258b8 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.uni @@ -0,0 +1,15 @@ +// /** @file +// Instance of Base Memory Library using Mmio operations. +// +// +// Copyright (c) 2020, ARM Limited. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Instance of Base = Memory Library using Mmio operations" + +#string STR_MODULE_DESCRIPTION #language en-US "Base Memory Libra= ry using Mmio operations" + diff --git a/MdePkg/Library/BaseMemoryLibMmio/CompareMemWrapper.c b/MdePkg/= Library/BaseMemoryLibMmio/CompareMemWrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..63e0e3ea583cb242a9242f483e8= c952e48122e77 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/CompareMemWrapper.c @@ -0,0 +1,62 @@ +/** @file + CompareMem() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Compares the contents of two buffers. + + This function compares Length bytes of SourceBuffer to Length bytes of D= estinationBuffer. + If all Length bytes of the two buffers are identical, then 0 is returned= . Otherwise, the + value returned is the first mismatched byte in SourceBuffer subtracted f= rom the first + mismatched byte in DestinationBuffer. + + If Length > 0 and DestinationBuffer is NULL, then ASSERT(). + If Length > 0 and SourceBuffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then AS= SERT(). + If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT(= ). + + @param DestinationBuffer A pointer to the destination buffer to compare. + @param SourceBuffer A pointer to the source buffer to compare. + @param Length The number of bytes to compare. + + @return 0 All Length bytes of the two buffers are identi= cal. + @retval Non-zero The first mismatched byte in SourceBuffer subt= racted from the first + mismatched byte in DestinationBuffer. + +**/ +INTN +EFIAPI +CompareMem ( + IN CONST VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ) +{ + if (Length =3D=3D 0 || DestinationBuffer =3D=3D SourceBuffer) { + return 0; + } + ASSERT (DestinationBuffer !=3D NULL); + ASSERT (SourceBuffer !=3D NULL); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)DestinationBuffer)); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)SourceBuffer)); + + return InternalMemCompareMem (DestinationBuffer, SourceBuffer, Length); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/CopyMem.c b/MdePkg/Library/Ba= seMemoryLibMmio/CopyMem.c new file mode 100644 index 0000000000000000000000000000000000000000..84a207bf0f8a537b0832b5c4c9f= 6735122ee7851 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/CopyMem.c @@ -0,0 +1,149 @@ +/** @file + Implementation of the InternalMemCopyMem routine. This function is broken + out into its own source file so that it can be excluded from a build for= a + particular platform easily if an optimized version is desired. + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2020, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Copy Length bytes from Source to Destination. + + @param DestinationBuffer The target of the copy request. + @param SourceBuffer The place to copy from. + @param Length The number of bytes to copy. + + @return Destination + +**/ +VOID * +EFIAPI +InternalMemCopyMem ( + OUT VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ) +{ + // + // Declare the local variables that actually move the data elements as + // volatile to prevent the optimizer from replacing this function with + // the intrinsic memcpy() + // + volatile UINT8 *Destination8; + CONST UINT8 *Source8; + volatile UINT32 *Destination32; + CONST UINT32 *Source32; + volatile UINT64 *Destination64; + CONST UINT64 *Source64; + UINTN Alignment; + + if ((((UINTN)DestinationBuffer & 0x7) =3D=3D 0) && + (((UINTN)SourceBuffer & 0x7) =3D=3D 0) && + (Length >=3D 8)) { + if (SourceBuffer > DestinationBuffer) { + Destination64 =3D (UINT64*)DestinationBuffer; + Source64 =3D (CONST UINT64*)SourceBuffer; + while (Length >=3D 8) { + MmioWrite64 ((UINTN)Destination64++, MmioRead64 ((UINTN)Source64++= )); + Length -=3D 8; + } + + // Finish if there are still some bytes to copy + Destination8 =3D (UINT8*)Destination64; + Source8 =3D (CONST UINT8*)Source64; + while (Length-- !=3D 0) { + MmioWrite8 ((UINTN)Destination8++, MmioRead8 ((UINTN)Source8++)); + } + } else if (SourceBuffer < DestinationBuffer) { + Destination64 =3D (UINT64*)((UINTN)DestinationBuffer + Length); + Source64 =3D (CONST UINT64*)((UINTN)SourceBuffer + Length); + + // Destination64 and Source64 were aligned on a 64-bit boundary + // but if length is not a multiple of 8 bytes then they won't be + // anymore. + + Alignment =3D Length & 0x7; + if (Alignment !=3D 0) { + Destination8 =3D (UINT8*)Destination64; + Source8 =3D (CONST UINT8*)Source64; + + while (Alignment-- !=3D 0) { + MmioWrite8 ((UINTN)--Destination8, MmioRead8 ((UINTN)--Source8)); + --Length; + } + Destination64 =3D (UINT64*)Destination8; + Source64 =3D (CONST UINT64*)Source8; + } + + while (Length > 0) { + MmioWrite64 ((UINTN)--Destination64, MmioRead64 ((UINTN)--Source64= )); + Length -=3D 8; + } + } + } else if ((((UINTN)DestinationBuffer & 0x3) =3D=3D 0) && + (((UINTN)SourceBuffer & 0x3) =3D=3D 0) && + (Length >=3D 4)) { + if (SourceBuffer > DestinationBuffer) { + Destination32 =3D (UINT32*)DestinationBuffer; + Source32 =3D (CONST UINT32*)SourceBuffer; + while (Length >=3D 4) { + MmioWrite32 ((UINTN)Destination32++, MmioRead32 ((UINTN)Source32++= )); + Length -=3D 4; + } + + // Finish if there are still some bytes to copy + Destination8 =3D (UINT8*)Destination32; + Source8 =3D (CONST UINT8*)Source32; + while (Length-- !=3D 0) { + MmioWrite8 ((UINTN)Destination8++, MmioRead8 ((UINTN)Source8++)); + } + } else if (SourceBuffer < DestinationBuffer) { + Destination32 =3D (UINT32*)((UINTN)DestinationBuffer + Length); + Source32 =3D (CONST UINT32*)((UINTN)SourceBuffer + Length); + + // Destination32 and Source32 were aligned on a 32-bit boundary + // but if length is not a multiple of 4 bytes then they won't be + // anymore. + + Alignment =3D Length & 0x3; + if (Alignment !=3D 0) { + Destination8 =3D (UINT8*)Destination32; + Source8 =3D (CONST UINT8*)Source32; + + while (Alignment-- !=3D 0) { + MmioWrite8 ((UINTN)--Destination8, MmioRead8 ((UINTN)--Source8)); + --Length; + } + Destination32 =3D (UINT32*)Destination8; + Source32 =3D (CONST UINT32*)Source8; + } + + while (Length > 0) { + MmioWrite32 ((UINTN)--Destination32, MmioRead32 ((UINTN)--Source32= )); + Length -=3D 4; + } + } + } else { + if (SourceBuffer > DestinationBuffer) { + Destination8 =3D (UINT8*)DestinationBuffer; + Source8 =3D (CONST UINT8*)SourceBuffer; + while (Length-- !=3D 0) { + MmioWrite8 ((UINTN)Destination8++, MmioRead8 ((UINTN)Source8++)); + } + } else if (SourceBuffer < DestinationBuffer) { + Destination8 =3D (UINT8*)DestinationBuffer + (Length - 1); + Source8 =3D (CONST UINT8*)SourceBuffer + (Length - 1); + while (Length-- !=3D 0) { + MmioWrite8 ((UINTN)Destination8--, MmioRead8 ((UINTN)Source8--)); + } + } + } + return DestinationBuffer; +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/CopyMemWrapper.c b/MdePkg/Lib= rary/BaseMemoryLibMmio/CopyMemWrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..d557bbb8904c2b07c644261290a= 62be6fc831c08 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/CopyMemWrapper.c @@ -0,0 +1,59 @@ +/** @file + CopyMem() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Copies a source buffer to a destination buffer, and returns the destinat= ion buffer. + + This function copies Length bytes from SourceBuffer to DestinationBuffer= , and returns + DestinationBuffer. The implementation must be reentrant, and it must ha= ndle the case + where SourceBuffer overlaps DestinationBuffer. + + If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then AS= SERT(). + If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT(= ). + + @param DestinationBuffer A pointer to the destination buffer of the m= emory copy. + @param SourceBuffer A pointer to the source buffer of the memory= copy. + @param Length The number of bytes to copy from SourceBuffe= r to DestinationBuffer. + + @return DestinationBuffer. + +**/ +VOID * +EFIAPI +CopyMem ( + OUT VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ) +{ + if (Length =3D=3D 0) { + return DestinationBuffer; + } + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)DestinationBuffer)); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)SourceBuffer)); + + if (DestinationBuffer =3D=3D SourceBuffer) { + return DestinationBuffer; + } + return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/IsZeroBufferWrapper.c b/MdePk= g/Library/BaseMemoryLibMmio/IsZeroBufferWrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..9c3133c668c434839b0d9bf105b= c7265eeb76a5b --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/IsZeroBufferWrapper.c @@ -0,0 +1,50 @@ +/** @file + Implementation of IsZeroBuffer function. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Checks if the contents of a buffer are all zeros. + + This function checks whether the contents of a buffer are all zeros. If = the + contents are all zeros, return TRUE. Otherwise, return FALSE. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to be checked. + @param Length The size of the buffer (in bytes) to be checked. + + @retval TRUE Contents of the buffer are all zeros. + @retval FALSE Contents of the buffer are not all zeros. + +**/ +BOOLEAN +EFIAPI +IsZeroBuffer ( + IN CONST VOID *Buffer, + IN UINTN Length + ) +{ + ASSERT (!(Buffer =3D=3D NULL && Length > 0)); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + return InternalMemIsZeroBuffer (Buffer, Length); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/MemLibGeneric.c b/MdePkg/Libr= ary/BaseMemoryLibMmio/MemLibGeneric.c new file mode 100644 index 0000000000000000000000000000000000000000..1c65b674230795e956c9d22f2b9= c151c41839706 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/MemLibGeneric.c @@ -0,0 +1,304 @@ +/** @file + Architecture Independent Base Memory Library Implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + BaseMemoryLib + BaseMemoryLibMmio + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Fills a target buffer with a 16-bit value, and returns the target buffer. + + @param Buffer The pointer to the target buffer to fill. + @param Length The count of 16-bit value to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemSetMem16 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT16 Value + ) +{ + volatile UINT16 *Destination16; + + Destination16 =3D (UINT16*)Buffer; + while (Length > 0) { + MmioWrite16 ((UINTN)--Destination16, Value); + Length -=3D 2; + } + + return Buffer; +} + +/** + Fills a target buffer with a 32-bit value, and returns the target buffer. + + @param Buffer The pointer to the target buffer to fill. + @param Length The count of 32-bit value to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemSetMem32 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT32 Value + ) +{ + volatile UINT32 *Destination32; + + Destination32 =3D (UINT32*)Buffer; + while (Length > 0) { + MmioWrite32 ((UINTN)--Destination32, Value); + Length -=3D 4; + } + return Buffer; +} + +/** + Fills a target buffer with a 64-bit value, and returns the target buffer. + + @param Buffer The pointer to the target buffer to fill. + @param Length The count of 64-bit value to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemSetMem64 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT64 Value + ) +{ + volatile UINT64 *Destination64; + + Destination64 =3D (UINT64*)Buffer; + while (Length > 0) { + MmioWrite64 ((UINTN)--Destination64, Value); + Length -=3D 8; + } + return Buffer; +} + +/** + Set Buffer to 0 for Size bytes. + + @param Buffer Memory to set. + @param Length The number of bytes to set. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemZeroMem ( + OUT VOID *Buffer, + IN UINTN Length + ) +{ + return InternalMemSetMem (Buffer, Length, 0); +} + +/** + Compares two memory buffers of a given length. + + @param DestinationBuffer The first memory buffer. + @param SourceBuffer The second memory buffer. + @param Length Length of DestinationBuffer and SourceBuffer m= emory + regions to compare. Must be non-zero. + + @return 0 All Length bytes of the two buffers are identi= cal. + @retval Non-zero The first mismatched byte in SourceBuffer subt= racted from the first + mismatched byte in DestinationBuffer. + +**/ +INTN +EFIAPI +InternalMemCompareMem ( + IN CONST VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ) +{ + while ((--Length !=3D 0) && + (MmioRead8 ((UINTN)DestinationBuffer) =3D=3D + MmioRead8 ((UINTN)SourceBuffer))) { + DestinationBuffer =3D (INT8*)DestinationBuffer + 1; + SourceBuffer =3D (INT8*)SourceBuffer + 1; + } + return (INTN)MmioRead8 ((UINTN)DestinationBuffer) - + (INTN)MmioRead8 ((UINTN)SourceBuffer); +} + +/** + Scans a target buffer for an 8-bit value, and returns a pointer to the + matching 8-bit value in the target buffer. + + @param Buffer The pointer to the target buffer to scan. + @param Length The count of 8-bit value to scan. Must be non-zero. + @param Value The value to search for in the target buffer. + + @return The pointer to the first occurrence, or NULL if not found. + +**/ +CONST VOID * +EFIAPI +InternalMemScanMem8 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ) +{ + CONST UINT8 *Pointer; + + Pointer =3D (CONST UINT8*)Buffer; + do { + if (MmioRead8 ((UINTN)Pointer) =3D=3D Value) { + return Pointer; + } + ++Pointer; + } while (--Length !=3D 0); + return NULL; +} + +/** + Scans a target buffer for a 16-bit value, and returns a pointer to the + matching 16-bit value in the target buffer. + + @param Buffer The pointer to the target buffer to scan. + @param Length The count of 16-bit value to scan. Must be non-zero. + @param Value The value to search for in the target buffer. + + @return The pointer to the first occurrence, or NULL if not found. + +**/ +CONST VOID * +EFIAPI +InternalMemScanMem16 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT16 Value + ) +{ + CONST UINT16 *Pointer; + + Pointer =3D (CONST UINT16*)Buffer; + do { + if (MmioRead16 ((UINTN)Pointer) =3D=3D Value) { + return Pointer; + } + ++Pointer; + } while (--Length !=3D 0); + return NULL; +} + +/** + Scans a target buffer for a 32-bit value, and returns a pointer to the + matching 32-bit value in the target buffer. + + @param Buffer The pointer to the target buffer to scan. + @param Length The count of 32-bit value to scan. Must be non-zero. + @param Value The value to search for in the target buffer. + + @return The pointer to the first occurrence, or NULL if not found. + +**/ +CONST VOID * +EFIAPI +InternalMemScanMem32 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT32 Value + ) +{ + CONST UINT32 *Pointer; + + Pointer =3D (CONST UINT32*)Buffer; + do { + if (MmioRead32 ((UINTN)Pointer) =3D=3D Value) { + return Pointer; + } + ++Pointer; + } while (--Length !=3D 0); + return NULL; +} + +/** + Scans a target buffer for a 64-bit value, and returns a pointer to the + matching 64-bit value in the target buffer. + + @param Buffer The pointer to the target buffer to scan. + @param Length The count of 64-bit value to scan. Must be non-zero. + @param Value The value to search for in the target buffer. + + @return The pointer to the first occurrence, or NULL if not found. + +**/ +CONST VOID * +EFIAPI +InternalMemScanMem64 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT64 Value + ) +{ + CONST UINT64 *Pointer; + + Pointer =3D (CONST UINT64*)Buffer; + do { + if (MmioRead64 ((UINTN)Pointer) =3D=3D Value) { + return Pointer; + } + ++Pointer; + } while (--Length !=3D 0); + return NULL; +} + +/** + Checks whether the contents of a buffer are all zeros. + + @param Buffer The pointer to the buffer to be checked. + @param Length The size of the buffer (in bytes) to be checked. + + @retval TRUE Contents of the buffer are all zeros. + @retval FALSE Contents of the buffer are not all zeros. + +**/ +BOOLEAN +EFIAPI +InternalMemIsZeroBuffer ( + IN CONST VOID *Buffer, + IN UINTN Length + ) +{ + CONST UINT8 *BufferData; + UINTN Index; + + BufferData =3D Buffer; + for (Index =3D 0; Index < Length; Index++) { + if (MmioRead8 ((UINTN)(BufferData + Index)) !=3D 0) { + return FALSE; + } + } + return TRUE; +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/MemLibGuid.c b/MdePkg/Library= /BaseMemoryLibMmio/MemLibGuid.c new file mode 100644 index 0000000000000000000000000000000000000000..ce69e431309f4447a4e99251a86= b5182123e5b97 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/MemLibGuid.c @@ -0,0 +1,143 @@ +/** @file + Implementation of GUID functions. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Copies a source GUID to a destination GUID. + + This function copies the contents of the 128-bit GUID specified by Sourc= eGuid + to DestinationGuid, and returns DestinationGuid. + + If DestinationGuid is NULL, then ASSERT(). + If SourceGuid is NULL, then ASSERT(). + + @param DestinationGuid A pointer to the destination GUID. + @param SourceGuid A pointer to the source GUID. + + @return DestinationGuid. + +**/ +GUID * +EFIAPI +CopyGuid ( + OUT GUID *DestinationGuid, + IN CONST GUID *SourceGuid + ) +{ + return InternalMemCopyMem (DestinationGuid, SourceGuid, sizeof (GUID)); +} + +/** + Compares two GUIDs. + + This function compares Guid1 to Guid2. If the GUIDs are identical then = TRUE is returned. + If there are any bit differences in the two GUIDs, then FALSE is returne= d. + + If Guid1 is NULL, then ASSERT(). + If Guid2 is NULL, then ASSERT(). + + @param Guid1 A pointer to a 128 bit GUID. + @param Guid2 A pointer to a 128 bit GUID. + + @retval TRUE Guid1 and Guid2 are identical. + @retval FALSE Guid1 and Guid2 are not identical. + +**/ +BOOLEAN +EFIAPI +CompareGuid ( + IN CONST GUID *Guid1, + IN CONST GUID *Guid2 + ) +{ + return (0 =3D=3D InternalMemCompareMem (Guid1, Guid2, sizeof (GUID))); +} + +/** + Scans a target buffer for a GUID, and returns a pointer to the matching = GUID + in the target buffer. + + This function searches the target buffer specified by Buffer and Length = from + the lowest address to the highest address at 128-bit increments for the = 128-bit + GUID value that matches Guid. If a match is found, then a pointer to th= e matching + GUID in the target buffer is returned. If no match is found, then NULL = is returned. + If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + If Length is not aligned on a 128-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Guid The value to search for in the target buffer. + + @return A pointer to the matching Guid in the target buffer or NULL othe= rwise. + +**/ +VOID * +EFIAPI +ScanGuid ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN CONST GUID *Guid + ) +{ + CONST GUID *GuidPtr; + + ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) =3D=3D 0); + ASSERT (Length <=3D (MAX_ADDRESS - (UINTN)Buffer + 1)); + ASSERT ((Length & (sizeof (*GuidPtr) - 1)) =3D=3D 0); + + GuidPtr =3D (GUID*)Buffer; + Buffer =3D GuidPtr + Length / sizeof (*GuidPtr); + while (GuidPtr < (CONST GUID*)Buffer) { + if (CompareGuid (GuidPtr, Guid)) { + return (VOID*)GuidPtr; + } + GuidPtr++; + } + return NULL; +} + +/** + Checks if the given GUID is a zero GUID. + + This function checks whether the given GUID is a zero GUID. If the GUID = is + identical to a zero GUID then TRUE is returned. Otherwise, FALSE is retu= rned. + + If Guid is NULL, then ASSERT(). + + @param Guid The pointer to a 128 bit GUID. + + @retval TRUE Guid is a zero GUID. + @retval FALSE Guid is not a zero GUID. + +**/ +BOOLEAN +EFIAPI +IsZeroGuid ( + IN CONST GUID *Guid + ) +{ + return InternalMemIsZeroBuffer (Guid, sizeof (GUID)); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/MemLibInternals.h b/MdePkg/Li= brary/BaseMemoryLibMmio/MemLibInternals.h new file mode 100644 index 0000000000000000000000000000000000000000..dc28a9078a8a707af8a83517d37= 56c6126093079 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/MemLibInternals.h @@ -0,0 +1,248 @@ +/** @file + Declaration of internal functions for Base Memory Library. + + The following BaseMemoryLib instances contain the same copy of this file: + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MEM_LIB_INTERNALS__ +#define __MEM_LIB_INTERNALS__ + +#include +#include +#include +#include +#include + +/** + Copy Length bytes from Source to Destination. + + @param DestinationBuffer Target of copy + @param SourceBuffer Place to copy from + @param Length The number of bytes to copy + + @return Destination + +**/ +VOID * +EFIAPI +InternalMemCopyMem ( + OUT VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ); + +/** + Set Buffer to Value for Size bytes. + + @param Buffer The memory to set. + @param Length The number of bytes to set + @param Value The value of the set operation. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemSetMem ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ); + +/** + Fills a target buffer with a 16-bit value, and returns the target buffer. + + @param Buffer The pointer to the target buffer to fill. + @param Length The count of 16-bit value to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemSetMem16 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT16 Value + ); + +/** + Fills a target buffer with a 32-bit value, and returns the target buffer. + + @param Buffer The pointer to the target buffer to fill. + @param Length The count of 32-bit value to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemSetMem32 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT32 Value + ); + +/** + Fills a target buffer with a 64-bit value, and returns the target buffer. + + @param Buffer The pointer to the target buffer to fill. + @param Length The count of 64-bit value to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemSetMem64 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT64 Value + ); + +/** + Set Buffer to 0 for Size bytes. + + @param Buffer The memory to set. + @param Length The number of bytes to set. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemZeroMem ( + OUT VOID *Buffer, + IN UINTN Length + ); + +/** + Compares two memory buffers of a given length. + + @param DestinationBuffer The first memory buffer. + @param SourceBuffer The second memory buffer. + @param Length The length of DestinationBuffer and SourceBuff= er memory + regions to compare. Must be non-zero. + + @return 0 All Length bytes of the two buffers are identi= cal. + @retval Non-zero The first mismatched byte in SourceBuffer subt= racted from the first + mismatched byte in DestinationBuffer. + +**/ +INTN +EFIAPI +InternalMemCompareMem ( + IN CONST VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ); + +/** + Scans a target buffer for an 8-bit value, and returns a pointer to the + matching 8-bit value in the target buffer. + + @param Buffer The pointer to the target buffer to scan. + @param Length The count of 8-bit value to scan. Must be non-zero. + @param Value The value to search for in the target buffer. + + @return The pointer to the first occurrence, or NULL if not found. + +**/ +CONST VOID * +EFIAPI +InternalMemScanMem8 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ); + +/** + Scans a target buffer for a 16-bit value, and returns a pointer to the + matching 16-bit value in the target buffer. + + @param Buffer The pointer to the target buffer to scan. + @param Length The count of 16-bit value to scan. Must be non-zero. + @param Value The value to search for in the target buffer. + + @return The pointer to the first occurrence, or NULL if not found. + +**/ +CONST VOID * +EFIAPI +InternalMemScanMem16 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT16 Value + ); + +/** + Scans a target buffer for a 32-bit value, and returns a pointer to the + matching 32-bit value in the target buffer. + + @param Buffer The pointer to the target buffer to scan. + @param Length The count of 32-bit value to scan. Must be non-zero. + @param Value The value to search for in the target buffer. + + @return The pointer to the first occurrence, or NULL if not found. + +**/ +CONST VOID * +EFIAPI +InternalMemScanMem32 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT32 Value + ); + +/** + Scans a target buffer for a 64-bit value, and returns a pointer to the + matching 64-bit value in the target buffer. + + @param Buffer The pointer to the target buffer to scan. + @param Length The count of 64-bit value to scan. Must be non-zero. + @param Value The calue to search for in the target buffer. + + @return The pointer to the first occurrence, or NULL if not found. + +**/ +CONST VOID * +EFIAPI +InternalMemScanMem64 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT64 Value + ); + +/** + Checks whether the contents of a buffer are all zeros. + + @param Buffer The pointer to the buffer to be checked. + @param Length The size of the buffer (in bytes) to be checked. + + @retval TRUE Contents of the buffer are all zeros. + @retval FALSE Contents of the buffer are not all zeros. + +**/ +BOOLEAN +EFIAPI +InternalMemIsZeroBuffer ( + IN CONST VOID *Buffer, + IN UINTN Length + ); + +#endif diff --git a/MdePkg/Library/BaseMemoryLibMmio/ScanMem16Wrapper.c b/MdePkg/L= ibrary/BaseMemoryLibMmio/ScanMem16Wrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..ad9330b9938df9995a597dbabc1= aa2744aa0d8c1 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/ScanMem16Wrapper.c @@ -0,0 +1,63 @@ +/** @file + ScanMem16() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Scans a target buffer for a 16-bit value, and returns a pointer to the m= atching 16-bit value + in the target buffer. + + This function searches the target buffer specified by Buffer and Length = from the lowest + address to the highest address for a 16-bit value that matches Value. I= f a match is found, + then a pointer to the matching byte in the target buffer is returned. I= f no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + If Length is not aligned on a 16-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer or NULL othe= rwise. + +**/ +VOID * +EFIAPI +ScanMem16 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT16 Value + ) +{ + if (Length =3D=3D 0) { + return NULL; + } + + ASSERT (Buffer !=3D NULL); + ASSERT (((UINTN)Buffer & (sizeof (Value) - 1)) =3D=3D 0); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + ASSERT ((Length & (sizeof (Value) - 1)) =3D=3D 0); + + return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Val= ue); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/ScanMem32Wrapper.c b/MdePkg/L= ibrary/BaseMemoryLibMmio/ScanMem32Wrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..84675697d12016f92c46c08c65a= ca647288a8b99 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/ScanMem32Wrapper.c @@ -0,0 +1,62 @@ +/** @file + ScanMem32() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Scans a target buffer for a 32-bit value, and returns a pointer to the m= atching 32-bit value + in the target buffer. + + This function searches the target buffer specified by Buffer and Length = from the lowest + address to the highest address for a 32-bit value that matches Value. I= f a match is found, + then a pointer to the matching byte in the target buffer is returned. I= f no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + If Length is not aligned on a 32-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer or NULL othe= rwise. + +**/ +VOID * +EFIAPI +ScanMem32 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT32 Value + ) +{ + if (Length =3D=3D 0) { + return NULL; + } + + ASSERT (Buffer !=3D NULL); + ASSERT (((UINTN)Buffer & (sizeof (Value) - 1)) =3D=3D 0); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + ASSERT ((Length & (sizeof (Value) - 1)) =3D=3D 0); + + return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Val= ue); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/ScanMem64Wrapper.c b/MdePkg/L= ibrary/BaseMemoryLibMmio/ScanMem64Wrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..df749dce457827fe070bad8b7c6= 071aae29ebb02 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/ScanMem64Wrapper.c @@ -0,0 +1,63 @@ +/** @file + ScanMem64() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Scans a target buffer for a 64-bit value, and returns a pointer to the m= atching 64-bit value + in the target buffer. + + This function searches the target buffer specified by Buffer and Length = from the lowest + address to the highest address for a 64-bit value that matches Value. I= f a match is found, + then a pointer to the matching byte in the target buffer is returned. I= f no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + If Length is not aligned on a 64-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer or NULL othe= rwise. + +**/ +VOID * +EFIAPI +ScanMem64 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT64 Value + ) +{ + if (Length =3D=3D 0) { + return NULL; + } + + ASSERT (Buffer !=3D NULL); + ASSERT (((UINTN)Buffer & (sizeof (Value) - 1)) =3D=3D 0); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + ASSERT ((Length & (sizeof (Value) - 1)) =3D=3D 0); + + return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Val= ue); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/ScanMem8Wrapper.c b/MdePkg/Li= brary/BaseMemoryLibMmio/ScanMem8Wrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..170981017dbe31cf5e0c3dabf26= a4fea33f7a7d7 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/ScanMem8Wrapper.c @@ -0,0 +1,95 @@ +/** @file + ScanMem8() and ScanMemN() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Scans a target buffer for an 8-bit value, and returns a pointer to the m= atching 8-bit value + in the target buffer. + + This function searches the target buffer specified by Buffer and Length = from the lowest + address to the highest address for an 8-bit value that matches Value. I= f a match is found, + then a pointer to the matching byte in the target buffer is returned. I= f no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer, or NULL oth= erwise. + +**/ +VOID * +EFIAPI +ScanMem8 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ) +{ + if (Length =3D=3D 0) { + return NULL; + } + ASSERT (Buffer !=3D NULL); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + + return (VOID*)InternalMemScanMem8 (Buffer, Length, Value); +} + +/** + Scans a target buffer for a UINTN sized value, and returns a pointer to = the matching + UINTN sized value in the target buffer. + + This function searches the target buffer specified by Buffer and Length = from the lowest + address to the highest address for a UINTN sized value that matches Valu= e. If a match is found, + then a pointer to the matching byte in the target buffer is returned. I= f no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a UINTN boundary, then ASSERT(). + If Length is not aligned on a UINTN boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer, or NULL oth= erwise. + +**/ +VOID * +EFIAPI +ScanMemN ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINTN Value + ) +{ + if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { + return ScanMem64 (Buffer, Length, (UINT64)Value); + } else { + return ScanMem32 (Buffer, Length, (UINT32)Value); + } +} + diff --git a/MdePkg/Library/BaseMemoryLibMmio/SetMem.c b/MdePkg/Library/Bas= eMemoryLibMmio/SetMem.c new file mode 100644 index 0000000000000000000000000000000000000000..40255670c6f26eb72a82568f035= 720fc6fe75546 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/SetMem.c @@ -0,0 +1,83 @@ +/** @file + Implementation of the EfiSetMem routine. This function is broken + out into its own source file so that it can be excluded from a + build for a particular platform easily if an optimized version + is desired. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2020, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Set Buffer to Value for Size bytes. + + @param Buffer The memory to set. + @param Length The number of bytes to set. + @param Value The value of the set operation. + + @return Buffer + +**/ +VOID * +EFIAPI +InternalMemSetMem ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ) +{ + // + // Declare the local variables that actually move the data elements as + // volatile to prevent the optimizer from replacing this function with + // the intrinsic memset() + // + volatile UINT8 *Pointer8; + volatile UINT32 *Pointer32; + volatile UINT64 *Pointer64; + UINT32 Value32; + UINT64 Value64; + + if ((((UINTN)Buffer & 0x7) =3D=3D 0) && (Length >=3D 8)) { + // Generate the 64bit value + Value32 =3D (Value << 24) | (Value << 16) | (Value << 8) | Value; + Value64 =3D LShiftU64 (Value32, 32) | Value32; + + Pointer64 =3D (UINT64*)Buffer; + while (Length >=3D 8) { + MmioWrite64 ((UINTN)Pointer64++, Value64); + Length -=3D 8; + } + + // Finish with bytes if needed + Pointer8 =3D (UINT8*)Pointer64; + } else if ((((UINTN)Buffer & 0x3) =3D=3D 0) && (Length >=3D 4)) { + // Generate the 32bit value + Value32 =3D (Value << 24) | (Value << 16) | (Value << 8) | Value; + + Pointer32 =3D (UINT32*)Buffer; + while (Length >=3D 4) { + MmioWrite32 ((UINTN)Pointer32++, Value32); + Length -=3D 4; + } + + // Finish with bytes if needed + Pointer8 =3D (UINT8*)Pointer32; + } else { + Pointer8 =3D (UINT8*)Buffer; + } + while (Length-- > 0) { + MmioWrite8 ((UINTN)Pointer8++, Value); + } + return Buffer; +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/SetMem16Wrapper.c b/MdePkg/Li= brary/BaseMemoryLibMmio/SetMem16Wrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..be785c5eb696ef6b913bf7bc008= 1a5f414c6f141 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/SetMem16Wrapper.c @@ -0,0 +1,60 @@ +/** @file + SetMem16() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Fills a target buffer with a 16-bit value, and returns the target buffer. + + This function fills Length bytes of Buffer with the 16-bit value specifi= ed by + Value, and returns Buffer. Value is repeated every 16-bits in for Length + bytes of Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + If Length is not aligned on a 16-bit boundary, then ASSERT(). + + @param Buffer The pointer to the target buffer to fill. + @param Length The number of bytes in Buffer to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMem16 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT16 Value + ) +{ + if (Length =3D=3D 0) { + return Buffer; + } + + ASSERT (Buffer !=3D NULL); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + ASSERT ((((UINTN)Buffer) & (sizeof (Value) - 1)) =3D=3D 0); + ASSERT ((Length & (sizeof (Value) - 1)) =3D=3D 0); + + return InternalMemSetMem16 (Buffer, Length / sizeof (Value), Value); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/SetMem32Wrapper.c b/MdePkg/Li= brary/BaseMemoryLibMmio/SetMem32Wrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..622c6eddccc88e846921782efc2= 9e40f816ae499 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/SetMem32Wrapper.c @@ -0,0 +1,60 @@ +/** @file + SetMem32() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Fills a target buffer with a 32-bit value, and returns the target buffer. + + This function fills Length bytes of Buffer with the 32-bit value specifi= ed by + Value, and returns Buffer. Value is repeated every 32-bits in for Length + bytes of Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + If Length is not aligned on a 32-bit boundary, then ASSERT(). + + @param Buffer The pointer to the target buffer to fill. + @param Length The number of bytes in Buffer to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMem32 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT32 Value + ) +{ + if (Length =3D=3D 0) { + return Buffer; + } + + ASSERT (Buffer !=3D NULL); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + ASSERT ((((UINTN)Buffer) & (sizeof (Value) - 1)) =3D=3D 0); + ASSERT ((Length & (sizeof (Value) - 1)) =3D=3D 0); + + return InternalMemSetMem32 (Buffer, Length / sizeof (Value), Value); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/SetMem64Wrapper.c b/MdePkg/Li= brary/BaseMemoryLibMmio/SetMem64Wrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..7653eed85cd633be5aea439cf4a= b62958dd62c47 --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/SetMem64Wrapper.c @@ -0,0 +1,60 @@ +/** @file + SetMem64() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Fills a target buffer with a 64-bit value, and returns the target buffer. + + This function fills Length bytes of Buffer with the 64-bit value specifi= ed by + Value, and returns Buffer. Value is repeated every 64-bits in for Length + bytes of Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + If Length is not aligned on a 64-bit boundary, then ASSERT(). + + @param Buffer The pointer to the target buffer to fill. + @param Length The number of bytes in Buffer to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMem64 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT64 Value + ) +{ + if (Length =3D=3D 0) { + return Buffer; + } + + ASSERT (Buffer !=3D NULL); + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + ASSERT ((((UINTN)Buffer) & (sizeof (Value) - 1)) =3D=3D 0); + ASSERT ((Length & (sizeof (Value) - 1)) =3D=3D 0); + + return InternalMemSetMem64 (Buffer, Length / sizeof (Value), Value); +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/SetMemWrapper.c b/MdePkg/Libr= ary/BaseMemoryLibMmio/SetMemWrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..96dd956686d15b4b4cb25157d76= 4849043d1b57b --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/SetMemWrapper.c @@ -0,0 +1,87 @@ +/** @file + SetMem() and SetMemN() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Fills a target buffer with a byte value, and returns the target buffer. + + This function fills Length bytes of Buffer with Value, and returns Buffe= r. + + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The memory to set. + @param Length The number of bytes to set. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMem ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ) +{ + if (Length =3D=3D 0) { + return Buffer; + } + + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Buffer)); + + return InternalMemSetMem (Buffer, Length, Value); +} + +/** + Fills a target buffer with a value that is size UINTN, and returns the t= arget buffer. + + This function fills Length bytes of Buffer with the UINTN sized value sp= ecified by + Value, and returns Buffer. Value is repeated every sizeof(UINTN) bytes f= or Length + bytes of Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + If Buffer is not aligned on a UINTN boundary, then ASSERT(). + If Length is not aligned on a UINTN boundary, then ASSERT(). + + @param Buffer The pointer to the target buffer to fill. + @param Length The number of bytes in Buffer to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMemN ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINTN Value + ) +{ + if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { + return SetMem64 (Buffer, Length, (UINT64)Value); + } else { + return SetMem32 (Buffer, Length, (UINT32)Value); + } +} diff --git a/MdePkg/Library/BaseMemoryLibMmio/ZeroMemWrapper.c b/MdePkg/Lib= rary/BaseMemoryLibMmio/ZeroMemWrapper.c new file mode 100644 index 0000000000000000000000000000000000000000..55246d121c6820d371af4637926= 14c1d73676e6f --- /dev/null +++ b/MdePkg/Library/BaseMemoryLibMmio/ZeroMemWrapper.c @@ -0,0 +1,52 @@ +/** @file + ZeroMem() implementation. + + The following BaseMemoryLib instances contain the same copy of this file: + + BaseMemoryLib + BaseMemoryLibMmio + BaseMemoryLibMmx + BaseMemoryLibSse2 + BaseMemoryLibRepStr + BaseMemoryLibOptDxe + BaseMemoryLibOptPei + PeiMemoryLib + UefiMemoryLib + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MemLibInternals.h" + +/** + Fills a target buffer with zeros, and returns the target buffer. + + This function fills Length bytes of Buffer with zeros, and returns Buffe= r. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to fill with zeros. + @param Length The number of bytes in Buffer to fill with zeros. + + @return Buffer. + +**/ +VOID * +EFIAPI +ZeroMem ( + OUT VOID *Buffer, + IN UINTN Length + ) +{ + if (Length =3D=3D 0) { + return Buffer; + } + + ASSERT (Buffer !=3D NULL); + ASSERT (Length <=3D (MAX_ADDRESS - (UINTN)Buffer + 1)); + return InternalMemZeroMem (Buffer, Length); +} --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: SCIllgrownqvsvM6ggllZ8hZx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445867; bh=pHM4P+es/0XjQ06vPRQTVggzK9czB1KfrhqK2WkgikA=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=tIbBpi5rryNvG6g/YCn5IJZ/FVHiMPRuiTn9fKZh50B7xi/Bk9d8B4+Iyr5pFDJHQGM Ra6/r/9Ibsz6Er4xQDKnjNFY1bsRFLFmmeOmRXErsGeSqoI62M/qhDryVFQcIF8lxR/9p aW2Jaz5LnoY156eCckKv8/NOHO8v1Nmhng8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NorFlashDxe must use aligned MMIO accesses to read data from flash as this is device memory. The AlignedCopyMem() was used to copy the flash data which prevented unaligned access to device memory. However, the compiler could optimize the code to generate pre/post indexed or LDP operations. This is a problem for guest/virtual firmware as the hypervisor code cannot get the syndrome information for the trapped accesses. Similarly, the GUIDS FwVolHeader->FileSystemGuid and VariableStoreHeader->Signature in ValidateFvHeader() are compared using CompareGuid(). These GUIDs point to flash data (which is device memory) and therefore need aligned MMIO accesses. To address the above issues, BaseMemoryLibMmio library has been introduced to perform aligned MMIO accesses. This patch removes the usage of AlignedCopyMem() and replaces it with CopyMem() with an expectation that the BaseMemoryLibMmio will be linked with NorFlashDxe. Signed-off-by: Sami Mujawar --- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c | 65 +------------------- 1 file changed, 3 insertions(+), 62 deletions(-) diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c b/ArmPlatform= Pkg/Drivers/NorFlashDxe/NorFlashDxe.c index d9e196cbf18c32fe5306cc3c0674a7b5798a9191..f9890de8244d37e0e860fd183bb= 216ff7d1e7035 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c @@ -1,6 +1,6 @@ /** @file NorFlashDxe.c =20 - Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2011 - 2020, ARM Ltd. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -735,65 +735,6 @@ NorFlashWriteBlocks ( return Status; } =20 -#define BOTH_ALIGNED(a, b, align) ((((UINTN)(a) | (UINTN)(b)) & ((align) -= 1)) =3D=3D 0) - -/** - Copy Length bytes from Source to Destination, using aligned accesses onl= y. - Note that this implementation uses memcpy() semantics rather then memmov= e() - semantics, i.e., SourceBuffer and DestinationBuffer should not overlap. - - @param DestinationBuffer The target of the copy request. - @param SourceBuffer The place to copy from. - @param Length The number of bytes to copy. - - @return Destination - -**/ -STATIC -VOID * -AlignedCopyMem ( - OUT VOID *DestinationBuffer, - IN CONST VOID *SourceBuffer, - IN UINTN Length - ) -{ - UINT8 *Destination8; - CONST UINT8 *Source8; - UINT32 *Destination32; - CONST UINT32 *Source32; - UINT64 *Destination64; - CONST UINT64 *Source64; - - if (BOTH_ALIGNED(DestinationBuffer, SourceBuffer, 8) && Length >=3D 8) { - Destination64 =3D DestinationBuffer; - Source64 =3D SourceBuffer; - while (Length >=3D 8) { - *Destination64++ =3D *Source64++; - Length -=3D 8; - } - - Destination8 =3D (UINT8 *)Destination64; - Source8 =3D (CONST UINT8 *)Source64; - } else if (BOTH_ALIGNED(DestinationBuffer, SourceBuffer, 4) && Length >= =3D 4) { - Destination32 =3D DestinationBuffer; - Source32 =3D SourceBuffer; - while (Length >=3D 4) { - *Destination32++ =3D *Source32++; - Length -=3D 4; - } - - Destination8 =3D (UINT8 *)Destination32; - Source8 =3D (CONST UINT8 *)Source32; - } else { - Destination8 =3D DestinationBuffer; - Source8 =3D SourceBuffer; - } - while (Length-- !=3D 0) { - *Destination8++ =3D *Source8++; - } - return DestinationBuffer; -} - EFI_STATUS NorFlashReadBlocks ( IN NOR_FLASH_INSTANCE *Instance, @@ -841,7 +782,7 @@ NorFlashReadBlocks ( SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); =20 // Readout the data - AlignedCopyMem (Buffer, (VOID *)StartAddress, BufferSizeInBytes); + CopyMem (Buffer, (VOID *)StartAddress, BufferSizeInBytes); =20 return EFI_SUCCESS; } @@ -882,7 +823,7 @@ NorFlashRead ( SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY); =20 // Readout the data - AlignedCopyMem (Buffer, (VOID *)(StartAddress + Offset), BufferSizeInByt= es); + CopyMem (Buffer, (VOID *)(StartAddress + Offset), BufferSizeInBytes); =20 return EFI_SUCCESS; } --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 14 May 2020 08:44:23 +0000 X-Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1415.2; Thu, 14 May 2020 08:40:27 +0000 X-Received: from E107187.Arm.com (10.57.42.179) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 14 May 2020 08:40:27 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , Subject: [edk2-devel] [PATCH v1 05/11] ArmPlatformPkg: Dynamic flash variable base Date: Thu, 14 May 2020 09:40:13 +0100 Message-ID: <20200514084019.71368-6-sami.mujawar@arm.com> In-Reply-To: <20200514084019.71368-1-sami.mujawar@arm.com> References: <20200514084019.71368-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(4636009)(396003)(136003)(376002)(39860400002)(346002)(46966005)(2906002)(70586007)(478600001)(7696005)(82310400002)(44832011)(1076003)(6666004)(54906003)(8676002)(5660300002)(356005)(6916009)(26005)(8936002)(426003)(70206006)(4326008)(82740400003)(336012)(47076004)(186003)(86362001)(36756003)(316002)(2616005)(81166007);DIR:OUT;SFP:1101; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: GNa4IFGpTjJlIyXkuE5GTvyQx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445876; bh=Og/rkXaGCPB6HmCH/H55f46jgUMaO2vNY1pk1pxx52E=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=U+/74vAtG+yXlSxDZDmM2zkJJwgT24L9k0ZoQ4+waOSy4KN5/IHbjsiteG9U9sBtacP 9UImkM6Sy+kHRTv79onEGs/ioTiRi+ShLvqfgDXg45iRtaLcDIFindIQfus9mXo3IfqmR mbk8lN8cloHiy1Vo4WGsZVmhFG7DTuy4d2g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some virtual machine managers like kvmtool can relocate the devices in the system memory map. The information about the devices location in memory is described in the device tree. Therefore, the CFI memory region and the associated Non volatile storage variables need to be adjusted accordingly. To support such use cases the non-volatile storage variable base PCD PcdFlashNvStorageVariableBase has been defined as a dynamic PCD. The NOR flash driver was using the Flash non-volatile storage variable base PCD as a fixed PCD, thereby preventing runtime resolution of the variable base address. Therefore update the NOR flash driver to load the PCD using PcdGet32 instead of FixedPcdGet32. Signed-off-by: Sami Mujawar Reviewed-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c b/ArmPlatf= ormPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c index e248fdf6db94191648b5d33bf1a9263f446ee141..9cdd85096a463f69b3b864cecde= af247e65f4f73 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c @@ -1,6 +1,6 @@ /*++ @file NorFlashFvbDxe.c =20 - Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2011 - 2020, ARM Ltd. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -736,7 +736,7 @@ NorFlashFvbInitialize ( EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); ASSERT_EFI_ERROR (Status); =20 - mFlashNvStorageVariableBase =3D FixedPcdGet32 (PcdFlashNvStorageVariable= Base); + mFlashNvStorageVariableBase =3D PcdGet32 (PcdFlashNvStorageVariableBase); =20 // Set the index of the first LBA for the FVB Instance->StartLba =3D (PcdGet32 (PcdFlashNvStorageVariableBase) - Insta= nce->RegionBaseAddress) / Instance->Media.BlockSize; --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 14 May 2020 08:44:37 +0000 X-Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1415.2; Thu, 14 May 2020 08:40:28 +0000 X-Received: from E107187.Arm.com (10.57.42.179) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 14 May 2020 08:40:27 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , Subject: [edk2-devel] [PATCH v2 06/11] ArmVirtPkg: Add kvmtool platform driver Date: Thu, 14 May 2020 09:40:14 +0100 Message-ID: <20200514084019.71368-7-sami.mujawar@arm.com> In-Reply-To: <20200514084019.71368-1-sami.mujawar@arm.com> References: <20200514084019.71368-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(4636009)(376002)(136003)(396003)(39860400002)(346002)(46966005)(54906003)(70206006)(186003)(26005)(6666004)(316002)(1076003)(2616005)(7696005)(8676002)(5660300002)(36756003)(336012)(8936002)(70586007)(6916009)(86362001)(44832011)(426003)(356005)(966005)(2906002)(47076004)(82310400002)(82740400003)(478600001)(81166007)(4326008);DIR:OUT;SFP:1101; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: 93LXj5bNSoRDtbRfxIEn3m8Kx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445883; bh=LAFimL2uAUoCqrERnyPkvAyHrIsIv2yqzXLeYJXo8X0=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=j74OPwAqv7ejjXCma+/R+vKxRrw6jAGRryP03Uisp9v2uatMupOxUOHcKCKFQ0W+221 8lK1d1sEE87HJxpSWBkUyJmOrzO031BsCcPCZCw/F6V4iiOj9rY/eItlr9RyDJAsTJrmV T2k1E5LYtT0y6v9Arn+nB8yRxrGnHy8H9Ww= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Kvmtool is a virtual machine manager that enables hosting KVM guests. It essentially provides an emulated platform for guest operating systems. Kvmtool hands of a device tree containing the current hardware configuration to the firmware. A standards-based operating system would use ACPI to consume the platform hardware information, while some operating systems may prefer to use Device Tree. The KvmtoolPlatformDxe performs the platform actions like determining if the firmware should expose ACPI or the Device Tree based hardware description to the operating system. Signed-off-by: Sami Mujawar Acked-by: Laszlo Ersek --- Notes: v2: - Updated according to review comments. [Sami] =20 v1: - Add kvmtool platform driver to support loading platform [Sami] specific information. - Keep code to initialise the variable storage PCDs in the [Laszlo] platform-specific FVB driver. - Document code derived from [Laszlo] "ArmVirtPkg/PlatformHasAcpiDtDxe" Ref: https://edk2.groups.io/g/devel/topic/30915278#30757 ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.c | 93 ++++++++++++++++= ++++ ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf | 47 ++++++++++ 2 files changed, 140 insertions(+) diff --git a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.c b/ArmVirtPk= g/KvmtoolPlatformDxe/KvmtoolPlatformDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..e7568f66f5ebeb0423fc1c10345= cd8dad0800d94 --- /dev/null +++ b/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.c @@ -0,0 +1,93 @@ +/** @file + + The KvmtoolPlatformDxe performs the platform specific initialization lik= e: + - It decides if the firmware should expose ACPI or Device Tree-based + hardware description to the operating system. + + Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** Decide if the firmware should expose ACPI tables or Device Tree and + install the appropriate protocol interface. + + Note: This function is derived from "ArmVirtPkg/PlatformHasAcpiDtDxe", + by dropping the word size check, and the fw_cfg check. + + @param [in] ImageHandle Handle for this image. + + @retval EFI_SUCCESS Success. + @retval EFI_OUT_OF_RESOURCES There was not enough memory to install t= he + protocols. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + +**/ +STATIC +EFI_STATUS +PlatformHasAcpiDt ( + IN EFI_HANDLE ImageHandle + ) +{ + if (!PcdGetBool (PcdForceNoAcpi)) { + // Expose ACPI tables + return gBS->InstallProtocolInterface ( + &ImageHandle, + &gEdkiiPlatformHasAcpiGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + } + + // Expose the Device Tree. + return gBS->InstallProtocolInterface ( + &ImageHandle, + &gEdkiiPlatformHasDeviceTreeGuid, + EFI_NATIVE_INTERFACE, + NULL + ); +} + +/** Entry point for Kvmtool Platform Dxe + + @param [in] ImageHandle Handle for this image. + @param [in] SystemTable Pointer to the EFI system table. + + @retval EFI_SUCCESS Success. + @retval EFI_OUT_OF_RESOURCES There was not enough memory to install t= he + protocols. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + +**/ +EFI_STATUS +EFIAPI +KvmtoolPlatformDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D PlatformHasAcpiDt (ImageHandle); + if (EFI_ERROR (Status)) { + goto Failed; + } + + return Status; + +Failed: + ASSERT_EFI_ERROR (Status); + CpuDeadLoop (); + + return Status; +} diff --git a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf b/ArmVirt= Pkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..08a0fe5ce14469133479046385b= dd48c22698639 --- /dev/null +++ b/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf @@ -0,0 +1,47 @@ +#/** @file +# +# The KvmtoolPlatformDxe performs the platform specific initialization li= ke: +# - It decides if the firmware should expose ACPI or Device Tree-based +# hardware description to the operating system. +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D KvmtoolPlatformDxe + FILE_GUID =3D 7479CCCD-D721-442A-8C73-A72DBB886669 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D KvmtoolPlatformDxeEntryPoint + +[Sources] + KvmtoolPlatformDxe.c + +[Packages] + ArmVirtPkg/ArmVirtPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DxeServicesTableLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + gEdkiiPlatformHasAcpiGuid ## SOMETIMES_PRODUCES ## PROTOCOL + gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL + +[Pcd] + gArmVirtTokenSpaceGuid.PcdForceNoAcpi + +[Depex] + TRUE --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 14 May 2020 08:44:38 +0000 X-Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1415.2; Thu, 14 May 2020 08:40:28 +0000 X-Received: from E107187.Arm.com (10.57.42.179) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 14 May 2020 08:40:28 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , Subject: [edk2-devel] [PATCH v1 07/11] ArmVirtPkg: kvmtool platform memory map Date: Thu, 14 May 2020 09:40:15 +0100 Message-ID: <20200514084019.71368-8-sami.mujawar@arm.com> In-Reply-To: <20200514084019.71368-1-sami.mujawar@arm.com> References: <20200514084019.71368-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(4636009)(39860400002)(396003)(376002)(136003)(346002)(46966005)(4326008)(47076004)(36756003)(7696005)(1076003)(8936002)(81166007)(5660300002)(356005)(86362001)(8676002)(82740400003)(82310400002)(2906002)(6666004)(6916009)(478600001)(336012)(2616005)(70586007)(70206006)(54906003)(26005)(44832011)(186003)(426003)(316002);DIR:OUT;SFP:1101; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: ohRmv4ziRRvJQ8IXYc5W1kKEx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445890; bh=BspGQXcMmFQlXq1Yxdg/4sbY3GyrigfPidKt61W+GOU=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=bPnOpxstv/dY88+BBUDSfakQJgdvaVPiGgI3gBZXSxjTQJvkD9rWtqe0WgpWOKfNFHg TBdmpAdQKmKZ7hkK0+02R5xAMM/ecP1T+F2wauxaxiCJd0psZWK76ascVidyplWOepoQ3 uLkx49Ej4ZIPEHByi18SR1Uh9I+HaphdL7w= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Kvmtool is a virtual machine manager that enables hosting KVM guests. Kvmtool allows to vary the hardware configuration of the emulated platform it provides to the guest partition. It provides the current hardware configuration to the firmware by handing off a device tree containing the hardware information. This library parses the kvmtool provided device tree and populates the system memory map for the kvmtool emulated platform. Signed-off-by: Sami Mujawar Acked-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel --- ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMemInfoLib.c | 114 += +++++++++++++++++++ ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMemInfoLib.inf | 42 += +++++++ 2 files changed, 156 insertions(+) diff --git a/ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMemInfoLib= .c b/ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMemInfoLib.c new file mode 100644 index 0000000000000000000000000000000000000000..0d353733478b2d097d160246007= 022990a9cbacb --- /dev/null +++ b/ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMemInfoLib.c @@ -0,0 +1,114 @@ +/** @file + + Copyright (c) 2018, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +// Number of Virtual Memory Map Descriptors +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5 + +#define LOG_VM_MAP(txt) \ + DEBUG (( \ + DEBUG_ERROR, \ + "%a: " #txt "\n" \ + "\tPhysicalBase: 0x%lX\n" \ + "\tVirtualBase: 0x%lX\n" \ + "\tLength: 0x%lX\n", \ + __FUNCTION__, \ + VirtualMemoryTable[Idx].PhysicalBase, \ + VirtualMemoryTable[Idx].VirtualBase, \ + VirtualMemoryTable[Idx].Length \ + )); + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR + describing a Physical-to-Virtual Memory + mapping. This array must be ended by a + zero-filled entry. The allocated memory + will not be freed. + +**/ +VOID +ArmVirtGetMemoryMap ( + OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + UINTN Idx =3D 0; + EFI_PHYSICAL_ADDRESS TopOfAddressSpace; + + ASSERT (VirtualMemoryMap !=3D NULL); + + TopOfAddressSpace =3D LShiftU64 (1ULL, ArmGetPhysicalAddressBits ()); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*) + AllocatePages ( + EFI_SIZE_TO_PAGES ( + sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + ) + ); + + if (VirtualMemoryTable =3D=3D NULL) { + DEBUG (( + DEBUG_ERROR, + "%a: Error: Failed to Allocate Pages\n", + __FUNCTION__ + )); + return; + } + + // System DRAM + VirtualMemoryTable[Idx].PhysicalBase =3D PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Idx].VirtualBase =3D VirtualMemoryTable[Idx].Physica= lBase; + VirtualMemoryTable[Idx].Length =3D PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Idx].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_WRI= TE_BACK; + LOG_VM_MAP ("System DRAM Memory Map"); + + // Peripheral space before DRAM + VirtualMemoryTable[++Idx].PhysicalBase =3D 0x0; + VirtualMemoryTable[Idx].VirtualBase =3D 0x0; + VirtualMemoryTable[Idx].Length =3D PcdGet64 (PcdSystemMemoryBase= ); + VirtualMemoryTable[Idx].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + LOG_VM_MAP ("Peripheral space before DRAM"); + + // Peripheral space after DRAM + VirtualMemoryTable[++Idx].PhysicalBase =3D PcdGet64 (PcdSystemMemoryBase= ) + + PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Idx].VirtualBase =3D VirtualMemoryTable[Idx].Physi= calBase; + VirtualMemoryTable[Idx].Length =3D TopOfAddressSpace - + VirtualMemoryTable[Idx].Physica= lBase; + VirtualMemoryTable[Idx].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + LOG_VM_MAP ("Peripheral space after DRAM"); + + // Map the FV region as normal executable memory + VirtualMemoryTable[++Idx].PhysicalBase =3D PcdGet64 (PcdFvBaseAddress); + VirtualMemoryTable[Idx].VirtualBase =3D VirtualMemoryTable[Idx].Physica= lBase; + VirtualMemoryTable[Idx].Length =3D FixedPcdGet32 (PcdFvSize); + VirtualMemoryTable[Idx].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_WRI= TE_BACK; + LOG_VM_MAP ("FV region"); + + // End of Table + VirtualMemoryTable[++Idx].PhysicalBase =3D 0; + VirtualMemoryTable[Idx].VirtualBase =3D 0; + VirtualMemoryTable[Idx].Length =3D 0; + VirtualMemoryTable[Idx].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTE= S)0; + + ASSERT((Idx + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMemInfoLib= .inf b/ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMemInfoLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..dbf4ceabe3ae0db5e743e1d9a57= 5542dca32ed0a --- /dev/null +++ b/ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMemInfoLib.inf @@ -0,0 +1,42 @@ +#/* @file +# +# Copyright (c) 2018, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D KvmtoolVirtMemInfoLib + FILE_GUID =3D B752E953-394F-462C-811C-F8BE35C8C071 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmVirtMemInfoLib + +[Sources] + KvmtoolVirtMemInfoLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmVirtPkg/ArmVirtPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + BaseLib + BaseMemoryLib + DebugLib + MemoryAllocationLib + PcdLib + +[Pcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvSize + --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 14 May 2020 08:44:39 +0000 X-Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1415.2; Thu, 14 May 2020 08:40:29 +0000 X-Received: from E107187.Arm.com (10.57.42.179) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 14 May 2020 08:40:29 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , Subject: [edk2-devel] [PATCH v1 08/11] ArmVirtPkg: Add Kvmtool NOR flash lib Date: Thu, 14 May 2020 09:40:16 +0100 Message-ID: <20200514084019.71368-9-sami.mujawar@arm.com> In-Reply-To: <20200514084019.71368-1-sami.mujawar@arm.com> References: <20200514084019.71368-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(4636009)(136003)(396003)(39860400002)(346002)(376002)(46966005)(82310400002)(8676002)(47076004)(54906003)(44832011)(70586007)(86362001)(8936002)(6916009)(82740400003)(4326008)(26005)(356005)(36756003)(2616005)(6666004)(7696005)(5660300002)(336012)(81166007)(2906002)(186003)(70206006)(1076003)(478600001)(426003)(316002);DIR:OUT;SFP:1101; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: 5DSQpTnWcSKvc6YQ3uiNwgKSx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445891; bh=S3M3g7uusXa4ZnS/p2wn8/PhpUhpcacp/0ajxqtswrc=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=hkrPLG+uugS+krfSd4YJiQLBcjBzK5cLIuHRQXyDxvGdu6uifp9qtu8kmYWfqL1PRFp zUxSr1eD0B8C/OpGCrZB3QhXgToaZhQUTtuxUy6FGDUansxeAjebv/DiJE+DF3Lf4mdX5 BCRt0of+F2yyGJSlRfiWJC/Mge/UA9tS5RM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Kvmtool places the base address of the CFI flash in the device tree it passes to UEFI. This library parses the kvmtool device tree to read the CFI base address and initialise the PCDs use by the NOR flash driver and the variable storage. Signed-off-by: Sami Mujawar Acked-by: Laszlo Ersek --- ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtool.c | 265 +++++++= +++++++++++++ ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtoolLib.inf | 50 ++++ 2 files changed, 315 insertions(+) diff --git a/ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtool.c b/ArmV= irtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtool.c new file mode 100644 index 0000000000000000000000000000000000000000..2e43c2e21bc9ef7dd1dd198eebb= d70c3b0b96d1c --- /dev/null +++ b/ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtool.c @@ -0,0 +1,265 @@ +/** @file + An instance of the NorFlashPlatformLib for Kvmtool platform. + + Copyright (c) 2020, ARM Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include +#include +#include + +/** Macro defining the maximum number of Flash Banks. + */ +#define MAX_FLASH_BANKS 4 + +STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[MAX_FLASH_BANKS]; +STATIC UINTN mNorFlashDeviceCount =3D 0; + +/** This function performs platform specific actions to initialise + the NOR flash, if required. + + @retval EFI_SUCCESS Success. +**/ +EFI_STATUS +NorFlashPlatformInitialization ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "NorFlashPlatformInitialization\n")); + // Nothing to do here + return EFI_SUCCESS; +} + +/** Initialise Non volatile Flash storage variables. + + @param [in] FlashDevice Pointer to the NOR Flash device. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_OUT_OF_RESOURCES Insufficient flash storage space. +**/ +EFI_STATUS +SetupVariableStore ( + IN NOR_FLASH_DESCRIPTION * FlashDevice + ) +{ + UINTN FlashRegion; + UINTN FlashNvStorageVariableBase; + UINTN FlashNvStorageFtwWorkingBase; + UINTN FlashNvStorageFtwSpareBase; + UINTN FlashNvStorageVariableSize; + UINTN FlashNvStorageFtwWorkingSize; + UINTN FlashNvStorageFtwSpareSize; + + FlashNvStorageVariableSize =3D PcdGet32 (PcdFlashNvStorageVariableSize); + FlashNvStorageFtwWorkingSize =3D PcdGet32 (PcdFlashNvStorageFtwWorkingSi= ze); + FlashNvStorageFtwSpareSize =3D PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + if ((FlashNvStorageVariableSize =3D=3D 0) || + (FlashNvStorageFtwWorkingSize =3D=3D 0) || + (FlashNvStorageFtwSpareSize =3D=3D 0)) { + DEBUG ((DEBUG_ERROR, "FlashNvStorage size not defined\n")); + return EFI_INVALID_PARAMETER; + } + + // Setup the variable store + FlashRegion =3D FlashDevice->DeviceBaseAddress; + + FlashNvStorageVariableBase =3D FlashRegion; + FlashRegion +=3D PcdGet32 (PcdFlashNvStorageVariableSize); + + FlashNvStorageFtwWorkingBase =3D FlashRegion; + FlashRegion +=3D PcdGet32 (PcdFlashNvStorageFtwWorkingSize); + + FlashNvStorageFtwSpareBase =3D FlashRegion; + FlashRegion +=3D PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + if (FlashRegion > (FlashDevice->DeviceBaseAddress + FlashDevice->Size)) { + DEBUG ((DEBUG_ERROR, "Insufficient flash storage size\n")); + return EFI_OUT_OF_RESOURCES; + } + + PcdSet32S ( + PcdFlashNvStorageVariableBase, + FlashNvStorageVariableBase + ); + + PcdSet32S ( + PcdFlashNvStorageFtwWorkingBase, + FlashNvStorageFtwWorkingBase + ); + + PcdSet32S ( + PcdFlashNvStorageFtwSpareBase, + FlashNvStorageFtwSpareBase + ); + + DEBUG (( + DEBUG_INFO, + "PcdFlashNvStorageVariableBase =3D 0x%x\n", + FlashNvStorageVariableBase + )); + DEBUG (( + DEBUG_INFO, + "PcdFlashNvStorageVariableSize =3D 0x%x\n", + FlashNvStorageVariableSize + )); + DEBUG (( + DEBUG_INFO, + "PcdFlashNvStorageFtwWorkingBase =3D 0x%x\n", + FlashNvStorageFtwWorkingBase + )); + DEBUG (( + DEBUG_INFO, + "PcdFlashNvStorageFtwWorkingSize =3D 0x%x\n", + FlashNvStorageFtwWorkingSize + )); + DEBUG (( + DEBUG_INFO, + "PcdFlashNvStorageFtwSpareBase =3D 0x%x\n", + FlashNvStorageFtwSpareBase + )); + DEBUG (( + DEBUG_INFO, + "PcdFlashNvStorageFtwSpareSize =3D 0x%x\n", + FlashNvStorageFtwSpareSize + )); + + return EFI_SUCCESS; +} + +/** Return the Flash devices on the platform. + + @param [out] NorFlashDescriptions Pointer to the Flash device descri= ption. + @param [out] Count Number of Flash devices. + + @retval EFI_SUCCESS Success. + @retval EFI_NOT_FOUND Flash device not found. +**/ +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions, + OUT UINT32 *Count + ) +{ + if (mNorFlashDeviceCount > 0) { + *NorFlashDescriptions =3D mNorFlashDevices; + *Count =3D mNorFlashDeviceCount; + return EFI_SUCCESS; + } + return EFI_NOT_FOUND; +} + +/** Entrypoint for NorFlashPlatformLib. + + @param [in] ImageHandle The handle to the image. + @param [in] SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND Flash device not found. +**/ +EFI_STATUS +EFIAPI +NorFlashPlatformLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE * SystemTable + ) +{ + FDT_CLIENT_PROTOCOL *FdtClient; + INT32 Node; + EFI_STATUS Status; + EFI_STATUS FindNodeStatus; + CONST UINT32 *Reg; + UINT32 PropSize; + UINT64 Base; + UINT64 Size; + + if (mNorFlashDeviceCount !=3D 0) { + return EFI_SUCCESS; + } + + Status =3D gBS->LocateProtocol ( + &gFdtClientProtocolGuid, + NULL, + (VOID **)&FdtClient + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + for (FindNodeStatus =3D FdtClient->FindCompatibleNode ( + FdtClient, + "cfi-flash", + &Node + ); + !EFI_ERROR (FindNodeStatus) && (mNorFlashDeviceCount < MAX_FLASH_BA= NKS); + FindNodeStatus =3D FdtClient->FindNextCompatibleNode ( + FdtClient, + "cfi-flash", + Node, + &Node + )) { + Status =3D FdtClient->GetNodeProperty ( + FdtClient, + Node, + "reg", + (CONST VOID **)&Reg, + &PropSize + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: GetNodeProperty () failed (Status =3D=3D %= r)\n", + __FUNCTION__, Status)); + continue; + } + + ASSERT ((PropSize % (4 * sizeof (UINT32))) =3D=3D 0); + + while ((PropSize >=3D (4 * sizeof (UINT32))) && + (mNorFlashDeviceCount < MAX_FLASH_BANKS)) { + Base =3D SwapBytes64 (ReadUnaligned64 ((VOID *)&Reg[0])); + Size =3D SwapBytes64 (ReadUnaligned64 ((VOID *)&Reg[2])); + Reg +=3D 4; + + PropSize -=3D 4 * sizeof (UINT32); + + // + // Disregard any flash devices that overlap with the primary FV. + // The firmware is not updatable from inside the guest anyway. + // + if ((PcdGet64 (PcdFvBaseAddress) + PcdGet32 (PcdFvSize) > Base) && + (Base + Size) > PcdGet64 (PcdFvBaseAddress)) { + continue; + } + + DEBUG (( + DEBUG_INFO, + "NOR%d : Base =3D 0x%lx, Size =3D 0x%lx\n", + mNorFlashDeviceCount, + Base, + Size + )); + + mNorFlashDevices[mNorFlashDeviceCount].DeviceBaseAddress =3D (UINTN)= Base; + mNorFlashDevices[mNorFlashDeviceCount].RegionBaseAddress =3D (UINTN)= Base; + mNorFlashDevices[mNorFlashDeviceCount].Size =3D (UINTN)= Size; + mNorFlashDevices[mNorFlashDeviceCount].BlockSize =3D SIZE_25= 6KB; + mNorFlashDeviceCount++; + } + } + + // Setup the variable store in the last bank + if ((mNorFlashDeviceCount > 0) && + (mNorFlashDevices[mNorFlashDeviceCount - 1].DeviceBaseAddress !=3D 0= )) { + return SetupVariableStore (&mNorFlashDevices[mNorFlashDeviceCount - 1]= ); + } + + return EFI_NOT_FOUND; +} + diff --git a/ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtoolLib.inf b= /ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtoolLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..8bd6f730dcb52e597b418e59766= c1566a9519789 --- /dev/null +++ b/ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtoolLib.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2020, ARM Ltd. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D NorFlashKvmtoolLib + FILE_GUID =3D E75F07A1-B160-4893-BDD4-09E32FF847DC + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NorFlashPlatformLib + CONSTRUCTOR =3D NorFlashPlatformLibConstructor + +[Sources.common] + NorFlashKvmtool.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmVirtPkg/ArmVirtPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + UefiBootServicesTableLib + +[Protocols] + gFdtClientProtocolGuid ## CONSUMES + +[Pcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + + +[Depex] + gFdtClientProtocolGuid + --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 14 May 2020 08:44:40 +0000 X-Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1415.2; Thu, 14 May 2020 08:40:30 +0000 X-Received: from E107187.Arm.com (10.57.42.179) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 14 May 2020 08:40:30 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , Subject: [edk2-devel] [PATCH v2 09/11] ArmVirtPkg: Support for kvmtool emulated platform Date: Thu, 14 May 2020 09:40:17 +0100 Message-ID: <20200514084019.71368-10-sami.mujawar@arm.com> In-Reply-To: <20200514084019.71368-1-sami.mujawar@arm.com> References: <20200514084019.71368-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(4636009)(136003)(396003)(39860400002)(346002)(376002)(46966005)(8676002)(8936002)(86362001)(30864003)(4326008)(19627235002)(966005)(70206006)(26005)(54906003)(7696005)(186003)(6916009)(82310400002)(47076004)(70586007)(6666004)(82740400003)(36756003)(44832011)(336012)(5660300002)(2616005)(1076003)(356005)(81166007)(316002)(478600001)(2906002)(426003);DIR:OUT;SFP:1101; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: Of6gjeocjw20vpd1kYkcbLZax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445899; bh=UUEceVZ8elk5KMO+5fwHOsxYcxdMJqFY/raRfLJ0qGo=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=sNaGvDQ+91pHpuCgrsRAYch36HxhjlC+/Xq/hpUKjPO6SThpzua47m11AMrZr7drtDH CSal2oaJBsPOY9rlc+Qqgvsu31AsndM1PUu6oD/wyx3atLTjQY/mYyFBqynBom9FZMZ/N UhzXyUjWfZDZkoCrN1rdijy7FKhp8+XE2D0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Kvmtool is a virtual machine manager that enables hosting KVM guests. Kvmtool emulates certain devices like serial port, RTC, etc. essentially providing an emulated platform. This patch adds support for kvmtool emulated platform. Following is a brief description of the firmware implementation choices: - Serial Port: 16550 UART On some platforms the 16550 UART is interfaced using PCI. Therefore, the 16550 Serial port library is dependent on the PCI library. The 16550 UART driver checks the Device ID represented using the PCD gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo to determine if the UART is behind PCI. If the Device ID is 0xFF then the serial 16550 UART is not behind PCI. For such platforms a NULL implementation of the PCI library has been provided so that the serial output is available during the early boot stages. On Kvmtool the Serial 16550 UART is not behind PCI, and therefore makes use of PciLibNull library during early boot stages. The DXE modules that make use of PCI functionality explicitly include the library BasePciLibPciExpress, so that the required PCI functionality is available. The PcdSerialPciDeviceInfo is also set to 0xFF to indicate that the Serial 16550 UART is not behind PCI. The PCD PcdSerialUseMmio is also set to TRUE to indicate MMIO accesses are required for the UART registers. - Dependency order for Flash FaultTolerantWriteDxe makes use of PCDs (e.g. PcdFlashNvStorageFtwSpareBase64 etc.), which in case of kvmtool will be evaluated based on the CFI flash base address read from the DT. These variables are populated in the NorFlashPlatformLib loaded by ArmVeNorFlashDxe. This results in a dependency issue with FaultTolerantWriteDxe. To resolve this make the NorFlashPlatformLib as a library dependency for FaultTolerantWriteDxe. Signed-off-by: Sami Mujawar Acked-by: Laszlo Ersek --- Notes: v2: - Updates to reflect review comments and support [Sami] for latest features emulated by kvmtool e.g. CFI. =20 v1: - Add support for Kvmtool emulated platform [Sami] - Add more justification for platform and [Laszlo] document platform maintainer. Ref: https://edk2.groups.io/g/devel/topic/30915279#30693 ArmVirtPkg/ArmVirtKvmTool.dsc | 408 ++++++++++++++++++++ ArmVirtPkg/ArmVirtKvmTool.fdf | 276 +++++++++++++ 2 files changed, 684 insertions(+) diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc new file mode 100644 index 0000000000000000000000000000000000000000..b2dc5eb2a09521c57a30babbee4= 0749abdb7f7ff --- /dev/null +++ b/ArmVirtPkg/ArmVirtKvmTool.dsc @@ -0,0 +1,408 @@ +# @file +# Workspace file for KVMTool virtual platform. +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D ArmVirtKvmTool + PLATFORM_GUID =3D 4CB2C61E-FA32-4130-8E37-54ABC71A1A43 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001B +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY =3D $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY =3D Build/ArmVirtKvmTool-$(ARCH) +!endif + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D ArmVirtPkg/ArmVirtKvmTool.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE HTTP_BOOT_ENABLE =3D FALSE + DEFINE TTY_TERMINAL =3D TRUE + DEFINE ENABLE_NETWORK =3D TRUE + DEFINE TPM2_ENABLE =3D FALSE + +!include ArmVirtPkg/ArmVirt.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf + + ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibN= ull.inf + ArmVirtMemInfoLib|ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/KvmtoolVirtMe= mInfoLib.inf + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + NorFlashPlatformLib|ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtoo= lLib.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + + # BDS Libraries + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + PciPcdProducerLib|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProdu= cerLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridge= Lib.inf + +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + +!if $(TPM2_ENABLE) =3D=3D FALSE + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + +[LibraryClasses.common, LibraryClasses.common.SEC, LibraryClasses.common.P= EI_CORE, LibraryClasses.common.PEIM] + # The 16550 Serial port library is dependent on PCI library. + # A null implementation of the PCI Library has been provided so that + # the serial output is available during the early boot stages. + # The DXE modules that make use of PCI override the PciLibNull library + # and are individually linked with the real PCI library. + PciLib|MdePkg/Library/PciLibNull/PciLibNull.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort= Lib16550.inf + +[LibraryClasses.common.UEFI_DRIVER] + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + +[BuildOptions.ARM.EDKII.SEC, BuildOptions.ARM.EDKII.BASE] + # Avoid MOVT/MOVW instruction pairs in code that may end up in the PIE + # executable we build for the relocatable PrePi. They are not runtime + # relocatable in ELF. + *_CLANG35_*_CC_FLAGS =3D -mno-movt + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + ## If TRUE, Graphics Output Protocol will be installed on virtual handle= created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + + gArmVirtTokenSpaceGuid.PcdTpm2SupportEnabled|$(TPM2_ENABLE) + +[PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 + +!if $(ARCH) =3D=3D AARCH64 + gArmTokenSpaceGuid.PcdVFPEnabled|1 +!endif + + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 + + # + # ARM PrimeCell + # + ## Default Terminal Type + ## 0-PCANSI, 1-VT100, 2-VT00+, 3-UTF8, 4-TTYTERM +#!if $(TTY_TERMINAL) =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 +#!else +# gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1 +#!endif + + # + # ARM Virtual Architectural Timer -- fetch frequency from KVM + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0 + +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE +!endif + + # Use MMIO for accessing Serial port registers. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xFF} + + # Use MMIO for accessing RTC controller registers. + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcUseMmio|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + # + # The maximum physical I/O addressability of the processor, set with + # BuildCpuHob(). + # + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16 + +[PcdsPatchableInModule.common] + # + # This will be overridden in the code + # + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x0 + + # + # The device tree base address is handed off by kvmtool. + # We are booting from RAM using the Linux kernel boot protocol, + # x0 will point to the DTB image in memory. + # + gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress|0x0 + + gArmTokenSpaceGuid.PcdFdBaseAddress|0x0 + gArmTokenSpaceGuid.PcdFvBaseAddress|0x0 + + # we need to provide a resolution for this PCD that supports PcdSet64() + # being called from ArmVirtPkg/Library/PlatformPeiLib/PlatformPeiLib.c, + # even though that call will be compiled out on this platform as it does + # not (and cannot) support the TPM2 driver stack + gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0 + +[PcdsDynamicDefault.common] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|0x0 + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|0x0 + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|0x0 + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|0x0 + + # + # ARM General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x0 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x0 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0 + + # + # PCI settings + # + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE + + # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this + # PCD and PcdPciDisableBusEnumeration above have not been assigned yet + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xFFFFFFFFFFFFFFFF + + gArmTokenSpaceGuid.PcdPciIoTranslation|0x0 + + # + # Set video resolution for boot options and for text setup. + # PlatformDxe can set the former at runtime. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + + ## Force DTB + gArmVirtTokenSpaceGuid.PcdForceNoAcpi|TRUE + + # Setup Flash storage variables + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x40000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x40000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x40000 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # PEI Phase modules + # + ArmVirtPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf { + + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectio= nLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaC= ustomDecompressLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib= /PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/Pre= PiMemoryAllocationLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedL= ib.inf + # don't use unaligned CopyMem () on the UEFI varstore NOR flash regi= on + BaseMemoryLib|MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.inf + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf { + + NULL|ArmVirtPkg/Library/NorFlashKvmtoolLib/NorFlashKvmtoolLib.inf + } + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.i= nf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf { + + NULL|ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClie= ntLib.inf + } + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf { + + BaseMemoryLib|MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.inf + } + + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # Platform Driver + # + ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf + ArmVirtPkg/VirtioFdtDxe/VirtioFdtDxe.inf + ArmVirtPkg/FdtClientDxe/FdtClientDxe.inf + ArmVirtPkg/HighMemDxe/HighMemDxe.inf + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + OvmfPkg/VirtioScsiDxe/VirtioScsi.inf + OvmfPkg/VirtioNetDxe/VirtioNet.inf + OvmfPkg/VirtioRngDxe/VirtioRng.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Logo/LogoDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + +!if $(ENABLE_NETWORK) =3D=3D TRUE + # + # Networking stack + # + NetworkPkg/SnpDxe/SnpDxe.inf + NetworkPkg/DpcDxe/DpcDxe.inf + NetworkPkg/ArpDxe/ArpDxe.inf + NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf + NetworkPkg/Ip4Dxe/Ip4Dxe.inf + NetworkPkg/MnpDxe/MnpDxe.inf + NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf + NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf + NetworkPkg/Udp4Dxe/Udp4Dxe.inf + NetworkPkg/TcpDxe/TcpDxe.inf + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + NetworkPkg/IScsiDxe/IScsiDxe.inf +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + NetworkPkg/DnsDxe/DnsDxe.inf + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + NetworkPkg/HttpDxe/HttpDxe.inf + NetworkPkg/HttpBootDxe/HttpBootDxe.inf +!endif +!endif + # + # SCSI Bus and Disk Driver + # + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # PCI support + # + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf { + + NULL|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + } + + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + + NULL|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + + OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf + OvmfPkg/Virtio10Dxe/Virtio10.inf diff --git a/ArmVirtPkg/ArmVirtKvmTool.fdf b/ArmVirtPkg/ArmVirtKvmTool.fdf new file mode 100644 index 0000000000000000000000000000000000000000..8b794e6a1f3652f3262faa35b37= f2f8d36d5438d --- /dev/null +++ b/ArmVirtPkg/ArmVirtKvmTool.fdf @@ -0,0 +1,276 @@ +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.KVMTOOL_EFI] +BaseAddress =3D 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress +# The size in bytes of the FLASH Device +Size =3D 0x00200000|gArmTokenSpaceGuid.PcdFdSize +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x00001000 +NumBlocks =3D 0x200 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### + +# +# Implement the Linux kernel header layout so that the loader will identify +# it as something bootable, and execute it with a FDT pointer in x0 or r2. +# This area will be reused to store a copy of the FDT so round it up to 32= KB. +# +0x00000000|0x00008000 +DATA =3D { +!if $(ARCH) =3D=3D AARCH64 + 0x01, 0x00, 0x00, 0x10, # code0: adr x1, . + 0xff, 0x1f, 0x00, 0x14, # code1: b 0x8000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, # text_offset: 512 KB + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, # image_size: 2 MB + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # flags + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res2 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res3 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # res4 + 0x41, 0x52, 0x4d, 0x64, # magic: "ARM\x64" + 0x00, 0x00, 0x00, 0x00 # res5 +!else + 0x08, 0x10, 0x4f, 0xe2, # adr r1, . + 0x02, 0x00, 0xa0, 0xe1, # mov r0, r2 (DTB) + 0x00, 0x00, 0xa0, 0xe1, # nop + 0x00, 0x00, 0xa0, 0xe1, # nop + 0x00, 0x00, 0xa0, 0xe1, # nop + 0x00, 0x00, 0xa0, 0xe1, # nop + 0x00, 0x00, 0xa0, 0xe1, # nop + 0x00, 0x00, 0xa0, 0xe1, # nop + + 0xf6, 0x1f, 0x00, 0xea, # b 0x8000 + 0x18, 0x28, 0x6f, 0x01, # magic + 0x00, 0x00, 0x00, 0x00, # start + 0x00, 0x00, 0x20, 0x00, # image size: 2 MB + 0x01, 0x02, 0x03, 0x04 # endiannness flag +!endif +} + +0x00008000|0x001f8000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 64074afe-340a-4be6-94ba-91b5b4d0f71e +BlockSize =3D 0x40 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 16 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF ArmVirtPkg/VirtioFdtDxe/VirtioFdtDxe.inf + INF ArmVirtPkg/FdtClientDxe/FdtClientDxe.inf + INF ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf + INF ArmVirtPkg/HighMemDxe/HighMemDxe.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConf= igDxe.inf +!endif + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime= Dxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + + # + # Platform Driver + # + INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + INF OvmfPkg/VirtioNetDxe/VirtioNet.inf + INF OvmfPkg/VirtioScsiDxe/VirtioScsi.inf + INF OvmfPkg/VirtioRngDxe/VirtioRng.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe= .inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +!if $(ENABLE_NETWORK) =3D=3D TRUE + # + # Networking stack + # + INF NetworkPkg/SnpDxe/SnpDxe.inf + INF NetworkPkg/DpcDxe/DpcDxe.inf + INF NetworkPkg/ArpDxe/ArpDxe.inf + INF NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf + INF NetworkPkg/Ip4Dxe/Ip4Dxe.inf + INF NetworkPkg/MnpDxe/MnpDxe.inf + INF NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf + INF NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf + INF NetworkPkg/Udp4Dxe/Udp4Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF NetworkPkg/IScsiDxe/IScsiDxe.inf +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + INF NetworkPkg/DnsDxe/DnsDxe.inf + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + INF NetworkPkg/HttpDxe/HttpDxe.inf + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf +!endif +!endif + # + # SCSI Bus and Disk Driver + # + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + +!if $(ARCH) =3D=3D AARCH64 + # + # EBC support + # + INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf +!endif + + # + # PCI support + # + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf + INF OvmfPkg/Virtio10Dxe/Virtio10.inf + + # + # TianoCore logo (splash screen) + # + INF MdeModulePkg/Logo/LogoDxe.inf + + # + # Ramdisk support + # + INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmVirtPkg/PrePi/ArmVirtPrePiUniCoreRelocatable.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + +!include ArmVirtRules.fdf.inc --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 14 May 2020 08:44:41 +0000 X-Received: from AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1415.2; Thu, 14 May 2020 08:40:32 +0000 X-Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1779.2; Thu, 14 May 2020 08:40:32 +0000 X-Received: from E107187.Arm.com (10.57.42.179) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.1415.2 via Frontend Transport; Thu, 14 May 2020 08:40:31 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , Subject: [edk2-devel] [PATCH v1 10/11] ArmVirtPkg: Link NorFlashDxe with BaseMemoryLibMmio Date: Thu, 14 May 2020 09:40:18 +0100 Message-ID: <20200514084019.71368-11-sami.mujawar@arm.com> In-Reply-To: <20200514084019.71368-1-sami.mujawar@arm.com> References: <20200514084019.71368-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(4636009)(346002)(39860400002)(396003)(136003)(376002)(46966005)(70586007)(4326008)(70206006)(6916009)(82310400002)(2906002)(47076004)(478600001)(426003)(86362001)(81166007)(356005)(82740400003)(336012)(6666004)(26005)(54906003)(186003)(8936002)(36756003)(316002)(44832011)(5660300002)(1076003)(8676002)(2616005)(7696005);DIR:OUT;SFP:1101; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: 7SlLSG65SgXtPKQpgav8N7fqx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445899; bh=4Sfc/fhFPSn1BSgugQ0JHTE2/Hoq5rw9nyp70Mer4D8=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=Pg+5/bdZ41baWE++v0fw5TspfQSBBoxjqY0Q+ooaasglMozXl9ylJYxPUEy+yTnxngj WzE+oeRx6jBcnYc00ma9D7EzD5LcM2/2k0y+9QnRv4hcPDqCeNdYb7WsQv04I/e+rcwbW uMycbMmihF0awsMBJ8tSa9QNXDD4KkGyh3U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NorFlashDxe must use aligned MMIO accesses to read data from flash as this is device memory. The AlignedCopyMem() in NorFlashDxe was used to copy the flash data which prevented unaligned access to device memory. However, the compiler could optimize the code to generate pre/post indexed or LDP operations. This is a problem for guest/virtual firmware as the hypervisor code cannot get the syndrome information for the trapped accesses. To address the such issues, BaseMemoryLibMmio library has been introduced to perform aligned MMIO accesses. The NorFlashDxe has been updated to use CopyMem() instead of using AlignedCopyMem() and therefore the NorFlashDxe must be linked with BaseMemoryLibMmio. This patch updates the workspace files to link NorFlashDxe with BaseMemoryLibMmio for the following platforms: - Arm Qemu - Arm Qemu Kernel Signed-off-by: Sami Mujawar --- ArmVirtPkg/ArmVirtQemu.dsc | 8 ++++++-- ArmVirtPkg/ArmVirtQemuKernel.dsc | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index 3f649c91d8d6a2e3f3e62f35aa40906e048a15c4..82b7d54c2031fed60dccff38353= d3ec19cfdefd0 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2011-2020, ARM Limited. All rights reserved. # Copyright (c) 2014, Linaro Limited. All rights reserved. # Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. # @@ -384,7 +384,11 @@ [Components.common] NULL|ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClie= ntLib.inf } - ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf { + + BaseMemoryLib|MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.inf + } + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf =20 # diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKerne= l.dsc index 2a6fd6bc06be1cc20d8c6f2bf00d88d593061edf..6cceb61e493c8c84f6564b120b0= 864ff817c3f31 100644 --- a/ArmVirtPkg/ArmVirtQemuKernel.dsc +++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2011-2020, ARM Limited. All rights reserved. # Copyright (c) 2014, Linaro Limited. All rights reserved. # Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. # @@ -323,7 +323,11 @@ [Components.common] NULL|ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClie= ntLib.inf } - ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf { + + BaseMemoryLib|MdePkg/Library/BaseMemoryLibMmio/BaseMemoryLibMmio.inf + } + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf =20 # --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: YUTgLGoMEbxB2vB7M9NsUxLex1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589445893; bh=+bkA2eQnTqwC66Dma8Iua7T74VmZqfzaJ2uAF0bwSfQ=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=H4rRlTWz/HTnxu+GlyhWgDsgJWkXuHDh3pZFa8nGvS2QShi1dvA9Sz7SjQZiwNas9h2 NxT24Cdy4aALZmg+m+RPwsVqKod8iHDLbVwq5QSE/GTiXJbTxZ5SD5cAfy0v1fu24eKV2 ifQfk0wTMT609UhRP1L4vInQHXX4mTxbu+k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Kvmtool is a virtual machine manager that can be used to launch guest partitions. It additionally emulates some hardware components e.g. RTC, CFI etc. essentially providing an emulated virtual platform for a guest operating system (OS) to run. A standards-based OS would need UEFI firmware support for the Kvmtool emulated platform, for which additional modules are added to ArmVirtPkg. Adding myself as maintainer for these modules as advised on mailing list discussion at https://edk2.groups.io/g/devel/topic/30915279#30693 Signed-off-by: Sami Mujawar Reviewed-by: Laszlo Ersek --- Maintainers.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 896ac5821fc6602e25db79b9aa47e4c2329c530b..3006bc1ea2feb224f0f71083146= 6c5a6a876e3ee 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -152,6 +152,13 @@ F: ArmVirtPkg/XenPlatformHasAcpiDtDxe/ F: ArmVirtPkg/XenioFdtDxe/ R: Julien Grall =20 +ArmVirtPkg: Kvmtool emulated platform support +F: ArmVirtPkg/ArmVirtKvmTool.* +F: ArmVirtPkg/KvmtoolPlatformDxe/ +F: ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/ +F: ArmVirtPkg/Library/NorFlashKvmtoolLib/ +M: Sami Mujawar + BaseTools F: BaseTools/ W: https://github.com/tianocore/tianocore.github.io/wiki/BaseTools --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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