From nobody Sun May 5 12:33:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+59028+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+59028+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1589168030; cv=none; d=zohomail.com; s=zohoarc; b=nL7myRpW4Q8VGkex8xUwYWWtb9yrRXlfphI9/DSEI/du3G36ANbKYbP73T5p3vfw3vnALB1Q0DFzU9bPNNgIG/fU+Tjq7crg5+tG4NPXsw7RH21y53ZbsJEdlee+8loImsknPrSbSZcYO1wCZBd32zH2Pb0tAGCsocskP/EmCB0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1589168030; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=5/e+Hi6z/URGXC9Q9cnMKUHSF+v0NoyQ5EUF4iHS7Lc=; b=V4UXStqZFyp/SHOgZUL/BQYLQZupb4lHHK1bpeeXYKVdtHgraAyfK6oToRpbGQONr+Lk0mk2MC5ouAk4gf+C2+IJ1J5kbBNnQRoY8AjBBPNKlRxT7W1M0ACqKMo5VYqq20PTMSeeyI514Doal3Wu8CWncGwHamdY2zcIJWZDukE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+59028+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1589168030359552.7316376427736; Sun, 10 May 2020 20:33:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7R5eYY1788612xvkT7e0XPEW; Sun, 10 May 2020 20:33:49 -0700 X-Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web12.5756.1589168029105319598 for ; Sun, 10 May 2020 20:33:49 -0700 IronPort-SDR: z4xQlnhpR0tYomje0k/Mypg7OJ/JIUQJjSEpfV4afythx9Mc6lSc3nldRlD8BJgwkGVOJJmYhR A9XaKU3Un3tg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2020 20:33:48 -0700 IronPort-SDR: GdcbQYOITJWRwgitSMt014ijKkLxMI/s23hHwOJX10mODb3B/5LW4d22s23LiNDTDi1ZeKbaY2 eE9AGvCUPTEw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,378,1583222400"; d="scan'208";a="306057646" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.254.96.132]) by FMSMGA003.fm.intel.com with ESMTP; 10 May 2020 20:33:46 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Maurice Ma , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH v6] IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers. Date: Mon, 11 May 2020 11:31:32 +0800 Message-Id: <20200511033132.18616-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: Se5X5ZbU2ac4xc3FEXt8iVpcx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1589168029; bh=5xdVtLj2L+cktBuv9wLPlMvuHfLC5mho9CEj3dx8kzw=; h=Cc:Date:From:Reply-To:Subject:To; b=O2F/QdVY7P8VmegsedFdLW+ReONiKg/jxpbO5ukY9NWAlq6ngKOTH6rcxf2PhfO9QDn gkr8+szPYJSH1C+B6+OgRbYqnUnownNK6lpMDzkm6gGUDUdTBnGbishpGkOzLFz2JdQCs bxVq3DZgXPskM3yJJ3W7N5kUmB6boTKc/jA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2698 To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Also new SecCore module created for FspMultiPhaseSiInit API New ARCH_UPD introduced for enhancing FSP debug message flexibility now bootloader can pass its own debug handler function pointer and FSP will call the function to handle debug message. Cc: Maurice Ma Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 6 += ++--- IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c | 19 += +++++++++++++++++- IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 52 += +++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm | 99 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | 5 += +++- IntelFsp2Pkg/Include/FspEas/FspApi.h | 122 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++-- IntelFsp2Pkg/Include/FspGlobalData.h | 3 += +- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10 += +++++++-- IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h | 16 += ++++++++++++++- 9 files changed, 321 insertions(+), 11 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index 8e0595fe9a..1334959005 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -59,7 +59,7 @@ FspApiCallingCheck ( Status =3D EFI_UNSUPPORTED; } } - } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) { + } else if ((ApiIdx =3D=3D FspSiliconInitApiIndex) || (ApiIdx =3D=3D FspM= ultiPhaseSiInitApiIndex)) { // // FspSiliconInit check // @@ -68,7 +68,7 @@ FspApiCallingCheck ( } else { if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) { Status =3D EFI_UNSUPPORTED; - } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) { + } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, = ApiParam))) { Status =3D EFI_INVALID_PARAMETER; } } diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNu= ll.c b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c index f7945b5240..df8c5d121f 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c @@ -1,7 +1,7 @@ /** @file Null instance of Platform Sec Lib. =20 - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -25,3 +25,20 @@ FspUpdSignatureCheck ( { return EFI_SUCCESS; } + +/** + This function handles FspMultiPhaseSiInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseSiInitApiHandler ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ) +{ + return EFI_SUCCESS; +} diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSe= cCore/Fsp22SecCoreS.inf new file mode 100644 index 0000000000..0a24eb2a8b --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf @@ -0,0 +1,52 @@ +## @file +# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization. +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D Fsp22SecCoreS + FILE_GUID =3D DF0FCD70-264A-40BF-BBD4-06C76DB19CB1 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + SecFspApiChk.c + SecFsp.h + +[Sources.IA32] + Ia32/Stack.nasm + Ia32/Fsp22ApiEntryS.nasm + Ia32/FspApiEntryCommon.nasm + Ia32/FspHelper.nasm + +[Binaries.Ia32] + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + PciCf8Lib + SerialPortLib + FspSwitchStackLib + FspCommonLib + FspSecPlatformLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid ## PRODUCES + diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp22ApiEntryS.nasm new file mode 100644 index 0000000000..c5e73a635b --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm @@ -0,0 +1,99 @@ +;; @file +; Provide FSP API entry points. +; +; Copyright (c) 2020, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + + SECTION .text + +; +; Following functions will be provided in C +; +extern ASM_PFX(FspApiCommon) +extern ASM_PFX(FspMultiPhaseSiInitApiHandler) + +;-------------------------------------------------------------------------= --- +; NotifyPhase API +; +; This FSP API will notify the FSP about the different phases in the boot +; process +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(NotifyPhaseApi) +ASM_PFX(NotifyPhaseApi): + mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspSiliconInit API +; +; This FSP API initializes the CPU and the chipset including the IO +; controllers in the chipset to enable normal operation of these devices. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspSiliconInitApi) +ASM_PFX(FspSiliconInitApi): + mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspMultiPhaseSiInitApi API +; +; This FSP API provides multi-phase silicon initialization, which brings g= reater +; modularity beyond the existing FspSiliconInit() API. +; Increased modularity is achieved by adding an extra API to FSP-S. +; This allows the bootloader to add board specific initialization steps th= roughout +; the SiliconInit flow as needed. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspMultiPhaseSiInitApi) +ASM_PFX(FspMultiPhaseSiInitApi): + mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex + jmp ASM_PFX(FspApiCommon) + +;-------------------------------------------------------------------------= --- +; FspApiCommonContinue API +; +; This is the FSP API common entry point to resume the FSP execution +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(FspApiCommonContinue) +ASM_PFX(FspApiCommonContinue): + ; + ; Handle FspMultiPhaseSiInitApiIndex API + ; + cmp eax, 6 + jnz NotMultiPhaseSiInitApi + + pushad + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam + push eax ; push ApiIdx + call ASM_PFX(FspMultiPhaseSiInitApiHandler) + add esp, 8 + mov dword [esp + (4 * 7)], eax + popad + ret + +NotMultiPhaseSiInitApi: + jmp $ + ret + +;-------------------------------------------------------------------------= --- +; TempRamInit API +; +; Empty function for WHOLEARCHIVE build option +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(TempRamInitApi) +ASM_PFX(TempRamInitApi): + jmp $ + ret + +;-------------------------------------------------------------------------= --- +; Module Entrypoint API +;-------------------------------------------------------------------------= --- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + jmp $ + diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm b/IntelFsp= 2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm index bb4451b145..26ae7d9fd3 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm @@ -1,7 +1,7 @@ ;; @file ; Provide FSP API entry points. ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ;; =20 @@ -62,6 +62,9 @@ FspApiCommon2: cmp eax, 3 ; FspMemoryInit API jz FspApiCommon3 =20 + cmp eax, 6 ; FspMultiPhaseSiInitApiIndex API + jz FspApiCommon3 + call ASM_PFX(AsmGetFspInfoHeader) jmp ASM_PFX(Loader2PeiSwitchStack) =20 diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index dcf489dbe6..2887848f69 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -2,7 +2,7 @@ Intel FSP API definition from Intel Firmware Support Package External Architecture Specification v2.0. =20 - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -10,6 +10,8 @@ #ifndef _FSP_API_H_ #define _FSP_API_H_ =20 +#include + /// /// FSP Reset Status code /// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code @@ -24,6 +26,59 @@ #define FSP_STATUS_RESET_REQUIRED_8 0x40000008 /// @} =20 +/* + FSP may optionally include the capability of generating events messages = to aid in the debugging of firmware issues. + These events fall under three catagories: Error, Progress, and Debug. Th= e event reporting mechanism follows the + status code services described in section 6 and 7 of the PI Specificatio= n v1.7 Volume 3. + + @param[in] Type Indicates the type of event being repo= rted. + See MdePkg/Include/Pi/PiStatusCode.h f= or the definition of EFI_STATUS_CODE_TYPE. + @param[in] Value Describes the current status of a hard= ware or software entity. + This includes information about the cl= ass and subclass that is used to classify the entity as well as an operatio= n. + For progress events, the operation is = the current activity. For error events, it is the exception. + For debug events, it is not defined at= this time. + See MdePkg/Include/Pi/PiStatusCode.h f= or the definition of EFI_STATUS_CODE_VALUE. + @param[in] Instance The enumeration of a hardware or softw= are entity within the system. + A system may contain multiple entities= that match a class/subclass pairing. The instance differentiates between t= hem. + An instance of 0 indicates that instan= ce information is unavailable, not meaningful, or not relevant. + Valid instance numbers start with 1. + @param[in] *CallerId This parameter can be used to identify= the sub-module within the FSP generating the event. + This parameter may be NULL. + @param[in] *Data This optional parameter may be used to= pass additional data. The contents can have event-specific data. + For example, the FSP provides a EFI_ST= ATUS_CODE_STRING_DATA instance to this parameter when sending debug message= s. + This parameter is NULL when no additio= nal data is provided. + + @retval EFI_SUCCESS The event was handled successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_DEVICE_ERROR The event handler failed. +*/ +typedef +EFI_STATUS +(EFIAPI *FSP_EVENT_HANDLER) ( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN OPTIONAL EFI_GUID *CallerId, + IN OPTIONAL EFI_STATUS_CODE_DATA *Data + ); + +/* + Handler for FSP-T debug log messages, provided by the bootloader. + + @param[in] DebugMessage A pointer to the debug message to be w= ritten to the log. + @param[in] MessageLength Number of bytes to written to the debu= g log. + + @retval UINT32 The return value indicates the number = of bytes actually written to + the debug log. If the return value is = less than MessageLength, + an error occurred. +*/ +typedef +UINT32 +(EFIAPI *FSP_DEBUG_HANDLER) ( + IN CHAR8* DebugMessage, + IN UINT32 MessageLength + ); + #pragma pack(1) /// /// FSP_UPD_HEADER Configuration. @@ -77,7 +132,12 @@ typedef struct { /// Current boot mode. /// UINT32 BootMode; - UINT8 Reserved1[8]; + /// + /// Optional event handler for the bootloader to be informed of events o= ccurring during FSP execution. + /// This value is only valid if Revision is >=3D 2. + /// + FSP_EVENT_HANDLER *FspEventHandler; + UINT8 Reserved1[4]; } FSPM_ARCH_UPD; =20 /// @@ -147,6 +207,40 @@ typedef struct { FSP_INIT_PHASE Phase; } NOTIFY_PHASE_PARAMS; =20 +/// +/// Action definition for FspMultiPhaseSiInit API +/// +typedef enum { + EnumMultiPhaseGetNumberOfPhases =3D 0x0, + EnumMultiPhaseExecutePhase =3D 0x1 +} FSP_MULTI_PHASE_ACTION; + +/// +/// Data structure returned by FSP when bootloader calling +/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases) +/// +typedef struct { + UINT32 NumberOfPhases; + UINT32 PhasesExecuted; +} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS; + +/// +/// FspMultiPhaseSiInit function parameter. +/// +/// For action 0 (EnumMultiPhaseGetNumberOfPhases): +/// - PhaseIndex must be 0. +/// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_= GET_NUMBER_OF_PHASES_PARAMS. +/// +/// For action 1 (EnumMultiPhaseExecutePhase): +/// - PhaseIndex will be the phase that will be executed by FSP. +/// - MultiPhaseParamPtr shall be NULL. +/// +typedef struct { + IN FSP_MULTI_PHASE_ACTION MultiPhaseAction; + IN UINT32 PhaseIndex; + IN OUT VOID *MultiPhaseParamPtr; +} FSP_MULTI_PHASE_PARAMS; + #pragma pack() =20 /** @@ -279,4 +373,28 @@ EFI_STATUS IN VOID *FspsUpdDataPtr ); =20 +/** + This FSP API is expected to be called after FspSiliconInit but before Fs= pNotifyPhase. + This FSP API provides multi-phase silicon initialization; which brings g= reater modularity + beyond the existing FspSiliconInit() API. Increased modularity is achiev= ed by adding an + extra API to FSP-S. This allows the bootloader to add board specific ini= tialization steps + throughout the SiliconInit flow as needed. + + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNu= mberOfPhases: + FSP_MULTI_PHASE_PARAMS->MultiP= haseParamPtr will contain + how many phases supported by F= SP. + For action - EnumMultiPhaseExecu= tePhase: + FSP_MULTI_PHASE_PARAMS->MultiP= haseParamPtr shall be NULL. + @retval EFI_SUCCESS FSP execution environment was in= itialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were = not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These statu= s codes will not be returned during S3. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_MULTI_PHASE_SI_INIT) ( + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr +); + #endif diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 1896b0240a..02df8463ed 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -22,6 +22,7 @@ typedef enum { FspMemoryInitApiIndex, TempRamExitApiIndex, FspSiliconInitApiIndex, + FspMultiPhaseSiInitApiIndex, FspApiIndexMax } FSP_API_INDEX; =20 diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Inclu= de/Guid/FspHeaderFile.h index 16f43a1273..3474bac1de 100644 --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -1,8 +1,8 @@ /** @file Intel FSP Header File definition from Intel Firmware Support Package Ext= ernal - Architecture Specification v2.0. + Architecture Specification v2.0 and above. =20 - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -110,6 +110,12 @@ typedef struct { /// Byte 0x44: The offset for the API to initialize the CPU and chipset. /// UINT32 FspSiliconInitEntryOffset; + /// + /// Byte 0x48: Offset for the API for the optional Multi-Phase processor= and chipset initialization. + /// This value is only valid if FSP HeaderRevision is >=3D 5. + /// If the value is set to 0x00000000, then this API is not a= vailable in this component. + /// + UINT32 FspMultiPhaseSiInitEntryOffset; } FSP_INFO_HEADER; =20 /// diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/IntelFsp2Pk= g/Include/Library/FspSecPlatformLib.h index 4d01b5f6d9..51a0309aed 100644 --- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -79,4 +79,18 @@ FspUpdSignatureCheck ( IN VOID *ApiParam ); =20 +/** + This function handles FspMultiPhaseSiInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseSiInitApiHandler ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + #endif --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#59028): https://edk2.groups.io/g/devel/message/59028 Mute This Topic: https://groups.io/mt/74129204/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-