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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: rm5ni1pZd1VVZiAK3hU862Jjx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225867; bh=9jq3+UlCPdvvCcUUZt9r2TjejBGlEOhGeEp+fS3rgpM=; h=Content-Type:Date:From:Reply-To:Subject:To; b=o/i9peUfW+UWruVhzVvH/GHJAXhmZsoqQKw7p5S53JiwmhDEJzyxNgmipovLCTOc+Rj 7uGyQoERkxGqzM+TOpkGszf7e9K+yowXJZLYydkXx15+BDeqSO8mkGcNEOB6rcBq3Ety8 ZwgHi63/XbhWMGlm4gzkXiozOO9uCcIQ7iI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Add an I2c library to control the i2c controllers to communicate with I2c device. We need this functionality in a lib because this is going to be used in PrePeiCore sec module to get the System clock information from devices connected to i2c (like fpga or clock generator) In subsequent patches I2c functionality in I2cDxe driver would be removed and I2cLib APIs would be used in I2cDxe. The I2cLib differs from I2c Controller functionality in I2c Dxe in several aspects: - I2cLib doesn't assume that each I2c Transaction would be of minimum two operations - I2cLib generates repeat start between operations which complies with PI I2c specs. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - Dividor -> divider - Added line between license and copyright in files - Fixed newline at the end of file errors - removed I2cEarlyInitialize - changed Ibfd from UINT16 to UINT8 in I2C_CLOCK_DIVISOR_PAIR in I2cLibInternal.h - Modify commit description =20 V3: - moved I2cLib addition in NxpQoriqLs.dsc.inc to PATCH 2 - Added Qoriq Layerscape in description of CLOCK_DIVISOR_PAIR - ERRXXXXXX -> A-XXXXXX - Added u-boot patch reference to errata workaround description - Added Glossary and Revision Reference in file header - Dividor -> divider - Added explaination before calling I2cErratumA009203 - PtrAddress -> AddressPtr - Update commit description Silicon/NXP/NxpQoriqLs.dec | 9 +- Silicon/NXP/Library/I2cLib/I2cLib.inf | 30 ++ Silicon/NXP/Include/Library/I2cLib.h | 100 ++++ Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 105 ++++ Silicon/NXP/Library/I2cLib/I2cLib.c | 545 ++++++++++++++++++++ 5 files changed, 788 insertions(+), 1 deletion(-) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 764b9bb0e2d3..1aff519bfaf4 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -1,6 +1,6 @@ # @file. # -# Copyright 2017-2019 NXP +# Copyright 2017-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -13,6 +13,10 @@ [Includes] Include =20 +[LibraryClasses] + ## @libraryclass Provides services to read/write to I2c devices + I2cLib|Include/Library/I2cLib.h + [Guids.common] gNxpQoriqLsTokenSpaceGuid =3D {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0= xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}} gNxpNonDiscoverableI2cMasterGuid =3D { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e= , 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}} @@ -101,3 +105,6 @@ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312 gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313 gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314 + +[PcdsFeatureFlag] + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315 diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.inf b/Silicon/NXP/Library/I2= cLib/I2cLib.inf new file mode 100644 index 000000000000..3da2331db37d --- /dev/null +++ b/Silicon/NXP/Library/I2cLib/I2cLib.inf @@ -0,0 +1,30 @@ +# @file +# Component description file for I2cLib module +# +# Copyright 2017, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D I2cLib + FILE_GUID =3D 8ecefc8f-a2c4-4091-b81f-20f7aeb0567f + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D I2cLib + +[Sources.common] + I2cLib.c + +[LibraryClasses] + IoLib + TimerLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203 diff --git a/Silicon/NXP/Include/Library/I2cLib.h b/Silicon/NXP/Include/Lib= rary/I2cLib.h new file mode 100644 index 000000000000..f09324c00e47 --- /dev/null +++ b/Silicon/NXP/Include/Library/I2cLib.h @@ -0,0 +1,100 @@ +/** @file + I2c Lib to control I2c controller. + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef I2C_LIB_H__ +#define I2C_LIB_H__ + +#include +#include + +/** + software reset of the entire I2C module. + The module is reset and disabled. + Status register fields (IBSR) are cleared. + + @param[in] Base Base Address of I2c controller's registers + + @return EFI_SUCCESS successfuly reset the I2c module +**/ +EFI_STATUS +I2cReset ( + IN UINTN Base + ); + +/** + Configure I2c bus to operate at a given speed + + @param[in] Base Base Address of I2c controller's registers + @param[in] I2cBusClock Input clock to I2c controller + @param[in] Speed speed to be configured for I2c bus + + @return EFI_SUCCESS successfuly setup the i2c bus +**/ +EFI_STATUS +I2cInitialize ( + IN UINTN Base, + IN UINT64 I2cBusClock, + IN UINT64 Speed + ); + +/** + Transfer data to/from I2c slave device + + @param[in] Base Base Address of I2c controller's registers + @param[in] SlaveAddress Slave Address from which data is to be read + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure + describing the I2C transaction + + @return EFI_SUCCESS successfuly transfer the data + @return EFI_DEVICE_ERROR There was an error while transferring data th= rough + I2c bus + @return EFI_NO_RESPONSE There was no Ack from i2c device + @return EFI_TIMEOUT I2c Bus is busy + @return EFI_NOT_READY I2c Bus Arbitration lost +**/ +EFI_STATUS +I2cBusXfer ( + IN UINTN Base, + IN UINT32 SlaveAddress, + IN EFI_I2C_REQUEST_PACKET *RequestPacket + ); + +/** + Read a register from I2c slave device. This API is wrapper around I2cBus= Xfer + + @param[in] Base Base Address of I2c controller's regi= sters + @param[in] SlaveAddress Slave Address from which register val= ue is + to be read + @param[in] RegAddress Register Address in Slave's memory map + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send= to + I2c Slave for simple reads without any + register, make this value =3D 0 + (RegAddress is don't care in that cas= e) + @param[out] RegValue Value to be read from I2c slave's reg= iser + @param[in] RegValueNumBytes Number of bytes to read from I2c slave + register + + @return EFI_SUCCESS successfuly read the registers + @return EFI_DEVICE_ERROR There was an error while transferring data th= rough + I2c bus + @return EFI_NO_RESPONSE There was no Ack from i2c device + @return EFI_TIMEOUT I2c Bus is busy + @return EFI_NOT_READY I2c Bus Arbitration lost +**/ +EFI_STATUS +I2cBusReadReg ( + IN UINTN Base, + IN UINT32 SlaveAddress, + IN UINT64 RegAddress, + IN UINT8 RegAddressWidthInBytes, + OUT UINT8 *RegValue, + IN UINT32 RegValueNumBytes + ); + +#endif // I2C_LIB_H__ diff --git a/Silicon/NXP/Library/I2cLib/I2cLibInternal.h b/Silicon/NXP/Libr= ary/I2cLib/I2cLibInternal.h new file mode 100644 index 000000000000..cd82c423947a --- /dev/null +++ b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h @@ -0,0 +1,105 @@ +/** @file + I2c Lib to control I2c controller. + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef I2C_LIB_INTERNAL_H__ +#define I2C_LIB_INTERNAL_H__ + +#include +#include + +/** Module Disable + 0b - The module is enabled. You must clear this field before any other I= BCR + fields have any effect. + 1b - The module is reset and disabled. This is the power-on reset situat= ion. + When high, the interface is held in reset, but registers can still = be + accessed. Status register fields (IBSR) are not valid when the modu= le + is disabled. +**/ +#define I2C_IBCR_MDIS BIT7 +// I2c Bus Interrupt Enable +#define I2C_IBCR_IBIE BIT6 +/** Master / Slave Mode 0b - Slave mode 1b - Master mode + When you change this field from 0 to 1, the module generates a START sig= nal + on the bus and selects the master mode. When you change this field from = 1 to + 0, the module generates a STOP signal and changes the operation mode from + master to slave. You should generate a STOP signal only if IBSR[IBIF]=3D= 1. + The module clears this field without generating a STOP signal when the + master loses arbitration. +*/ +#define I2C_IBCR_MSSL BIT5 +// 0b - Receive 1b - Transmit +#define I2C_IBCR_TXRX BIT4 +/** Data acknowledge disable + Values written to this field are only used when the I2C module is a rece= iver, + not a transmitter. + 0b - The module sends an acknowledge signal to the bus at the 9th clock = bit + after receiving one byte of data. + 1b - The module does not send an acknowledge-signal response (that is, + acknowledge bit =3D 1). +**/ +#define I2C_IBCR_NOACK BIT3 +/**Repeat START + If the I2C module is the current bus master, and you program RSTA=3D1, t= he I2C + module generates a repeated START condition. This field always reads as = a 0. + If you attempt a repeated START at the wrong time, if the bus is owned by + another master the result is loss of arbitration. +**/ +#define I2C_IBCR_RSTA BIT2 +// DMA enable +#define I2C_IBCR_DMAEN BIT1 + +// Transfer Complete +#define I2C_IBSR_TCF BIT7 +// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy +#define I2C_IBSR_IBB BIT5 +// Arbitration Lost. software must clear this field by writing a one to it. +#define I2C_IBSR_IBAL BIT4 +// I2C bus interrupt flag +#define I2C_IBSR_IBIF BIT1 +// Received acknowledge 0b - Acknowledge received 1b - No acknowledge rece= ived +#define I2C_IBSR_RXAK BIT0 + +//Bus idle interrupt enable +#define I2C_IBIC_BIIE BIT7 + +// Glitch filter enable +#define I2C_IBDBG_GLFLT_EN BIT3 + +#define I2C_BUS_TEST_BUSY TRUE +#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY +#define I2C_BUS_TEST_RX_ACK TRUE +#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK + +#define ARRAY_LAST_ELEM(x) (x)[ARRAY_SIZE (x) - 1] +#define I2C_NUM_RETRIES 500 + +typedef struct _I2C_REGS { + UINT8 Ibad; // I2c Bus Address Register + UINT8 Ibfd; // I2c Bus Frequency Divider Register + UINT8 Ibcr; // I2c Bus Control Register + UINT8 Ibsr; // I2c Bus Status Register + UINT8 Ibdr; // I2C Bus Data I/O Register + UINT8 Ibic; // I2C Bus Interrupt Config Register + UINT8 Ibdbg; // I2C Bus Debug Register +} I2C_REGS; + +/* + * sorted list of clock divisor, Ibfd register value pairs + */ +typedef struct _I2C_CLOCK_DIVISOR_PAIR { + UINT16 Divisor; + UINT8 Ibfd; // I2c Bus Frequency Divider Register value +} I2C_CLOCK_DIVISOR_PAIR; + +typedef struct { + UINTN OperationCount; + EFI_I2C_OPERATION Operation[2]; +} I2C_REG_REQUEST; + +#endif // I2C_LIB_INTERNAL_H__ diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.c b/Silicon/NXP/Library/I2cL= ib/I2cLib.c new file mode 100644 index 000000000000..4b9055969112 --- /dev/null +++ b/Silicon/NXP/Library/I2cLib/I2cLib.c @@ -0,0 +1,545 @@ +/** @file + I2c Lib to control I2c controller. + + Copyright 2017, 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - PI Version 1.7 + + @par Glossary: + - Ibfd - I2c Bus Frequency Divider +**/ +#include +#include +#include +#include +#include + +#include "I2cLibInternal.h" + +/** + I2C divisor and Ibfd register values when glitch filter is enabled + + In case of duplicate SCL Divisor value, the Ibfd value with high MUL val= ue + has been selected. A higher MUL value results in a lower sampling rate of + the I2C signals. This gives the I2C module greater immunity against glit= ches + in the I2C signals. + + These values can be referred from NXP QorIQ Layerscape series SOC Refere= nce + Manual in which this I2C ip has been used. e.g. LX2160ARM, LS1043ARM +**/ +STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchEnabled[] =3D { + { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 }, + { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA }, + { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 }, + { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 }, + { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A }, + { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 }, + { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 }, + { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A }, + { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 }, + { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 }, + { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 }, + { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D }, + { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 }, + { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 }, + { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC }, + { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF }, + { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 }, + { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC }, + { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF } +}; + +/** + I2C divisor and Ibfd register values when glitch filter is disabled + + In case of duplicate SCL Divisor value, the Ibfd value with high MUL val= ue + has been selected. A higher MUL value results in a lower sampling rate of + the I2C signals. This gives the I2C module greater immunity against glit= ches + in the I2C signals. + + These values can be referred from NXP QorIQ Layerscape series SOC Refere= nce + Manual in which this I2C ip has been used. e.g. LX2160ARM, LS1043ARM +**/ +STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchDisabled[] =3D { + { 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 }, + { 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 }, + { 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 }, + { 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 }, + { 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 }, + { 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 }, + { 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B }, + { 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 }, + { 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 }, + { 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 }, + { 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C }, + { 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F }, + { 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 }, + { 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC }, + { 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF }, + { 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 }, + { 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC }, + { 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF } +}; + +/** + A-009203 : I2C may not work reliably with the default setting + + Description : The clocking circuitry of I2C module may not work reliably= due + to the slow rise time of SCL signal. + Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_= EN] + to 1. refer https://patchwork.ozlabs.org/patch/453575/ +**/ +STATIC +VOID +I2cErratumA009203 ( + IN UINTN Base + ) +{ + I2C_REGS *Regs; + + Regs =3D (I2C_REGS *)Base; + + MmioOr8 ((UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN); +} + +/** + software reset of the entire I2C module. + The module is reset and disabled. + Status register fields (IBSR) are cleared. + + @param[in] Base Base Address of I2c controller's registers + + @return EFI_SUCCESS successfuly reset the I2c module +**/ +EFI_STATUS +I2cReset ( + IN UINTN Base + ) +{ + I2C_REGS *Regs; + + Regs =3D (I2C_REGS *)Base; + + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS); + MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF)); + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN)); + MmioAnd8 ((UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE)); + + return EFI_SUCCESS; +} + +/** + Configure I2c bus to operate at a given speed + + @param[in] Base Base Address of I2c controller's registers + @param[in] I2cBusClock Input clock to I2c controller + @param[in] Speed speed to be configured for I2c bus + + @return EFI_SUCCESS successfuly setup the i2c bus +**/ +EFI_STATUS +I2cInitialize ( + IN UINTN Base, + IN UINT64 I2cBusClock, + IN UINT64 Speed + ) +{ + I2C_REGS *Regs; + UINT16 ClockDivisor; + UINT8 Ibfd; // I2c Bus Frequency Divider Regist= er + CONST I2C_CLOCK_DIVISOR_PAIR *ClockDivisorPair; + UINT32 ClockDivisorPairSize; + UINT32 Index; + + Regs =3D (I2C_REGS *)Base; + if (FeaturePcdGet (PcdI2cErratumA009203)) { + // Apply Erratum A-009203 before writing Ibfd register + I2cErratumA009203 (Base); + } + + Ibfd =3D 0; + ClockDivisor =3D (I2cBusClock + Speed - 1) / Speed; + + if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) { + ClockDivisorPair =3D mI2cClockDivisorGlitchEnabled; + ClockDivisorPairSize =3D ARRAY_SIZE (mI2cClockDivisorGlitchEnabled); + } else { + ClockDivisorPair =3D mI2cClockDivisorGlitchDisabled; + ClockDivisorPairSize =3D ARRAY_SIZE (mI2cClockDivisorGlitchDisabled); + } + + if (ClockDivisor > ClockDivisorPair[ClockDivisorPairSize - 1].Divisor) { + Ibfd =3D ClockDivisorPair[ClockDivisorPairSize - 1].Ibfd; + } else { + for (Index =3D 0; Index < ClockDivisorPairSize; Index++) { + if (ClockDivisorPair[Index].Divisor >=3D ClockDivisor) { + Ibfd =3D ClockDivisorPair[Index].Ibfd; + break; + } + } + } + + MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd); + + I2cReset (Base); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2cBusTestBusBusy ( + IN I2C_REGS *Regs, + IN BOOLEAN TestBusy + ) +{ + UINT32 Index; + UINT8 Reg; + + for (Index =3D 0; Index < I2C_NUM_RETRIES; Index++) { + Reg =3D MmioRead8 ((UINTN)&Regs->Ibsr); + + if (Reg & I2C_IBSR_IBAL) { + MmioWrite8 ((UINTN)&Regs->Ibsr, Reg); + return EFI_NOT_READY; + } + + if (TestBusy && (Reg & I2C_IBSR_IBB)) { + break; + } + + if (!TestBusy && !(Reg & I2C_IBSR_IBB)) { + break; + } + + MicroSecondDelay (1); + } + + if (Index =3D=3D I2C_NUM_RETRIES) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2cTransferComplete ( + IN I2C_REGS *Regs, + IN BOOLEAN TestRxAck +) +{ + UINT32 Index; + UINT8 Reg; + + for (Index =3D 0; Index < I2C_NUM_RETRIES; Index++) { + Reg =3D MmioRead8 ((UINTN)&Regs->Ibsr); + + if (Reg & I2C_IBSR_IBIF) { + // Write 1 to clear the IBIF field + MmioWrite8 ((UINTN)&Regs->Ibsr, Reg); + break; + } + + MicroSecondDelay (1); + } + + if (Index =3D=3D I2C_NUM_RETRIES) { + return EFI_TIMEOUT; + } + + if (TestRxAck && (Reg & I2C_IBSR_RXAK)) { + return EFI_NO_RESPONSE; + } + + if (Reg & I2C_IBSR_TCF) { + return EFI_SUCCESS; + } + + return EFI_DEVICE_ERROR; +} + +STATIC +EFI_STATUS +I2cRead ( + IN I2C_REGS *Regs, + IN UINT32 SlaveAddress, + IN EFI_I2C_OPERATION *Operation, + IN BOOLEAN IsLastOperation +) +{ + EFI_STATUS Status; + UINTN Index; + + // Write Slave Address + MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0); + Status =3D I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK); + if (EFI_ERROR (Status)) { + return Status; + } + // select Receive mode. + MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX); + if (Operation->LengthInBytes > 1) { + // Set No ACK =3D 0 + MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_NOACK); + } + + // Perform a dummy read to initiate the receive operation. + MmioRead8 ((UINTN)&Regs->Ibdr); + + for (Index =3D 0; Index < Operation->LengthInBytes; Index++) { + Status =3D I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK); + if (EFI_ERROR (Status)) { + return Status; + } + if (Index =3D=3D (Operation->LengthInBytes - 2)) { + // Set No ACK =3D 1 + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_NOACK); + } else if (Index =3D=3D (Operation->LengthInBytes - 1)) { + if (!IsLastOperation) { + // select Transmit mode (for repeat start) + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_TXRX); + } else { + // Generate Stop Signal + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX)); + Status =3D I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE); + if (EFI_ERROR (Status)) { + return Status; + } + } + } + Operation->Buffer[Index] =3D MmioRead8 ((UINTN)&Regs->Ibdr); + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2cWrite ( + IN I2C_REGS *Regs, + IN UINT32 SlaveAddress, + IN EFI_I2C_OPERATION *Operation +) +{ + EFI_STATUS Status; + UINTN Index; + + // Write Slave Address + MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) & (UINT8)(~BIT0)); + Status =3D I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK); + if (EFI_ERROR (Status)) { + return Status; + } + + // Write Data + for (Index =3D 0; Index < Operation->LengthInBytes; Index++) { + MmioWrite8 ((UINTN)&Regs->Ibdr, Operation->Buffer[Index]); + Status =3D I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK); + if (EFI_ERROR (Status)) { + return Status; + } + } + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2cStop ( + IN I2C_REGS *Regs + ) +{ + EFI_STATUS Status; + UINT8 Reg; + + Status =3D EFI_SUCCESS; + Reg =3D MmioRead8 ((UINTN)&Regs->Ibsr); + if (Reg & I2C_IBSR_IBB) { + // Generate Stop Signal + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX)); + Status =3D I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE); + if (EFI_ERROR (Status)) { + return Status; + } + } + + // Disable I2c Controller + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS); + + return Status; +} + +STATIC +EFI_STATUS +I2cStart ( + IN I2C_REGS *Regs + ) +{ + EFI_STATUS Status; + + MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF)); + MmioAnd8 ((UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS)); + + //Wait controller to be stable + MicroSecondDelay (1); + + // Generate Start Signal + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MSSL); + Status =3D I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY); + if (EFI_ERROR (Status)) { + return Status; + } + + // Select Transmit Mode. set No ACK =3D 1 + MmioOr8 ((UINTN)&Regs->Ibcr, (I2C_IBCR_TXRX | I2C_IBCR_NOACK)); + + return Status; +} + +/** + Transfer data to/from I2c slave device + + @param[in] Base Base Address of I2c controller's registers + @param[in] SlaveAddress Slave Address from which data is to be read + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure + describing the I2C transaction + + @return EFI_SUCCESS successfuly transfer the data + @return EFI_DEVICE_ERROR There was an error while transferring data th= rough + I2c bus + @return EFI_NO_RESPONSE There was no Ack from i2c device + @return EFI_TIMEOUT I2c Bus is busy + @return EFI_NOT_READY I2c Bus Arbitration lost +**/ +EFI_STATUS +I2cBusXfer ( + IN UINTN Base, + IN UINT32 SlaveAddress, + IN EFI_I2C_REQUEST_PACKET *RequestPacket + ) +{ + UINTN Index; + I2C_REGS *Regs; + EFI_I2C_OPERATION *Operation; + EFI_STATUS Status; + BOOLEAN IsLastOperation; + + Regs =3D (I2C_REGS *)Base; + IsLastOperation =3D FALSE; + + Status =3D I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE); + if (EFI_ERROR (Status)) { + goto ErrorExit; + } + + Status =3D I2cStart (Regs); + if (EFI_ERROR (Status)) { + goto ErrorExit; + } + + for (Index =3D 0, Operation =3D RequestPacket->Operation; + Index < RequestPacket->OperationCount; + Index++, Operation++) { + if (Index =3D=3D (RequestPacket->OperationCount - 1)) { + IsLastOperation =3D TRUE; + } + // Send repeat start after first transmit/recieve + if (Index) { + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_RSTA); + Status =3D I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY); + if (EFI_ERROR (Status)) { + goto ErrorExit; + } + } + // Read/write data + if (Operation->Flags & I2C_FLAG_READ) { + Status =3D I2cRead (Regs, SlaveAddress, Operation, IsLastOperation); + } else { + Status =3D I2cWrite (Regs, SlaveAddress, Operation); + } + if (EFI_ERROR (Status)) { + goto ErrorExit; + } + } + +ErrorExit: + + I2cStop (Regs); + + return Status; +} + +/** + Read a register from I2c slave device. This API is wrapper around I2cBus= Xfer + + @param[in] Base Base Address of I2c controller's regi= sters + @param[in] SlaveAddress Slave Address from which register val= ue is + to be read + @param[in] RegAddress Register Address in Slave's memory map + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send= to + I2c Slave for simple reads without any + register, make this value =3D 0 + (RegAddress is don't care in that cas= e) + @param[out] RegValue Value to be read from I2c slave's reg= iser + @param[in] RegValueNumBytes Number of bytes to read from I2c slave + register + + @return EFI_SUCCESS successfuly read the registers + @return EFI_DEVICE_ERROR There was an error while transferring data th= rough + I2c bus + @return EFI_NO_RESPONSE There was no Ack from i2c device + @return EFI_TIMEOUT I2c Bus is busy + @return EFI_NOT_READY I2c Bus Arbitration lost +**/ +EFI_STATUS +I2cBusReadReg ( + IN UINTN Base, + IN UINT32 SlaveAddress, + IN UINT64 RegAddress, + IN UINT8 RegAddressWidthInBytes, + OUT UINT8 *RegValue, + IN UINT32 RegValueNumBytes + ) +{ + EFI_I2C_OPERATION *Operations; + I2C_REG_REQUEST RequestPacket; + UINTN OperationCount; + UINT8 Address[sizeof (RegAddress)]; + UINT8 *AddressPtr; + EFI_STATUS Status; + + ZeroMem (&RequestPacket, sizeof (RequestPacket)); + OperationCount =3D 0; + Operations =3D RequestPacket.Operation; + AddressPtr =3D Address; + + if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) { + return EFI_INVALID_PARAMETER; + } + + if (RegAddressWidthInBytes !=3D 0) { + Operations[OperationCount].LengthInBytes =3D RegAddressWidthInBytes; + Operations[OperationCount].Buffer =3D AddressPtr; + while (RegAddressWidthInBytes--) { + *AddressPtr++ =3D RegAddress >> (8 * RegAddressWidthInBytes); + } + OperationCount++; + } + + Operations[OperationCount].LengthInBytes =3D RegValueNumBytes; + Operations[OperationCount].Buffer =3D RegValue; + Operations[OperationCount].Flags =3D I2C_FLAG_READ; + OperationCount++; + + RequestPacket.OperationCount =3D OperationCount; + + Status =3D I2cBusXfer ( + Base, SlaveAddress, + (EFI_I2C_REQUEST_PACKET *)&RequestPacket + ); + + return Status; +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:06 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 02/24] Silicon/NXP: changes to use I2clib in i2cdxe Date: Fri, 1 May 2020 11:19:33 +0530 Message-ID: <20200501054955.13025-3-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:04 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 00f79a34-0eb7-41b5-fef6-08d7ecca79a1 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: F5lXav1u42reAU8lo38inE02x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225869; bh=26YsMZ/gol+Y8m7h2AaOCERng61QMBr6srkpOoFaTZE=; h=Content-Type:Date:From:Reply-To:Subject:To; b=NPCCytMeBGPUugwCMhzxUSoZn4xTxmYNqLeJc1xeUyuyaey8SwjYdGuqKdb5ytJMv5+ ShXmFMt39HRbOEzWad9fRG6YJ9AxoaRhXmZ/57X5Zdp4LwHanDCQWfDbS3BwNvm32V/ZZ wRI/bmZwg/qm91nLo7DGPDtI0EtZBAoIrKg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal I2c lib contains the i2c controller functionality. this can be used in I2c DXE driver to communicate with i2c devices. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - moved I2cLib addition to NxpQoriqLs.dsc.inc Platform/NXP/NxpQoriqLs.dsc.inc | 4 +- Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 9 +- Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 44 +- Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 526 +------------------- 4 files changed, 19 insertions(+), 564 deletions(-) diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.= inc index fa5f30dd3909..25c0a41e5d4a 100644 --- a/Platform/NXP/NxpQoriqLs.dsc.inc +++ b/Platform/NXP/NxpQoriqLs.dsc.inc @@ -1,6 +1,6 @@ # @file # -# Copyright 2017-2019 NXP. +# Copyright 2017-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -94,6 +94,8 @@ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl= eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf =20 + I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf + [LibraryClasses.common.SEC] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2= cDxe/I2cDxe.inf index 0c0bf63bb2e2..84adb837c249 100644 --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf @@ -3,7 +3,7 @@ # Component description file for I2c driver # # Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. -# Copyright 2017-2019 NXP +# Copyright 2017-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -27,6 +27,7 @@ ArmLib BaseMemoryLib DevicePathLib + I2cLib IoLib MemoryAllocationLib PcdLib @@ -48,11 +49,5 @@ gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START gEfiI2cMasterProtocolGuid ## BY_START =20 -[Pcd] - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController - [Depex] TRUE diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.h index 02a29a5cf2b9..88316f313380 100644 --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h @@ -1,7 +1,7 @@ /** I2cDxe.h Header defining the constant, base address amd function for I2C controll= er =20 - Copyright 2017-2019 NXP + Copyright 2017-2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -16,32 +16,6 @@ #include #include =20 -#define I2C_CR_IIEN (1 << 6) -#define I2C_CR_MSTA (1 << 5) -#define I2C_CR_MTX (1 << 4) -#define I2C_CR_TX_NO_AK (1 << 3) -#define I2C_CR_RSTA (1 << 2) - -#define I2C_SR_ICF (1 << 7) -#define I2C_SR_IBB (1 << 5) -#define I2C_SR_IAL (1 << 4) -#define I2C_SR_IIF (1 << 1) -#define I2C_SR_RX_NO_AK (1 << 0) - -#define I2C_CR_IEN (0 << 7) -#define I2C_CR_IDIS (1 << 7) -#define I2C_SR_IIF_CLEAR (1 << 1) - -#define BUS_IDLE (0 | (I2C_SR_IBB << 8)) -#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8)) -#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8)) - -#define I2C_FLAG_WRITE 0x0 - -#define I2C_STATE_RETRIES 50000 - -#define RETRY_COUNT 3 - #define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C') #define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \ I2cMaster, NXP_I2C_SIGNATURE) @@ -63,22 +37,6 @@ typedef struct { NON_DISCOVERABLE_DEVICE *Dev; } NXP_I2C_MASTER; =20 -/** - Record defining i2c registers -**/ -typedef struct { - UINT8 I2cAdr; - UINT8 I2cFdr; - UINT8 I2cCr; - UINT8 I2cSr; - UINT8 I2cDr; -} I2C_REGS; - -typedef struct { - UINT16 SCLDivider; - UINT16 BusClockRate; -} CLK_DIV; - extern UINT64 GetBusFrequency ( diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.c index 853c426fbca2..848e707c1673 100644 --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c @@ -1,7 +1,7 @@ /** I2cDxe.c I2c driver APIs for read, write, initialize, set speed and reset =20 - Copyright 2017-2019 NXP + Copyright 2017-2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -25,444 +26,6 @@ STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES mI2cContro= llerCapabilities =3D { 0 }; =20 -STATIC CONST CLK_DIV mClkDiv[] =3D { - { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, - { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, - { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, - { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, - { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, - { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, - { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, - { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, - { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, - { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, - { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, - { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, - { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, - { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, - { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E } -}; - -/** - Calculate and return proper clock divider - - @param Rate desired clock rate - - @retval ClkDiv Index value used to get Bus Clock Rate - -**/ -STATIC -UINT8 -GetClkDivIndex ( - IN UINT32 Rate - ) -{ - UINTN ClkRate; - UINT32 Div; - UINT8 Index; - - Index =3D 0; - ClkRate =3D GetBusFrequency (); - - Div =3D (ClkRate + Rate - 1) / Rate; - - if (Div < mClkDiv[0].SCLDivider) { - return 0; - } - - do { - if (mClkDiv[Index].SCLDivider >=3D Div ) { - return Index; - } - Index++; - } while (Index < ARRAY_SIZE (mClkDiv)); - - return (ARRAY_SIZE (mClkDiv) - 1); -} - -/** - Function used to check if i2c is in mentioned state or not - - @param I2cRegs Pointer to I2C registers - @param State i2c state need to be checked - - @retval EFI_NOT_READY Arbitration was lost - @retval EFI_TIMEOUT Timeout occured - @retval CurrState Value of state register - -**/ -STATIC -EFI_STATUS -WaitForI2cState ( - IN I2C_REGS *I2cRegs, - IN UINT32 State - ) -{ - UINT8 CurrState; - UINT64 Count; - - for (Count =3D 0; Count < I2C_STATE_RETRIES; Count++) { - MemoryFence (); - CurrState =3D MmioRead8 ((UINTN)&I2cRegs->I2cSr); - if (CurrState & I2C_SR_IAL) { - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL); - return EFI_NOT_READY; - } - - if ((CurrState & (State >> 8)) =3D=3D (UINT8)State) { - return CurrState; - } - } - - return EFI_TIMEOUT; -} - -/** - Function to transfer byte on i2c - - @param I2cRegs Pointer to i2c registers - @param Byte Byte to be transferred on i2c bus - - @retval EFI_NOT_READY Arbitration was lost - @retval EFI_TIMEOUT Timeout occured - @retval EFI_NOT_FOUND ACK was not recieved - @retval EFI_SUCCESS Data transfer was succesful - -**/ -STATIC -EFI_STATUS -TransferByte ( - IN I2C_REGS *I2cRegs, - IN UINT8 Byte - ) -{ - EFI_STATUS RetVal; - - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); - MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte); - - RetVal =3D WaitForI2cState (I2cRegs, IIF); - if ((RetVal =3D=3D EFI_TIMEOUT) || (RetVal =3D=3D EFI_NOT_READY)) { - return RetVal; - } - - if (RetVal & I2C_SR_RX_NO_AK) { - return EFI_NOT_FOUND; - } - - return EFI_SUCCESS; -} - -/** - Function to stop transaction on i2c bus - - @param I2cRegs Pointer to i2c registers - - @retval EFI_NOT_READY Arbitration was lost - @retval EFI_TIMEOUT Timeout occured - @retval EFI_SUCCESS Stop operation was successful - -**/ -STATIC -EFI_STATUS -I2cStop ( - IN I2C_REGS *I2cRegs - ) -{ - EFI_STATUS RetVal; - UINT32 Temp; - - Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); - - Temp &=3D ~(I2C_CR_MSTA | I2C_CR_MTX); - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); - - RetVal =3D WaitForI2cState (I2cRegs, BUS_IDLE); - - if (RetVal < 0) { - return RetVal; - } else { - return EFI_SUCCESS; - } -} - -/** - Function to send start signal, Chip Address and - memory offset - - @param I2cRegs Pointer to i2c base registers - @param Chip Chip Address - @param Offset Slave memory's offset - @param AddressLength length of chip address - - @retval EFI_NOT_READY Arbitration lost - @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time - @retval EFI_NOT_FOUND ACK was not recieved - @retval EFI_SUCCESS Read was successful - -**/ -STATIC -EFI_STATUS -InitTransfer ( - IN I2C_REGS *I2cRegs, - IN UINT8 Chip, - IN UINT32 Offset, - IN INT32 AddressLength - ) -{ - UINT32 Temp; - EFI_STATUS RetVal; - - // Enable I2C controller - if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) { - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN); - } - - if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) =3D=3D (Chip << 1)) { - MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2); - } - - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); - RetVal =3D WaitForI2cState (I2cRegs, BUS_IDLE); - if ((RetVal =3D=3D EFI_TIMEOUT) || (RetVal =3D=3D EFI_NOT_READY)) { - return RetVal; - } - - // Start I2C transaction - Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); - // set to master mode - Temp |=3D I2C_CR_MSTA; - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); - - RetVal =3D WaitForI2cState (I2cRegs, BUS_BUSY); - if ((RetVal =3D=3D EFI_TIMEOUT) || (RetVal =3D=3D EFI_NOT_READY)) { - return RetVal; - } - - Temp |=3D I2C_CR_MTX | I2C_CR_TX_NO_AK; - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); - - // write slave Address - RetVal =3D TransferByte (I2cRegs, Chip << 1); - if (RetVal !=3D EFI_SUCCESS) { - return RetVal; - } - - if (AddressLength >=3D 0) { - while (AddressLength--) { - RetVal =3D TransferByte (I2cRegs, (Offset >> (AddressLength * 8)) & = 0xff); - if (RetVal !=3D EFI_SUCCESS) - return RetVal; - } - } - return EFI_SUCCESS; -} - -/** - Function to check if i2c bus is idle - - @param Base Pointer to base address of I2c controller - - @retval EFI_SUCCESS - -**/ -STATIC -INT32 -I2cBusIdle ( - IN VOID *Base - ) -{ - return EFI_SUCCESS; -} - -/** - Function to initiate data transfer on i2c bus - - @param I2cRegs Pointer to i2c base registers - @param Chip Chip Address - @param Offset Slave memory's offset - @param AddressLength length of chip address - - @retval EFI_NOT_READY Arbitration lost - @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time - @retval EFI_NOT_FOUND ACK was not recieved - @retval EFI_SUCCESS Read was successful - -**/ -STATIC -EFI_STATUS -InitDataTransfer ( - IN I2C_REGS *I2cRegs, - IN UINT8 Chip, - IN UINT32 Offset, - IN INT32 AddressLength - ) -{ - EFI_STATUS RetVal; - INT32 Retry; - - for (Retry =3D 0; Retry < RETRY_COUNT; Retry++) { - RetVal =3D InitTransfer (I2cRegs, Chip, Offset, AddressLength); - if (RetVal =3D=3D EFI_SUCCESS) { - return EFI_SUCCESS; - } - - I2cStop (I2cRegs); - - if (EFI_NOT_FOUND =3D=3D RetVal) { - return RetVal; - } - - // Disable controller - if (RetVal !=3D EFI_NOT_READY) { - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS); - } - - if (I2cBusIdle (I2cRegs) < 0) { - break; - } - } - return RetVal; -} - -/** - Function to read data using i2c bus - - @param BaseAddr I2c Controller Base Address - @param Chip Address of slave device from where data to be r= ead - @param Offset Offset of slave memory - @param AddressLength Address length of slave - @param Buffer A pointer to the destination buffer for the data - @param Len Length of data to be read - - @retval EFI_NOT_READY Arbitration lost - @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time - @retval EFI_NOT_FOUND ACK was not recieved - @retval EFI_SUCCESS Read was successful - -**/ -STATIC -EFI_STATUS -I2cDataRead ( - IN UINTN BaseAddr, - IN UINT8 Chip, - IN UINT32 Offset, - IN UINT32 AddressLength, - IN UINT8 *Buffer, - IN UINT32 Len - ) -{ - EFI_STATUS RetVal; - UINT32 Temp; - INT32 I; - I2C_REGS *I2cRegs; - - I2cRegs =3D (I2C_REGS *)(BaseAddr); - - RetVal =3D InitDataTransfer (I2cRegs, Chip, Offset, AddressLength); - if (RetVal !=3D EFI_SUCCESS) { - return RetVal; - } - - Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); - Temp |=3D I2C_CR_RSTA; - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); - - RetVal =3D TransferByte (I2cRegs, (Chip << 1) | 1); - if (RetVal !=3D EFI_SUCCESS) { - I2cStop (I2cRegs); - return RetVal; - } - - // setup bus to read data - Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); - Temp &=3D ~(I2C_CR_MTX | I2C_CR_TX_NO_AK); - if (Len =3D=3D 1) { - Temp |=3D I2C_CR_TX_NO_AK; - } - - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); - - // Dummy Read to initiate recieve operation - MmioRead8 ((UINTN)&I2cRegs->I2cDr); - - for (I =3D 0; I < Len; I++) { - RetVal =3D WaitForI2cState (I2cRegs, IIF); - if ((RetVal =3D=3D EFI_TIMEOUT) || (RetVal =3D=3D EFI_NOT_READY)) { - I2cStop (I2cRegs); - return RetVal; - } - // - // It must generate STOP before read I2DR to prevent - // controller from generating another clock cycle - // - if (I =3D=3D (Len - 1)) { - I2cStop (I2cRegs); - } else if (I =3D=3D (Len - 2)) { - Temp =3D MmioRead8 ((UINTN)&I2cRegs->I2cCr); - Temp |=3D I2C_CR_TX_NO_AK; - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp); - } - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR); - Buffer[I] =3D MmioRead8 ((UINTN)&I2cRegs->I2cDr); - } - - I2cStop (I2cRegs); - - return EFI_SUCCESS; -} - -/** - Function to write data using i2c bus - - @param BaseAddr I2c Controller Base Address - @param Chip Address of slave device where data to be written - @param Offset Offset of slave memory - @param AddressLength Address length of slave - @param Buffer A pointer to the source buffer for the data - @param Len Length of data to be write - - @retval EFI_NOT_READY Arbitration lost - @retval EFI_TIMEOUT Failed to initialize data transfer in predefine= d time - @retval EFI_NOT_FOUND ACK was not recieved - @retval EFI_SUCCESS Read was successful - -**/ -STATIC -EFI_STATUS -I2cDataWrite ( - IN UINTN BaseAddr, - IN UINT8 Chip, - IN UINT32 Offset, - IN INT32 AddressLength, - OUT UINT8 *Buffer, - IN INT32 Len - ) -{ - EFI_STATUS RetVal; - I2C_REGS *I2cRegs; - INT32 I; - - I2cRegs =3D (I2C_REGS *)BaseAddr; - - RetVal =3D InitDataTransfer (I2cRegs, Chip, Offset, AddressLength); - if (RetVal !=3D EFI_SUCCESS) { - return RetVal; - } - - // Write operation - for (I =3D 0; I < Len; I++) { - RetVal =3D TransferByte (I2cRegs, Buffer[I]); - if (RetVal !=3D EFI_SUCCESS) { - break; - } - } - - I2cStop (I2cRegs); - return RetVal; -} - /** Function to set i2c bus frequency =20 @@ -479,22 +42,17 @@ SetBusFrequency ( IN OUT UINTN *BusClockHertz ) { - I2C_REGS *I2cRegs; - UINT8 ClkId; - UINT8 SpeedId; + UINTN I2cBase; + UINT64 I2cClock; NXP_I2C_MASTER *I2c; =20 I2c =3D NXP_I2C_FROM_THIS (This); =20 - I2cRegs =3D (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin); + I2cBase =3D (UINTN)(I2c->Dev->Resources[0].AddrRangeMin); =20 - ClkId =3D GetClkDivIndex (*BusClockHertz); - SpeedId =3D mClkDiv[ClkId].BusClockRate; + I2cClock =3D GetBusFrequency (); =20 - // Store divider value - MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId); - - MemoryFence (); + I2cInitialize (I2cBase, I2cClock, *BusClockHertz); =20 return EFI_SUCCESS; } @@ -513,19 +71,6 @@ Reset ( IN CONST EFI_I2C_MASTER_PROTOCOL *This ) { - I2C_REGS *I2cRegs; - NXP_I2C_MASTER *I2c; - - I2c =3D NXP_I2C_FROM_THIS (This); - - I2cRegs =3D (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin); - - // Reset module - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS); - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0); - - MemoryFence (); - return EFI_SUCCESS; } =20 @@ -540,62 +85,17 @@ StartRequest ( OUT EFI_STATUS *I2cStatus OPTIONAL ) { - NXP_I2C_MASTER *I2c; - UINT32 Count; - INT32 RetVal; - UINT32 Length; - UINT8 *Buffer; - UINT32 Flag; - UINT32 RegAddress; - UINT32 OffsetLength; - - RegAddress =3D 0; + NXP_I2C_MASTER *I2c; + UINTN I2cBase; + EFI_STATUS Status; =20 I2c =3D NXP_I2C_FROM_THIS (This); =20 - if (RequestPacket->OperationCount <=3D 0) { - DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n", - __FUNCTION__, RequestPacket->OperationCount)); - return EFI_INVALID_PARAMETER; - } + I2cBase =3D (UINTN)(I2c->Dev->Resources[0].AddrRangeMin); =20 - OffsetLength =3D RequestPacket->Operation[0].LengthInBytes; - RegAddress =3D *RequestPacket->Operation[0].Buffer; + Status =3D I2cBusXfer (I2cBase, SlaveAddress, RequestPacket); =20 - for (Count =3D 1; Count < RequestPacket->OperationCount; Count++) { - Flag =3D RequestPacket->Operation[Count].Flags; - Length =3D RequestPacket->Operation[Count].LengthInBytes; - Buffer =3D RequestPacket->Operation[Count].Buffer; - - if (Length <=3D 0) { - DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n", - __FUNCTION__, Length)); - return EFI_INVALID_PARAMETER; - } - - if (Flag =3D=3D I2C_FLAG_READ) { - RetVal =3D I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAd= dress, - RegAddress, OffsetLength, Buffer, Length); - if (RetVal !=3D EFI_SUCCESS) { - DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n", - __FUNCTION__, RetVal)); - return RetVal; - } - } else if (Flag =3D=3D I2C_FLAG_WRITE) { - RetVal =3D I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveA= ddress, - RegAddress, OffsetLength, Buffer, Length); - if (RetVal !=3D EFI_SUCCESS) { - DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n", - __FUNCTION__, RetVal)); - return RetVal; - } - } else { - DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n", __FUNCTION__, Flag)); - return EFI_INVALID_PARAMETER; - } - } - - return EFI_SUCCESS; + return Status; } =20 EFI_STATUS --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:09 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 03/24] Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC Date: Fri, 1 May 2020 11:19:34 +0530 Message-ID: <20200501054955.13025-4-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:07 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 9b0b346f-142d-4480-30e3-08d7ecca7b74 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: XEtqQpH6xOTkgcB6m3WmH6tfx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225872; bh=KUP99GZNp719UY0UOf4mExW8YFgI+pBH5QElLG31Er0=; h=Content-Type:Date:From:Reply-To:Subject:To; b=EAzxv21sTxv+7AMLCOedZMMoFMVB42eMfuAFBcth+5PNI5771RfjLOOdzSHcJzCqOgR uKmhV0rk3c/NGGmCPDIM0jIEoHVdoSHnk0lkzHC5rCv7vh36YhB6vqLsrW3Y8X+Rxo7zO 5uKdQqR+z9Zu1zE82kNy+4VUOV2ef+wU0NQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal With latest edk2 codebase, sometimes i2c timeout is observed when Network devices are being probed. This is happening when gRT->GetTime request is ongoing. gRT->GetTime triggers a read request to Real Time Clock which is connected to I2c bus. In between read request, if an event occurs, which also triggers gRT->GetTime (i.e. RTC read), the I2c bus goes into unrecoverable state. This state is not even recovered, when rebooting the board. We need to power off the board completely to recover i2c bus. To prevent this, TPL level of I2c read is being raised to high, so that no other event can pre-empt this. with this solution no timeout has been observed so far. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 3 ++- Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 12 ++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2= cDxe/I2cDxe.inf index 84adb837c249..867376044656 100644 --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf @@ -13,7 +13,7 @@ INF_VERSION =3D 0x0001001A BASE_NAME =3D I2cDxe FILE_GUID =3D 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7 - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D DXE_RUNTIME_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D I2cDxeEntryPoint UNLOAD =3D I2cDxeUnload @@ -36,6 +36,7 @@ UefiBootServicesTableLib UefiDriverEntryPoint UefiLib + UefiRuntimeLib =20 [Guids] gNxpNonDiscoverableI2cMasterGuid diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.c index 848e707c1673..a5aba47b3ed4 100644 --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include "I2cDxe.h" =20 @@ -88,6 +89,13 @@ StartRequest ( NXP_I2C_MASTER *I2c; UINTN I2cBase; EFI_STATUS Status; + EFI_TPL Tpl; + BOOLEAN AtRuntime; + + AtRuntime =3D EfiAtRuntime (); + if (!AtRuntime) { + Tpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + } =20 I2c =3D NXP_I2C_FROM_THIS (This); =20 @@ -95,6 +103,10 @@ StartRequest ( =20 Status =3D I2cBusXfer (I2cBase, SlaveAddress, RequestPacket); =20 + if (!AtRuntime) { + gBS->RestoreTPL (Tpl); + } + return Status; } =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:12 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 04/24] Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib Date: Fri, 1 May 2020 11:19:35 +0530 Message-ID: <20200501054955.13025-5-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: TL8J6Xc7jdfVNnKgfYX7bAqPx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225875; bh=UUoGKYDQK+wbpbANzDesqXtgVgvC0/MYrD9wOKRrudM=; h=Content-Type:Date:From:Reply-To:Subject:To; b=bG8xXAlebwZsA35wdr2T/c7w0TAtSG42BX2O/TZEs61Whs2XqM1nqTG6eL5BsAKSlkP nkDSq4Kf2qEQIDSaEthDOQd19TueEDZcOB0BLmUUJcRnYXGyqKeyilrUouEaBt37EG7ZX n3FO9cEHOKITqpOPF6kECNKzqMfd49TbhVE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal There was a bug in I2C DXE implementation, which caused the Ds1307 RTC device to issue two operation for register write, while this is a single operation task. refer page 12 (Slave Receiver Mode (Write Mode)) on https://datasheets.maximintegrated.com/en/ds/DS1307.pdf Modify ds1307 RtcWrite code accordingly. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Ma= xim/Library/Ds1307RtcLib/Ds1307RtcLib.c index 88dc198ffec8..fd7a8696e405 100644 --- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c @@ -5,7 +5,7 @@ EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c =20 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright 2017 NXP + Copyright 2017, 2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -84,16 +84,15 @@ RtcWrite ( { RTC_I2C_REQUEST Req; EFI_STATUS Status; + UINT8 Buffer[2]; =20 - Req.OperationCount =3D 2; + Req.OperationCount =3D 1; + Buffer[0] =3D RtcRegAddr; + Buffer[1] =3D Val; =20 Req.SetAddressOp.Flags =3D 0; - Req.SetAddressOp.LengthInBytes =3D sizeof (RtcRegAddr); - Req.SetAddressOp.Buffer =3D &RtcRegAddr; - - Req.GetSetDateTimeOp.Flags =3D 0; - Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); - Req.GetSetDateTimeOp.Buffer =3D &Val; + Req.SetAddressOp.LengthInBytes =3D sizeof (Buffer); + Req.SetAddressOp.Buffer =3D Buffer; =20 Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), (VOID *)&Req, --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:15 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 05/24] Silicon/Maxim: Add comments in Ds1307RtcLib Date: Fri, 1 May 2020 11:19:36 +0530 Message-ID: <20200501054955.13025-6-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:12 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: cffa2a40-4710-49bd-ae3a-08d7ecca7ee1 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: pFKjEGweiupVyaWJZknPWiVTx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225878; bh=MDOEgILv6FdTOeYX/WvtR/RPGtFoz+k2QA73wTFNcCE=; h=Content-Type:Date:From:Reply-To:Subject:To; b=Q18OfsyI2EG0IH+8OTc/1luf6p1rwh6xVWUWU2DzJYYOSknjjpbfPDB7X3HOzCMHGEp y12Xj3M9PIdApLFwwsHkBNWco/Qdc1XCUo0UIYolOMlXpqP/mYeQidKRGf8lMKW8WVVPm IrisOMIpwD9hVzxsgDeQDK/5WyDZxTuQnWM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Add comments to explain the register read and write operation on Ds1307. These comments have been referred from data sheet: https://datasheets.maximintegrated.com/en/ds/DS1307.pdf Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Ma= xim/Library/Ds1307RtcLib/Ds1307RtcLib.c index fd7a8696e405..444e01124811 100644 --- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c @@ -28,6 +28,11 @@ STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster; =20 /** Read RTC register. + Data Read-Slave Transmitter Mode + + = + + The first byte is received and handled as in the slave receiver mode. =20 @param RtcRegAddr Register offset of RTC to be read. =20 @@ -69,6 +74,9 @@ RtcRead ( =20 /** Write RTC register. + Data Write-Slave Receiver Mode + + =20 @param RtcRegAddr Register offset of RTC to write. @param Val Value to be written --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:18 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 06/24] NXP/LS1043aRdb: Move Soc specific components to soc files Date: Fri, 1 May 2020 11:19:37 +0530 Message-ID: <20200501054955.13025-7-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: KkXMpQDVNwELStbPEMiY9TeJx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225881; bh=mOM0lFAIQaTbJvviXadYy/C1tWWmcTj/9KMz3rCYAXI=; h=Content-Type:Date:From:Reply-To:Subject:To; b=IXbEWDAaNnhncmIoCw4wnY7cgfBMVduX381idF3cmtNA2pMuA7SvTpwsoWl/MhM0UnY CDfw1rbG5axLr25RHoggpzqdryeTQyQ4UZVQQiXb3EdexjwCkVaFgiXHAILBeXGpzEV4G WMTsoZDPOOjI9XXNN11FdPqok1KS3mhCyDY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Soc specific components ought to be part of Soc files and not platform files. move the same to SOC files Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++ Silicon/NXP/LS1043A/LS1043A.dsc.inc | 7 ++++++- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 7 +------ 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.= inc index 25c0a41e5d4a..8fbd6288cfae 100644 --- a/Platform/NXP/NxpQoriqLs.dsc.inc +++ b/Platform/NXP/NxpQoriqLs.dsc.inc @@ -95,6 +95,8 @@ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf =20 I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf + IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf =20 [LibraryClasses.common.SEC] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc index dbd680b0ad28..d2d4133428c3 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -1,12 +1,16 @@ # LS1043A.dsc # LS1043A Soc package. # -# Copyright 2017-2019 NXP +# Copyright 2017-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # # =20 +[LibraryClasses.common] + SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + ##########################################################################= ###### # # Pcd Section - list of all EDK II PCD Entries defined by this Platform @@ -20,6 +24,7 @@ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000 =20 [PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 =20 # # CCSR Address Space and other attached Memories diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index c8105593533f..802cccdce63b 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -2,7 +2,7 @@ # # LS1043ARDB Board package. # -# Copyright 2017-2019 NXP +# Copyright 2017-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -26,11 +26,7 @@ !include Silicon/NXP/LS1043A/LS1043A.dsc.inc =20 [LibraryClasses.common] - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatfor= mLib.inf - ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf - SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf - IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf =20 [PcdsFixedAtBuild.common] @@ -46,7 +42,6 @@ # # Board Specific Pcds # - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:21 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 07/24] Silicon/NXP: remove print information from Soc lib Date: Fri, 1 May 2020 11:19:38 +0530 Message-ID: <20200501054955.13025-8-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: DPpqWq0IHfVltAxQ1YKTG5DYx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225884; bh=npWtUk1tdNGbGq5GWKcQNJ2x5h8jsvDtWRkMPBv8Ww8=; h=Content-Type:Date:From:Reply-To:Subject:To; b=pkU7Ba2QnjNFhmdlufX4fzcOJXNtMsxtBz5DG//ZyAD23d+iNjAXapUgFr8hIZLpUaV 4dF3tVV5z8Qr9Qcj6Fbd/2yjFJaaJayWtFzYES2T8YbWes+ZuDcDnuGpTT8Gy3slf2+Eg /RiJrZET6GtgU3PzsHDFfgiRikrC/yUTxGw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal The Soc info being printed can be removed from SOC lib. We are in the process of implementing PEI Phase. After PEI phase implementation this info would be printed in common PEIM based on the information retrieved from PPIs. e.g. gArmMpCoreInfoPpiGuid can be used to print cluster and core info. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - cluser -> cluster =20 V3: - remove CpuMaskNext from this patch and put in previous patch Silicon/NXP/Library/SocLib/NxpChassis.h | 26 +--- Silicon/NXP/Library/SocLib/Chassis.c | 144 -------------------- Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 16 +-- 3 files changed, 2 insertions(+), 184 deletions(-) diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/= SocLib/NxpChassis.h index 99f6439d8f35..a11acf71563e 100644 --- a/Silicon/NXP/Library/SocLib/NxpChassis.h +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h @@ -1,7 +1,7 @@ /** @file * Header defining the Base addresses, sizes, flags etc for chassis 1 * -* Copyright 2017-2019 NXP +* Copyright 2017-2020 NXP * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -54,14 +54,6 @@ typedef struct { UINTN SdhcClk; } SOC_CLOCK_INFO; =20 -/* - * Print Soc information - */ -VOID -PrintSoc ( - VOID - ); - /* * Initialize Clock structure */ @@ -79,22 +71,6 @@ SmmuInit ( VOID ); =20 -/* - * Print CPU information - */ -VOID -PrintCpuInfo ( - VOID - ); - -/* - * Dump RCW (Reset Control Word) on console - */ -VOID -PrintRCW ( - VOID - ); - UINT32 InitiatorType ( IN UINT32 Cluster, diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index b8a8118c5e24..adca7b8dd413 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -204,79 +204,6 @@ QoriqCoreToType ( return EFI_NOT_FOUND; /* cannot identify the cluster */ } =20 -STATIC -UINTN -CpuMaskNext ( - IN UINTN Cpu, - IN UINTN Mask - ) -{ - for (Cpu++; !((1 << Cpu) & Mask); Cpu++); - - return Cpu; -} - -/* - * Print CPU information - */ -VOID -PrintCpuInfo ( - VOID - ) -{ - SYS_INFO SysInfo; - UINTN CoreIndex; - UINTN Core; - UINT32 Type; - UINT32 NumCpus; - UINT32 Mask; - CHAR8 *CoreName; - - GetSysInfo (&SysInfo); - DEBUG ((DEBUG_INIT, "Clock Configuration:")); - - NumCpus =3D CpuNumCores (); - Mask =3D CpuMask (); - - for (CoreIndex =3D 0, Core =3D CpuMaskNext(-1, Mask); - CoreIndex < NumCpus; - CoreIndex++, Core =3D CpuMaskNext(Core, Mask)) - { - if (!(CoreIndex % 3)) { - DEBUG ((DEBUG_INIT, "\n ")); - } - - Type =3D TP_ITYP_VERSION (QoriqCoreToType (Core)); - switch (Type) { - case TY_ITYP_VERSION_A7: - CoreName =3D "A7"; - break; - case TY_ITYP_VERSION_A53: - CoreName =3D "A53"; - break; - case TY_ITYP_VERSION_A57: - CoreName =3D "A57"; - break; - case TY_ITYP_VERSION_A72: - CoreName =3D "A72"; - break; - default: - CoreName =3D " Unknown Core "; - } - DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", - Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ)); - } - - DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBu= s / MHZ)); - DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ)); - - if (SysInfo.FreqFman[0] !=3D 0) { - DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[= 0] / MHZ)); - } - - DEBUG ((DEBUG_INIT, "\n")); -} - /* * Return system bus frequency */ @@ -307,77 +234,6 @@ GetSdxcFrequency ( return SocSysInfo.FreqSdhc; } =20 -/* - * Print Soc information - */ -VOID -PrintSoc ( - VOID - ) -{ - CHAR8 Buf[20]; - CCSR_GUR *GurBase; - UINTN Count; - // - // Svr : System Version Register - // - UINTN Svr; - UINTN Ver; - - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - - Svr =3D GurRead ((UINTN)&GurBase->Svr); - Ver =3D SVR_SOC_VER (Svr); - - for (Count =3D 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) =3D=3D Ver) { - AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name); - - if (IS_E_PROCESSOR (Svr)) { - AsciiStrCatS (Buf, sizeof (Buf), "E"); - } - break; - } - } - - DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n", - Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr))); - - return; -} - -/* - * Dump RCW (Reset Control Word) on console - */ -VOID -PrintRCW ( - VOID - ) -{ - CCSR_GUR *Base; - UINTN Count; - - Base =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - - /* - * Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - - DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):")); - for (Count =3D 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) { - UINT32 Rcw =3D SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]); - - if ((Count % 4) =3D=3D 0) { - DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4)); - } - - DEBUG ((DEBUG_INIT, " %08x", Rcw)); - } - - DEBUG ((DEBUG_INIT, "\n")); -} - /* * Setup SMMU in bypass mode * and also set its pagesize diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index bfb8b8cb339a..687a1d940066 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -1,7 +1,7 @@ /** @Soc.c SoC specific Library containg functions to initialize various SoC compon= ents =20 - Copyright 2017-2019 NXP + Copyright 2017-2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -131,10 +131,6 @@ GetSysInfo ( =20 /** Function to initialize SoC specific constructs - CPU Info - SoC Personality - Board Personality - RCW prints **/ VOID SocInit ( @@ -147,16 +143,6 @@ SocInit ( // Early init serial Port to get board information. // SerialPortInitialize (); - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n", - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE_= _)); - - PrintCpuInfo (); - - // - // Print Reset control Word - // - PrintRCW (); - PrintSoc (); =20 return; } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:24 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 08/24] Silicon/NXP: remove not needed components Date: Fri, 1 May 2020 11:19:39 +0530 Message-ID: <20200501054955.13025-9-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:21 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 9185f214-7120-4973-d850-08d7ecca840d X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: 4kJsuZQPgmfL099KrISwWGRqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225887; bh=AjpckPw/+9ZaEvgC7UCOpH/QZf88/a5klA7PPKVRiDU=; h=Content-Type:Date:From:Reply-To:Subject:To; b=UszYP+NiDjrhIfTrdte9thYc6wplNOW3LPxTq5ZlUN20UZYripOQr2xIlVcjxm74zBi rVlIWDSr8FMVFqSFm4SPdb9khl4DnJrb3q2e2f9PgusC0Bdd6gUpx2sQgINeHFcLJZ2WX 6+0i/cgsPB5QDRbMmDWY5zY9HaTD5YR4AnI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal The structures elements and functions that are not necessary for booting for now are being deleted. Once the directory structure has been changed (i.e. we have clear distinction between chassis code and header files and SOC code and header files), we will put back the code and structure components back at their appropriate respective place. Also right now all the elements are being defined in structures, which are not being used right now. So to simplify the code restructuring, I have removed those for now. When we need to use those elements, we can define those one by one. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - remove CpuMaskNext from this patch and put in previous patch Silicon/NXP/NxpQoriqLs.dec | 27 -- Silicon/NXP/LS1043A/LS1043A.dsc.inc | 6 - Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 4 - Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 7 +- Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ---- Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +------------------- Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ---- Silicon/NXP/Library/SocLib/NxpChassis.h | 90 ------ Silicon/NXP/Library/SocLib/Chassis.c | 208 ------------- Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 ----- Silicon/NXP/Library/SocLib/SerDes.c | 268 ----------------- 11 files changed, 3 insertions(+), 1113 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 1aff519bfaf4..bc604e586283 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -32,10 +32,7 @@ # Pcds for base address and size # gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100 - gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101 - gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102 gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103 - gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104 gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105 gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106 gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107 @@ -61,10 +58,6 @@ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D - gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E - gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F - gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120 - gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121 gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122 gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123 =20 @@ -75,36 +68,16 @@ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191 gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192 gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193 - gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194 - gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195 - gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x0000= 0196 - - # - # NV Pcd - # - gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210 - gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211 =20 # # Platform PCDs # gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250 - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251 - - # - # Clock PCDs - # - gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0 - gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1 =20 # # Pcds to support Big Endian IPs # - gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310 gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311 - gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312 - gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313 - gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314 =20 [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315 diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc index d2d4133428c3..f6ada08dad9d 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -31,12 +31,10 @@ # gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000 gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 @@ -47,10 +45,7 @@ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000 gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 - gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000 - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000 gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 @@ -61,6 +56,5 @@ # Big Endian IPs # gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE - gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE =20 ## diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index 802cccdce63b..385b6e067e26 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -39,10 +39,6 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 =20 - # - # Board Specific Pcds - # - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 =20 # diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index cb670a12797e..f75a8d19f5a5 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -1,6 +1,6 @@ # @file # -# Copyright 2017-2019 NXP +# Copyright 2017-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -18,7 +18,6 @@ MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Silicon/NXP/NxpQoriqLs.dec - Silicon/NXP/LS1043A/LS1043A.dec =20 [LibraryClasses] ArmSmcLib @@ -30,16 +29,12 @@ [Sources.common] Chassis.c Chassis2/Soc.c - SerDes.c =20 [BuildOptions] GCC:*_*_*_CC_FLAGS =3D -DCHASSIS2 =20 [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/= Chassis2/LsSerDes.h deleted file mode 100644 index 9afbc522398a..000000000000 --- a/Silicon/NXP/Include/Chassis2/LsSerDes.h +++ /dev/null @@ -1,62 +0,0 @@ -/** LsSerDes.h - The Header file of SerDes Module for Chassis 2 - - Copyright 2017-2019 NXP - - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef LS_SERDES_H_ -#define LS_SERDES_H_ - -#include - -#define SRDS_MAX_LANES 4 - -typedef enum { - None =3D 0, - Pcie1, - Pcie2, - Pcie3, - Sata, - SgmiiFm1Dtsec1, - SgmiiFm1Dtsec2, - SgmiiFm1Dtsec5, - SgmiiFm1Dtsec6, - SgmiiFm1Dtsec9, - SgmiiFm1Dtsec10, - QsgmiiFm1A, - XfiFm1Mac9, - XfiFm1Mac10, - Sgmii2500Fm1Dtsec2, - Sgmii2500Fm1Dtsec5, - Sgmii2500Fm1Dtsec9, - Sgmii2500Fm1Dtsec10, - SerdesPrtclCount -} SERDES_PROTOCOL; - -typedef enum { - Srds1 =3D 0, - Srds2, - SrdsMaxNum -} SERDES_NUMBER; - -typedef struct { - UINT16 Protocol; - UINT8 SrdsLane[SRDS_MAX_LANES]; -} SERDES_CONFIG; - -typedef VOID -(*SERDES_PROBE_LANES_CALLBACK) ( - IN SERDES_PROTOCOL LaneProtocol, - IN VOID *Arg - ); - -VOID -SerDesProbeLanes( - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, - IN VOID *Arg - ); - -#endif /* LS_SERDES_H_ */ diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Ch= assis2/NxpSoc.h index f05a813750e8..74330b6205e7 100644 --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h @@ -1,7 +1,7 @@ /** Soc.h * Header defining the Base addresses, sizes, flags etc for chassis 1 * -* Copyright 2017-2019 NXP +* Copyright 2017-2020 NXP * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -10,22 +10,7 @@ #ifndef NXP_SOC_H_ #define NXP_SOC_H_ =20 -#define HWA_CGA_M1_CLK_SEL 0xe0000000 -#define HWA_CGA_M1_CLK_SHIFT 29 - -#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */ -#define NUM_CC_PLLS 2 #define CLK_FREQ 100000000 -#define MAX_CPUS 4 -#define NUM_FMAN 1 -#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) =3D=3D = 0x0) - -/* RCW SERDES MACRO */ -#define RCWSR_INDEX 4 -#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000 -#define RCWSR_SRDS1_PRTCL_SHIFT 16 -#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff -#define RCWSR_SRDS2_PRTCL_SHIFT 0 =20 /* SMMU Defintions */ #define SMMU_BASE_ADDR 0x09000000 @@ -41,312 +26,17 @@ #define IDR1_PAGESIZE_MASK 0x80000000 =20 typedef struct { - UINTN FreqProcessor[MAX_CPUS]; UINTN FreqSystemBus; - UINTN FreqDdrBus; - UINTN FreqLocalBus; - UINTN FreqSdhc; - UINTN FreqFman[NUM_FMAN]; - UINTN FreqQman; } SYS_INFO; =20 /* Device Configuration and Pin Control */ typedef struct { - UINT32 PorSr1; /* POR status 1 */ -#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 - UINT32 PorSr2; /* POR status 2 */ - UINT8 Res008[0x20-0x8]; - UINT32 GppOrCr1; /* General-purpose POR configuration */ - UINT32 GppOrCr2; - UINT32 DcfgFuseSr; /* Fuse status register */ - UINT8 Res02c[0x70-0x2c]; - UINT32 DevDisr; /* Device disable control */ - UINT32 DevDisr2; /* Device disable control 2 */ - UINT32 DevDisr3; /* Device disable control 3 */ - UINT32 DevDisr4; /* Device disable control 4 */ - UINT32 DevDisr5; /* Device disable control 5 */ - UINT32 DevDisr6; /* Device disable control 6 */ - UINT32 DevDisr7; /* Device disable control 7 */ - UINT8 Res08c[0x94-0x8c]; - UINT32 CoreDisrU; /* uppper portion for support of 64 cores */ - UINT32 CoreDisrL; /* lower portion for support of 64 cores */ - UINT8 Res09c[0xa0-0x9c]; - UINT32 Pvr; /* Processor version */ - UINT32 Svr; /* System version */ - UINT32 Mvr; /* Manufacturing version */ - UINT8 Res0ac[0xb0-0xac]; - UINT32 RstCr; /* Reset control */ - UINT32 RstRqPblSr; /* Reset request preboot loader status */ - UINT8 Res0b8[0xc0-0xb8]; - UINT32 RstRqMr1; /* Reset request mask */ - UINT8 Res0c4[0xc8-0xc4]; - UINT32 RstRqSr1; /* Reset request status */ - UINT8 Res0cc[0xd4-0xcc]; - UINT32 RstRqWdTmrL; /* Reset request WDT mask */ - UINT8 Res0d8[0xdc-0xd8]; - UINT32 RstRqWdtSrL; /* Reset request WDT status */ - UINT8 Res0e0[0xe4-0xe0]; - UINT32 BrrL; /* Boot release */ - UINT8 Res0e8[0x100-0xe8]; + UINT8 Res0[0x100-0x00]; UINT32 RcwSr[16]; /* Reset control word status */ #define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 #define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f -#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 -#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f - UINT8 Res140[0x200-0x140]; - UINT32 ScratchRw[4]; /* Scratch Read/Write */ - UINT8 Res210[0x300-0x210]; - UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */ - UINT8 Res310[0x400-0x310]; - UINT32 CrstSr[12]; - UINT8 Res430[0x500-0x430]; - /* PCI Express n Logical I/O Device Number register */ - UINT32 DcfgCcsrPex1LiodNr; - UINT32 DcfgCcsrPex2LiodNr; - UINT32 DcfgCcsrPex3LiodNr; - UINT32 DcfgCcsrPex4LiodNr; - /* RIO n Logical I/O Device Number register */ - UINT32 DcfgCcsrRio1LiodNr; - UINT32 DcfgCcsrRio2LiodNr; - UINT32 DcfgCcsrRio3LiodNr; - UINT32 DcfgCcsrRio4LiodNr; - /* USB Logical I/O Device Number register */ - UINT32 DcfgCcsrUsb1LiodNr; - UINT32 DcfgCcsrUsb2LiodNr; - UINT32 DcfgCcsrUsb3LiodNr; - UINT32 DcfgCcsrUsb4LiodNr; - /* SD/MMC Logical I/O Device Number register */ - UINT32 DcfgCcsrSdMmc1LiodNr; - UINT32 DcfgCcsrSdMmc2LiodNr; - UINT32 DcfgCcsrSdMmc3LiodNr; - UINT32 DcfgCcsrSdMmc4LiodNr; - /* RIO Message Unit Logical I/O Device Number register */ - UINT32 DcfgCcsrRiomaintLiodNr; - UINT8 Res544[0x550-0x544]; - UINT32 SataLiodNr[4]; - UINT8 Res560[0x570-0x560]; - UINT32 DcfgCcsrMisc1LiodNr; - UINT32 DcfgCcsrMisc2LiodNr; - UINT32 DcfgCcsrMisc3LiodNr; - UINT32 DcfgCcsrMisc4LiodNr; - UINT32 DcfgCcsrDma1LiodNr; - UINT32 DcfgCcsrDma2LiodNr; - UINT32 DcfgCcsrDma3LiodNr; - UINT32 DcfgCcsrDma4LiodNr; - UINT32 DcfgCcsrSpare1LiodNr; - UINT32 DcfgCcsrSpare2LiodNr; - UINT32 DcfgCcsrSpare3LiodNr; - UINT32 DcfgCcsrSpare4LiodNr; - UINT8 Res5a0[0x600-0x5a0]; - UINT32 DcfgCcsrPblSr; - UINT32 PamuBypENr; - UINT32 DmaCr1; - UINT8 Res60c[0x610-0x60c]; - UINT32 DcfgCcsrGenSr1; - UINT32 DcfgCcsrGenSr2; - UINT32 DcfgCcsrGenSr3; - UINT32 DcfgCcsrGenSr4; - UINT32 DcfgCcsrGenCr1; - UINT32 DcfgCcsrGenCr2; - UINT32 DcfgCcsrGenCr3; - UINT32 DcfgCcsrGenCr4; - UINT32 DcfgCcsrGenCr5; - UINT32 DcfgCcsrGenCr6; - UINT32 DcfgCcsrGenCr7; - UINT8 Res63c[0x658-0x63c]; - UINT32 DcfgCcsrcGenSr1; - UINT32 DcfgCcsrcGenSr0; - UINT8 Res660[0x678-0x660]; - UINT32 DcfgCcsrcGenCr1; - UINT32 DcfgCcsrcGenCr0; - UINT8 Res680[0x700-0x680]; - UINT32 DcfgCcsrSrIoPstecr; - UINT32 DcfgCcsrDcsrCr; - UINT8 Res708[0x740-0x708]; /* add more registers when needed */ - UINT32 TpItyp[64]; /* Topology Initiator Type Register */ - struct { - UINT32 Upper; - UINT32 Lower; - } TpCluster[16]; - UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */ - UINT32 DcfgCcsrQmBmWarmRst; - UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */ - UINT32 DcfgCcsrReserved0; - UINT32 DcfgCcsrReserved1; } CCSR_GUR; =20 -/* Supplemental Configuration Unit */ -typedef struct { - UINT8 Res000[0x070-0x000]; - UINT32 Usb1Prm1Cr; - UINT32 Usb1Prm2Cr; - UINT32 Usb1Prm3Cr; - UINT32 Usb2Prm1Cr; - UINT32 Usb2Prm2Cr; - UINT32 Usb2Prm3Cr; - UINT32 Usb3Prm1Cr; - UINT32 Usb3Prm2Cr; - UINT32 Usb3Prm3Cr; - UINT8 Res094[0x100-0x094]; - UINT32 Usb2Icid; - UINT32 Usb3Icid; - UINT8 Res108[0x114-0x108]; - UINT32 DmaIcid; - UINT32 SataIcid; - UINT32 Usb1Icid; - UINT32 QeIcid; - UINT32 SdhcIcid; - UINT32 EdmaIcid; - UINT32 EtrIcid; - UINT32 Core0SftRst; - UINT32 Core1SftRst; - UINT32 Core2SftRst; - UINT32 Core3SftRst; - UINT8 Res140[0x158-0x140]; - UINT32 AltCBar; - UINT32 QspiCfg; - UINT8 Res160[0x180-0x160]; - UINT32 DmaMcr; - UINT8 Res184[0x188-0x184]; - UINT32 GicAlign; - UINT32 DebugIcid; - UINT8 Res190[0x1a4-0x190]; - UINT32 SnpCnfGcr; -#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31 -#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30 -#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23 -#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22 -#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21 -#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20 -#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15 -#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16 -#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13 -#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14 - UINT8 Res1a8[0x1ac-0x1a8]; - UINT32 IntpCr; - UINT8 Res1b0[0x204-0x1b0]; - UINT32 CoreSrEnCr; - UINT8 Res208[0x220-0x208]; - UINT32 RvBar00; - UINT32 RvBar01; - UINT32 RvBar10; - UINT32 RvBar11; - UINT32 RvBar20; - UINT32 RvBar21; - UINT32 RvBar30; - UINT32 RvBar31; - UINT32 LpmCsr; - UINT8 Res244[0x400-0x244]; - UINT32 QspIdQScr; - UINT32 EcgTxcMcr; - UINT32 SdhcIoVSelCr; - UINT32 RcwPMuxCr0; - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT - *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS - Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/ -#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333 - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT - *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL - Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/ -#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300 - UINT32 UsbDrvVBusSelCr; -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003 - UINT32 UsbPwrFaultSelCr; -#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000 -#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001 -#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002 -#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4 -#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2 -#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0 - UINT32 UsbRefclkSelcr1; - UINT32 UsbRefclkSelcr2; - UINT32 UsbRefclkSelcr3; - UINT8 Res424[0x600-0x424]; - UINT32 ScratchRw[4]; - UINT8 Res610[0x680-0x610]; - UINT32 CoreBCr; - UINT8 Res684[0x1000-0x684]; - UINT32 Pex1MsiIr; - UINT32 Pex1MsiR; - UINT8 Res1008[0x2000-0x1008]; - UINT32 Pex2; - UINT32 Pex2MsiR; - UINT8 Res2008[0x3000-0x2008]; - UINT32 Pex3MsiIr; - UINT32 Pex3MsiR; -} CCSR_SCFG; - -#define USB_TXVREFTUNE 0x9 -#define USB_SQRXTUNE 0xFC7FFFFF -#define USB_PCSTXSWINGFULL 0x47 -#define USB_PHY_RX_EQ_VAL_1 0x0000 -#define USB_PHY_RX_EQ_VAL_2 0x8000 -#define USB_PHY_RX_EQ_VAL_3 0x8003 -#define USB_PHY_RX_EQ_VAL_4 0x800b - -/*USB_PHY_SS memory map*/ -typedef struct { - UINT16 IpIdcodeLo; - UINT16 SupIdcodeHi; - UINT8 Res4[0x0006-0x0004]; - UINT16 RtuneDebug; - UINT16 RtuneStat; - UINT16 SupSsPhase; - UINT16 SsFreq; - UINT8 ResE[0x0020-0x000e]; - UINT16 Ateovrd; - UINT16 MpllOvrdInLo; - UINT8 Res24[0x0026-0x0024]; - UINT16 SscOvrdIn; - UINT8 Res28[0x002A-0x0028]; - UINT16 LevelOvrdIn; - UINT8 Res2C[0x0044-0x002C]; - UINT16 ScopeCount; - UINT8 Res46[0x0060-0x0046]; - UINT16 MpllLoopCtl; - UINT8 Res62[0x006C-0x0062]; - UINT16 SscClkCntrl; - UINT8 Res6E[0x2002-0x006E]; - UINT16 Lane0TxOvrdInHi; - UINT16 Lane0TxOvrdDrvLo; - UINT8 Res2006[0x200C-0x2006]; - UINT16 Lane0RxOvrdInHi; - UINT8 Res200E[0x2022-0x200E]; - UINT16 Lane0TxCmWaitTimeOvrd; - UINT8 Res2024[0x202A-0x2024]; - UINT16 Lane0TxLbertCtl; - UINT16 Lane0RxLbertCtl; - UINT16 Lane0RxLbertErr; - UINT8 Res2030[0x205A-0x2030]; - UINT16 Lane0TxAltBlock; -} CCSR_USB_PHY; - -/* Clocking */ -typedef struct { - struct { - UINT32 ClkCnCSr; /* core cluster n clock control status */ - UINT8 Res004[0x0c]; - UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */ - UINT8 Res014[0x0c]; - } ClkcSr[4]; - UINT8 Res040[0x780]; /* 0x100 */ - struct { - UINT32 PllCnGSr; - UINT8 Res804[0x1c]; - } PllCgSr[NUM_CC_PLLS]; - UINT8 Res840[0x1c0]; - UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */ - UINT8 Resa04[0x1fc]; - UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */ - UINT8 Resc04[0x1c]; - UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */ - UINT8 Resc24[0x3dc]; -} CCSR_CLOCK; - VOID GetSysInfo ( OUT SYS_INFO * diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/= Include/SocSerDes.h deleted file mode 100644 index 2d1c6f10f932..000000000000 --- a/Silicon/NXP/LS1043A/Include/SocSerDes.h +++ /dev/null @@ -1,51 +0,0 @@ -/** @file - The Header file of SerDes Module for LS1043A - - Copyright 2017-2019 NXP - - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef SOC_SERDES_H_ -#define SOC_SERDES_H_ - -#ifdef CHASSIS2 -#include -#endif - -SERDES_CONFIG SerDes1ConfigTbl[] =3D { - /* SerDes 1 */ - {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } }, - {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } }, - {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } }, - {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } }, - {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, - {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, - {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } }, - {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, - {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } }, - {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } }, - {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } }, - {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } }, - {0x9998, {Pcie1, Pcie2, Pcie3, Sata } }, - {0x6058, {Pcie1, Pcie1, Pcie2, Sata } }, - {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } }, - {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } }, - {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } }, - {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6= } }, - {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } }, - {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } }, - {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } }, - {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } }, - {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } }, - {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dt= sec6 }}, - {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } }, - {} -}; - -SERDES_CONFIG *SerDesConfigTbl[] =3D { - SerDes1ConfigTbl -}; - -#endif /* SOC_SERDES_H_ */ diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/= SocLib/NxpChassis.h index a11acf71563e..836df103f80f 100644 --- a/Silicon/NXP/Library/SocLib/NxpChassis.h +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h @@ -10,58 +10,6 @@ #ifndef NXP_CHASSIS_H_ #define NXP_CHASSIS_H_ =20 -#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */ -#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */ -#define TP_ITYP_TYPE_ARM 0x0 -#define TP_ITYP_TYPE_PPC 0x1 -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ -#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Versi= on */ -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ -#define TP_INIT_PER_CLUSTER 4 - -#define TY_ITYP_VERSION_A7 0x1 -#define TY_ITYP_VERSION_A53 0x2 -#define TY_ITYP_VERSION_A57 0x3 -#define TY_ITYP_VERSION_A72 0x4 - -#define CPU_TYPE_ENTRY(N, V, NC) { .Name =3D #N, .SocVer =3D SVR_##V, .N= umCores =3D (NC)} - -#define SVR_WO_E 0xFFFFFE -#define SVR_LS1043A 0x879200 -#define SVR_LS1046A 0x870700 -#define SVR_LS2088A 0x870901 - -#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) -#define SVR_MINOR(svr) (((svr) >> 0) & 0xf) -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) - -#define MHZ 1000000 - -typedef struct { - CHAR8 *Name; - UINT32 SocVer; - UINT32 NumCores; -} CPU_TYPE; - -typedef struct { - UINTN CpuClk; /* CPU clock in Hz! */ - UINTN BusClk; - UINTN MemClk; - UINTN PciClk; - UINTN SdhcClk; -} SOC_CLOCK_INFO; - -/* - * Initialize Clock structure - */ -VOID -ClockInit ( - VOID - ); - /* * Setup SMMU in bypass mode * and also set its pagesize @@ -71,42 +19,4 @@ SmmuInit ( VOID ); =20 -UINT32 -InitiatorType ( - IN UINT32 Cluster, - IN UINTN InitId - ); - -/* - * Return the mask for number of cores on this SOC. - */ -UINT32 -CpuMask ( - VOID - ); - -/* - * Return the number of cores on this SOC. - */ -UINTN -CpuNumCores ( - VOID - ); - -/* - * Return the type of initiator for core/hardware accelerator for given co= re index. - */ -UINTN -QoriqCoreToType ( - IN UINTN Core - ); - -/* - * Return the cluster of initiator for core/hardware accelerator for give= n core index. - */ -INT32 -QoriqCoreToCluster ( - IN UINTN Core - ); - #endif /* NXP_CHASSIS_H_ */ diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index adca7b8dd413..847331a63152 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -25,16 +25,6 @@ #include #include "NxpChassis.h" =20 -/* - * Structure to list available SOCs. - * Name, Soc Version, Number of Cores - */ -STATIC CPU_TYPE mCpuTypeList[] =3D { - CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), - CPU_TYPE_ENTRY (LS1046A, LS1046A, 4), - CPU_TYPE_ENTRY (LS2088A, LS2088A, 8), -}; - UINT32 EFIAPI GurRead ( @@ -48,162 +38,6 @@ GurRead ( } } =20 -/* - * Return the type of initiator (core or hardware accelerator) - */ -UINT32 -InitiatorType ( - IN UINT32 Cluster, - IN UINTN InitId - ) -{ - CCSR_GUR *GurBase; - UINT32 Idx; - UINT32 Type; - - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - Idx =3D (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK; - Type =3D GurRead ((UINTN)&GurBase->TpItyp[Idx]); - - if (Type & TP_ITYP_AV_MASK) { - return Type; - } - - return 0; -} - -/* - * Return the mask for number of cores on this SOC. - */ -UINT32 -CpuMask ( - VOID - ) -{ - CCSR_GUR *GurBase; - UINTN ClusterIndex; - UINTN Count; - UINT32 Cluster; - UINT32 Type; - UINT32 Mask; - UINTN InitiatorIndex; - - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - ClusterIndex =3D 0; - Count =3D 0; - Mask =3D 0; - - do { - Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); - for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { - Type =3D InitiatorType (Cluster, InitiatorIndex); - if (Type) { - if (TP_ITYP_TYPE_MASK (Type) =3D=3D TP_ITYP_TYPE_ARM) { - Mask |=3D 1 << Count; - } - Count++; - } - } - ClusterIndex++; - } while (CHECK_CLUSTER (Cluster)); - - return Mask; -} - -/* - * Return the number of cores on this SOC. - */ -UINTN -CpuNumCores ( - VOID - ) -{ - UINTN Count; - UINTN Num; - - Count =3D 0; - Num =3D CpuMask (); - - while (Num) { - Count +=3D Num & 1; - Num >>=3D 1; - } - - return Count; -} - -/* - * Return core's cluster - */ -INT32 -QoriqCoreToCluster ( - IN UINTN Core - ) -{ - CCSR_GUR *GurBase; - UINTN ClusterIndex; - UINTN Count; - UINT32 Cluster; - UINT32 Type; - UINTN InitiatorIndex; - - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - ClusterIndex =3D 0; - Count =3D 0; - do { - Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); - for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { - Type =3D InitiatorType (Cluster, InitiatorIndex); - if (Type) { - if (Count =3D=3D Core) { - return ClusterIndex; - } - Count++; - } - } - ClusterIndex++; - } while (CHECK_CLUSTER (Cluster)); - - return -1; // cannot identify the cluster -} - -/* - * Return the type of core i.e. A53, A57 etc of inputted - * core number. - */ -UINTN -QoriqCoreToType ( - IN UINTN Core - ) -{ - CCSR_GUR *GurBase; - UINTN ClusterIndex; - UINTN Count; - UINT32 Cluster; - UINT32 Type; - UINTN InitiatorIndex; - - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - ClusterIndex =3D 0; - Count =3D 0; - - do { - Cluster =3D GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); - for (InitiatorIndex =3D 0; InitiatorIndex < TP_INIT_PER_CLUSTER; Initi= atorIndex++) { - Type =3D InitiatorType (Cluster, InitiatorIndex); - if (Type) { - if (Count =3D=3D Core) { - return Type; - } - Count++; - } - } - ClusterIndex++; - } while (CHECK_CLUSTER (Cluster)); - - return EFI_NOT_FOUND; /* cannot identify the cluster */ -} - /* * Return system bus frequency */ @@ -219,21 +53,6 @@ GetBusFrequency ( return SocSysInfo.FreqSystemBus; } =20 -/* - * Return SDXC bus frequency - */ -UINT64 -GetSdxcFrequency ( - VOID - ) -{ - SYS_INFO SocSysInfo; - - GetSysInfo (&SocSysInfo); - - return SocSysInfo.FreqSdhc; -} - /* * Setup SMMU in bypass mode * and also set its pagesize @@ -256,33 +75,6 @@ SmmuInit ( MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); } =20 -/* - * Return current Soc Name form mCpuTypeList - */ -CHAR8 * -GetSocName ( - VOID - ) -{ - UINT8 Count; - UINTN Svr; - UINTN Ver; - CCSR_GUR *GurBase; - - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - - Svr =3D GurRead ((UINTN)&GurBase->Svr); - Ver =3D SVR_SOC_VER (Svr); - - for (Count =3D 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) =3D=3D Ver) { - return (CHAR8 *)mCpuTypeList[Count].Name; - } - } - - return NULL; -} - UINTN GetDramSize ( IN VOID diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index 687a1d940066..d992e53546f4 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -32,38 +32,14 @@ GetSysInfo ( ) { CCSR_GUR *GurBase; - CCSR_CLOCK *ClkBase; - UINTN CpuIndex; - UINT32 TempRcw; - UINT32 CPllSel; - UINT32 CplxPll; - CONST UINT8 CoreCplxPll[8] =3D { - [0] =3D 0, /* CC1 PPL / 1 */ - [1] =3D 0, /* CC1 PPL / 2 */ - [4] =3D 1, /* CC2 PPL / 1 */ - [5] =3D 1, /* CC2 PPL / 2 */ - }; - - CONST UINT8 CoreCplxPllDivisor[8] =3D { - [0] =3D 1, /* CC1 PPL / 1 */ - [1] =3D 2, /* CC1 PPL / 2 */ - [4] =3D 1, /* CC2 PPL / 1 */ - [5] =3D 2, /* CC2 PPL / 2 */ - }; - - UINTN PllCount; - UINTN FreqCPll[NUM_CC_PLLS]; - UINTN PllRatio[NUM_CC_PLLS]; UINTN SysClk; =20 GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - ClkBase =3D (VOID *)PcdGet64 (PcdClkBaseAddr); SysClk =3D CLK_FREQ; =20 SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); =20 PtrSysInfo->FreqSystemBus =3D SysClk; - PtrSysInfo->FreqDdrBus =3D SysClk; =20 // // selects the platform clock:SYSCLK ratio and calculate @@ -72,61 +48,6 @@ GetSysInfo ( PtrSysInfo->FreqSystemBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; - // - // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency - // - PtrSysInfo->FreqDdrBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> - CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & - CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; - - for (PllCount =3D 0; PllCount < NUM_CC_PLLS; PllCount++) { - PllRatio[PllCount] =3D (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].Pl= lCnGSr) >> 1) & 0xff; - if (PllRatio[PllCount] > 4) { - FreqCPll[PllCount] =3D SysClk * PllRatio[PllCount]; - } else { - FreqCPll[PllCount] =3D PtrSysInfo->FreqSystemBus * PllRatio[PllCount= ]; - } - } - - // - // Calculate Core frequency - // - for (CpuIndex =3D 0; CpuIndex < MAX_CPUS; CpuIndex++) { - CPllSel =3D (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 2= 7) & 0xf; - CplxPll =3D CoreCplxPll[CPllSel]; - - PtrSysInfo->FreqProcessor[CpuIndex] =3D FreqCPll[CplxPll] / CoreCplxPl= lDivisor[CPllSel]; - } - - // - // Calculate FMAN frequency - // - TempRcw =3D GurRead ((UINTN)&GurBase->RcwSr[7]); - switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { - case 2: - PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 2; - break; - case 3: - PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 3; - break; - case 4: - PtrSysInfo->FreqFman[0] =3D FreqCPll[0] / 4; - break; - case 5: - PtrSysInfo->FreqFman[0] =3D PtrSysInfo->FreqSystemBus; - break; - case 6: - PtrSysInfo->FreqFman[0] =3D FreqCPll[1] / 2; - break; - case 7: - PtrSysInfo->FreqFman[0] =3D FreqCPll[1] / 3; - break; - default: - DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n")); - break; - } - PtrSysInfo->FreqSdhc =3D PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatform= FreqDiv); - PtrSysInfo->FreqQman =3D PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatform= FreqDiv); } =20 /** diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocL= ib/SerDes.c deleted file mode 100644 index b9909d922138..000000000000 --- a/Silicon/NXP/Library/SocLib/SerDes.c +++ /dev/null @@ -1,268 +0,0 @@ -/** SerDes.c - Provides the basic interfaces for SerDes Module - - Copyright 2017-2019 NXP - - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifdef CHASSIS2 -#include -#include -#elif CHASSIS3 -#include -#include -#endif -#include -#include -#include - -/** - Function to get serdes Lane protocol corresponding to - serdes protocol. - - @param SerDes Serdes number. - @param Cfg Serdes Protocol. - @param Lane Serdes Lane number. - - @return Serdes Lane protocol. - -**/ -STATIC -SERDES_PROTOCOL -GetSerDesPrtcl ( - IN INTN SerDes, - IN INTN Cfg, - IN INTN Lane - ) -{ - SERDES_CONFIG *Config; - - if (SerDes >=3D ARRAY_SIZE (SerDesConfigTbl)) { - return 0; - } - - Config =3D SerDesConfigTbl[SerDes]; - while (Config->Protocol) { - if (Config->Protocol =3D=3D Cfg) { - return Config->SrdsLane[Lane]; - } - Config++; - } - - return EFI_SUCCESS; -} - -/** - Function to check if inputted protocol is a valid serdes protocol. - - @param SerDes Serdes number. - @param Prtcl Serdes Protocol to be verified. - - @return EFI_INVALID_PARAMETER Input parameter in invalid. - @return EFI_NOT_FOUND Serdes Protocol not a valid protocol. - @return EFI_SUCCESS Serdes Protocol is a valid protocol. - -**/ -STATIC -EFI_STATUS -CheckSerDesPrtclValid ( - IN INTN SerDes, - IN UINT32 Prtcl - ) -{ - SERDES_CONFIG *Config; - INTN Cnt; - - if (SerDes >=3D ARRAY_SIZE (SerDesConfigTbl)) { - return EFI_INVALID_PARAMETER; - } - - Config =3D SerDesConfigTbl[SerDes]; - while (Config->Protocol) { - if (Config->Protocol =3D=3D Prtcl) { - DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", = Prtcl)); - break; - } - Config++; - } - - if (!Config->Protocol) { - return EFI_NOT_FOUND; - } - - for (Cnt =3D 0; Cnt < SRDS_MAX_LANES; Cnt++) { - if (Config->SrdsLane[Cnt] !=3D None) { - return EFI_SUCCESS; - } - } - - return EFI_NOT_FOUND; -} - -/** - Function to fill serdes map information. - - @param Srds Serdes number. - @param SerdesProtocolMask Serdes Protocol Mask. - @param SerdesProtocolShift Serdes Protocol shift value. - @param SerDesPrtclMap Pointer to Serdes Protocol map. - -**/ -STATIC -VOID -LSSerDesMap ( - IN UINT32 Srds, - IN UINT32 SerdesProtocolMask, - IN UINT32 SerdesProtocolShift, - OUT UINT64 *SerDesPrtclMap - ) -{ - CCSR_GUR *Gur; - UINT32 SrdsProt; - INTN Lane; - UINT32 Flag; - - Gur =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - *SerDesPrtclMap =3D 0x0; - Flag =3D 0; - - SrdsProt =3D GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolM= ask; - SrdsProt >>=3D SerdesProtocolShift; - - DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n", - Srds + 1, SrdsProt, SrdsProt)); - - if (EFI_SUCCESS !=3D CheckSerDesPrtclValid (Srds, SrdsProt)) { - DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] =3D 0x%x is not valid\n", - Srds + 1, SrdsProt)); - Flag++; - } - - for (Lane =3D 0; Lane < SRDS_MAX_LANES; Lane++) { - SERDES_PROTOCOL LanePrtcl =3D GetSerDesPrtcl (Srds, SrdsProt, Lane); - if (LanePrtcl >=3D SerdesPrtclCount) { - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)= ); - Flag++; - } else { - *SerDesPrtclMap |=3D (1u << LanePrtcl); - } - } - - if (Flag) { - DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n")); - } else { - DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n")); - } -} - -/** - Get lane protocol on provided serdes lane and execute callback function. - - @param Srds Serdes number. - @param SerdesProtocolMask Mask to get Serdes Protocol for Srds - @param SerdesProtocolShift Shift value to get Serdes Protocol for S= rds. - @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol - @param Arg Pointer to Arguments to be passed to cal= lback function. - -**/ -STATIC -VOID -SerDesInstanceProbeLanes ( - IN UINT32 Srds, - IN UINT32 SerdesProtocolMask, - IN UINT32 SerdesProtocolShift, - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, - IN VOID *Arg - ) -{ - - CCSR_GUR *Gur; - UINT32 SrdsProt; - INTN Lane; - - Gur =3D (VOID *)PcdGet64 (PcdGutsBaseAddr);; - - SrdsProt =3D GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolM= ask; - SrdsProt >>=3D SerdesProtocolShift; - - /* - * Invoke callback for all lanes in the SerDes instance: - */ - for (Lane =3D 0; Lane < SRDS_MAX_LANES; Lane++) { - SERDES_PROTOCOL LanePrtcl =3D GetSerDesPrtcl (Srds, SrdsProt, Lane); - if ((LanePrtcl >=3D SerdesPrtclCount) || (LanePrtcl < None)) { - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)= ); - } else if (LanePrtcl !=3D None) { - SerDesLaneProbeCallback (LanePrtcl, Arg); - } - } -} - -/** - Probe all serdes lanes for lane protocol and execute provided callback f= unction. - - @param SerDesLaneProbeCallback Pointer Callback function to be called f= or Lane protocol - @param Arg Pointer to Arguments to be passed to cal= lback function. - -**/ -VOID -SerDesProbeLanes ( - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, - IN VOID *Arg - ) -{ - SerDesInstanceProbeLanes (Srds1, - RCWSR_SRDS1_PRTCL_MASK, - RCWSR_SRDS1_PRTCL_SHIFT, - SerDesLaneProbeCallback, - Arg); - - if (PcdGetBool (PcdSerdes2Enabled)) { - SerDesInstanceProbeLanes (Srds2, - RCWSR_SRDS2_PRTCL_MASK, - RCWSR_SRDS2_PRTCL_SHIFT, - SerDesLaneProbeCallback, - Arg); - } -} - -/** - Function to return Serdes protocol map for all serdes available on board. - - @param SerDesPrtclMap Pointer to Serdes protocl map. - -**/ -VOID -GetSerdesProtocolMaps ( - OUT UINT64 *SerDesPrtclMap - ) -{ - LSSerDesMap (Srds1, - RCWSR_SRDS1_PRTCL_MASK, - RCWSR_SRDS1_PRTCL_SHIFT, - SerDesPrtclMap); - - if (PcdGetBool (PcdSerdes2Enabled)) { - LSSerDesMap (Srds2, - RCWSR_SRDS2_PRTCL_MASK, - RCWSR_SRDS2_PRTCL_SHIFT, - SerDesPrtclMap); - } - -} - -BOOLEAN -IsSerDesLaneProtocolConfigured ( - IN UINT64 SerDesPrtclMap, - IN SERDES_PROTOCOL Device - ) -{ - if ((Device >=3D SerdesPrtclCount) || (Device < None)) { - ASSERT ((Device > None) && (Device < SerdesPrtclCount)); - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Devic= e)); - } - - return (SerDesPrtclMap & (1u << Device)) !=3D 0 ; -} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:27 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 09/24] Silicon/NXP: Remove unnecessary PCDs Date: Fri, 1 May 2020 11:19:40 +0530 Message-ID: <20200501054955.13025-10-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:24 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: cb9a645c-cf7a-4aec-7327-08d7ecca85d4 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: 3RAGWYaDsTZmVPJdd6FzdIOwx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225890; bh=PyhlgFKrBkrjaHdWYbgmxvWUD8QAY4APjN/88AIhazg=; h=Content-Type:Date:From:Reply-To:Subject:To; b=gXAq7zKeLl/nOK44Eyk9qyIiTaKF07ZST4agciyurXRuSqRlDqkjQtUK1Z2AXfushIL L1xLIEbJDyehJb05cYkO1ptRrDr2RUtwE5dhwoC6+dwzLR+s4QIGPOSDf3mc69blpPVKn rHGToUuBAAWfLZp/1FMYl3k59wKblauEnrE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal The memory map of an SOC is fixed in hardware. it doesn't change with platform that uses SOC. So, there is no need to keep PCDs for these values and we can use macros for these in SOC header file. Any Platform using the SOC, can make use of the SOC header file. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Silicon/NXP/NxpQoriqLs.dec | 47 ---= --------- Silicon/NXP/LS1043A/LS1043A.dsc.inc | 26 ---= ---- Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 10 +-- Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 21 +--= --- Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 - Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 + Silicon/NXP/LS1043A/Include/Soc.h | 44 +++= ++++++++ Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c | 15 ++-- Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 79 +++= ++++++----------- Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +- 10 files changed, 97 insertions(+), 150 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index bc604e586283..841d403f6f10 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -22,53 +22,6 @@ gNxpNonDiscoverableI2cMasterGuid =3D { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e= , 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}} =20 [PcdsFixedAtBuild.common] - # - # Pcds for I2C Controller - # - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001 - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002 - - # - # Pcds for base address and size - # - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100 - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103 - gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105 - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106 - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107 - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108 - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109 - gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A - gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B - gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C - gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110 - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119 - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122 - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123 - - # - # IFC PCDs - # - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193 - # # Platform PCDs # diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc index f6ada08dad9d..7690e4caa593 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -26,32 +26,6 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 =20 - # - # CCSR Address Space and other attached Memories - # - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 - # # Big Endian IPs # diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf= b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf index d689cf4db58e..038d48949a39 100644 --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf @@ -2,7 +2,7 @@ # # Component description file for LS1043 DXE platform driver. # -# Copyright 2018-2019 NXP +# Copyright 2018-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -21,9 +21,10 @@ =20 [Packages] ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec + Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] @@ -43,10 +44,5 @@ gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES =20 -[FixedPcd] - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController - [Depex] TRUE diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf index f7ae74afc6ca..7563a1c43630 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -1,7 +1,7 @@ # @file # # Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. -# Copyright 2017, 2019 NXP +# Copyright 2017, 2019-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -19,6 +19,7 @@ ArmPlatformPkg/ArmPlatformPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec + Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] @@ -35,21 +36,3 @@ =20 [FixedPcd] gArmTokenSpaceGuid.PcdArmPrimaryCore - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index f75a8d19f5a5..b7c7fc78cc8f 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -36,5 +36,4 @@ [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Ch= assis2/NxpSoc.h index 74330b6205e7..6812beafe447 100644 --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h @@ -12,6 +12,8 @@ =20 #define CLK_FREQ 100000000 =20 +#define CHASSIS2_DCFG_ADDRESS 0x1EE0000 + /* SMMU Defintions */ #define SMMU_BASE_ADDR 0x09000000 #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Includ= e/Soc.h new file mode 100644 index 000000000000..441871757d67 --- /dev/null +++ b/Silicon/NXP/LS1043A/Include/Soc.h @@ -0,0 +1,44 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SOC_H__ +#define SOC_H__ + +/** + Soc Memory Map +**/ +#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000 +#define LS1043A_DRAM0_SIZE SIZE_2GB +#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000 +#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB + +#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000 +#define LS1043A_CCSR_SIZE 0xF000000 + +#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000 +#define LS1043A_IFC0_SIZE SIZE_512MB +#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000 +#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB + +#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000 +#define LS1043A_QSPI_SIZE SIZE_512MB + +#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000 +#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB +#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000 +#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB + +#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000 +#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000 +#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000 +#define LS1043A_PCI_SIZE SIZE_32GB + +#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000 +#define LS1043A_I2C_SIZE 0x10000 +#define LS1043A_I2C_NUM_CONTROLLERS 4 + +#endif // SOC_H__ diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b= /Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c index f89dcdeff3c1..62c400eb1a58 100644 --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c @@ -1,7 +1,7 @@ /** @file LS1043 DXE platform driver. =20 - Copyright 2018-2019 NXP + Copyright 2018-2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include =20 @@ -22,7 +23,7 @@ typedef struct { UINT8 EndDesc; } ADDRESS_SPACE_DESCRIPTOR; =20 -STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cControlle= r)]; +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS]; =20 STATIC EFI_STATUS @@ -65,19 +66,19 @@ PopulateI2cInformation ( { UINT32 Index; =20 - for (Index =3D 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) { + for (Index =3D 0; Index < ARRAY_SIZE (mI2cDesc); Index++) { mI2cDesc[Index].StartDesc.Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; mI2cDesc[Index].StartDesc.Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCR= IPTOR) - 3; mI2cDesc[Index].StartDesc.ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; mI2cDesc[Index].StartDesc.GenFlag =3D 0; mI2cDesc[Index].StartDesc.SpecificFlag =3D 0; mI2cDesc[Index].StartDesc.AddrSpaceGranularity =3D 32; - mI2cDesc[Index].StartDesc.AddrRangeMin =3D FixedPcdGet64 (PcdI2c0BaseA= ddr) + - (Index * FixedPcdGet32 (PcdI2= cSize)); + mI2cDesc[Index].StartDesc.AddrRangeMin =3D LS1043A_I2C0_PHYS_ADDRESS + + (Index * LS1043A_I2C_SIZE); mI2cDesc[Index].StartDesc.AddrRangeMax =3D mI2cDesc[Index].StartDesc.A= ddrRangeMin + - FixedPcdGet32 (PcdI2cSize) - = 1; + LS1043A_I2C_SIZE - 1; mI2cDesc[Index].StartDesc.AddrTranslationOffset =3D 0; - mI2cDesc[Index].StartDesc.AddrLen =3D FixedPcdGet32 (PcdI2cSize); + mI2cDesc[Index].StartDesc.AddrLen =3D LS1043A_I2C_SIZE; =20 mI2cDesc[Index].EndDesc =3D ACPI_END_TAG_DESCRIPTOR; } diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c index c6c256da0727..f5fa308551aa 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -6,7 +6,7 @@ * * Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. -* Copyright 2017, 2019 NXP +* Copyright 2017, 2019-2020 NXP * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -16,7 +16,7 @@ #include #include #include -#include +#include =20 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 =20 @@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap ( { UINTN Index; ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; - DRAM_INFO DramInfo; =20 Index =3D 0; =20 @@ -51,24 +50,20 @@ ArmPlatformGetVirtualMemoryMap ( return; } =20 - if (GetDramBankInfo (&DramInfo)) { - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n")); - return; - } + VirtualMemoryTable[Index].PhysicalBase =3D LS1043A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_DRAM0_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK; =20 - - for (Index =3D 0; Index < DramInfo.NumOfDrams; Index++) { - // DRAM1 (Must be 1st entry) - VirtualMemoryTable[Index].PhysicalBase =3D DramInfo.DramRegion[Index].= BaseAddress; - VirtualMemoryTable[Index].VirtualBase =3D DramInfo.DramRegion[Index].= BaseAddress; - VirtualMemoryTable[Index].Length =3D DramInfo.DramRegion[Index].= Size; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK; - } + VirtualMemoryTable[Index].PhysicalBase =3D LS1043A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_DRAM1_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK; =20 // CCSR Space - VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); + VirtualMemoryTable[Index].PhysicalBase =3D LS1043A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_CCSR_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // IFC region 1 @@ -85,51 +80,51 @@ ArmPlatformGetVirtualMemoryMap ( // For write transactions from non-core masters (like system= DMA), the address // should be 16 byte aligned and the data size should be = multiple of 16 bytes. // - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 1BaseAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion1B= aseAddr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion1S= ize); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_IFC0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_IFC0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_IFC0_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // QMAN SWP - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQmanSwpBa= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQmanSwpBase= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQmanSwpSize= ); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_QMAN_SW_PORTAL_PHYS= _ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_QMAN_SW_PORTAL_PHYS_A= DDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_QMAN_SW_PORTAL_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; =20 // BMAN SWP - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdBmanSwpBa= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdBmanSwpBase= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdBmanSwpSize= ); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_BMAN_SW_PORTAL_PHYS= _ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_BMAN_SW_PORTAL_PHYS_A= DDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_QMAN_SW_PORTAL_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; =20 // IFC region 2 - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 2BaseAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion2B= aseAddr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion2S= ize); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_IFC1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_IFC1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_IFC1_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // PCIe1 - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp1Ba= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp1Base= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp1Base= Size); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_PCI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_PCI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_PCI_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // PCIe2 - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp2Ba= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp2Base= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp2Base= Size); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_PCI1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_PCI1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_PCI_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // PCIe3 - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp3Ba= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp3Base= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp3Base= Size); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_PCI2_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_PCI2_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_PCI_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // QSPI region - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQspiRegio= nBaseAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQspiRegionB= aseAddr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQspiRegionS= ize); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_QSPI_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_QSPI_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_QSPI_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; =20 // End of Table diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index d992e53546f4..98ca2e162f7b 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -34,7 +34,7 @@ GetSysInfo ( CCSR_GUR *GurBase; UINTN SysClk; =20 - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + GurBase =3D (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS; SysClk =3D CLK_FREQ; =20 SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:30 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 10/24] Silicon/NXP: Move dsc file Date: Fri, 1 May 2020 11:19:41 +0530 Message-ID: <20200501054955.13025-11-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:27 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 5f8984cc-314f-433b-1c0d-08d7ecca878c X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: sRksBg71kwNkph3OST3fqysdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225892; bh=QRcw3tqK/pFsUUy1xopsdywI3tD3wNqVkGW0Q87vFd0=; h=Content-Type:Date:From:Reply-To:Subject:To; b=OzmY2jWtWEkGNsczQxCDtc7LtRNEevgz9QH/iu474ofDUescYv2BjGW3EK8mQiilN7O +XC5tyyLt4SK+Ik63xASTOSEGbSq0gUYpQ3brmT2aPmFcQa2jSVVrYy0TfM08iI/AG61i MSYYpOI7S5/RTZAL81Bm3e+gw6R0n4Mfa7g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal As per convention being followed in edk2-platforms, keep the dec file and dsc file together. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change {Platform =3D> Silicon}/NXP/NxpQoriqLs.dsc.inc | 0 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.i= nc similarity index 100% rename from Platform/NXP/NxpQoriqLs.dsc.inc rename to Silicon/NXP/NxpQoriqLs.dsc.inc diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index 385b6e067e26..1975f2c4c52c 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -22,7 +22,7 @@ OUTPUT_DIRECTORY =3D Build/LS1043aRdbPkg FLASH_DEFINITION =3D Platform/NXP/LS1043aRdbPkg/LS1043aRdb= Pkg.fdf =20 -!include Platform/NXP/NxpQoriqLs.dsc.inc +!include Silicon/NXP/NxpQoriqLs.dsc.inc !include Silicon/NXP/LS1043A/LS1043A.dsc.inc =20 [LibraryClasses.common] --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:33 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 11/24] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Date: Fri, 1 May 2020 11:19:42 +0530 Message-ID: <20200501054955.13025-12-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: AmLvuAd4NFBcNdNxvLJjfcRox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225895; bh=BkvmpFat6q8OUJeYoVLDstyDPcqmfsSSC/KpoJZGKmo=; h=Content-Type:Date:From:Reply-To:Subject:To; b=uAmJkmAAxDa1JLSoPvagi1VWusY/wPpmebqLaxSMuLenbu2Dsb0PqS2bTqqgdg0Q9ZB Yabvo9UE2/1erCUpWesyrvRfcPwCJ9Rjv0UnJS43qAj305z+u1KjQrR6rknCvVrpqA7Ae GrtUGy7bNdae3ZZtYy0ZP/zsuOayfaAtN54= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Keep the names and location of files as mentioned in ArmPlatformPkg. This helps in porting the common changes (if any in future) easily. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc = | 2 +- Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib =3D> ArmPlatformLib}/ArmPl= atformLib.inf | 4 ++-- Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib =3D> ArmPlatformLib}/ArmPl= atformLib.c | 2 +- Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c =3D> ArmPl= atformLib/ArmPlatformLibMem.c} | 0 Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsHelper.S =3D> Ar= mPlatformLib/AArch64/ArmPlatformHelper.S} | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index 1975f2c4c52c..e5383aaf0cc5 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -26,7 +26,7 @@ !include Silicon/NXP/LS1043A/LS1043A.dsc.inc =20 [LibraryClasses.common] - ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatfor= mLib.inf + ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlat= formLib.inf RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf =20 [PcdsFixedAtBuild.common] diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf similarity index 89% rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.i= nf rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.= inf index 7563a1c43630..7a43ad86d183 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -27,8 +27,8 @@ SocLib =20 [Sources.common] - NxpQoriqLsHelper.S | GCC - NxpQoriqLsMem.c + AArch64/ArmPlatformHelper.S | GCC + ArmPlatformLibMem.c ArmPlatformLib.c =20 [Ppis] diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c similarity index 93% rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c index eac7d4aa4e47..718c71bf02eb 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -6,7 +6,7 @@ * * Copyright (c) 2011-2012, ARM Limited. All rights reserved. * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. -* Copyright 2017 NXP +* Copyright 2017, 2020 NXP * SPDX-License-Identifier: BSD-2-Clause-Patent * **/ diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c similarity index 100% rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibM= em.c diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelpe= r.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatform= Helper.S similarity index 88% rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper= .S rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlat= formHelper.S index 84ee8c9f9700..dfbf73675a2d 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatform= Helper.S @@ -1,7 +1,7 @@ # @file # # Copyright (c) 2012-2013, ARM Limited. All rights reserved. -# Copyright 2017 NXP +# Copyright 2017, 2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:36 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 12/24] Silicon/NXP: Move RAM retrieval from SocLib Date: Fri, 1 May 2020 11:19:43 +0530 Message-ID: <20200501054955.13025-13-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:33 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 6ebbbb2a-7392-4d42-6bfa-08d7ecca8b16 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: UmJ965zOK4vZwEjb6ZLnQLnLx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225899; bh=6zunXdroDUh2r0Kcta+zeV4KgkEe6S047L78cohSrQA=; h=Content-Type:Date:From:Reply-To:Subject:To; b=b/SLOsNbw5cUOPhy04Okq75Xlp6fwzDLNJj9Y7sADgAmK22Kdbi4qinH9BSbWGrzIfi wFAX1jcrdIuIHqzAnZF6WAYDwJ67lwU3R0ama9cZy6RpTnkNvnCanqDsE9IZG/gYi5a6Y yf9Iqy0a39CjGM9Uv4Kegcy4z2dBdNBk8Wk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal RAM retrieval using SMC commands is common to all Layerscape SOCs. Therefore, move it to common MemoryInit Pei Lib. Signed-off-by: Pankaj Bansal --- Notes: V4: - fixed line adds white space error in MemoryInitPeiLib.h - Added SMC_OK and SMC_UOK Macros to denote the return values from SMC calls - Added explanation for SMC_DRAM_BANK_INFO and DRAM_REGION_INFO in MemoryInitPeiLib.h - Modified GetDramSize to check for return value of SMC call against SMC_OK. Also added comments when returning 0 from this function - Modified GetDramRegionsInfo for loop and return values as per Leif's suggestion. Also added DEBUG_ERROR in case of return BUFFER_TOO_SMALL. - Added SMC_OK in GetDramRegionsInfo - Check for GetDramRegionsInfo return value in MemoryPeim - regios -> regions =20 V3: - sort headers alphabetically - Moved DRAM region retrieval and Total DRAM size retrieval to separate functions - Fixed MemoryPeim function description - Modified check on FoundSystemMem =3D TRUE to check the RAM region aga= inst MemoryPeim function input arguments UefiMemoryBase and UefiMemorySize - (!DramRegions[Index].Size) =3D> (DramRegions[Index].Size =3D=3D 0) - (FoundSystemMem) =3D> (FoundSystemMem =3D=3D TRUE) - Added explanation for starting for loop from the last DRAM region Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 7 +- Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 - Silicon/NXP/Include/DramInfo.h | 38 ---- Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h | 38 ++++ Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 205 +++++++++++++= +++---- Silicon/NXP/Library/SocLib/Chassis.c | 67 ------- 6 files changed, 211 insertions(+), 145 deletions(-) diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silic= on/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf index a5bd39415def..ad2371115b17 100644 --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -18,7 +18,6 @@ [Sources] MemoryInitPeiLib.c =20 - [Packages] ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec @@ -30,6 +29,7 @@ [LibraryClasses] ArmMmuLib ArmPlatformLib + ArmSmcLib DebugLib HobLib PcdLib @@ -40,6 +40,11 @@ [FeaturePcd] gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob =20 +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index b7c7fc78cc8f..99d89498e0e2 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -20,7 +20,6 @@ Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] - ArmSmcLib BaseLib DebugLib IoAccessLib diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h deleted file mode 100644 index a934aaeff1f5..000000000000 --- a/Silicon/NXP/Include/DramInfo.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @file -* Header defining the structure for Dram Information -* -* Copyright 2019 NXP -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef DRAM_INFO_H_ -#define DRAM_INFO_H_ - -#include - -#define SMC_DRAM_BANK_INFO (0xC200FF12) - -typedef struct { - UINTN BaseAddress; - UINTN Size; -} DRAM_REGION_INFO; - -typedef struct { - UINT32 NumOfDrams; - UINT32 Reserved; - DRAM_REGION_INFO DramRegion[3]; -} DRAM_INFO; - -EFI_STATUS -GetDramBankInfo ( - IN OUT DRAM_INFO *DramInfo - ); - -VOID -UpdateDpaaDram ( - IN OUT DRAM_INFO *DramInfo - ); - -#endif /* DRAM_INFO_H_ */ diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon= /NXP/Library/MemoryInitPei/MemoryInitPeiLib.h new file mode 100644 index 000000000000..7a41f4d226f1 --- /dev/null +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h @@ -0,0 +1,38 @@ +/** @file +* +* Copyright 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef MEMORY_INIT_PEI_LIB_H_ +#define MEMORY_INIT_PEI_LIB_H_ + +#include + +// Specifies the Maximum regions onto which DDR memory can be mapped in +// a Platform +#define MAX_DRAM_REGIONS 3 + +// Unique SMC call to retrieve the total DDR RAM size installed in system +// and the SOC memory map regions to which DDR RAM is mapped +// This SMC call works in this way: +// x1 =3D -1 : return x0: SMC_OK, x1: total DDR Ram size +// x1 >=3D number of DRAM regions to which DDR RAM is mapped : return x0: = SMC_UNK +// 0 <=3D x1 < number of DRAM regions to which DDR RAM is mapped : return +// x0: SMC_OK, x1: Base address of DRAM region, +// x2: Size of DRAM region +#define SMC_DRAM_BANK_INFO (0xC200FF12) + +// Return values from SMC calls. return values are always in x0 +#define SMC_OK 0 +#define SMC_UNK -1 + +// Regions in SOC memory map to which DDR RAM is mapped. +typedef struct { + UINTN BaseAddress; + UINTN Size; +} DRAM_REGION_INFO; + +#endif // MEMORY_INIT_PEI_LIB_H_ diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon= /NXP/Library/MemoryInitPei/MemoryInitPeiLib.c index 3ea773678667..905d326893e5 100644 --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -12,13 +12,15 @@ =20 #include #include +#include #include #include #include #include #include =20 -#include +#include "MemoryInitPeiLib.h" + =20 VOID BuildMemoryTypeInformationHob ( @@ -44,22 +46,88 @@ InitMmu ( } } =20 -/*++ +STATIC +UINTN +GetDramSize ( + IN VOID + ) +{ + ARM_SMC_ARGS ArmSmcArgs; =20 -Routine Description: + ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; + ArmSmcArgs.Arg1 =3D -1; =20 + ArmCallSmc (&ArmSmcArgs); =20 + if (ArmSmcArgs.Arg0 =3D=3D SMC_OK) { + return ArmSmcArgs.Arg1; + } =20 -Arguments: + // return 0 means no DDR found. + return 0; +} =20 - FileHandle - Handle of the file being invoked. - PeiServices - Describes the list of possible PEI Services. +STATIC +EFI_STATUS +GetDramRegionsInfo ( + OUT DRAM_REGION_INFO *DramRegions, + IN UINT32 NumRegions + ) +{ + ARM_SMC_ARGS ArmSmcArgs; + UINT32 Index; + UINTN RemainingDramSize; + UINTN BaseAddress; + UINTN Size; =20 -Returns: + RemainingDramSize =3D GetDramSize (); + DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", RemainingDramSize)); =20 - Status - EFI_SUCCESS if the boot mode could be set + // Ensure Total Dram Size is valid + ASSERT (RemainingDramSize !=3D 0); =20 ---*/ + for (Index =3D 0; Index < NumRegions; Index++) { + ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; + ArmSmcArgs.Arg1 =3D Index; + + ArmCallSmc (&ArmSmcArgs); + + if (ArmSmcArgs.Arg0 =3D=3D SMC_OK) { + BaseAddress =3D ArmSmcArgs.Arg1; + Size =3D ArmSmcArgs.Arg2; + ASSERT (BaseAddress && Size); + + DramRegions[Index].BaseAddress =3D BaseAddress; + DramRegions[Index].Size =3D Size; + RemainingDramSize -=3D Size; + + DEBUG ((DEBUG_INFO, "DRAM Region[%d]: start 0x%lx, size 0x%lx\n", + Index, BaseAddress, Size)); + + if (RemainingDramSize =3D=3D 0) { + return EFI_SUCCESS; + } + } else { + break; + } + } + + DEBUG ((DEBUG_ERROR, "RemainingDramSize =3D %u !! Ensure that all DDR re= gions " + "have been accounted for\n", RemainingDramSize)); + + return EFI_BUFFER_TOO_SMALL; +} + +/** + Get the installed RAM information. + Initialize MMU and Memory HOBs (Resource Descriptor HOBs) + + @param[in] UefiMemoryBase Base address of region used by UEFI in + permanent memory + @param[in] UefiMemorySize Size of the region used by UEFI in permanent = memory + + @return EFI_SUCCESS Successfuly Initialize MMU and Memory HOBs. +**/ EFI_STATUS EFIAPI MemoryPeim ( @@ -67,11 +135,17 @@ MemoryPeim ( IN UINT64 UefiMemorySize ) { - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; - EFI_PEI_HOB_POINTERS NextHob; - BOOLEAN Found; - DRAM_INFO DramInfo; + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + INT32 Index; + UINTN BaseAddress; + UINTN Size; + UINTN Top; + DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS]; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + UINTN FdBase; + UINTN FdTop; + BOOLEAN FoundSystemMem; + EFI_STATUS Status; =20 // Get Virtual Memory Map from the Platform Library ArmPlatformGetVirtualMemoryMap (&MemoryTable); @@ -94,40 +168,95 @@ MemoryPeim ( EFI_RESOURCE_ATTRIBUTE_TESTED ); =20 - if (GetDramBankInfo (&DramInfo)) { - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n")); - return EFI_UNSUPPORTED; - } + FoundSystemMem =3D FALSE; + ZeroMem (DramRegions, sizeof (DramRegions)); =20 - while (DramInfo.NumOfDrams--) { - // - // Check if the resource for the main system memory has been declared - // - Found =3D FALSE; - NextHob.Raw =3D GetHobList (); - while ((NextHob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, = NextHob.Raw)) !=3D NULL) { - if ((NextHob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SY= STEM_MEMORY) && - (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >=3D NextH= ob.ResourceDescriptor->PhysicalStart) && - (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDes= criptor->ResourceLength <=3D - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo= .DramRegion[DramInfo.NumOfDrams].Size)) - { - Found =3D TRUE; - break; - } - NextHob.Raw =3D GET_NEXT_HOB (NextHob); + Status =3D GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions)); + ASSERT_EFI_ERROR (Status); + + FdBase =3D (UINTN)FixedPcdGet64 (PcdFdBaseAddress); + FdTop =3D FdBase + (UINTN)FixedPcdGet32 (PcdFdSize); + + // Declare memory regions to system + // The DRAM region info is sorted based on the RAM address is SOC memory= map. + // i.e. DramRegions[0] is at lower address, as compared to DramRegions[1= ]. + // The goal to start from last region is to find the topmost RAM region = that + // can contain UEFI DXE region i.e. PcdSystemMemoryUefiRegionSize. + // If UEFI were to allocate any reserved or runtime region, it would be + // allocated from topmost RAM region. + // This ensures that maximum amount of lower RAM (32 bit addresses) are = left + // for OS to allocate to devices that can only work with 32bit physical + // addresses. E.g. legacy devices that need to DMA to 32bit addresses. + for (Index =3D MAX_DRAM_REGIONS - 1; Index >=3D 0; Index--) { + if (DramRegions[Index].Size =3D=3D 0) { + continue; } =20 - if (!Found) { - // Reserved the memory space occupied by the firmware volume + BaseAddress =3D DramRegions[Index].BaseAddress; + Top =3D DramRegions[Index].BaseAddress + DramRegions[Index].Size; + + // EDK2 does not have the concept of boot firmware copied into DRAM. + // To avoid the DXE core to overwrite this area we must create a memory + // allocation HOB for the region, but this only works if we split off = the + // underlying resource descriptor as well. + if (FdBase >=3D BaseAddress && FdTop <=3D Top) { + // Update Size + Size =3D FdBase - BaseAddress; + if (Size) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + BaseAddress, + Size + ); + } + // create the System Memory HOB for the firmware BuildResourceDescriptorHob ( EFI_RESOURCE_SYSTEM_MEMORY, ResourceAttributes, - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress, - DramInfo.DramRegion[DramInfo.NumOfDrams].Size + FdBase, + PcdGet32 (PcdFdSize) ); + // Create the System Memory HOB for the remaining region (top of the= FD)s + Size =3D Top - FdTop; + if (Size) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FdTop, + Size + ); + }; + // Mark the memory covering the Firmware Device as boot services data + BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress), + FixedPcdGet32 (PcdFdSize), + EfiBootServicesData); + } else { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + DramRegions[Index].BaseAddress, + DramRegions[Index].Size + ); + } + + if (FoundSystemMem =3D=3D TRUE) { + continue; + } + + Size =3D DramRegions[Index].Size; + + if (FdBase >=3D BaseAddress && FdTop <=3D Top) { + Size -=3D (UINTN)FixedPcdGet32 (PcdFdSize); + } + + if ((UefiMemoryBase >=3D BaseAddress) && (Size >=3D UefiMemorySize)) { + FoundSystemMem =3D TRUE; } } =20 + ASSERT (FoundSystemMem =3D=3D TRUE); + // Build Memory Allocation Hob InitMmu (MemoryTable); =20 diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index 847331a63152..1ef99e8de25f 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -22,7 +22,6 @@ #include #include =20 -#include #include "NxpChassis.h" =20 UINT32 @@ -75,69 +74,3 @@ SmmuInit ( MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); } =20 -UINTN -GetDramSize ( - IN VOID - ) -{ - ARM_SMC_ARGS ArmSmcArgs; - - ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; - ArmSmcArgs.Arg1 =3D -1; - - ArmCallSmc (&ArmSmcArgs); - - if (ArmSmcArgs.Arg0) { - return 0; - } else { - return ArmSmcArgs.Arg1; - } -} - -EFI_STATUS -GetDramBankInfo ( - IN OUT DRAM_INFO *DramInfo - ) -{ - ARM_SMC_ARGS ArmSmcArgs; - UINT32 I; - UINTN DramSize; - - DramSize =3D GetDramSize (); - DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize)); - - // Ensure DramSize has been set - ASSERT (DramSize !=3D 0); - - I =3D 0; - - do { - ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; - ArmSmcArgs.Arg1 =3D I; - - ArmCallSmc (&ArmSmcArgs); - if (ArmSmcArgs.Arg0) { - if (I > 0) { - break; - } else { - ASSERT (ArmSmcArgs.Arg0 =3D=3D 0); - } - } - - DramInfo->DramRegion[I].BaseAddress =3D ArmSmcArgs.Arg1; - DramInfo->DramRegion[I].Size =3D ArmSmcArgs.Arg2; - - DramSize -=3D DramInfo->DramRegion[I].Size; - - DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", - I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size= )); - - I++; - } while (DramSize); - - DramInfo->NumOfDrams =3D I; - - DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDra= ms)); - - return EFI_SUCCESS; -} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:38 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 13/24] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs Date: Fri, 1 May 2020 11:19:44 +0530 Message-ID: <20200501054955.13025-14-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: UpF8BmNvoGptDhur6ezTTzc1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225902; bh=e2AqJcUkXufgZVi635POwwZVL0ctwiL4v3stJW8qydM=; h=Content-Type:Date:From:Reply-To:Subject:To; b=Q4KjEFOs4RIC87pcBs4rCS49ITMf8bkUp9sZoSI7i05+OKpJtI3Bw6bNmyXK3rXnBuW gmAEtHIK+NstAQSl43pqRhwqGiJFqhHr7JPiwOF7ZGPqGXDiUzPnNSIA9a4fz2yIG43py B3gkVQ82KOjI7IyR02PlqNXSX4UO9MxY5rA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal The SOC takes primary clocking input from the external signal (a clock generator on board). The input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Therefore, move the clock retrieval APIs to Platform Lib. The Input clock is retrieved from board components in Platform Lib, and passed on to SOC Lib APIs to get the correct clock for an IP (after PLL multiplication). Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - fixed line adds whitespace error in NxpPlatformGetClock.h =20 V3: - sorted NXP_IP_CLOCK enum alphabetically Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 + Silicon/NXP/Include/Library/SocLib.h | 44 ++= +++++++++++++++ Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 52 ++= ++++++++++++++++++ Silicon/NXP/LS1043A/Include/Soc.h | 11 ++= +++ Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 51 ++= +++++++++++++++++ Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 52 ++= ++++++++++++++++++ 6 files changed, 211 insertions(+) diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index 99d89498e0e2..3d38a7e58b91 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -17,6 +17,7 @@ ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Lib= rary/SocLib.h new file mode 100644 index 000000000000..fc4d786c710b --- /dev/null +++ b/Silicon/NXP/Include/Library/SocLib.h @@ -0,0 +1,44 @@ +/** @file + + Copyright 2020 NXP + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SOC_LIB_H__ +#define SOC_LIB_H__ + +#include +#include + +/** + Return the input clock frequency to an IP Module. + This function reads the RCW bits and calculates the PLL multiplier/divi= der + values to be applied to various IP modules. + If a module is disabled or doesn't exist on platform, then return zero. + + @param[in] BaseClock Base clock to which PLL multiplier/divider values= is + to be applied. + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] Args Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within the + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +SocGetClock ( + IN UINT64 BaseClock, + IN NXP_IP_CLOCK ClockType, + IN VA_LIST Args + ); + +#endif // SOC_LIB_H__ diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h b/Silicon/NXP/In= clude/Ppi/NxpPlatformGetClock.h new file mode 100644 index 000000000000..8431148acb9f --- /dev/null +++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h @@ -0,0 +1,52 @@ +/** @file +* +* Copyright 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef NXP_PLATFORM_PPI_H__ +#define NXP_PLATFORM_PPI_H__ + +#include + +typedef enum _NXP_IP_CLOCK { + NXP_CORE_CLOCK, + NXP_I2C_CLOCK, + NXP_SYSTEM_CLOCK, + NXP_UART_CLOCK +} NXP_IP_CLOCK; + +/** + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs + + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] ... Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within the + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +typedef +UINT64 +(EFIAPI * NXP_PLATFORM_GET_CLOCK)( + IN NXP_IP_CLOCK ClockType, + ... + ); + +typedef struct { + NXP_PLATFORM_GET_CLOCK PlatformGetClock; +} NXP_PLATFORM_GET_CLOCK_PPI; + +extern NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi; + +#endif // NXP_PLATFORM_PPI_H__ diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Includ= e/Soc.h index 441871757d67..e62de570da8a 100644 --- a/Silicon/NXP/LS1043A/Include/Soc.h +++ b/Silicon/NXP/LS1043A/Include/Soc.h @@ -8,6 +8,8 @@ #ifndef SOC_H__ #define SOC_H__ =20 +#include + /** Soc Memory Map **/ @@ -41,4 +43,13 @@ #define LS1043A_I2C_SIZE 0x10000 #define LS1043A_I2C_NUM_CONTROLLERS 4 =20 +#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS + +/** + Reset Control Word (RCW) Bits +**/ +#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 + +typedef CCSR_GUR LS1043A_DEVICE_CONFIG; + #endif // SOC_H__ diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c index 718c71bf02eb..7f5872a78cfc 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -12,10 +12,60 @@ **/ =20 #include +#include #include +#include =20 extern VOID SocInit (VOID); =20 +/** + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs + + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] ... Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. + if ClockType is NXP_CORE_CLOCK, then second argum= ent + is interpreted as cluster number and third argume= nt is + interpreted as core number (within the cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +EFIAPI +NxpPlatformGetClock( + IN UINT32 ClockType, + ... + ) +{ + UINT64 Clock; + VA_LIST Args; + + Clock =3D 0; + + VA_START (Args, ClockType); + + switch (ClockType) { + case NXP_SYSTEM_CLOCK: + Clock =3D 100 * 1000 * 1000; // 100 MHz + break; + case NXP_I2C_CLOCK: + case NXP_UART_CLOCK: + Clock =3D NxpPlatformGetClock (NXP_SYSTEM_CLOCK); + Clock =3D SocGetClock (Clock, ClockType, Args); + break; + default: + break; + } + + VA_END (Args); + + return Clock; +} + /** Return the current Boot Mode =20 @@ -69,6 +119,7 @@ PrePeiCoreGetMpCoreInfo ( } =20 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi =3D { NxpPlatformGetClock = }; =20 EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { { diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index 98ca2e162f7b..973ae630440b 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include =20 /** Calculate the frequency of various controllers and @@ -50,6 +52,56 @@ GetSysInfo ( CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; } =20 +/** + Return the input clock frequency to an IP Module. + This function reads the RCW bits and calculates the PLL multiplier/divi= der + values to be applied to various IP modules. + If a module is disabled or doesn't exist on platform, then return zero. + + @param[in] BaseClock Base clock to which PLL multiplier/divider values= is + to be applied. + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] Args Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within the + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +SocGetClock ( + IN UINT64 BaseClock, + IN NXP_IP_CLOCK ClockType, + IN VA_LIST Args + ) +{ + LS1043A_DEVICE_CONFIG *Dcfg; + UINT32 RcwSr; + UINT64 ReturnValue; + + ReturnValue =3D 0; + Dcfg =3D (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; + + switch (ClockType) { + case NXP_UART_CLOCK: + case NXP_I2C_CLOCK: + RcwSr =3D GurRead ((UINTN)&Dcfg->RcwSr[0]); + ReturnValue =3D BaseClock * SYS_PLL_RAT (RcwSr); + break; + default: + break; + } + + return ReturnValue; +} + /** Function to initialize SoC specific constructs **/ --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:41 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 14/24] Silicon/NXP: Use Clock retrieval PPI in modules Date: Fri, 1 May 2020 11:19:45 +0530 Message-ID: <20200501054955.13025-15-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: 5ZfFALkFNiVXyEJtxUU1MISPx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225905; bh=cSoxgaD6fyJt9IZSVyKCSok6fN7uGzkFrV5CvldeoG0=; h=Content-Type:Date:From:Reply-To:Subject:To; b=jV11Pmz5QVt+MRFvQtoeixga8fMxoksNm5C89ToJGLKtNareF20GfAxhHeVXzlwQGSs zJezh0Tv5RRMorZiPQBID2PzSu9uAtA517trmziEJza5EoZ+1aH/sWmF3YlaLWGRyzxLo Jic0RZRz4ANtNkpt0MWL2I3fomWKSNytLT4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Use NXP_PLATFORM_GET_CLOCK_PPI in various Layerscape IP modules. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - Added clock retrieval APIs to DUartPortLib Silicon/NXP/NxpQoriqLs.dec | 5 ---- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 -- Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 2 +- Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 5 ++-- Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 - Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 6 ---- Silicon/NXP/Include/Chassis2/NxpSoc.h | 9 ------ Silicon/NXP/Library/DUartPortLib/DUart.h | 8 +---- Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 3 +- Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 7 ++--- Silicon/NXP/Library/SocLib/Chassis.c | 15 ---------- Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 31 -------------------- 12 files changed, 9 insertions(+), 85 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 841d403f6f10..e61592b4fe61 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -22,11 +22,6 @@ gNxpNonDiscoverableI2cMasterGuid =3D { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e= , 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}} =20 [PcdsFixedAtBuild.common] - # - # Platform PCDs - # - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250 - # # Pcds to support Big Endian IPs # diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index e5383aaf0cc5..d486c9b36fab 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -39,8 +39,6 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 =20 - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 - # # RTC Pcds # diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2= cDxe/I2cDxe.inf index 867376044656..3bf7a8124fc6 100644 --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf @@ -25,13 +25,13 @@ =20 [LibraryClasses] ArmLib + ArmPlatformLib BaseMemoryLib DevicePathLib I2cLib IoLib MemoryAllocationLib PcdLib - SocLib TimerLib UefiBootServicesTableLib UefiDriverEntryPoint diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NX= P/Library/DUartPortLib/DUartPortLib.inf index 7a2fa619b027..b8a77ae05243 100644 --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf @@ -3,7 +3,7 @@ # Component description file for DUartPortLib module # # Copyright (c) 2013, Freescale Ltd. All rights reserved. -# Copyright 2017 NXP +# Copyright 2017, 2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,8 +20,8 @@ DUartPortLib.c =20 [LibraryClasses] + ArmPlatformLib PcdLib - SocLib =20 [Packages] MdeModulePkg/MdeModulePkg.dec @@ -31,4 +31,3 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index 3d38a7e58b91..bb15e0a3d710 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -36,4 +36,3 @@ [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.h index 88316f313380..7c4a306c16a0 100644 --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h @@ -37,12 +37,6 @@ typedef struct { NON_DISCOVERABLE_DEVICE *Dev; } NXP_I2C_MASTER; =20 -extern -UINT64 -GetBusFrequency ( - VOID - ); - EFI_STATUS NxpI2cInit ( IN EFI_HANDLE DriverBindingHandle, diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Ch= assis2/NxpSoc.h index 6812beafe447..3f00a2614131 100644 --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h @@ -27,10 +27,6 @@ #define SACR_PAGESIZE_MASK 0x00010000 #define IDR1_PAGESIZE_MASK 0x80000000 =20 -typedef struct { - UINTN FreqSystemBus; -} SYS_INFO; - /* Device Configuration and Pin Control */ typedef struct { UINT8 Res0[0x100-0x00]; @@ -39,11 +35,6 @@ typedef struct { #define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f } CCSR_GUR; =20 -VOID -GetSysInfo ( - OUT SYS_INFO * - ); - UINT32 EFIAPI GurRead ( diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library= /DUartPortLib/DUart.h index c71e2ce55d1d..aca7cd8d3f01 100644 --- a/Silicon/NXP/Library/DUartPortLib/DUart.h +++ b/Silicon/NXP/Library/DUartPortLib/DUart.h @@ -5,7 +5,7 @@ * * Copyright (c) 2011-2012, ARM Limited. All rights reserved. * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. -* Copyright 2017 NXP +* Copyright 2017, 2020 NXP * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -113,10 +113,4 @@ #define USCR 0x7 #define UDSR 0x10 =20 -extern -UINT64 -GetBusFrequency ( - VOID - ); - #endif /* DUART_H_ */ diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cD= xe/I2cDxe.c index a5aba47b3ed4..30804450d2b7 100644 --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include "I2cDxe.h" =20 @@ -51,7 +52,7 @@ SetBusFrequency ( =20 I2cBase =3D (UINTN)(I2c->Dev->Resources[0].AddrRangeMin); =20 - I2cClock =3D GetBusFrequency (); + I2cClock =3D gPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0); =20 I2cInitialize (I2cBase, I2cClock, *BusClockHertz); =20 diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/= Library/DUartPortLib/DUartPortLib.c index c3c738d3cca8..f9c2c44a4c3b 100644 --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c @@ -6,7 +6,7 @@ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.
Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. - Copyright 2017 NXP + Copyright 2017, 2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include "DUart.h" =20 @@ -169,10 +170,8 @@ CalculateBaudDivisor ( ) { UINTN DUartClk; - UINTN FreqSystemBus; =20 - FreqSystemBus =3D GetBusFrequency (); - DUartClk =3D FreqSystemBus/PcdGet32(PcdPlatformFreqDiv); + DUartClk =3D gPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0); =20 return ((DUartClk)/(BaudRate * 16)); } diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index 1ef99e8de25f..90677f0f36ca 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -37,21 +37,6 @@ GurRead ( } } =20 -/* - * Return system bus frequency - */ -UINT64 -GetBusFrequency ( - VOID - ) -{ - SYS_INFO SocSysInfo; - - GetSysInfo (&SocSysInfo); - - return SocSysInfo.FreqSystemBus; -} - /* * Setup SMMU in bypass mode * and also set its pagesize diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index 973ae630440b..b3e419ef3d7d 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -21,37 +21,6 @@ #include #include =20 -/** - Calculate the frequency of various controllers and - populate the passed structure with frequuencies. - - @param PtrSysInfo Input structure to populate with - frequencies. -**/ -VOID -GetSysInfo ( - OUT SYS_INFO *PtrSysInfo - ) -{ - CCSR_GUR *GurBase; - UINTN SysClk; - - GurBase =3D (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS; - SysClk =3D CLK_FREQ; - - SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); - - PtrSysInfo->FreqSystemBus =3D SysClk; - - // - // selects the platform clock:SYSCLK ratio and calculate - // system frequency - // - PtrSysInfo->FreqSystemBus *=3D (GurRead ((UINTN)&GurBase->RcwSr[0]) >> - CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & - CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; -} - /** Return the input clock frequency to an IP Module. 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Thu, 30 Apr 2020 05:51:44 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 15/24] Silicon: NXP: Remove direct calls to SwapMmio* APIs Date: Fri, 1 May 2020 11:19:46 +0530 Message-ID: <20200501054955.13025-16-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: CxGnlSbf7gi7CSbkNZOYewL6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225908; bh=0JzMYw0vyKe1LBwOLIJgSxY0+9k8N6eh0hB4X/F9Brk=; h=Content-Type:Date:From:Reply-To:Subject:To; b=AFzc/JfSrTDaNb0GUuSeyWvHUC3Vy82yEbY+qCNoSJmHoLglMYvvzRbTcCaC2MKG1tO GfUDA7aVKVUjQZ/1lqrXhEbCQoQbJLZEvRC6qggK90l9+ylSd/8c4m9g6nVyZR/T8g6h+ GBZ0SYJjTsF8xxEBprnfd74IIkVRllVLuSc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal The SwapMmio** APIs are supposed to be called indirectly via GetMmioOperations** APIs. Therefore, remove the SwapMmio** APIs from IoAccessLib.h and make these APIs STATIC to IoAccessLib.c, so that no accidental call can be made to these. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - Use GetMmioOperations in place of GetMmioOperations32 - Use MMIO_OPERATIONS in place of MMIO_OPERATIONS_32 =20 V3: - New commit Silicon/NXP/Include/Library/IoAccessLib.h | 236 +------------------- Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 17 +- Silicon/NXP/Library/SocLib/Chassis.c | 10 +- 3 files changed, 22 insertions(+), 241 deletions(-) diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Includ= e/Library/IoAccessLib.h index 0f5b19dcf149..3dbb35d2ce5a 100644 --- a/Silicon/NXP/Include/Library/IoAccessLib.h +++ b/Silicon/NXP/Include/Library/IoAccessLib.h @@ -1,6 +1,6 @@ /** @file * - * Copyright 2017-2019 NXP + * Copyright 2017-2020 NXP * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -47,238 +47,4 @@ GetMmioOperations ( IN BOOLEAN Swap ); =20 -/** - MmioRead16 for Big-Endian modules. - - @param Address The MMIO register to read. - - @return The value read. - -**/ -UINT16 -EFIAPI -SwapMmioRead16 ( - IN UINTN Address - ); - -/** - MmioRead32 for Big-Endian modules. - - @param Address The MMIO register to read. - - @return The value read. - -**/ -UINT32 -EFIAPI -SwapMmioRead32 ( - IN UINTN Address - ); - -/** - MmioRead64 for Big-Endian modules. - - @param Address The MMIO register to read. - - @return The value read. - -**/ -UINT64 -EFIAPI -SwapMmioRead64 ( - IN UINTN Address - ); - -/** - MmioWrite16 for Big-Endian modules. - - @param Address The MMIO register to write. - @param Value The value to write to the MMIO register. - -**/ -UINT16 -EFIAPI -SwapMmioWrite16 ( - IN UINTN Address, - IN UINT16 Value - ); - -/** - MmioWrite32 for Big-Endian modules. - - @param Address The MMIO register to write. - @param Value The value to write to the MMIO register. - -**/ -UINT32 -EFIAPI -SwapMmioWrite32 ( - IN UINTN Address, - IN UINT32 Value - ); - -/** - MmioWrite64 for Big-Endian modules. - - @param Address The MMIO register to write. - @param Value The value to write to the MMIO register. - -**/ -UINT64 -EFIAPI -SwapMmioWrite64 ( - IN UINTN Address, - IN UINT64 Value - ); - -/** - MmioAndThenOr16 for Big-Endian modules. - - @param Address The MMIO register to write. - @param AndData The value to AND with the read value from the MMIO regis= ter. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the MMIO register. - -**/ -UINT16 -EFIAPI -SwapMmioAndThenOr16 ( - IN UINTN Address, - IN UINT16 AndData, - IN UINT16 OrData - ); - -/** - MmioAndThenOr32 for Big-Endian modules. - - @param Address The MMIO register to write. - @param AndData The value to AND with the read value from the MMIO regis= ter. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the MMIO register. - -**/ -UINT32 -EFIAPI -SwapMmioAndThenOr32 ( - IN UINTN Address, - IN UINT32 AndData, - IN UINT32 OrData - ); - -/** - MmioAndThenOr64 for Big-Endian modules. - - @param Address The MMIO register to write. - @param AndData The value to AND with the read value from the MMIO regis= ter. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the MMIO register. - -**/ -UINT64 -EFIAPI -SwapMmioAndThenOr64 ( - IN UINTN Address, - IN UINT64 AndData, - IN UINT64 OrData - ); - -/** - MmioOr16 for Big-Endian modules. - - @param Address The MMIO register to write. - @param OrData The value to OR with the read value from the MMIO regist= er. - - @return The value written back to the MMIO register. - -**/ -UINT16 -EFIAPI -SwapMmioOr16 ( - IN UINTN Address, - IN UINT16 OrData - ); - -/** - MmioOr32 for Big-Endian modules. - - @param Address The MMIO register to write. - @param OrData The value to OR with the read value from the MMIO regist= er. - - @return The value written back to the MMIO register. - -**/ -UINT32 -EFIAPI -SwapMmioOr32 ( - IN UINTN Address, - IN UINT32 OrData - ); - -/** - MmioOr64 for Big-Endian modules. - - @param Address The MMIO register to write. - @param OrData The value to OR with the read value from the MMIO regist= er. - - @return The value written back to the MMIO register. - -**/ -UINT64 -EFIAPI -SwapMmioOr64 ( - IN UINTN Address, - IN UINT64 OrData - ); - -/** - MmioAnd16 for Big-Endian modules. - - @param Address The MMIO register to write. - @param AndData The value to AND with the read value from the MMIO regis= ter. - - @return The value written back to the MMIO register. - -**/ -UINT16 -EFIAPI -SwapMmioAnd16 ( - IN UINTN Address, - IN UINT16 AndData - ); - -/** - MmioAnd32 for Big-Endian modules. - - @param Address The MMIO register to write. - @param AndData The value to AND with the read value from the MMIO regis= ter. - - @return The value written back to the MMIO register. - -**/ -UINT32 -EFIAPI -SwapMmioAnd32 ( - IN UINTN Address, - IN UINT32 AndData - ); - -/** - MmioAnd64 for Big-Endian modules. - - @param Address The MMIO register to write. - @param AndData The value to AND with the read value from the MMIO regis= ter. - - @return The value written back to the MMIO register. - -**/ -UINT64 -EFIAPI -SwapMmioAnd64 ( - IN UINTN Address, - IN UINT64 AndData - ); - #endif /* IO_ACCESS_LIB_H_ */ diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Li= brary/IoAccessLib/IoAccessLib.c index 33039afda40f..2c6160e8acef 100644 --- a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c @@ -2,7 +2,7 @@ =20 Provide MMIO APIs for BE modules. =20 - Copyright 2017-2019 NXP + Copyright 2017-2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -21,6 +21,7 @@ @return The value read. =20 **/ +STATIC UINT16 EFIAPI SwapMmioRead16 ( @@ -38,6 +39,7 @@ SwapMmioRead16 ( @return The value read. =20 **/ +STATIC UINT32 EFIAPI SwapMmioRead32 ( @@ -55,6 +57,7 @@ SwapMmioRead32 ( @return The value read. =20 **/ +STATIC UINT64 EFIAPI SwapMmioRead64 ( @@ -71,6 +74,7 @@ SwapMmioRead64 ( @param Value The value to write to the MMIO register. =20 **/ +STATIC UINT16 EFIAPI SwapMmioWrite16 ( @@ -88,6 +92,7 @@ SwapMmioWrite16 ( @param Value The value to write to the MMIO register. =20 **/ +STATIC UINT32 EFIAPI SwapMmioWrite32 ( @@ -105,6 +110,7 @@ SwapMmioWrite32 ( @param Value The value to write to the MMIO register. =20 **/ +STATIC UINT64 EFIAPI SwapMmioWrite64 ( @@ -125,6 +131,7 @@ SwapMmioWrite64 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT16 EFIAPI SwapMmioAndThenOr16 ( @@ -149,6 +156,7 @@ SwapMmioAndThenOr16 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT32 EFIAPI SwapMmioAndThenOr32 ( @@ -173,6 +181,7 @@ SwapMmioAndThenOr32 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT64 EFIAPI SwapMmioAndThenOr64 ( @@ -196,6 +205,7 @@ SwapMmioAndThenOr64 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT16 EFIAPI SwapMmioOr16 ( @@ -215,6 +225,7 @@ SwapMmioOr16 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT32 EFIAPI SwapMmioOr32 ( @@ -234,6 +245,7 @@ SwapMmioOr32 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT64 EFIAPI SwapMmioOr64 ( @@ -253,6 +265,7 @@ SwapMmioOr64 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT16 EFIAPI SwapMmioAnd16 ( @@ -272,6 +285,7 @@ SwapMmioAnd16 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT32 EFIAPI SwapMmioAnd32 ( @@ -291,6 +305,7 @@ SwapMmioAnd32 ( @return The value written back to the MMIO register. =20 **/ +STATIC UINT64 EFIAPI SwapMmioAnd64 ( diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index 90677f0f36ca..05c5462446a4 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -30,11 +30,11 @@ GurRead ( IN UINTN Address ) { - if (FixedPcdGetBool (PcdGurBigEndian)) { - return SwapMmioRead32 (Address); - } else { - return MmioRead32 (Address); - } + MMIO_OPERATIONS *GurOps; + + GurOps =3D GetMmioOperations (FixedPcdGetBool (PcdGurBigEndian)); + + return GurOps->Read32 (Address); } =20 /* --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:47 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 16/24] Silicon/NXP: Add Chassis2 Package Date: Fri, 1 May 2020 11:19:47 +0530 Message-ID: <20200501054955.13025-17-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:45 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: db070cd3-5936-4245-f373-08d7ecca9212 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:989; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: NuKt5kLnWfE4mA2qPRBayexDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225910; bh=sz52+cWDBPjySIoL2ZguFk6nooeeYuJC+jGYza8WIvc=; h=Content-Type:Date:From:Reply-To:Subject:To; b=kBylMkHxPqP1/toUi43QPVAE86m7A30n+Uli1mOc+/2bl8pWh2uWuE0+zs2XztiIjRj ilA3ynjfI9yGdHWkeaNI/s0zpwQlvnmW0RB8L+0NTJwEWqVhBf/Z4ENSeZ2ZfLxbhP2bl j0O6dKVfRrktuSqkmG/PumXqZ2OdQE/AJEM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal A Chassis is a base framework used for building SoCs. We can think of Chassis/Soc/Platform(a.k.a Board) in Object model terms. Chassis is base. Soc is based on some Chassis. Platform is based on some Soc. SOCs that are designed around same chassis, reuse most of the components. Therefore, add the package for Chassis2. LS1043A and LS1046A SOCs belong to Chassis2. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - Fixed line adds whitespace error - Added Uefi.h in Chassis.h - Fixed Typo Borad -> Board in commit description - Fixed license in ChassisLib.inf - Added lines between Copyright and license in ChassisLib.c =20 V3: - in patch description Oops -> Object model - Sorted includes alphabetically - removed direct calls to SwapMmio** APIs and used GetMmioOperations** Silicon/NXP/Chassis2/Chassis2.dec | 22 +++++ Silicon/NXP/NxpQoriqLs.dec | 4 + Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 ++ Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 33 +++++++ Silicon/NXP/Chassis2/Include/Chassis.h | 36 +++++++ Silicon/NXP/Include/Library/ChassisLib.h | 51 ++++++++++ Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 98 ++++++++++++++= ++++++ 7 files changed, 254 insertions(+) diff --git a/Silicon/NXP/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis2/Chass= is2.dec new file mode 100644 index 000000000000..d3674cd6dff9 --- /dev/null +++ b/Silicon/NXP/Chassis2/Chassis2.dec @@ -0,0 +1,22 @@ +# @file +# NXP Layerscape processor package. +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + DEC_SPECIFICATION =3D 1.27 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index e61592b4fe61..b327e52da139 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -14,6 +14,9 @@ Include =20 [LibraryClasses] + ## @libraryclass Provides Chassis specific functions to other modules + ChassisLib|Include/Library/ChassisLib.h + ## @libraryclass Provides services to read/write to I2c devices I2cLib|Include/Library/I2cLib.h =20 @@ -29,3 +32,4 @@ =20 [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315 + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316 diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc b/Silicon/NXP/Chassis2/C= hassis2.dsc.inc new file mode 100644 index 000000000000..db8e5a92eacb --- /dev/null +++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc @@ -0,0 +1,10 @@ +# @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[LibraryClasses.common] + ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silic= on/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf new file mode 100644 index 000000000000..f5dbd1349dc5 --- /dev/null +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf @@ -0,0 +1,33 @@ +# @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION =3D 1.27 + BASE_NAME =3D Chassis2Lib + FILE_GUID =3D fae0d077-5fc2-494f-b8e1-c51a3023ee3e + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ChassisLib + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/Chassis2/Chassis2.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + IoAccessLib + IoLib + PcdLib + SerialPortLib + +[Sources.common] + ChassisLib.c + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/= Include/Chassis.h new file mode 100644 index 000000000000..14e21ef9daf4 --- /dev/null +++ b/Silicon/NXP/Chassis2/Include/Chassis.h @@ -0,0 +1,36 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef CHASSIS_H__ +#define CHASSIS_H__ + +#include + +#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000 + +/* SMMU Defintions */ +#define SMMU_BASE_ADDR 0x09000000 +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) + +#define SCR0_USFCFG_MASK 0x00000400 +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SACR_PAGESIZE_MASK 0x00010000 + +/** + The Device Configuration Unit provides general purpose configuration and + status for the device. These registers only support 32-bit accesses. +**/ +#pragma pack(1) +typedef struct { + UINT8 Reserved0[0x100 - 0x0]; + UINT32 RcwSr[16]; // Reset Control Word Status Register +} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG; +#pragma pack() + +#endif // CHASSIS_H__ diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include= /Library/ChassisLib.h new file mode 100644 index 000000000000..89992a4b6fd5 --- /dev/null +++ b/Silicon/NXP/Include/Library/ChassisLib.h @@ -0,0 +1,51 @@ +/** @file + Chassis Lib to provide Chessis specific functionality to all SOCs in + a Chassis. + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef CHASSIS_LIB_H__ +#define CHASSIS_LIB_H__ + +#include + +/** + Read Dcfg register + + @param Address The MMIO register to read. + + @return The value read. +**/ +UINT32 +EFIAPI +DcfgRead32 ( + IN UINTN Address + ); + +/** + Write Dcfg register + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. +**/ +UINT32 +EFIAPI +DcfgWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + Function to initialize Chassis Specific functions + **/ +VOID +ChassisInit ( + VOID + ); + +#endif // CHASSIS_LIB_H__ diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon= /NXP/Chassis2/Library/ChassisLib/ChassisLib.c new file mode 100644 index 000000000000..91b19f832f00 --- /dev/null +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c @@ -0,0 +1,98 @@ +/** @file + Chassis specific functions common to all SOCs based on a specific Chessis + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Read Dcfg register + + @param Address The MMIO register to read. + + @return The value read. +**/ +UINT32 +EFIAPI +DcfgRead32 ( + IN UINTN Address + ) +{ + MMIO_OPERATIONS *DcfgOps; + + DcfgOps =3D GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian)); + + return DcfgOps->Read32 (Address); +} + +/** + Write Dcfg register + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. +**/ +UINT32 +EFIAPI +DcfgWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + MMIO_OPERATIONS *DcfgOps; + + DcfgOps =3D GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian)); + + return DcfgOps->Write32 (Address, Value); +} + +/* + * Setup SMMU in bypass mode + * and also set its pagesize + */ +STATIC +VOID +SmmuInit ( + VOID + ) +{ + UINT32 Value; + + /* set pagesize as 64K and ssmu-500 in bypass mode */ + Value =3D (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK); + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value); + + Value =3D (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK); + Value &=3D ~SCR0_USFCFG_MASK; + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value); + + Value =3D (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK); + Value &=3D ~SCR0_USFCFG_MASK; + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); +} + +/** + Function to initialize Chassis Specific functions + **/ +VOID +ChassisInit ( + VOID + ) +{ + // + // Early init serial Port to get board information. + // + SerialPortInitialize (); + + SmmuInit (); +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:50 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 17/24] Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg Date: Fri, 1 May 2020 11:19:48 +0530 Message-ID: <20200501054955.13025-18-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: 8kzUvSquPeupZgxT3fw5mCZMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225913; bh=oG8ygNgGluMCndeIlmIz9DMuxpeyPe0GLTYpSgY3W5I=; h=Content-Type:Date:From:Reply-To:Subject:To; b=qbZ7tIL9SqDKpcbsk3MEfHNrc3dsZdaKN2ufj3IAcwHdf6Nnpktm7fFg3b1kF9Ucc4t oY6/M4HGkK7tNWqgWFKu3tQQib7c6Et0Uq7ZffVO4iKr3pMcIYu3sLI32ky1kzrwfsE70 DXziWXplqB/dXmD2GEj0e8oqRoEG+t03EpY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Now the we have added Chassis Package, move the chassis specific common code for all SOCs belonging to same chassis to ChassisLib. Use ChassisLib APIs in SocLib. Signed-off-by: Pankaj Bansal --- Notes: V4: - No change =20 V3: - No change Silicon/NXP/NxpQoriqLs.dec | 6 = -- Silicon/NXP/LS1043A/LS1043A.dsc.inc | 9 = ++- Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 1 + Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 1 + Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 15 = +---- Silicon/NXP/Include/Chassis2/NxpSoc.h | 44 = -------------- Silicon/NXP/LS1043A/Include/Soc.h | 6 = +- Silicon/NXP/Library/SocLib/NxpChassis.h | 22 = ------- Silicon/NXP/Library/SocLib/Chassis.c | 61 = -------------------- Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 19 = +----- 10 files changed, 14 insertions(+), 170 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index b327e52da139..0722f59ef4f6 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -24,12 +24,6 @@ gNxpQoriqLsTokenSpaceGuid =3D {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0= xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}} gNxpNonDiscoverableI2cMasterGuid =3D { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e= , 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}} =20 -[PcdsFixedAtBuild.common] - # - # Pcds to support Big Endian IPs - # - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311 - [PcdsFeatureFlag] gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315 gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316 diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc index 7690e4caa593..ea0854f967a3 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -7,6 +7,8 @@ # # =20 +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc + [LibraryClasses.common] SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf @@ -26,9 +28,6 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 =20 - # - # Big Endian IPs - # - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE - +[PcdsFeatureFlag] + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE ## diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf= b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf index 038d48949a39..e522db81e5c0 100644 --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf @@ -24,6 +24,7 @@ MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec + Silicon/NXP/Chassis2/Chassis2.dec Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.i= nf index 7a43ad86d183..07ca6b34445f 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -19,6 +19,7 @@ ArmPlatformPkg/ArmPlatformPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec + Silicon/NXP/Chassis2/Chassis2.dec Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index bb15e0a3d710..1d042bbfc4e4 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -14,25 +14,14 @@ LIBRARY_CLASS =3D SocLib =20 [Packages] - ArmPkg/ArmPkg.dec - MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/NXP/Chassis2/Chassis2.dec Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] - BaseLib + ChassisLib DebugLib - IoAccessLib - SerialPortLib =20 [Sources.common] - Chassis.c Chassis2/Soc.c - -[BuildOptions] - GCC:*_*_*_CC_FLAGS =3D -DCHASSIS2 - -[FixedPcd] - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Ch= assis2/NxpSoc.h deleted file mode 100644 index 3f00a2614131..000000000000 --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h +++ /dev/null @@ -1,44 +0,0 @@ -/** Soc.h -* Header defining the Base addresses, sizes, flags etc for chassis 1 -* -* Copyright 2017-2020 NXP -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef NXP_SOC_H_ -#define NXP_SOC_H_ - -#define CLK_FREQ 100000000 - -#define CHASSIS2_DCFG_ADDRESS 0x1EE0000 - -/* SMMU Defintions */ -#define SMMU_BASE_ADDR 0x09000000 -#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) -#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) -#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24) -#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) -#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410) - -#define SCR0_USFCFG_MASK 0x00000400 -#define SCR0_CLIENTPD_MASK 0x00000001 -#define SACR_PAGESIZE_MASK 0x00010000 -#define IDR1_PAGESIZE_MASK 0x80000000 - -/* Device Configuration and Pin Control */ -typedef struct { - UINT8 Res0[0x100-0x00]; - UINT32 RcwSr[16]; /* Reset control word status */ -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f -} CCSR_GUR; - -UINT32 -EFIAPI -GurRead ( - IN UINTN Address - ); - -#endif /* NXP_SOC_H_ */ diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Includ= e/Soc.h index e62de570da8a..97a77d3f5da6 100644 --- a/Silicon/NXP/LS1043A/Include/Soc.h +++ b/Silicon/NXP/LS1043A/Include/Soc.h @@ -8,7 +8,7 @@ #ifndef SOC_H__ #define SOC_H__ =20 -#include +#include =20 /** Soc Memory Map @@ -43,13 +43,13 @@ #define LS1043A_I2C_SIZE 0x10000 #define LS1043A_I2C_NUM_CONTROLLERS 4 =20 -#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS +#define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS =20 /** Reset Control Word (RCW) Bits **/ #define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 =20 -typedef CCSR_GUR LS1043A_DEVICE_CONFIG; +typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG; =20 #endif // SOC_H__ diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/= SocLib/NxpChassis.h deleted file mode 100644 index 836df103f80f..000000000000 --- a/Silicon/NXP/Library/SocLib/NxpChassis.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file -* Header defining the Base addresses, sizes, flags etc for chassis 1 -* -* Copyright 2017-2020 NXP -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef NXP_CHASSIS_H_ -#define NXP_CHASSIS_H_ - -/* - * Setup SMMU in bypass mode - * and also set its pagesize - */ -VOID -SmmuInit ( - VOID - ); - -#endif /* NXP_CHASSIS_H_ */ diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c deleted file mode 100644 index 05c5462446a4..000000000000 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ /dev/null @@ -1,61 +0,0 @@ -/** @file - SoC specific Library containg functions to initialize various SoC compon= ents - - Copyright 2017-2020 NXP - - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#ifdef CHASSIS2 -#include -#elif CHASSIS3 -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include - -#include "NxpChassis.h" - -UINT32 -EFIAPI -GurRead ( - IN UINTN Address - ) -{ - MMIO_OPERATIONS *GurOps; - - GurOps =3D GetMmioOperations (FixedPcdGetBool (PcdGurBigEndian)); - - return GurOps->Read32 (Address); -} - -/* - * Setup SMMU in bypass mode - * and also set its pagesize - */ -VOID -SmmuInit ( - VOID - ) -{ - UINT32 Value; - - /* set pagesize as 64K and ssmu-500 in bypass mode */ - Value =3D (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK); - MmioWrite32 ((UINTN)SMMU_REG_SACR, Value); - - Value =3D (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SC= R0_USFCFG_MASK; - MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value); - - Value =3D (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~S= CR0_USFCFG_MASK; - MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); -} - diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index b3e419ef3d7d..39fb4c14e0b9 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -8,16 +8,8 @@ **/ =20 #include -#include -#include -#include -#include +#include #include -#include -#include -#include -#include -#include #include #include =20 @@ -61,7 +53,7 @@ SocGetClock ( switch (ClockType) { case NXP_UART_CLOCK: case NXP_I2C_CLOCK: - RcwSr =3D GurRead ((UINTN)&Dcfg->RcwSr[0]); + RcwSr =3D DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]); ReturnValue =3D BaseClock * SYS_PLL_RAT (RcwSr); break; default: @@ -79,12 +71,7 @@ SocInit ( VOID ) { - SmmuInit (); - - // - // Early init serial Port to get board information. - // - SerialPortInitialize (); + ChassisInit (); =20 return; } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:53 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 18/24] Silicon/NXP/LS1043A: Move SocLib to Soc Package Date: Fri, 1 May 2020 11:19:49 +0530 Message-ID: <20200501054955.13025-19-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: GYOJMDJvkWnjqg9zMPLSRt6vx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225916; bh=Ot7Quxzkh/Hnp367obsAmyDQJrSYoTk3zPT8U3KnVKc=; h=Content-Type:Date:From:Reply-To:Subject:To; b=jRsPgsnwfSndbF9WP0W4DPFur2U3rs6BQ/Zloc/3QVjU1o6DKgtEsHuApOG191lmOJj /XuteNzDmeHUdAqPwxkvwnbiweXZboG/8FW1tXHcecn/ePpZLbLNjV8huf94/cCSBYoWC pgO9zMe8LS6Idos+JTaIIDazyS6P4UxcUeQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal The SocLib contains code specific to an Soc. it should be part of SOC package. Therefore, move the SocLib to Soc Package. Since we are moving the files to Soc Package, no need to mention the Soc name in file names. Their location is enough to indicate for which Soc the files are. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Silicon/NXP/LS1043A/LS1043A.dsc.inc = | 2 +- Silicon/NXP/{Library/SocLib/LS1043aSocLib.inf =3D> LS1043A/Library/SocLib/= SocLib.inf} | 2 +- Silicon/NXP/{Library/SocLib/Chassis2/Soc.c =3D> LS1043A/Library/SocLib/Soc= Lib.c} | 0 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc index ea0854f967a3..67f5ba68dcd5 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -10,7 +10,7 @@ !include Silicon/NXP/Chassis2/Chassis2.dsc.inc =20 [LibraryClasses.common] - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf + SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf =20 ##########################################################################= ###### diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/LS1= 043A/Library/SocLib/SocLib.inf similarity index 92% rename from Silicon/NXP/Library/SocLib/LS1043aSocLib.inf rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf index 1d042bbfc4e4..3d0f988e1c67 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf @@ -24,4 +24,4 @@ DebugLib =20 [Sources.common] - Chassis2/Soc.c + SocLib.c diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/LS1043= A/Library/SocLib/SocLib.c similarity index 100% rename from Silicon/NXP/Library/SocLib/Chassis2/Soc.c rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.c --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:56 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 19/24] NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit Date: Fri, 1 May 2020 11:19:50 +0530 Message-ID: <20200501054955.13025-20-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: K0f8d16XBj2JoXUcsjGBRICZx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225919; bh=OKekk5CVRVmbjCAxfg5oBITisBKGq2N3uxR+XmaS8CQ=; h=Content-Type:Date:From:Reply-To:Subject:To; b=O89NEnFR1A5y7Hxm+VsOwWJPFNGvyMiixX4Z1Le4ODP8YlfiA781GVoMndD2tpi2Fqm IDnwhi2MblBt4YBmrppL5OlwFyjUUROGxh2bOasBulyfXB3vBLy9UyhYEKq6c5GR7IP6o r0d3F+F32Wm9HI565hokVPa1i7u1hayoeKQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal SocInit can be defined in SocLib.h No need to make it extern in ArmPlatformLib Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - Moved commit three commits before in series Silicon/NXP/Include/Library/SocLib.h | 8 +++= +++++ Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 2 -- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Lib= rary/SocLib.h index fc4d786c710b..7b25107e4746 100644 --- a/Silicon/NXP/Include/Library/SocLib.h +++ b/Silicon/NXP/Include/Library/SocLib.h @@ -41,4 +41,12 @@ SocGetClock ( IN VA_LIST Args ); =20 +/** + Function to initialize SoC specific constructs + **/ +VOID +SocInit ( + VOID + ); + #endif // SOC_LIB_H__ diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c index 7f5872a78cfc..a554d1377484 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -16,8 +16,6 @@ #include #include =20 -extern VOID SocInit (VOID); - /** Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:51:59 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 20/24] NXP: LS1043aRdbPkg: Use ArmPlatformHelper.S from ArmPlatformPkg Date: Fri, 1 May 2020 11:19:51 +0530 Message-ID: <20200501054955.13025-21-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: 1NY8QZhmKfBBHWoa5T9un9Zix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225922; bh=KzaGdb/2J3IqWaARgRZt5EYMvZigRliFGNxosllDlsA=; h=Content-Type:Date:From:Reply-To:Subject:To; b=Ed6WGvbiATqVgLN40LEQVFKES8/9cJozVz5Yl4hhRo2NlqOqH4FzyNQGfG1SZoHhHkt 1APREtboWpi7GeJaOOy+W7/ZFNIRO9LJQAdncUlgdHPj/vC0Mn2hKPdmAAsb7E+/lpHwu MZ17V6d3H/6M+8/wu/50Rx/NSHUjbcpyElQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal ArmPlatformHelper.S is being replaced by the ArmPlatformPkg version at commit hash f4dfad05dda2c7b29e8105605621f2b413f0af2b. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - fixed line adds whitespace error =20 V3: - Modify commit description Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf = | 1 + Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c = | 8 --- Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelpe= r.S | 60 ++++++++++++-------- 3 files changed, 38 insertions(+), 31 deletions(-) diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.i= nf index 07ca6b34445f..cae0c7d1afc6 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -37,3 +37,4 @@ =20 [FixedPcd] gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c index a554d1377484..dc81e7ba3101 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -137,11 +137,3 @@ ArmPlatformGetPlatformPpiList ( *PpiList =3D gPlatformPpiTable; } =20 - -UINTN -ArmPlatformGetCorePosition ( - IN UINTN MpId - ) -{ - return 1; -} diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmP= latformHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64= /ArmPlatformHelper.S index dfbf73675a2d..b7c6dbdc2e61 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatform= Helper.S +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatform= Helper.S @@ -1,31 +1,45 @@ -# @file -# -# Copyright (c) 2012-2013, ARM Limited. All rights reserved. -# Copyright 2017, 2020 NXP -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// =20 #include -#include - -.text -.align 2 - -GCC_ASM_IMPORT(ArmReadMpidr) - -ASM_FUNC(ArmPlatformIsPrimaryCore) - tst x0, #3 - cset x0, eq - ret +#include =20 ASM_FUNC(ArmPlatformPeiBootAction) -EL1_OR_EL2(x0) -1: -2: ret =20 +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) - MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) - ldrh w0, [x0] + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore)) + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq ret --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:52:02 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 21/24] Platform/NXP: Use FV rules from ArmVirtPkg Date: Fri, 1 May 2020 11:19:52 +0530 Message-ID: <20200501054955.13025-22-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:51:59 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 3b978e19-8c46-46ba-d5ca-08d7ecca9ac6 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:353; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: EHqh8YilhFmVl18TQb5mZhZtx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225927; bh=3dX8rUuDXw2djCouIL9ppOS1K59pFasxcNeSuRFDB9Q=; h=Content-Type:Date:From:Reply-To:Subject:To; b=FewpxxxMvu4tQwIYca/81kvMS3tHbz/t/dIgogboXqhEENtPL5CKg/tqkuS90zeUyVv A6f0RBpCdKoG7TVQEFU57kN2R6lI4qGQ+IkYzN4CdcxKmGoPXOvf25T5jLFm7C5ZQwUZU t+nrcQ06ktZAGeYn+DlzILvmKgHW/fB3VYc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal FVRules.fdf.inc is being replaced by the ArmVirtPkg/ArmVirtRules.fdf.inc at commit hash 746c5b6238f1ee55deb4b3ec32a6d732e27eeeaa Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - Modify commit description Platform/NXP/FVRules.fdf.inc | 59 +++++++++++++------- 1 file changed, 38 insertions(+), 21 deletions(-) diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc index c9fba65dae85..63de26abe056 100644 --- a/Platform/NXP/FVRules.fdf.inc +++ b/Platform/NXP/FVRules.fdf.inc @@ -1,8 +1,7 @@ -# FvRules.fdf.inc # -# Rules for creating FD. -# -# Copyright 2017-2019 NXP +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved. +# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -16,40 +15,49 @@ # ##########################################################################= ###### =20 + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + [Rule.Common.SEC] - FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { - TE TE Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi } =20 [Rule.Common.PEI_CORE] - FILE PEI_CORE =3D $(NAMED_GUID) { - TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING =3D"$(MODULE_NAME)" Optional } =20 [Rule.Common.PEIM] - FILE PEIM =3D $(NAMED_GUID) { + FILE PEIM =3D $(NAMED_GUID) FIXED { PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING=3D"$(MODULE_NAME)" Optional } =20 -[Rule.Common.PEIM.TIANOCOMPRESSED] - FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING=3D"$(MODULE_NAME)" Optional - } - } - [Rule.Common.DXE_CORE] FILE DXE_CORE =3D $(NAMED_GUID) { PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING=3D"$(MODULE_NAME)" Optional } =20 - [Rule.Common.UEFI_DRIVER] FILE DRIVER =3D $(NAMED_GUID) { DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex @@ -62,6 +70,8 @@ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING=3D"$(MODULE_NAME)" Optional + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml } =20 [Rule.Common.DXE_RUNTIME_DRIVER] @@ -73,7 +83,7 @@ =20 [Rule.Common.UEFI_APPLICATION] FILE APPLICATION =3D $(NAMED_GUID) { - UI STRING =3D"$(MODULE_NAME)" Optional + UI STRING =3D"$(MODULE_NAME)" Optional PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi } =20 @@ -91,3 +101,10 @@ UI STRING=3D"$(MODULE_NAME)" Optional VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + UI STRING=3D"$(MODULE_NAME)" Optional + } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:52:05 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 22/24] Platform/NXP/LS1043aRdbPkg: Add VarStore Date: Fri, 1 May 2020 11:19:53 +0530 Message-ID: <20200501054955.13025-23-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:52:02 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: bd0a2c25-306f-4d78-27ad-08d7ecca9c82 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: 1Fdtgoe3IQKzZx2WmhnYgJwPx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225928; bh=EEWzvzTIic9l+at9td0c5AVJvPKxasg9bOiao9VmyrQ=; h=Content-Type:Date:From:Reply-To:Subject:To; b=IxrzZpmbpWASnvwnG3gInIA/JKC/VP248aKysQIv+HrdP8zjkJGLXyWi5Bm1Krfbecb A8V4Ya1LfGKfSKWLqam+Qfja5Uk9iQs6zrLuqJQyc8Mheww3/84b7fL215DjYEoUJSX0i 5d0jnjUnatr8opd2PsLirRsGbcqkXOwMMlY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Add VarStore Fd. This Fd is used to store non volatile variables in flash. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 3 +- Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 ++++++++++++++++++++ 2 files changed, 93 insertions(+), 1 deletion(-) diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf index 8d66f36d7407..99fbc87e1200 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -3,7 +3,7 @@ # FLASH layout file for LS1043a board. # # Copyright (c) 2016, Freescale Ltd. All rights reserved. -# Copyright 2017-2019 NXP +# Copyright 2017-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -49,6 +49,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.Pc= dFvSize FV =3D FVMAIN_COMPACT =20 !include Platform/NXP/FVRules.fdf.inc +!include VarStore.fdf.inc ##########################################################################= ###### # # FV Section diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1= 043aRdbPkg/VarStore.fdf.inc new file mode 100644 index 000000000000..391e4ae5eaf8 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc @@ -0,0 +1,91 @@ +## @file +# FDF include file with FD definition that defines an empty variable stor= e. +# +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved. +# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2016, Linaro, Ltd. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved. +# Copyright 2017-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[FD.LS1043aRdbNv_EFI] +BaseAddress =3D 0x60500000 #The base address of the FLASH device +Size =3D 0x000C0000 #The size in bytes of the FLASH device +ErasePolarity =3D 1 +BlockSize =3D 0x40000 +NumBlocks =3D 0x3 + +# +# Place NV Storage just above Platform Data Base +# +DEFINE NVRAM_AREA_VARIABLE_BASE =3D 0x00000000 +DEFINE NVRAM_AREA_VARIABLE_SIZE =3D 0x00040000 +DEFINE FTW_WORKING_BASE =3D $(NVRAM_AREA_VARIABLE_B= ASE) + $(NVRAM_AREA_VARIABLE_SIZE) +DEFINE FTW_WORKING_SIZE =3D 0x00040000 +DEFINE FTW_SPARE_BASE =3D $(FTW_WORKING_BASE) + $= (FTW_WORKING_SIZE) +DEFINE FTW_SPARE_SIZE =3D 0x00040000 + +##########################################################################= ### +# LS1043ARDB NVRAM Area +# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare +##########################################################################= ### + + +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0xC0000 + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block + 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + # It is compatible with SECURE_BOOT_ENABLE =3D=3D FALSE as well. + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3ffb8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:52:08 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 23/24] Silicon/NXP: move MemoryInitPeiLib as per PEIM structures Date: Fri, 1 May 2020 11:19:54 +0530 Message-ID: <20200501054955.13025-24-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: EvlsqxdG4H68bVFuCI0cwZWCx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225931; bh=ULpxCRSPvy2nua5Kn4jFj5kmF1oIeAL/1eS8J2ttLAI=; h=Content-Type:Date:From:Reply-To:Subject:To; b=bxgKgE6vRyjV28oq8tGQgqV8xACSfLyFJURnla1q2DwUkgIDMYEgAQxbNALPD+471Rr z1sHbkELxqyhSHfEWUS+1vQfulQo44RdAWRzpg6UR2yQik/+VIkq6li30I/BOcD8NnKfq CIU5Jd1imVmhCvAzjeFww6vDB37VqUwIbaI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal MemoryInitPeiLib would be linked to MemoryInitPeim, when we implement PEI phase. therefore, move the library to directory of same name. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: V4: - No change =20 V3: - No change Silicon/NXP/NxpQoriqLs.dsc.inc = | 4 ++-- Silicon/NXP/Library/{MemoryInitPei =3D> MemoryInitPeiLib}/MemoryInitPeiLib= .inf | 0 Silicon/NXP/Library/{MemoryInitPei =3D> MemoryInitPeiLib}/MemoryInitPeiLib= .h | 0 Silicon/NXP/Library/{MemoryInitPei =3D> MemoryInitPeiLib}/MemoryInitPeiLib= .c | 0 4 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc index 8fbd6288cfae..3c8b11d9e04c 100644 --- a/Silicon/NXP/NxpQoriqLs.dsc.inc +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc @@ -98,6 +98,8 @@ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf =20 + MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.i= nf + [LibraryClasses.common.SEC] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf @@ -109,7 +111,6 @@ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf - MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf =20 # 1/123 faster than Stm or Vstm version BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf @@ -139,7 +140,6 @@ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf - MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf =20 [LibraryClasses.common.UEFI_APPLICATION] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silic= on/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf similarity index 100% rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon= /NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h similarity index 100% rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon= /NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c similarity index 100% rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 30 Apr 2020 05:52:11 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v4 24/24] Platform/NXP/LS1043aRdbPkg: Add PEI Phase Date: Fri, 1 May 2020 11:19:55 +0530 Message-ID: <20200501054955.13025-25-pankaj.bansal@oss.nxp.com> In-Reply-To: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> References: <20200501054955.13025-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR03CA0131.apcprd03.prod.outlook.com (2603:1096:4:91::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2979.14 via Frontend Transport; Thu, 30 Apr 2020 05:52:08 +0000 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: ae9993c0-a597-437e-b26c-08d7ecca9fe9 X-MS-TrafficTypeDiagnostic: VI1PR04MB4429:|VI1PR04MB4429: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: C4jWsBBvx5WKoeqgqE1qJ973x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1588225934; bh=VVjzRjUanIjaYhazlYyfeNUDcz0fF/8Bo0X4SK13C/k=; h=Content-Type:Date:From:Reply-To:Subject:To; b=kmWrTPG9fDcVEeOVSwRiXH94suzwztPrZwFmze+uBRjqvgD9oPq+Dv2OmwbCcZGZ+74 WtzsIX3/AQv4UfrOIlr8N6oJyI8ack14wAS+rTR2rVw8yW4QjYtICOou870I7odQqA4kw UpVPFV8F01fOGarQ5jjHqt/lV50G5EmeZNw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Pankaj Bansal Add PEI phase to LS1043aRdb. This is needed because we need to have dynamic PCDs support to be able to reserve memory before reporting memory to UEFI firmware. Using PEI phase we are now also dynamically setting the PcdSystemMemoryBase and PcdSystemMemorySize depending upon the DRAM regions detected. This in turn would depend on the DDR DIMMs installed on board. Signed-off-by: Pankaj Bansal --- Notes: V4: - Use ArmPkg version of PeiServicesTablePointerLib instead of MdePkg. This allows us to run PEI phase from memory mapped flash devices =20 V3: - Update commit description Silicon/NXP/NxpQoriqLs.dsc.inc | 63 +++++++++++= ++----- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 18 ++++-- Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf | 3 +- Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c | 67 +++++++++++= --------- 5 files changed, 99 insertions(+), 61 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc index 3c8b11d9e04c..03759c7cee7c 100644 --- a/Silicon/NXP/NxpQoriqLs.dsc.inc +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc @@ -93,46 +93,53 @@ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl= eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf =20 I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf =20 + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.i= nf =20 [LibraryClasses.common.SEC] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf - ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf - LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCusto= mDecompressLib.inf - PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf - HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf - PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf - MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsB= aseLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + +[LibraryClasses.common.PEI_CORE] + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf =20 - # 1/123 faster than Stm or Vstm version - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - - # Uncomment to turn on GDB stub in SEC. - #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf =20 [LibraryClasses.common.PEIM] PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf - PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf =20 [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf =20 @@ -204,6 +211,9 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 =20 + gArmTokenSpaceGuid.PcdSystemMemoryBase|0 + gArmTokenSpaceGuid.PcdSystemMemorySize|0 + [PcdsDynamicHii.common.DEFAULT] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|10 =20 @@ -224,6 +234,12 @@ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 =20 + ## Base of DRAM + ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this= space + ## for temporary ram + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 + !if $(TARGET) =3D=3D RELEASE gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001 @@ -281,13 +297,26 @@ ##########################################################################= ###### [Components.common] # - # SEC + # PEI Phase modules # - ArmPlatformPkg/PrePi/PeiUniCore.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf + + MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Universal/PCD/Pei/Pcd.inf { PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf } + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } =20 # # DXE diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index d486c9b36fab..d45fd67c03b5 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -30,15 +30,6 @@ RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf =20 [PcdsFixedAtBuild.common] - - # - # LS1043a board Specific PCDs - # XX (DRAM - Region 1 2GB) - # (NOR - IFC Region 1 512MB) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000 - gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 - # # RTC Pcds # diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf index 99fbc87e1200..931d0bb14f9b 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -24,10 +24,10 @@ =20 [FD.LS1043ARDB_EFI] BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. -Size =3D 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +Size =3D 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device ErasePolarity =3D 1 -BlockSize =3D 0x1 -NumBlocks =3D 0xED000 +BlockSize =3D 0x40000 +NumBlocks =3D 0x5 =20 ##########################################################################= ###### # @@ -44,7 +44,7 @@ NumBlocks =3D 0xED000 # RegionType # ##########################################################################= ###### -0x00000000|0x000ED000 +0x00000000|0x00140000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV =3D FVMAIN_COMPACT =20 @@ -159,7 +159,15 @@ READ_STATUS =3D TRUE READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE =20 - INF ArmPlatformPkg/PrePi/PeiUniCore.inf + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.i= nf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf =20 FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf b/Si= licon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf index ad2371115b17..a33f8cd3f743 100644 --- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf @@ -13,7 +13,8 @@ FILE_GUID =3D 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D MemoryInitPeiLib|SEC PEIM DXE_DRIVER + LIBRARY_CLASS =3D MemoryInitPeiLib|PEIM + CONSTRUCTOR =3D MemoryInitPeiLibConstructor =20 [Sources] MemoryInitPeiLib.c diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c b/Sili= con/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c index 905d326893e5..5599239ede4a 100644 --- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c @@ -120,22 +120,17 @@ GetDramRegionsInfo ( =20 /** Get the installed RAM information. - Initialize MMU and Memory HOBs (Resource Descriptor HOBs) + Initialize Memory HOBs (Resource Descriptor HOBs) + Set the PcdSystemMemoryBase and PcdSystemMemorySize. =20 - @param[in] UefiMemoryBase Base address of region used by UEFI in - permanent memory - @param[in] UefiMemorySize Size of the region used by UEFI in permanent = memory - - @return EFI_SUCCESS Successfuly Initialize MMU and Memory HOBs. + @return EFI_SUCCESS Successfuly retrieved the system memory information **/ EFI_STATUS EFIAPI -MemoryPeim ( - IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, - IN UINT64 UefiMemorySize +MemoryInitPeiLibConstructor ( + VOID ) { - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; INT32 Index; UINTN BaseAddress; UINTN Size; @@ -147,18 +142,6 @@ MemoryPeim ( BOOLEAN FoundSystemMem; EFI_STATUS Status; =20 - // Get Virtual Memory Map from the Platform Library - ArmPlatformGetVirtualMemoryMap (&MemoryTable); - - // - // Ensure MemoryTable[0].Length which is size of DRAM has been set - // by ArmPlatformGetVirtualMemoryMap () - // - ASSERT (MemoryTable[0].Length !=3D 0); - - // - // Now, the permanent memory has been installed, we can call AllocatePag= es() - // ResourceAttributes =3D ( EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | @@ -174,8 +157,8 @@ MemoryPeim ( Status =3D GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions)); ASSERT_EFI_ERROR (Status); =20 - FdBase =3D (UINTN)FixedPcdGet64 (PcdFdBaseAddress); - FdTop =3D FdBase + (UINTN)FixedPcdGet32 (PcdFdSize); + FdBase =3D (UINTN)PcdGet64 (PcdFdBaseAddress); + FdTop =3D FdBase + (UINTN)PcdGet32 (PcdFdSize); =20 // Declare memory regions to system // The DRAM region info is sorted based on the RAM address is SOC memory= map. @@ -228,8 +211,8 @@ MemoryPeim ( ); }; // Mark the memory covering the Firmware Device as boot services data - BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress), - FixedPcdGet32 (PcdFdSize), + BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress), + PcdGet32 (PcdFdSize), EfiBootServicesData); } else { BuildResourceDescriptorHob ( @@ -247,17 +230,43 @@ MemoryPeim ( Size =3D DramRegions[Index].Size; =20 if (FdBase >=3D BaseAddress && FdTop <=3D Top) { - Size -=3D (UINTN)FixedPcdGet32 (PcdFdSize); + Size -=3D (UINTN)PcdGet32 (PcdFdSize); } =20 - if ((UefiMemoryBase >=3D BaseAddress) && (Size >=3D UefiMemorySize)) { + if (Size >=3D FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) { FoundSystemMem =3D TRUE; + PcdSet64S (PcdSystemMemoryBase, BaseAddress); + PcdSet64S (PcdSystemMemorySize, Size); } } =20 ASSERT (FoundSystemMem =3D=3D TRUE); =20 - // Build Memory Allocation Hob + return EFI_SUCCESS; +} + +/** + Initialize MMU + + @param[in] UefiMemoryBase Base address of region used by UEFI in + permanent memory + @param[in] UefiMemorySize Size of the region used by UEFI in permanent = memory + + @return EFI_SUCCESS Successfuly Initialize MMU +**/ +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + + // Get Virtual Memory Map from the Platform Library + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + // Initialize Mmu InitMmu (MemoryTable); =20 if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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