From nobody Mon Feb 9 02:28:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57194+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57194+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505552; cv=none; d=zohomail.com; s=zohoarc; b=nDzg5te2wn/ARJfrYQBdeKAf/CPqd0rUTPIt1vsWJ/3LIVdKKvWay1gxKMRq6CcSksR0wBe38KJiSDWgGhJmRT5UBtZ9Atk/Uq6ZWyj/fziNsQU0IWvPFbsR0oBNqgEk6+YC43ezGwwOrlsvm1XC9sjgn/z4l9+RAn0kzBqoEcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505552; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=iIdXmqf1jH6ph2Tv7U2QabDvuA2w/x52rjZ8glO0OVM=; b=kIA3pNw/RTIPlXFPIVSwjaz9WVYgF2GisvNKgO5M5IhIlxcW9N5Oy1lS0zVUrUdBTX04s12TQeTXwDhrz4ms+FYZdJx4RWQ+ehfYFSwm1rr+GBmhuObEtC5QqIKHc1cOj8Uutn2HU1/DN9GBPS8dTHA93svJfNmu68CDbqd8gD0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57194+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505552064726.42934934088; Fri, 10 Apr 2020 00:59:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VtwiYY1788612x6lF2SjVLy7; Fri, 10 Apr 2020 00:59:11 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5058.1586505551259537265 for ; Fri, 10 Apr 2020 00:59:11 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7urCo000536; Fri, 10 Apr 2020 07:59:11 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 3091pkm0rf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:10 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 2A6929D; Fri, 10 Apr 2020 07:59:10 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id C4F5436; Fri, 10 Apr 2020 07:59:08 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 3/9] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor. Date: Fri, 10 Apr 2020 15:21:06 +0800 Message-Id: <20200410072112.7310-4-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 2h2a3qLozfj2ER5c8gwaeOHCx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505551; bh=KXmTssN3ag9fva5Gyvf/inA1gSfJPgobRqJM1sFsVjY=; h=Cc:Date:From:Reply-To:Subject:To; b=BhBwiroWaQwbC0SRemqKbnEru2VBBjFlyX9YnIseruVxLA9IOBrwi2a7QtSEgKBFuds GEzOplh7jHuxGXZwJVorcBDT/5TPQlwxsr0D0Qu3hqNX/fvpV34HLMnpE6wRPL6SqFnYR Oi6IcDZ5f8V0lwpbTI8WmY1O0Acysb2osDY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add RISC-V RV64 BaseLib functions. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- MdePkg/Library/BaseLib/BaseLib.inf | 18 +++++- MdePkg/Include/Library/BaseLib.h | 26 +++++++++ .../Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++++++++ MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 ++++++++++ .../BaseLib/RiscV64/DisableInterrupts.c | 24 ++++++++ .../BaseLib/RiscV64/EnableInterrupts.c | 25 +++++++++ .../BaseLib/RiscV64/GetInterruptState.c | 35 ++++++++++++ .../BaseLib/RiscV64/InternalSwitchStack.c | 55 +++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++++++++++ MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 +++++++ .../BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +++++ .../Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +++++ .../Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++++++++++ .../BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 +++++++++++++++++++ 14 files changed, 406 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3586beb0ab..a57ae2da31 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -4,6 +4,7 @@ # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,7 +21,7 @@ LIBRARY_CLASS =3D BaseLib =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] @@ -381,6 +382,21 @@ AArch64/CpuBreakpoint.asm | MSFT AArch64/SpeculationBarrier.asm | MSFT =20 +[Sources.RISCV64] + Math64.c + Unaligned.c + RiscV64/InternalSwitchStack.c + RiscV64/CpuBreakpoint.c + RiscV64/GetInterruptState.c + RiscV64/DisableInterrupts.c + RiscV64/EnableInterrupts.c + RiscV64/CpuPause.c + RiscV64/RiscVSetJumpLongJump.S | GCC + RiscV64/RiscVCpuBreakpoint.S | GCC + RiscV64/RiscVCpuPause.S | GCC + RiscV64/RiscVInterrupt.S | GCC + RiscV64/FlushCache.S | GCC + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index ecadff8b23..41862e4285 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -4,6 +4,8 @@ =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -124,6 +126,30 @@ typedef struct { =20 #endif // defined (MDE_CPU_AARCH64) =20 +#if defined (MDE_CPU_RISCV64) +/// +/// The RISC-V architecture context buffer used by SetJump() and LongJump(= ). +/// +typedef struct { + UINT64 RA; + UINT64 S0; + UINT64 S1; + UINT64 S2; + UINT64 S3; + UINT64 S4; + UINT64 S5; + UINT64 S6; + UINT64 S7; + UINT64 S8; + UINT64 S9; + UINT64 S10; + UINT64 S11; + UINT64 SP; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 + +#endif // defined (MDE_CPU_RISCV64) =20 // // String Services diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Librar= y/BaseLib/RiscV64/CpuBreakpoint.c new file mode 100644 index 0000000000..88d0877a2f --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c @@ -0,0 +1,27 @@ +/** @file + CPU breakpoint for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVCpuBreakpoint (VOID); + +/** + Generates a breakpoint on the CPU. + + Generates a breakpoint on the CPU. The breakpoint must be implemented su= ch + that code can resume normal execution after the breakpoint. + +**/ +VOID +EFIAPI +CpuBreakpoint ( + VOID + ) +{ + RiscVCpuBreakpoint (); +} diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/Bas= eLib/RiscV64/CpuPause.c new file mode 100644 index 0000000000..9931bad294 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c @@ -0,0 +1,29 @@ +/** @file + CPU pause for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVCpuPause (VOID); + + +/** + Requests CPU to pause for a short period of time. + + Requests CPU to pause for a short period of time. Typically used in MP + systems to prevent memory starvation while waiting for a spin lock. + +**/ +VOID +EFIAPI +CpuPause ( + VOID + ) +{ + RiscVCpuPause (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Li= brary/BaseLib/RiscV64/DisableInterrupts.c new file mode 100644 index 0000000000..867086c09c --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c @@ -0,0 +1,24 @@ +/** @file + CPU disable interrupt function for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include "BaseLibInternals.h" + +extern VOID RiscVDisableSupervisorModeInterrupts (VOID); + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +DisableInterrupts ( + VOID + ) +{ + RiscVDisableSupervisorModeInterrupts (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Lib= rary/BaseLib/RiscV64/EnableInterrupts.c new file mode 100644 index 0000000000..22ef73067e --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c @@ -0,0 +1,25 @@ +/** @file + CPU enable interrupt function for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVEnableSupervisorModeInterrupt (VOID); + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +EnableInterrupts ( + VOID + ) +{ + RiscVEnableSupervisorModeInterrupt (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Li= brary/BaseLib/RiscV64/GetInterruptState.c new file mode 100644 index 0000000000..292f1ec441 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c @@ -0,0 +1,35 @@ +/** @file + CPU get interrupt state function for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern UINT32 RiscVGetSupervisorModeInterrupts (VOID); + +/** + Retrieves the current CPU interrupt state. + + Returns TRUE is interrupts are currently enabled. Otherwise + returns FALSE. + + @retval TRUE CPU interrupts are enabled. + @retval FALSE CPU interrupts are disabled. + +**/ +BOOLEAN +EFIAPI +GetInterruptState ( + VOID + ) +{ + unsigned long RetValue; + + RetValue =3D RiscVGetSupervisorModeInterrupts (); + return RetValue? TRUE: FALSE; +} + + diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/= Library/BaseLib/RiscV64/InternalSwitchStack.c new file mode 100644 index 0000000000..0bb292141d --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c @@ -0,0 +1,55 @@ +/** @file + Switch stack function for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +/** + Transfers control to a function starting with a new stack. + + Transfers control to the function specified by EntryPoint using the + new stack specified by NewStack and passing in the parameters specified + by Context1 and Context2. Context1 and Context2 are optional and may + be NULL. The function EntryPoint must never return. + Marker will be ignored on IA-32, x64, and EBC. + IPF CPUs expect one additional parameter of type VOID * that specifies + the new backing store pointer. + + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + @param EntryPoint A pointer to function to call with the new stack. + @param Context1 A pointer to the context to pass into the EntryPoint + function. + @param Context2 A pointer to the context to pass into the EntryPoint + function. + @param NewStack A pointer to the new stack to use for the EntryPoint + function. + @param Marker VA_LIST marker for the variable argument list. + +**/ +VOID +EFIAPI +InternalSwitchStack ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack, + IN VA_LIST Marker + ) +{ + BASE_LIBRARY_JUMP_BUFFER JumpBuffer; + + DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Con= text2:%x NewStack%x\n", \ + EntryPoint, Context1, Context2, NewStack)); + JumpBuffer.RA =3D (UINTN)EntryPoint; + JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID *); + JumpBuffer.S0 =3D (UINT64)(UINTN)Context1; + JumpBuffer.S1 =3D (UINT64)(UINTN)Context2; + LongJump (&JumpBuffer, (UINTN)-1); + ASSERT(FALSE); +} diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c b/MdePkg/Library/Bas= eLib/RiscV64/LongJump.c new file mode 100644 index 0000000000..fb2ed3fa2d --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c @@ -0,0 +1,32 @@ +/** @file + Long jump implementation of RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + + +/** + Restores the CPU context that was saved with SetJump(). + + Restores the CPU context from the buffer specified by JumpBuffer. + This function never returns to the caller. + Instead is resumes execution based on the state of JumpBuffer. + + @param JumpBuffer A pointer to CPU context buffer. + @param Value The value to return when the SetJump() context is = restored. + +**/ +VOID +EFIAPI +InternalLongJump ( + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, + IN UINTN Value + ) +{ + ASSERT (FALSE); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/FlushCache.S new file mode 100644 index 0000000000..7c10fdd268 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -0,0 +1,21 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V cache operation. +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +.align 3 +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm) +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) + +ASM_PFX(RiscVInvalidateInstCacheAsm): + fence.i + ret + +ASM_PFX(RiscVInvalidateDataCacheAsm): + fence + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/L= ibrary/BaseLib/RiscV64/RiscVCpuBreakpoint.S new file mode 100644 index 0000000000..ccf91df816 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------= ------ +// +// CpuBreakpoint for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint) +ASM_PFX(RiscVCpuBreakpoint): + ebreak + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Librar= y/BaseLib/RiscV64/RiscVCpuPause.S new file mode 100644 index 0000000000..6660c2fcb3 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------= ------ +// +// CpuPause for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVCpuPause) +ASM_PFX(RiscVCpuPause): + nop + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S new file mode 100644 index 0000000000..766fcfb9cb --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -0,0 +1,32 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V Supervisor Mode interrupt enable/disable +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) +ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) +ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) + +# define MSTATUS_SIE 0x00000002 +# define CSR_SSTATUS 0x100 + +ASM_PFX(RiscVDisableSupervisorModeInterrupts): + li a1, MSTATUS_SIE + csrc CSR_SSTATUS, a1 + ret + +ASM_PFX(RiscVEnableSupervisorModeInterrupt): + li a1, MSTATUS_SIE + csrs CSR_SSTATUS, a1 + ret + +ASM_PFX(RiscVGetSupervisorModeInterrupts): + csrr a0, CSR_SSTATUS + andi a0, a0, MSTATUS_SIE + ret + diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg= /Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S new file mode 100644 index 0000000000..34486eabba --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------= ------ +// +// Set/Long jump for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +# define REG_S sd +# define REG_L ld +# define SZREG 8 +.align 3 + .globl SetJump + +SetJump: + REG_S ra, 0*SZREG(a0) + REG_S s0, 1*SZREG(a0) + REG_S s1, 2*SZREG(a0) + REG_S s2, 3*SZREG(a0) + REG_S s3, 4*SZREG(a0) + REG_S s4, 5*SZREG(a0) + REG_S s5, 6*SZREG(a0) + REG_S s6, 7*SZREG(a0) + REG_S s7, 8*SZREG(a0) + REG_S s8, 9*SZREG(a0) + REG_S s9, 10*SZREG(a0) + REG_S s10, 11*SZREG(a0) + REG_S s11, 12*SZREG(a0) + REG_S sp, 13*SZREG(a0) + li a0, 0 + ret + + .globl InternalLongJump +InternalLongJump: + REG_L ra, 0*SZREG(a0) + REG_L s0, 1*SZREG(a0) + REG_L s1, 2*SZREG(a0) + REG_L s2, 3*SZREG(a0) + REG_L s3, 4*SZREG(a0) + REG_L s4, 5*SZREG(a0) + REG_L s5, 6*SZREG(a0) + REG_L s6, 7*SZREG(a0) + REG_L s7, 8*SZREG(a0) + REG_L s8, 9*SZREG(a0) + REG_L s9, 10*SZREG(a0) + REG_L s10, 11*SZREG(a0) + REG_L s11, 12*SZREG(a0) + REG_L sp, 13*SZREG(a0) + + add a0, s0, 0 + add a1, s1, 0 + add a2, s2, 0 + add a3, s3, 0 + ret --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57194): https://edk2.groups.io/g/devel/message/57194 Mute This Topic: https://groups.io/mt/72916361/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-