From nobody Mon Feb 9 08:55:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57192+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57192+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505548; cv=none; d=zohomail.com; s=zohoarc; b=BMN91YhTACXWx7uZirtYFO0+jfCUxKvLLu+xQ3vzt8YV4llYzWJ1Z/TponX4LrvNPx2HdpKdM6DV7va1iPuJjJD1Cq3jJ6D6sp6fqxfqRHyDJi7a6wd+iDLHX2I+2Fpuhhexe6BGdoRHApFmgTSc3e5LD6lsL7R2w4dKDsaeJLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505548; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wIbltJN4cibNOyRcAdHMLEElbMSi8TpB5tVo1C85pu0=; b=VoIfD61qMRVEHXuAMZZb9rVbKisyocI5CdKlcvJ04TvXjQSEGSh8J+5kf/AhujvwQ7Y6qlTJMi0w5Sr496JHUy5EMdcp32pNgxQYidQdvcYbsrxtWULCJ8yXJctEspXwFQ7k2daToAKjrkzY7bB1ojH5PpTWRL/D+8tLqnXFygA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57192+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505548741536.2412568663483; Fri, 10 Apr 2020 00:59:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id vQMBYY1788612xA5zZhqHRSz; Fri, 10 Apr 2020 00:59:08 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5057.1586505548067268282 for ; Fri, 10 Apr 2020 00:59:08 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7tJdI012429; Fri, 10 Apr 2020 07:59:07 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 3091nt4200-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:07 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id C298691; Fri, 10 Apr 2020 07:59:06 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 630FD39; Fri, 10 Apr 2020 07:59:05 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 1/9] MdePkg: RISC-V RV64 binding in MdePkg Date: Fri, 10 Apr 2020 15:21:04 +0800 Message-Id: <20200410072112.7310-2-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: HMlUiy6l8cpYMl1wKxRnmIOkx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505548; bh=gMapyWOU+mVKvJ/SPlAaDUgAfZM4SAXcyF/e8KHw2ns=; h=Cc:Date:From:Reply-To:Subject:To; b=JhfsPfngKApF353PSCg7ygvRZzruN+tb7VgOkD6QQMEvyrjtPAWlFggTb3IghkKSMsn g0EYIlvYy2EDLjlVIGAeEdDmdg9sMaDFPKD1d4Y4JKLQJq0ghB7IfEMWh+mBF9idrru/U yBqOk1N3U01cFd9vDIH2Yqh9UbhRJ1/JEEQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- MdePkg/MdePkg.dec | 5 +- MdePkg/MdePkg.dsc | 3 +- MdePkg/Include/RiscV64/ProcessorBind.h | 173 +++++++++++++++++++++++++ 3 files changed, 179 insertions(+), 2 deletions(-) create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 6c37c2181c..0b9c4bc40a 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -6,7 +6,7 @@ # # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+# (C) Copyright 2016 - 2020 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -39,6 +39,9 @@ [Includes.AARCH64] Include/AArch64 =20 +[Includes.RISCV64] + Include/RiscV64 + [LibraryClasses] ## @libraryclass Provides most usb APIs to support the Hid requests de= fined in Usb Hid 1.1 spec # and the standard requests defined in Usb 1.1 spec. diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 2b2d5981e8..6cd38e7ec3 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# (C) Copyright 2020 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,7 +15,7 @@ PLATFORM_VERSION =3D 1.08 DSC_SPECIFICATION =3D 0x00010005 OUTPUT_DIRECTORY =3D Build/Mde - SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64 + SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64 BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT =20 diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV6= 4/ProcessorBind.h new file mode 100644 index 0000000000..2b11f041ea --- /dev/null +++ b/MdePkg/Include/RiscV64/ProcessorBind.h @@ -0,0 +1,173 @@ +/** @file + Processor or Compiler specific defines and types for RISC-V + + Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PROCESSOR_BIND_H__ +#define PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choic= es +/// +#define MDE_CPU_RISCV64 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) +#pragma pack() +#endif + +/// +/// 8-byte unsigned value +/// +typedef unsigned long long UINT64 __attribute__ ((aligned (8))); +/// +/// 8-byte signed value +/// +typedef long long INT64 __attribute__ ((aligned (8))); +/// +/// 4-byte unsigned value +/// +typedef unsigned int UINT32 __attribute__ ((aligned (4))); +/// +/// 4-byte signed value +/// +typedef int INT32 __attribute__ ((aligned (4))); +/// +/// 2-byte unsigned value +/// +typedef unsigned short UINT16 __attribute__ ((aligned (2))); +/// +/// 2-byte Character. Unless otherwise specified all strings are stored i= n the +/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 sta= ndards. +/// +typedef unsigned short CHAR16 __attribute__ ((aligned (2))); +/// +/// 2-byte signed value +/// +typedef short INT16 __attribute__ ((aligned (2))); +/// +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE.= Other +/// values are undefined. +/// +typedef unsigned char BOOLEAN; +/// +/// 1-byte unsigned value +/// +typedef unsigned char UINT8; +/// +/// 1-byte Character +/// +typedef char CHAR8; +/// +/// 1-byte signed value +/// +typedef signed char INT8; +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processo= r instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef UINT64 UINTN __attribute__ ((aligned (8))); +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor = instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef INT64 INTN __attribute__ ((aligned (8))); + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x8000000000000000ULL +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC000000000000000ULL + +/// +/// Maximum legal RV64 address +/// +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL + +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages in Super= visor mode) +/// +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL + +/// +/// Maximum legal RISC-V INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) + +/// +/// The stack alignment required for RISC-V +/// +#define CPU_STACK_ALIGNMENT 16 + +/// +/// Page allocation granularity for RISC-V +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAP= I. +// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#elif defined(__GNUC__) + /// + /// Define the standard calling convention regardless of optimization le= vel + /// The GCC support assumes a GCC compiler that supports the EFI ABI. Th= e EFI + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-= 64) + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used f= or + /// x64. Warning the assembly code in the MDE x64 does not follow the co= rrect + /// ABI for the standard x64 (x86-64) GCC. + /// + #define EFIAPI +#else + /// + /// The default for a non Microsoft* or GCC compiler is to assume the EF= I ABI + /// is the standard. + /// + #define EFIAPI +#endif + +#if defined(__GNUC__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl +#endif + +/** + Return the pointer to the first instruction of a function given a functi= on pointer. + On x64 CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a funct= ion pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPoin= ter) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57192): https://edk2.groups.io/g/devel/message/57192 Mute This Topic: https://groups.io/mt/72916359/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-