From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57192+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57192+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505548; cv=none; d=zohomail.com; s=zohoarc; b=BMN91YhTACXWx7uZirtYFO0+jfCUxKvLLu+xQ3vzt8YV4llYzWJ1Z/TponX4LrvNPx2HdpKdM6DV7va1iPuJjJD1Cq3jJ6D6sp6fqxfqRHyDJi7a6wd+iDLHX2I+2Fpuhhexe6BGdoRHApFmgTSc3e5LD6lsL7R2w4dKDsaeJLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505548; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wIbltJN4cibNOyRcAdHMLEElbMSi8TpB5tVo1C85pu0=; b=VoIfD61qMRVEHXuAMZZb9rVbKisyocI5CdKlcvJ04TvXjQSEGSh8J+5kf/AhujvwQ7Y6qlTJMi0w5Sr496JHUy5EMdcp32pNgxQYidQdvcYbsrxtWULCJ8yXJctEspXwFQ7k2daToAKjrkzY7bB1ojH5PpTWRL/D+8tLqnXFygA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57192+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505548741536.2412568663483; Fri, 10 Apr 2020 00:59:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id vQMBYY1788612xA5zZhqHRSz; Fri, 10 Apr 2020 00:59:08 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5057.1586505548067268282 for ; Fri, 10 Apr 2020 00:59:08 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7tJdI012429; Fri, 10 Apr 2020 07:59:07 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 3091nt4200-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:07 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id C298691; Fri, 10 Apr 2020 07:59:06 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 630FD39; Fri, 10 Apr 2020 07:59:05 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 1/9] MdePkg: RISC-V RV64 binding in MdePkg Date: Fri, 10 Apr 2020 15:21:04 +0800 Message-Id: <20200410072112.7310-2-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: HMlUiy6l8cpYMl1wKxRnmIOkx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505548; bh=gMapyWOU+mVKvJ/SPlAaDUgAfZM4SAXcyF/e8KHw2ns=; h=Cc:Date:From:Reply-To:Subject:To; b=JhfsPfngKApF353PSCg7ygvRZzruN+tb7VgOkD6QQMEvyrjtPAWlFggTb3IghkKSMsn g0EYIlvYy2EDLjlVIGAeEdDmdg9sMaDFPKD1d4Y4JKLQJq0ghB7IfEMWh+mBF9idrru/U yBqOk1N3U01cFd9vDIH2Yqh9UbhRJ1/JEEQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- MdePkg/MdePkg.dec | 5 +- MdePkg/MdePkg.dsc | 3 +- MdePkg/Include/RiscV64/ProcessorBind.h | 173 +++++++++++++++++++++++++ 3 files changed, 179 insertions(+), 2 deletions(-) create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 6c37c2181c..0b9c4bc40a 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -6,7 +6,7 @@ # # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+# (C) Copyright 2016 - 2020 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -39,6 +39,9 @@ [Includes.AARCH64] Include/AArch64 =20 +[Includes.RISCV64] + Include/RiscV64 + [LibraryClasses] ## @libraryclass Provides most usb APIs to support the Hid requests de= fined in Usb Hid 1.1 spec # and the standard requests defined in Usb 1.1 spec. diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 2b2d5981e8..6cd38e7ec3 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# (C) Copyright 2020 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,7 +15,7 @@ PLATFORM_VERSION =3D 1.08 DSC_SPECIFICATION =3D 0x00010005 OUTPUT_DIRECTORY =3D Build/Mde - SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64 + SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64 BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT =20 diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV6= 4/ProcessorBind.h new file mode 100644 index 0000000000..2b11f041ea --- /dev/null +++ b/MdePkg/Include/RiscV64/ProcessorBind.h @@ -0,0 +1,173 @@ +/** @file + Processor or Compiler specific defines and types for RISC-V + + Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PROCESSOR_BIND_H__ +#define PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choic= es +/// +#define MDE_CPU_RISCV64 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) +#pragma pack() +#endif + +/// +/// 8-byte unsigned value +/// +typedef unsigned long long UINT64 __attribute__ ((aligned (8))); +/// +/// 8-byte signed value +/// +typedef long long INT64 __attribute__ ((aligned (8))); +/// +/// 4-byte unsigned value +/// +typedef unsigned int UINT32 __attribute__ ((aligned (4))); +/// +/// 4-byte signed value +/// +typedef int INT32 __attribute__ ((aligned (4))); +/// +/// 2-byte unsigned value +/// +typedef unsigned short UINT16 __attribute__ ((aligned (2))); +/// +/// 2-byte Character. Unless otherwise specified all strings are stored i= n the +/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 sta= ndards. +/// +typedef unsigned short CHAR16 __attribute__ ((aligned (2))); +/// +/// 2-byte signed value +/// +typedef short INT16 __attribute__ ((aligned (2))); +/// +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE.= Other +/// values are undefined. +/// +typedef unsigned char BOOLEAN; +/// +/// 1-byte unsigned value +/// +typedef unsigned char UINT8; +/// +/// 1-byte Character +/// +typedef char CHAR8; +/// +/// 1-byte signed value +/// +typedef signed char INT8; +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processo= r instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef UINT64 UINTN __attribute__ ((aligned (8))); +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor = instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef INT64 INTN __attribute__ ((aligned (8))); + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x8000000000000000ULL +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC000000000000000ULL + +/// +/// Maximum legal RV64 address +/// +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL + +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages in Super= visor mode) +/// +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL + +/// +/// Maximum legal RISC-V INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) + +/// +/// The stack alignment required for RISC-V +/// +#define CPU_STACK_ALIGNMENT 16 + +/// +/// Page allocation granularity for RISC-V +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAP= I. +// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#elif defined(__GNUC__) + /// + /// Define the standard calling convention regardless of optimization le= vel + /// The GCC support assumes a GCC compiler that supports the EFI ABI. Th= e EFI + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-= 64) + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used f= or + /// x64. Warning the assembly code in the MDE x64 does not follow the co= rrect + /// ABI for the standard x64 (x86-64) GCC. + /// + #define EFIAPI +#else + /// + /// The default for a non Microsoft* or GCC compiler is to assume the EF= I ABI + /// is the standard. + /// + #define EFIAPI +#endif + +#if defined(__GNUC__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl +#endif + +/** + Return the pointer to the first instruction of a function given a functi= on pointer. + On x64 CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a funct= ion pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPoin= ter) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57192): https://edk2.groups.io/g/devel/message/57192 Mute This Topic: https://groups.io/mt/72916359/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57193+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57193+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505550; cv=none; d=zohomail.com; s=zohoarc; b=B7gLz2OQ+PLYEsu0p7Ibh4fkCjHZJrL3Ll6Zi5uDpMa2T7hErmZg4Ou7r8Lu4/fS82BS0Ipk/kdXSupWSUjVaR+vTHUvkbPyzz6nZy0Rfd7utNZhDyYp/mnem1mkfR1PqlGmylsHWkoUgIXMzxYWItnT1+xsLHdHIZHatt4326g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505550; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jA1W7b4HI3Ju3MF/xTbHgfTJAA2B1rU7NjGUBMbfk6I=; b=FxL4O3EvIv/8UMUqiAskW13yUynETh2EhYDM5U63jN4CwGyjYZCc2nLOehFGTZIceslO01kw45x+e9Hf4DkJ7mlPz2WDPiz6DvtVXS+KnOsInHwTMUv1e0oFMiQmn2OaJCh2AeJRhq4W6oeihtsHhGoYST5NJFK6iKibh+59Nh4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57193+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505550279372.09180329941705; Fri, 10 Apr 2020 00:59:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BCkkYY1788612xijyXjjiLCl; Fri, 10 Apr 2020 00:59:09 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.4998.1586505549533420443 for ; Fri, 10 Apr 2020 00:59:09 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7tnti013263; Fri, 10 Apr 2020 07:59:09 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 3091nt4206-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:09 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 787AB6D; Fri, 10 Apr 2020 07:59:08 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 1D17836; Fri, 10 Apr 2020 07:59:06 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 2/9] MdePkg/Include: RISC-V definitions. Date: Fri, 10 Apr 2020 15:21:05 +0800 Message-Id: <20200410072112.7310-3-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: uHSLptonusbkDc4Y2Q6urqi6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505549; bh=qe6LJnamKPhyN9kqfDeuETmoyWKp3lvNl1a5Zgfjl7U=; h=Cc:Date:From:Reply-To:Subject:To; b=opt/+B5x8dfugVa52cnYgJQ1r49fdsyeYECbqsSq98GA0CEYO07sT5+R1WV3dYHEnb1 hOsN+oAiNWqfKgxkK5ZzCpFAgFKo8QmPv+wSuF7/eXNENjhgG5Z1fbx1qzUbbTAnYe25D UVH8snYImw1QfcG2bdZyVXGC6wsJYj6AD7Q= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add RISC-V processor related definitions. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- MdePkg/Include/IndustryStandard/PeImage.h | 12 +++++ MdePkg/Include/Protocol/DebugSupport.h | 55 +++++++++++++++++++++++ MdePkg/Include/Protocol/PxeBaseCode.h | 4 ++ MdePkg/Include/Uefi/UefiBaseType.h | 13 ++++++ MdePkg/Include/Uefi/UefiSpec.h | 5 +++ 5 files changed, 89 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/Ind= ustryStandard/PeImage.h index a3d9bbed75..9b267002a1 100644 --- a/MdePkg/Include/IndustryStandard/PeImage.h +++ b/MdePkg/Include/IndustryStandard/PeImage.h @@ -9,6 +9,8 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development= LP. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define IMAGE_FILE_MACHINE_X64 0x8664 #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2 #define IMAGE_FILE_MACHINE_ARM64 0xAA64 +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 +#define IMAGE_FILE_MACHINE_RISCV128 0x5128 =20 // // EXE file formats @@ -493,6 +498,13 @@ typedef struct { #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR16 9 #define EFI_IMAGE_REL_BASED_DIR64 10 =20 +/// +/// Relocation types of RISC-V processor. +/// +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 + /// /// Line number format. /// diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protoc= ol/DebugSupport.h index 800e7710e6..7fb1d3b3e4 100644 --- a/MdePkg/Include/Protocol/DebugSupport.h +++ b/MdePkg/Include/Protocol/DebugSupport.h @@ -7,6 +7,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -603,6 +604,59 @@ typedef struct { UINT64 FAR; // Fault Address Register } EFI_SYSTEM_CONTEXT_AARCH64; =20 +/// +/// RISC-V processor exception types. +/// +#define EXCEPT_RISCV_INST_MISALIGNED 0 +#define EXCEPT_RISCV_INST_ACCESS_FAULT 1 +#define EXCEPT_RISCV_ILLEGAL_INST 2 +#define EXCEPT_RISCV_BREAKPOINT 3 +#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4 +#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5 +#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6 +#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7 +#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8 +#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9 +#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10 +#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11 + +#define EXCEPT_RISCV_SOFTWARE_INT 0x0 +#define EXCEPT_RISCV_TIMER_INT 0x1 + +typedef struct { + UINT64 X0; + UINT64 X1; + UINT64 X2; + UINT64 X3; + UINT64 X4; + UINT64 X5; + UINT64 X6; + UINT64 X7; + UINT64 X8; + UINT64 X9; + UINT64 X10; + UINT64 X11; + UINT64 X12; + UINT64 X13; + UINT64 X14; + UINT64 X15; + UINT64 X16; + UINT64 X17; + UINT64 X18; + UINT64 X19; + UINT64 X20; + UINT64 X21; + UINT64 X22; + UINT64 X23; + UINT64 X24; + UINT64 X25; + UINT64 X26; + UINT64 X27; + UINT64 X28; + UINT64 X29; + UINT64 X30; + UINT64 X31; +} EFI_SYSTEM_CONTEXT_RISCV64; =20 /// /// Universal EFI_SYSTEM_CONTEXT definition. @@ -614,6 +668,7 @@ typedef union { EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf; EFI_SYSTEM_CONTEXT_ARM *SystemContextArm; EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64; + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64; } EFI_SYSTEM_CONTEXT; =20 // diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protoco= l/PxeBaseCode.h index b02d270134..c666d312b5 100644 --- a/MdePkg/Include/Protocol/PxeBaseCode.h +++ b/MdePkg/Include/Protocol/PxeBaseCode.h @@ -3,6 +3,8 @@ devices for network access and network booting. =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Revision Reference: @@ -153,6 +155,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT; #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A #elif defined (MDE_CPU_AARCH64) #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B +#elif defined (MDE_CPU_RISCV64) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B #endif =20 =20 diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiB= aseType.h index a62f13dd06..934fc07285 100644 --- a/MdePkg/Include/Uefi/UefiBaseType.h +++ b/MdePkg/Include/Uefi/UefiBaseType.h @@ -3,6 +3,7 @@ =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -240,6 +241,12 @@ typedef union { /// #define EFI_IMAGE_MACHINE_AARCH64 0xAA64 =20 +/// +/// PE32+ Machine type for RISC-V 32/64/128 +/// +#define EFI_IMAGE_MACHINE_RISCV32 0x5032 +#define EFI_IMAGE_MACHINE_RISCV64 0x5064 +#define EFI_IMAGE_MACHINE_RISCV128 0x5128 =20 #if defined (MDE_CPU_IA32) =20 @@ -268,6 +275,12 @@ typedef union { =20 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) =20 +#elif defined (MDE_CPU_RISCV64) +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + ((Machine) =3D=3D EFI_IMAGE_MACHINE_RISCV64) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + #elif defined (MDE_CPU_EBC) =20 /// diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h index 444aa35eca..8ffaf97515 100644 --- a/MdePkg/Include/Uefi/UefiSpec.h +++ b/MdePkg/Include/Uefi/UefiSpec.h @@ -6,6 +6,8 @@ by this include file. =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -2198,6 +2200,7 @@ typedef struct { #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI" #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI" #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.E= FI" =20 #if defined (MDE_CPU_IA32) #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA= 32 @@ -2208,6 +2211,8 @@ typedef struct { #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM #elif defined (MDE_CPU_AARCH64) #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AA= RCH64 +#elif defined (MDE_CPU_RISCV64) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RI= SCV64 #else #error Unknown Processor Type #endif --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57193): https://edk2.groups.io/g/devel/message/57193 Mute This Topic: https://groups.io/mt/72916360/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57194+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57194+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505552; cv=none; d=zohomail.com; s=zohoarc; b=nDzg5te2wn/ARJfrYQBdeKAf/CPqd0rUTPIt1vsWJ/3LIVdKKvWay1gxKMRq6CcSksR0wBe38KJiSDWgGhJmRT5UBtZ9Atk/Uq6ZWyj/fziNsQU0IWvPFbsR0oBNqgEk6+YC43ezGwwOrlsvm1XC9sjgn/z4l9+RAn0kzBqoEcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505552; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=iIdXmqf1jH6ph2Tv7U2QabDvuA2w/x52rjZ8glO0OVM=; b=kIA3pNw/RTIPlXFPIVSwjaz9WVYgF2GisvNKgO5M5IhIlxcW9N5Oy1lS0zVUrUdBTX04s12TQeTXwDhrz4ms+FYZdJx4RWQ+ehfYFSwm1rr+GBmhuObEtC5QqIKHc1cOj8Uutn2HU1/DN9GBPS8dTHA93svJfNmu68CDbqd8gD0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57194+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505552064726.42934934088; Fri, 10 Apr 2020 00:59:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VtwiYY1788612x6lF2SjVLy7; Fri, 10 Apr 2020 00:59:11 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5058.1586505551259537265 for ; Fri, 10 Apr 2020 00:59:11 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7urCo000536; Fri, 10 Apr 2020 07:59:11 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 3091pkm0rf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:10 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 2A6929D; Fri, 10 Apr 2020 07:59:10 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id C4F5436; Fri, 10 Apr 2020 07:59:08 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 3/9] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor. Date: Fri, 10 Apr 2020 15:21:06 +0800 Message-Id: <20200410072112.7310-4-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 2h2a3qLozfj2ER5c8gwaeOHCx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505551; bh=KXmTssN3ag9fva5Gyvf/inA1gSfJPgobRqJM1sFsVjY=; h=Cc:Date:From:Reply-To:Subject:To; b=BhBwiroWaQwbC0SRemqKbnEru2VBBjFlyX9YnIseruVxLA9IOBrwi2a7QtSEgKBFuds GEzOplh7jHuxGXZwJVorcBDT/5TPQlwxsr0D0Qu3hqNX/fvpV34HLMnpE6wRPL6SqFnYR Oi6IcDZ5f8V0lwpbTI8WmY1O0Acysb2osDY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add RISC-V RV64 BaseLib functions. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- MdePkg/Library/BaseLib/BaseLib.inf | 18 +++++- MdePkg/Include/Library/BaseLib.h | 26 +++++++++ .../Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++++++++ MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 ++++++++++ .../BaseLib/RiscV64/DisableInterrupts.c | 24 ++++++++ .../BaseLib/RiscV64/EnableInterrupts.c | 25 +++++++++ .../BaseLib/RiscV64/GetInterruptState.c | 35 ++++++++++++ .../BaseLib/RiscV64/InternalSwitchStack.c | 55 +++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++++++++++ MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 +++++++ .../BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +++++ .../Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +++++ .../Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++++++++++ .../BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 +++++++++++++++++++ 14 files changed, 406 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3586beb0ab..a57ae2da31 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -4,6 +4,7 @@ # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,7 +21,7 @@ LIBRARY_CLASS =3D BaseLib =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] @@ -381,6 +382,21 @@ AArch64/CpuBreakpoint.asm | MSFT AArch64/SpeculationBarrier.asm | MSFT =20 +[Sources.RISCV64] + Math64.c + Unaligned.c + RiscV64/InternalSwitchStack.c + RiscV64/CpuBreakpoint.c + RiscV64/GetInterruptState.c + RiscV64/DisableInterrupts.c + RiscV64/EnableInterrupts.c + RiscV64/CpuPause.c + RiscV64/RiscVSetJumpLongJump.S | GCC + RiscV64/RiscVCpuBreakpoint.S | GCC + RiscV64/RiscVCpuPause.S | GCC + RiscV64/RiscVInterrupt.S | GCC + RiscV64/FlushCache.S | GCC + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index ecadff8b23..41862e4285 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -4,6 +4,8 @@ =20 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -124,6 +126,30 @@ typedef struct { =20 #endif // defined (MDE_CPU_AARCH64) =20 +#if defined (MDE_CPU_RISCV64) +/// +/// The RISC-V architecture context buffer used by SetJump() and LongJump(= ). +/// +typedef struct { + UINT64 RA; + UINT64 S0; + UINT64 S1; + UINT64 S2; + UINT64 S3; + UINT64 S4; + UINT64 S5; + UINT64 S6; + UINT64 S7; + UINT64 S8; + UINT64 S9; + UINT64 S10; + UINT64 S11; + UINT64 SP; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 + +#endif // defined (MDE_CPU_RISCV64) =20 // // String Services diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Librar= y/BaseLib/RiscV64/CpuBreakpoint.c new file mode 100644 index 0000000000..88d0877a2f --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c @@ -0,0 +1,27 @@ +/** @file + CPU breakpoint for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVCpuBreakpoint (VOID); + +/** + Generates a breakpoint on the CPU. + + Generates a breakpoint on the CPU. The breakpoint must be implemented su= ch + that code can resume normal execution after the breakpoint. + +**/ +VOID +EFIAPI +CpuBreakpoint ( + VOID + ) +{ + RiscVCpuBreakpoint (); +} diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/Bas= eLib/RiscV64/CpuPause.c new file mode 100644 index 0000000000..9931bad294 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c @@ -0,0 +1,29 @@ +/** @file + CPU pause for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVCpuPause (VOID); + + +/** + Requests CPU to pause for a short period of time. + + Requests CPU to pause for a short period of time. Typically used in MP + systems to prevent memory starvation while waiting for a spin lock. + +**/ +VOID +EFIAPI +CpuPause ( + VOID + ) +{ + RiscVCpuPause (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Li= brary/BaseLib/RiscV64/DisableInterrupts.c new file mode 100644 index 0000000000..867086c09c --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c @@ -0,0 +1,24 @@ +/** @file + CPU disable interrupt function for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include "BaseLibInternals.h" + +extern VOID RiscVDisableSupervisorModeInterrupts (VOID); + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +DisableInterrupts ( + VOID + ) +{ + RiscVDisableSupervisorModeInterrupts (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Lib= rary/BaseLib/RiscV64/EnableInterrupts.c new file mode 100644 index 0000000000..22ef73067e --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c @@ -0,0 +1,25 @@ +/** @file + CPU enable interrupt function for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern VOID RiscVEnableSupervisorModeInterrupt (VOID); + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +EnableInterrupts ( + VOID + ) +{ + RiscVEnableSupervisorModeInterrupt (); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Li= brary/BaseLib/RiscV64/GetInterruptState.c new file mode 100644 index 0000000000..292f1ec441 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c @@ -0,0 +1,35 @@ +/** @file + CPU get interrupt state function for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +extern UINT32 RiscVGetSupervisorModeInterrupts (VOID); + +/** + Retrieves the current CPU interrupt state. + + Returns TRUE is interrupts are currently enabled. Otherwise + returns FALSE. + + @retval TRUE CPU interrupts are enabled. + @retval FALSE CPU interrupts are disabled. + +**/ +BOOLEAN +EFIAPI +GetInterruptState ( + VOID + ) +{ + unsigned long RetValue; + + RetValue =3D RiscVGetSupervisorModeInterrupts (); + return RetValue? TRUE: FALSE; +} + + diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/= Library/BaseLib/RiscV64/InternalSwitchStack.c new file mode 100644 index 0000000000..0bb292141d --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c @@ -0,0 +1,55 @@ +/** @file + Switch stack function for RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + +/** + Transfers control to a function starting with a new stack. + + Transfers control to the function specified by EntryPoint using the + new stack specified by NewStack and passing in the parameters specified + by Context1 and Context2. Context1 and Context2 are optional and may + be NULL. The function EntryPoint must never return. + Marker will be ignored on IA-32, x64, and EBC. + IPF CPUs expect one additional parameter of type VOID * that specifies + the new backing store pointer. + + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + @param EntryPoint A pointer to function to call with the new stack. + @param Context1 A pointer to the context to pass into the EntryPoint + function. + @param Context2 A pointer to the context to pass into the EntryPoint + function. + @param NewStack A pointer to the new stack to use for the EntryPoint + function. + @param Marker VA_LIST marker for the variable argument list. + +**/ +VOID +EFIAPI +InternalSwitchStack ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack, + IN VA_LIST Marker + ) +{ + BASE_LIBRARY_JUMP_BUFFER JumpBuffer; + + DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Con= text2:%x NewStack%x\n", \ + EntryPoint, Context1, Context2, NewStack)); + JumpBuffer.RA =3D (UINTN)EntryPoint; + JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID *); + JumpBuffer.S0 =3D (UINT64)(UINTN)Context1; + JumpBuffer.S1 =3D (UINT64)(UINTN)Context2; + LongJump (&JumpBuffer, (UINTN)-1); + ASSERT(FALSE); +} diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c b/MdePkg/Library/Bas= eLib/RiscV64/LongJump.c new file mode 100644 index 0000000000..fb2ed3fa2d --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c @@ -0,0 +1,32 @@ +/** @file + Long jump implementation of RISC-V + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BaseLibInternals.h" + + +/** + Restores the CPU context that was saved with SetJump(). + + Restores the CPU context from the buffer specified by JumpBuffer. + This function never returns to the caller. + Instead is resumes execution based on the state of JumpBuffer. + + @param JumpBuffer A pointer to CPU context buffer. + @param Value The value to return when the SetJump() context is = restored. + +**/ +VOID +EFIAPI +InternalLongJump ( + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, + IN UINTN Value + ) +{ + ASSERT (FALSE); +} + diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/FlushCache.S new file mode 100644 index 0000000000..7c10fdd268 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -0,0 +1,21 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V cache operation. +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +.align 3 +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm) +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) + +ASM_PFX(RiscVInvalidateInstCacheAsm): + fence.i + ret + +ASM_PFX(RiscVInvalidateDataCacheAsm): + fence + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/L= ibrary/BaseLib/RiscV64/RiscVCpuBreakpoint.S new file mode 100644 index 0000000000..ccf91df816 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------= ------ +// +// CpuBreakpoint for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint) +ASM_PFX(RiscVCpuBreakpoint): + ebreak + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Librar= y/BaseLib/RiscV64/RiscVCpuPause.S new file mode 100644 index 0000000000..6660c2fcb3 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------= ------ +// +// CpuPause for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVCpuPause) +ASM_PFX(RiscVCpuPause): + nop + ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S new file mode 100644 index 0000000000..766fcfb9cb --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -0,0 +1,32 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V Supervisor Mode interrupt enable/disable +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts) +ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) +ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts) + +# define MSTATUS_SIE 0x00000002 +# define CSR_SSTATUS 0x100 + +ASM_PFX(RiscVDisableSupervisorModeInterrupts): + li a1, MSTATUS_SIE + csrc CSR_SSTATUS, a1 + ret + +ASM_PFX(RiscVEnableSupervisorModeInterrupt): + li a1, MSTATUS_SIE + csrs CSR_SSTATUS, a1 + ret + +ASM_PFX(RiscVGetSupervisorModeInterrupts): + csrr a0, CSR_SSTATUS + andi a0, a0, MSTATUS_SIE + ret + diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg= /Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S new file mode 100644 index 0000000000..34486eabba --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------= ------ +// +// Set/Long jump for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +# define REG_S sd +# define REG_L ld +# define SZREG 8 +.align 3 + .globl SetJump + +SetJump: + REG_S ra, 0*SZREG(a0) + REG_S s0, 1*SZREG(a0) + REG_S s1, 2*SZREG(a0) + REG_S s2, 3*SZREG(a0) + REG_S s3, 4*SZREG(a0) + REG_S s4, 5*SZREG(a0) + REG_S s5, 6*SZREG(a0) + REG_S s6, 7*SZREG(a0) + REG_S s7, 8*SZREG(a0) + REG_S s8, 9*SZREG(a0) + REG_S s9, 10*SZREG(a0) + REG_S s10, 11*SZREG(a0) + REG_S s11, 12*SZREG(a0) + REG_S sp, 13*SZREG(a0) + li a0, 0 + ret + + .globl InternalLongJump +InternalLongJump: + REG_L ra, 0*SZREG(a0) + REG_L s0, 1*SZREG(a0) + REG_L s1, 2*SZREG(a0) + REG_L s2, 3*SZREG(a0) + REG_L s3, 4*SZREG(a0) + REG_L s4, 5*SZREG(a0) + REG_L s5, 6*SZREG(a0) + REG_L s6, 7*SZREG(a0) + REG_L s7, 8*SZREG(a0) + REG_L s8, 9*SZREG(a0) + REG_L s9, 10*SZREG(a0) + REG_L s10, 11*SZREG(a0) + REG_L s11, 12*SZREG(a0) + REG_L sp, 13*SZREG(a0) + + add a0, s0, 0 + add a1, s1, 0 + add a2, s2, 0 + add a3, s3, 0 + ret --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57194): https://edk2.groups.io/g/devel/message/57194 Mute This Topic: https://groups.io/mt/72916361/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57195+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57195+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505553; cv=none; d=zohomail.com; s=zohoarc; b=gCKOkRmQSaxGCzF0NJ6RvcrqDDbzoNCPecG4z+L65ix0DCiDtVkNQ++DfUfjdb0TgxYuvuEi4PERzmNw3GMJfoJSqy1jGqCXpg43nHsjMakHSY0WE4ez2lDPX1GhcR0VOKZuM7ZEYGXY5DLw1BXiZE4qy5KMLeELNFwSdmMYD5k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505553; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=y23uDpmVSG5K2uCUuSaqGQ5TmstbZ7emj5j+xuxIVp4=; b=CVeYSVQ/IhYhhLfj8TriDXGpsClFMvMAXQmiUitHizsnhu0c3lszn3HRYegoVRWPbMPRtw3r5sd7WxGu7KZENsZ5sIuheXLsP4uvQWVRhhI4+LsLm7A5YnTmvXQFqKk4rm5p7m/Gtpeg20LqQm7stX3js5qnekKr+xNeJx2XvYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57195+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505553940502.21971965402076; Fri, 10 Apr 2020 00:59:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VWv7YY1788612xjJiVuJALdm; Fri, 10 Apr 2020 00:59:13 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5059.1586505552965315956 for ; Fri, 10 Apr 2020 00:59:13 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7wXri009909; Fri, 10 Apr 2020 07:59:12 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 30a5ehwygu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:12 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id D00D765; Fri, 10 Apr 2020 07:59:11 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 78F0B39; Fri, 10 Apr 2020 07:59:10 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 4/9] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Date: Fri, 10 Apr 2020 15:21:07 +0800 Message-Id: <20200410072112.7310-5-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: bFC4Df3851Rs5AaoWCjxUpfix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505553; bh=0IZVPkVavgU/7drYh9/C+hsSvULILlOAPNH0v1qJQ74=; h=Cc:Date:From:Reply-To:Subject:To; b=L+YoZoC7KvxwZR4jcR66lReuKDz0VapVU6Hwlvm+OSsnvox9U/jYIUzpaojgBbWszT6 X3KtMeCb2N9l6zpPRe4ouk7SztWJdd0YB8+okas8656qPUoLeGfAuhMdu6lgkJCrfGQac 3hHj7EQqfL/64VdpAnW4hwvbV1WwU6PwtGM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Implement RISC-V cache maintenance functions in BaseCacheMaintenanceLib. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- .../BaseCacheMaintenanceLib.inf | 4 + .../BaseCacheMaintenanceLib/RiscVCache.c | 250 ++++++++++++++++++ 2 files changed, 254 insertions(+) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index ec7feecf9c..33114243d5 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -6,6 +6,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +42,9 @@ [Sources.AARCH64] ArmCache.c =20 +[Sources.RISCV64] + RiscVCache.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c new file mode 100644 index 0000000000..21a695c843 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -0,0 +1,250 @@ +/** @file + RISC-V specific functionality for cache. + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + RISC-V invalidate instruction cache. + +**/ +VOID +EFIAPI +RiscVInvalidateInstCacheAsm ( + VOID + ); + +/** + RISC-V invalidate data cache. + +**/ +VOID +EFIAPI +RiscVInvalidateDataCacheAsm ( + VOID + ); + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + RiscVInvalidateInstCacheAsm (); +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} + +/** + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); +} + +/** + Writes back and invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes back and invalidates the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} + +/** + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); +} + +/** + Writes back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + RiscVInvalidateDataCacheAsm (); +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, then no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + return Address; +} --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57195): https://edk2.groups.io/g/devel/message/57195 Mute This Topic: https://groups.io/mt/72916362/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57196+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57196+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505555; cv=none; d=zohomail.com; s=zohoarc; b=cX4jcVMPhHgY89kM0pLc5MyhjbXi3+hEPudz/l1efGmJGzRDMtnvFeRh3vuTTtXT4hy8aA4FXv+4V0Dksc4PdR7tBiVgKa+n6ZwzkutCIbrExZcaxInJYdu1wObwdVtQaqzrL6gXSZFpl2Q892dDgaY3HOEKG82J90xjf6eBgH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505555; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=U4rLznd6RYQyj0lFfSbXL4nIfT3zkcieh1HIxf5mtwg=; b=f1CXCWDCXFmwfn/5WpOXS/kE9zIscZ1RNs3T0Y7rfxivxIMd0/vXLe3T62XbP6U5SUQCsWx9mWPSD8Eyl2PzWMM8+4wKaG6VYL2dhuD0srUWri5amrSZ45OZ7ehXogN3mmbxnGZKsvHy+siqMGuTrdozD6wAqtw/K6fpV2iPVtQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57196+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505555379731.7230034817992; Fri, 10 Apr 2020 00:59:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id wL7cYY1788612xksocOD5BS8; Fri, 10 Apr 2020 00:59:15 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5061.1586505554623644634 for ; Fri, 10 Apr 2020 00:59:14 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7tJNB012397; Fri, 10 Apr 2020 07:59:14 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 3091nt420j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:14 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 85F6481; Fri, 10 Apr 2020 07:59:13 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 2BEE93A; Fri, 10 Apr 2020 07:59:12 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 5/9] MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=>IoLibNoIo.c Date: Fri, 10 Apr 2020 15:21:08 +0800 Message-Id: <20200410072112.7310-6-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: m9GF5HlIElbNbvTFEGop2Wyqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505555; bh=unCaMq9SMdMfmCmPuPHMkCul0uik+kkazyrJU4EauL0=; h=Cc:Date:From:Reply-To:Subject:To; b=c9eH37KIVl+3QV/GWM6Ab4edpwWWWKC7EFZER+1LjuEUq2kmGQNPqSGDxPeUadOAeUm wRcSq8SEnP1JKqQ+g0jnqOcynZuq9RZeIyN+vabMS20TyzQqd4hXhgZeEY1BeUrozygDq c4fwKbZVmvVnNR5/HjPYBX8vfFp2kDr3kPU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" RISC-V MMIO library instance. IoLibArm.c in fact implements a generic Mmio-only (and ANSI C compliant), so rename it to better reflect this. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 12 ++++++++---- .../BaseIoLibIntrinsic/{IoLibArm.c =3D> IoLibNoIo.c} | 4 +++- 2 files changed, 11 insertions(+), 5 deletions(-) rename MdePkg/Library/BaseIoLibIntrinsic/{IoLibArm.c =3D> IoLibNoIo.c} (94= %) diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/Mde= Pkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf index 457cce9378..cc23b6b227 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf @@ -4,11 +4,12 @@ # I/O Library that uses compiler intrinsics to perform IN and OUT instruc= tions # for IA-32 and x64. On IPF, I/O port requests are translated into MMIO = requests. # MMIO requests are forwarded directly to memory. For EBC, I/O port requ= ests -# ASSERT(). +# ASSERT(). This I/O library only provides non I/O read and write. # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@ =20 =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources] @@ -50,10 +51,13 @@ IoLib.c =20 [Sources.ARM] - IoLibArm.c + IoLibNoIo.c =20 [Sources.AARCH64] - IoLibArm.c + IoLibNoIo.c + +[Sources.RISCV64] + IoLibNoIo.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c b/MdePkg/Library/= BaseIoLibIntrinsic/IoLibNoIo.c similarity index 94% rename from MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c rename to MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c index c6b822461d..a107136a74 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c @@ -1,9 +1,11 @@ /** @file - I/O Library for ARM. + I/O library for non I/O read and write access (memory map I/O read and + write only) architecture, such as ARM and RISC-V processor. =20 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57196): https://edk2.groups.io/g/devel/message/57196 Mute This Topic: https://groups.io/mt/72916363/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57197+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57197+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505556; cv=none; d=zohomail.com; s=zohoarc; b=Lh59W2wcDTPmTgHtrCOqBRn5c9qXz/vSD+yXIN/bPOXtOo30W4aYYmKjczb7/ice39E4IHU3bBSTf1KFvcbphp7HuoXzX4D3o6NWnax/3FdnUgDDZqhxU8A77P6+tI5kAJVUc19VvXevABurXr5eERHIIYx1L9J6OqiTLSYxgDs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505556; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5mTAHEd7kkppxerade7+WYyZjHiuimiiS7mcInVGrmM=; b=XX4WuKejgKw8uVsupLpvmrMNhVlhDeAOzYbHoMWmDRsuaT4mzbaOlAlHfaDdA/IW7OOFQU1KvAoQyUwhUG6PhXG/T/ojW+kbAWWtz0obldvpfxLkSnCjniwQbOmfp/WTqLm5lwL1dpow1116bxk+Linc5LAJlmtSs98fKwvqt40= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57197+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505556715578.3653704479118; Fri, 10 Apr 2020 00:59:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2DkBYY1788612xzlRAC0VuOf; Fri, 10 Apr 2020 00:59:16 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5062.1586505556025684764 for ; Fri, 10 Apr 2020 00:59:16 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7ur3c000569; Fri, 10 Apr 2020 07:59:15 GMT X-Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 3091pkm0rr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:15 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 3A7DEAC; Fri, 10 Apr 2020 07:59:15 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id D4FFB39; Fri, 10 Apr 2020 07:59:13 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 6/9] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code. Date: Fri, 10 Apr 2020 15:21:09 +0800 Message-Id: <20200410072112.7310-7-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: tAK5wBLDV32B1wjekJDoj7t0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505556; bh=0oWLW6FHXVeDQFs6W7Ud/Ope0I6OSwI++oPevmwQ/78=; h=Cc:Date:From:Reply-To:Subject:To; b=tBHhURHUHbXL9D0JR5bvNyopaj5CHicVDSX3V9THBSG8QpTb7xBCfrxF29Bkoc5SI1W XFrgs8/AK2ov68PfCXxQk9g/ZfAHuSE0lJjaVAalwQ0Kav31ulZCgrHjWhuRwatTucGkA C1SmCASdZgBZ5Iyg70vGyE2b4i+NNghQ7ME= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Support RISC-V image relocation. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- .../Library/BasePeCoffLib/BasePeCoffLib.inf | 5 + .../BasePeCoffLib/BasePeCoffLibInternals.h | 9 ++ MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +- .../BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 133 ++++++++++++++++++ .../Library/BasePeCoffLib/BasePeCoffLib.uni | 2 + 5 files changed, 151 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.inf index 395c1403c0..110b6d5a09 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf @@ -3,6 +3,7 @@ # The IPF version library supports loading IPF and EBC PE/COFF image. # The IA32 version library support loading IA32, X64 and EBC PE/COFF imag= es. # The X64 version library support loading IA32, X64 and EBC PE/COFF image= s. +# The RISC-V version library support loading RISC-V images. # # Caution: This module requires additional review when modified. # This library will have external input - PE/COFF image. @@ -11,6 +12,7 @@ # # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9 @@ [Sources.ARM] Arm/PeCoffLoaderEx.c =20 +[Sources.RISCV64] + RiscV/PeCoffLoaderEx.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg= /Library/BasePeCoffLib/BasePeCoffLibInternals.h index b74277f3e8..3ee56e0e5f 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h @@ -2,6 +2,7 @@ Declaration of internal functions in PE/COFF Lib. =20 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. = All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -16,6 +17,14 @@ #include #include =20 +// +// Macro definitions for RISC-V architecture. +// +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RISCV_IMM_BITS 12 +#define RISCV_IMM_REACH (1LL< Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. = All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/L= ibrary/BasePeCoffLib/RiscV/PeCoffLoaderEx.c new file mode 100644 index 0000000000..23170a6603 --- /dev/null +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c @@ -0,0 +1,133 @@ +/** @file + PE/Coff loader for RISC-V PE image + + Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. = All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include "BasePeCoffLibInternals.h" +#include + +/** + Performs an RISC-V specific relocation fixup and is a no-op on + other instruction sets. + RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation + types. We have to know the lower 12-bit fixup first then we can deal + carry over on high 20-bit fixup. So we log the high 20-bit in + FixupData. + + @param Reloc The pointer to the relocation record. + @param Fixup The pointer to the address to fix up. + @param FixupData The pointer to a buffer to log the fixups. + @param Adjust The offset to adjust the fixup. + + @return Status code. + +**/ +RETURN_STATUS +PeCoffLoaderRelocateImageEx ( + IN UINT16 *Reloc, + IN OUT CHAR8 *Fixup, + IN OUT CHAR8 **FixupData, + IN UINT64 Adjust + ) +{ + UINT32 Value; + UINT32 Value2; + UINT32 *RiscVHi20Fixup; + + switch ((*Reloc) >> 12) { + case EFI_IMAGE_REL_BASED_RISCV_HI20: + *(UINT64 *)(*FixupData) =3D (UINT64)(UINTN)Fixup; + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12I: + RiscVHi20Fixup =3D (UINT32 *)(*(UINT64 *)(*FixupData)); + if (RiscVHi20Fixup !=3D NULL) { + + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) |\ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + *(UINT32 *)Fixup =3D (RV_X (Value, 0, 12) << 20) |\ + (RV_X (*(UINT32 *)Fixup, 0, 20)); + } + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12S: + RiscVHi20Fixup =3D (UINT32 *)(*(UINT64 *)(*FixupData)); + if (RiscVHi20Fixup !=3D NULL) { + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 = *)Fixup, 25, 7) << 5)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |=3D ~(RISCV_IMM_REACH-1); + } + Value +=3D Value2; + Value +=3D (UINT32)Adjust; + Value2 =3D RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12)); + Value2 =3D *(UINT32 *)Fixup & 0x01fff07f; + Value &=3D RISCV_IMM_REACH - 1; + *(UINT32 *)Fixup =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |= (RV_X(Value, 5, 7) << 25))); + } + break; + + default: + return RETURN_UNSUPPORTED; + + } + return RETURN_SUCCESS; +} + +/** + Returns TRUE if the machine type of PE/COFF image is supported. Supported + does not mean the image can be executed it means the PE/COFF loader supp= orts + loading and relocating of the image type. It's up to the caller to suppo= rt + the entry point. + + @param Machine Machine type from the PE Header. + + @return TRUE if this PE/COFF loader can load the image + +**/ +BOOLEAN +PeCoffLoaderImageFormatSupported ( + IN UINT16 Machine + ) +{ + if (Machine =3D=3D IMAGE_FILE_MACHINE_RISCV64) { + return TRUE; + } + + return FALSE; +} + +/** + Performs an Itanium-based specific re-relocation fixup and is a no-op on= other + instruction sets. This is used to re-relocated the image into the EFI vi= rtual + space for runtime calls. + + @param Reloc The pointer to the relocation record. + @param Fixup The pointer to the address to fix up. + @param FixupData The pointer to a buffer to log the fixups. + @param Adjust The offset to adjust the fixup. + + @return Status code. + +**/ +RETURN_STATUS +PeHotRelocateImageEx ( + IN UINT16 *Reloc, + IN OUT CHAR8 *Fixup, + IN OUT CHAR8 **FixupData, + IN UINT64 Adjust + ) +{ + return RETURN_UNSUPPORTED; +} diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.uni index b0ea702f76..55417029f2 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni @@ -4,6 +4,7 @@ // The IPF version library supports loading IPF and EBC PE/COFF image. // The IA32 version library support loading IA32, X64 and EBC PE/COFF imag= es. // The X64 version library support loading IA32, X64 and EBC PE/COFF image= s. +// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COF= F images. // // Caution: This module requires additional review when modified. // This library will have external input - PE/COFF image. @@ -12,6 +13,7 @@ // // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57197): https://edk2.groups.io/g/devel/message/57197 Mute This Topic: https://groups.io/mt/72916364/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57200+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57200+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505581; cv=none; d=zohomail.com; s=zohoarc; b=cnf/cmnQWa3zlsilR1TmY2I8S+HaUbC+imImkcTUMVI+ajz+rJA9Xq3vB0oeZRizyLNMLv4ntYcL5eSq86lX6RaCCQDyvVtqpzHP6CLY9kRD2lVjWR/WDuDAcehS0rlMlJq0xLQi29Do82gHQ6CQrqh0GM0bY3xzJ+GWJEmGovM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505581; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=oTMSDsXad0OciDed/i6/PfEWXjCrFnJ4Ucv3Ly/rsMQ=; b=OGfXHJlC17m4EZUkpZwl0W2nsZimS2ukOxbUdoU+6APlEog6AlbvrjSj5FqQEmxVsKMldcd/8di6QBvyEq+mY1SgYun2dMNP0DCVbvkOEonUaFe+G6vbmls00RquN00vTXGHqYQjKccJPVbHqWV+GUbgUKkn6EZbaW4PotRTbrk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57200+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505581150492.99338593747996; Fri, 10 Apr 2020 00:59:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id yineYY1788612xFPeNGWvp9O; Fri, 10 Apr 2020 00:59:40 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.5063.1586505580205824353 for ; Fri, 10 Apr 2020 00:59:40 -0700 X-Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7xdwK009719; Fri, 10 Apr 2020 07:59:39 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 3091n0m2n4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:39 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id E25BD65; Fri, 10 Apr 2020 07:59:16 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 89AF63A; Fri, 10 Apr 2020 07:59:15 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 7/9] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation. Date: Fri, 10 Apr 2020 15:21:10 +0800 Message-Id: <20200410072112.7310-8-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: rD3NOdCx0aIIx7IDvxqNVrClx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505580; bh=EccB2qTDmwXe4YZ6RFZWnJccTGKrG+wXVDvb2UANL0s=; h=Cc:Date:From:Reply-To:Subject:To; b=aRisFhLV91ePbXlaNK+b9taaeqlIRufZVKADMQiLbaIyMvCK+l0WcKZBJrRC9TYRXb2 RW/x7QSpDlk1cB3Zg+qn//Xbfu7+GeQHtG+mflEs/WANBQg+1wZ1bP8KNNsTKRvGdYlW0 GuXwsO8FIiXQ8bCbxdgkGIYUE5JncGfa9DM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Implement RISC-V CPU related functions in BaseCpuLib. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++- MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++-- MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++ 3 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index a7cb381a85..950f5229b2 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -7,6 +7,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -24,7 +25,7 @@ =20 =20 # -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 # =20 [Sources.IA32] @@ -59,6 +60,9 @@ AArch64/CpuFlushTlb.asm | MSFT AArch64/CpuSleep.asm | MSFT =20 +[Sources.RISCV64] + RiscV/Cpu.S + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/Base= CpuLib/BaseCpuLib.uni index fc95cda9fc..80dc495786 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni @@ -1,12 +1,13 @@ // /** @file // Instance of CPU Library for various architecture. // -// CPU Library implemented using ASM functions for IA-32 and X64, +// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, // PAL CALLs for IPF, and empty functions for EBC. // // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -15,5 +16,5 @@ =20 #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU L= ibrary for various architectures" =20 -#string STR_MODULE_DESCRIPTION #language en-US "CPU Library imple= mented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty = functions for EBC." +#string STR_MODULE_DESCRIPTION #language en-US "CPU Library imple= mented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, a= nd empty functions for EBC." =20 diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpu= Lib/RiscV/Cpu.S new file mode 100644 index 0000000000..375b91d314 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S @@ -0,0 +1,19 @@ +//------------------------------------------------------------------------= ------ +// +// CpuSleep for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +.data +.align 3 +.section .text + +.global ASM_PFX(_CpuSleep) + +ASM_PFX(_CpuSleep): + wfi + ret + + --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57200): https://edk2.groups.io/g/devel/message/57200 Mute This Topic: https://groups.io/mt/72916367/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57198+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57198+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505560; cv=none; d=zohomail.com; s=zohoarc; b=WLm3KTpVyrSdzZuGRw5XExxG9IT2XEMpaXE5jjK6azrQe5XLLt/zT203Wgyywc+ozUCRPheiB0IoP+TPNi+X12cSTB4zvZ9NWcNyii7hNlu+TUuRwKyfbUPo4UsbxbsI6aJJUOCj0WuoGClhQzwrqCBKKDdY3vh/JrBxeLFFkQA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505560; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NoDQKsxQOufdZzfYcxYYJgAbGQ4+ApZ+urOUOH89bsU=; b=iohJ9oSge+II0+LP+1YRHC/nRUrpdZp3cVIzH5xSgFqfFY/5nD0BVAYlOrsRvhp7KB9eZNh845lPhptsNM7hpdTnvMVfstuel+HwqvQQJkhV5kqcc2AMRtP4xqKSUEsRxGUw9ocEtA/mGJKXMh2RelNL79Gm62TbYRw7Y9CZM4c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57198+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505560373261.17168603962205; Fri, 10 Apr 2020 00:59:20 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id fNj8YY1788612xqsUC6wIlTe; Fri, 10 Apr 2020 00:59:20 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.5090.1586505559640193090 for ; Fri, 10 Apr 2020 00:59:19 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7wYAu009963; Fri, 10 Apr 2020 07:59:19 GMT X-Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 30a5ehwyhc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:19 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 98BBBAF; Fri, 10 Apr 2020 07:59:18 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 3F3F03A; Fri, 10 Apr 2020 07:59:17 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v1 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code. Date: Fri, 10 Apr 2020 15:21:11 +0800 Message-Id: <20200410072112.7310-9-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: eN6bQDxS6q1Rh90BmKjCqtvex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505560; bh=QOSdK/MtdLFu4f9frWOk7o4eQuFiqual93iyqt5HHAY=; h=Cc:Date:From:Reply-To:Subject:To; b=mfRI5xhb+Y+HtPYmR6j7s906pdyL3NMMoffQ0hPnpTbkg1wpBQp3sPGGIgD60hAvuRa C3eHPfRzEpNgGlHvZBAzDyG0mquWJ7+YCfvu1ThlPbGzKBUqfvozwI5IZlJGb6g60fmle X4JdPJ3rSX4LEUPorR9t3E91SHX2et/o0ro= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Support RISC-V cache related functions. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Reviewed-by: Zhiguang Liu --- .../BaseSynchronizationLib.inf | 5 ++ .../RiscV64/SynchronizationAsm.S | 78 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zationAsm.S diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 446bc19b63..9309d2e1d5 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +79,10 @@ AArch64/Synchronization.S | GCC AArch64/Synchronization.asm | MSFT =20 +[Sources.RISCV64] + Synchronization.c + RiscV64/SynchronizationAsm.S + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationA= sm.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S new file mode 100644 index 0000000000..bac80d6871 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V synchronization functions. +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(InternalSyncCompareExchange32) +.global ASM_PFX(InternalSyncCompareExchange64) +.global ASM_PFX(InternalSyncIncrement) +.global ASM_PFX(InternalSyncDecrement) + +// +// ompare and xchange a 32-bit value. +// +// @param a0 : Pointer to 32-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (InternalSyncCompareExchange32): + lr.w a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.w a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit: + mv a0, a3 + ret + +.global ASM_PFX(InternalSyncCompareExchange64) + +// +// Compare and xchange a 64-bit value. +// +// @param a0 : Pointer to 64-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (SyncCompareExchange64): + lr.d a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.d a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit2: + mv a0, a3 + ret + +// +// Performs an atomic increment of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (InternalSyncIncrement): + li a1, 1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret + +// +// Performs an atomic decrement of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (InternalSyncDecrement): + li a1, -1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57198): https://edk2.groups.io/g/devel/message/57198 Mute This Topic: https://groups.io/mt/72916365/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 05:15:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+57199+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57199+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1586505562; cv=none; d=zohomail.com; s=zohoarc; b=PhWuc8E3/5bitpmzZJvTMlmrk9lA+GD08aEN+AEWDrNysbQ2VoCQxhkJ3ibjiIXcqNTcNy0P5gd2PeOvznI4+DRbAFPW1IJGruiCOQf9Oe7s9cBacCFSF9/dBUFNb7pfznODn2IMn8nhRbTX2fcM6HQXd4Ju2QFmlGwyZDzmP0c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586505562; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jRN7UGZjF0gAwUewSOjt/Ic/gvecRsc5pxKt2LbC1bQ=; b=XG4bF11jWO48NC/UkwgiESodIOEhJdM2CLq5aK5TUWEK03DRSw8uyt3ipC6IyaCYOEZIJuQTVJZ5hXG0psGsA3xcxoSBerm6zyjxGTfScaENG5zgFVXwgs/mU/NlsQ6nlFo31nNAokWF9yGzA0nqjLFDsdGHbdCzXdH4byKxDsU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+57199+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1586505562409145.5325104206072; Fri, 10 Apr 2020 00:59:22 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8uWnYY1788612xR5bZ3xkI0b; Fri, 10 Apr 2020 00:59:22 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.4999.1586505561735706470 for ; Fri, 10 Apr 2020 00:59:21 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7tJoF012422; Fri, 10 Apr 2020 07:59:21 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 3091nt4218-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:21 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id AE8FF77; Fri, 10 Apr 2020 07:59:20 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id E987C3B; Fri, 10 Apr 2020 07:59:18 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Leif Lindholm , Michael D Kinney , Liming Gao , Leif Lindholm , Gilbert Chen , Daniel Helmut Schaefer Subject: [edk2-devel] [PATCH v1 9/9] MdePkg/BaseSafeIntLib: Add RISCV64 arch for BaseSafeIntLib. Date: Fri, 10 Apr 2020 15:21:12 +0800 Message-Id: <20200410072112.7310-10-abner.chang@hpe.com> In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: CxnSKA2jlf2apcfd6zLnn7WMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1586505562; bh=EDwGnAt7nfivHtIwTcx+mPQYxIQE0Q8ZssDLBgwCR/I=; h=Cc:Date:From:Reply-To:Subject:To; b=Q3Y4VUUukF7Lta7DLW8f8f1kkq1xtyN4QdIYmCCSvguOqSjS11LAfTOepXcdrOYCXA7 tUmLRqxKLBnQEfBNGy23LRYNKYRnOUXMkcmHUd+dyjyko69OknejCu1Z55n8fUHdEredt yaakyZ/h209y0kieMVsjGyev4P45NiLOHmc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add RISCV64 arch for BaseSafeIntLib library. Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen Cc: Daniel Helmut Schaefer --- MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf b/MdePkg/Libr= ary/BaseSafeIntLib/BaseSafeIntLib.inf index 68ade962d6..40017ec88b 100644 --- a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf +++ b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf @@ -6,6 +6,8 @@ # # Copyright (c) 2018, Intel Corporation. All rights reserved.
# Copyright (c) 2017, Microsoft Corporation +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+ # # All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -23,7 +25,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64 # =20 [Sources] @@ -32,7 +34,7 @@ [Sources.Ia32, Sources.ARM] SafeIntLib32.c =20 -[Sources.X64, Sources.AARCH64] +[Sources.X64, Sources.AARCH64, Sources.RISCV64] SafeIntLib64.c =20 [Sources.EBC] --=20 2.25.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#57199): https://edk2.groups.io/g/devel/message/57199 Mute This Topic: https://groups.io/mt/72916366/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-