From nobody Fri Mar 29 07:12:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+56068+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+56068+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1584810470; cv=none; d=zohomail.com; s=zohoarc; b=iyy0KzKtO4EoBw4YHK1uGONqm4g05VlCXk6RQQH/PR/GsCbetm7dNk1hwx1a3xJG616HeLpmh///eHUigV9O30v3K5ENRQmLl+vzvas3TpnU93cpPfZTGSJPng+wnGE5LgIsDLmna7grLH8FjrmSpO5/Y7c5z5JLZDPg6xRTtZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584810470; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=D/eAvKBlIGP59Sg/KMRudw3QDTZFc9HEsBcjbzBKnp4=; b=NhWROqRIA2EKj1zltuHVe0rA0Z3vFOQ2N1SRZ4iW9Yogria0JcDtYa0ikPgrSFGYcggxSKKw5DT0FEAZB4VNLimp7rJBj5WiImTekTyg2Lv0OnQRfSdmhMcrGrcOxHLHxdFKKSDNsokoLWi3Fb5H67yRaTTqUUUNECA8vd0H2MY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+56068+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1584810470596805.9437817137936; Sat, 21 Mar 2020 10:07:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id IX8sYY1788612x57jSvRO2TZ; Sat, 21 Mar 2020 10:07:50 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.12336.1584810469766332861 for ; Sat, 21 Mar 2020 10:07:49 -0700 IronPort-SDR: 65eqccBMCp5fIkTGixwW56pfHbyevnPoXNe1jwS9XmP0P7JyTWFi2rqxiPLm6S3TI4DnNiuFwX GIe6W+D3JQ/A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2020 10:07:49 -0700 IronPort-SDR: n3xkqAKvlGiA7LjoJl58o/W+roxde+Uu/JkWjRgRyr9syOf6X7/ttiz5ER3VXyrSkzrRWxYPST z3HBIioVXlmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,289,1580803200"; d="scan'208";a="234811086" X-Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.37]) by orsmga007.jf.intel.com with ESMTP; 21 Mar 2020 10:07:46 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH V2 1/2] MdePkg-IndustryStandard: CXL 1.1 Base Specification registers Date: Sat, 21 Mar 2020 22:37:25 +0530 Message-Id: <20200321170726.9760-2-ashraf.javeed@intel.com> In-Reply-To: <20200321170726.9760-1-ashraf.javeed@intel.com> References: <20200321170726.9760-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: PIvsOTWGNrm8hJawsFSSJcCAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1584810470; bh=pm3vlrr7j3eDbVdASVsGwpxL7VIan2D/Y9hexUTpkKk=; h=Cc:Date:From:Reply-To:Subject:To; b=JWdktTVr9rQMvLO7PWI2Fh/jCTrpHagzP4RHSY0PqWo1YQliBbhoaxnsjoMDIJVHaSl vSFx9OB6kbOQxU9wdln6b9KEdPKaCczZCYLEbjgXeRjARBseM1l/oMnSpapwq33lf2z5y iOQ1yQdHwo1jUGv9ms7u8BaWAyTmHmeuh8Q= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2611 Register definitions from chapter 7 of CXL Base Specification Rev.1.1 are ported into the new Cxl11.h. The CXL Flex Bus registers are based on the PCIe Extended Capability DVSEC structure headers, hence the Pci.h has to upgraded. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao --- MdePkg/Include/IndustryStandard/Cxl11.h | 526 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++ MdePkg/Include/IndustryStandard/Pci.h | 1 + 2 files changed, 527 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/Cxl11.h b/MdePkg/Include/Indus= tryStandard/Cxl11.h new file mode 100644 index 0000000000..65c900142e --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl11.h @@ -0,0 +1,526 @@ +/** @file + CXL 1.1 Register definitions + + This file contains the register definitions based on the Compute Express= Link + (CXL) Base Specification Revision 1.1. + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CXL11_H_ +#define _CXL11_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// The PCIe DVSEC for Flex Bus device +/// +typedef union { + struct { + UINT16 CacheCapable : 1; // bi= t 0 + UINT16 IoCapable : 1; // bi= t 1 + UINT16 MemCapable : 1; // bi= t 2 + UINT16 MemHwInitMode : 1; // bi= t 3 + UINT16 HdmCount : 2; // bi= t 4..5 + UINT16 Reserved1 : 8; // bi= t 6..13 + UINT16 ViralCapable : 1; // bi= t 14 + UINT16 Reserved2 : 1; // bi= t 15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bi= t 0 + UINT16 IoEnable : 1; // bi= t 1 + UINT16 MemEnable : 1; // bi= t 2 + UINT16 CacheSfCoverage : 5; // bi= t 3..7 + UINT16 CacheSfGranularity : 3; // bi= t 8..10 + UINT16 CacheCleanEviction : 1; // bi= t 11 + UINT16 Reserved1 : 2; // bi= t 12..13 + UINT16 ViralEnable : 1; // bi= t 14 + UINT16 Reserved2 : 1; // bi= t 15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL; + +typedef union { + struct { + UINT16 Reserved1 : 14; // b= it 0..13 + UINT16 ViralStatus : 1; // b= it 14 + UINT16 Reserved2 : 1; // b= it 15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS; + +typedef union { + struct { + UINT16 Reserved1 : 1; // b= it 0 + UINT16 Reserved2 : 1; // b= it 1 + UINT16 Reserved3 : 1; // b= it 2 + UINT16 Reserved4 : 13; // b= it 3..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2; + +typedef union { + struct { + UINT16 Reserved1 : 1; // b= it 0 + UINT16 Reserved2 : 1; // b= it 1 + UINT16 Reserved3 : 14; // b= it 2..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2; + +typedef union { + struct { + UINT16 ConfigLock : 1; // b= it 0 + UINT16 Reserved1 : 15; // b= it 1..15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK; + +typedef union { + struct { + UINT32 MemorySizeHigh : 32; // b= it 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH; + +typedef union { + struct { + UINT32 MemoryInfoValid : 1; // b= it 0 + UINT32 MemoryActive : 1; // b= it 1 + UINT32 MediaType : 3; // b= it 2..4 + UINT32 MemoryClass : 3; // b= it 5..7 + UINT32 DesiredInterleave : 3; // b= it 8..10 + UINT32 Reserved : 17; // b= it 11..27 + UINT32 MemorySizeLow : 4; // b= it 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW; + +typedef union { + struct { + UINT32 MemoryBaseHigh : 32; // b= it 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH; + +typedef union { + struct { + UINT32 Reserved : 28; // b= it 0..27 + UINT32 MemoryBaseLow : 4; // b= it 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW; + + +typedef union { + struct { + UINT32 MemorySizeHigh : 32; // b= it 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH; + +typedef union { + struct { + UINT32 MemoryInfoValid : 1; // b= it 0 + UINT32 MemoryActive : 1; // b= it 1 + UINT32 MediaType : 3; // b= it 2..4 + UINT32 MemoryClass : 3; // b= it 5..7 + UINT32 DesiredInterleave : 3; // b= it 8..10 + UINT32 Reserved : 17; // b= it 11..27 + UINT32 MemorySizeLow : 4; // b= it 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW; + +typedef union { + struct { + UINT32 MemoryBaseHigh : 32; // b= it 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH; + +typedef union { + struct { + UINT32 Reserved : 28; // b= it 0..27 + UINT32 MemoryBaseLow : 4; // b= it 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; = // offset 0 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 Designated= VendorSpecificHeader1; // offset 4 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 Designated= VendorSpecificHeader2; // offset 8 + CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DvsecFlexB= usDeviceCapability; // offset 10 + CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DvsecFlexB= usDeviceControl; // offset 12 + CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DvsecFlexB= usDeviceStatus; // offset 14 + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DvsecFlexB= usDeviceControl2; // offset 16 + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DvsecFlexB= usDeviceStatus2; // offset 18 + CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DvsecFlexB= usDeviceLock; // offset 20 + UINT16 Reserved; = // offset 22 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DvsecFlexB= usDeviceRange1SizeHigh; // offset 24 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DvsecFlexB= usDeviceRange1SizeLow; // offset 28 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DvsecFlexB= usDeviceRange1BaseHigh; // offset 32 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DvsecFlexB= usDeviceRange1BaseLow; // offset 36 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DvsecFlexB= usDeviceRange2SizeHigh; // offset 40 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DvsecFlexB= usDeviceRange2SizeLow; // offset 44 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DvsecFlexB= usDeviceRange2BaseHigh; // offset 48 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DvsecFlexB= usDeviceRange2BaseLow; // offset 52 +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE; + +/// +/// PCIe DVSEC for FLex Bus Port +/// +typedef union { + struct { + UINT16 CacheCapable : 1; // b= it 0 + UINT16 IoCapable : 1; // b= it 1 + UINT16 MemCapable : 1; // b= it 2 + UINT16 Reserved : 13; // b= it 3..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bi= t 0 + UINT16 IoEnable : 1; // bi= t 1 + UINT16 MemEnable : 1; // bi= t 2 + UINT16 CxlSyncBypassEnable : 1; // bi= t 3 + UINT16 DriftBufferEnable : 1; // bi= t 4 + UINT16 Reserved : 3; // bi= t 5..7 + UINT16 Retimer1Present : 1; // bi= t 8 + UINT16 Retimer2Present : 1; // bi= t 9 + UINT16 Reserved2 : 6; // bi= t 10..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bi= t 0 + UINT16 IoEnable : 1; // bi= t 1 + UINT16 MemEnable : 1; // bi= t 2 + UINT16 CxlSyncBypassEnable : 1; // bi= t 3 + UINT16 DriftBufferEnable : 1; // bi= t 4 + UINT16 Reserved : 3; // bi= t 5..7 + UINT16 CxlCorrectableProtocolIdFramingError : 1; // bi= t 8 + UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bi= t 9 + UINT16 CxlUnexpectedProtocolIdDropped : 1; // bi= t 10 + UINT16 Reserved2 : 5; // bi= t 11..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; = // offset 0 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 Designated= VendorSpecificHeader1; // offset 4 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 Designated= VendorSpecificHeader2; // offset 8 + CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY DvsecFlexB= usPortCapability; // offset 10 + CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL DvsecFlexB= usPortControl; // offset 12 + CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS DvsecFlexB= usPortStatus; // offset 14 +} CXL_1_1_DVSEC_FLEX_BUS_PORT; + +/// +/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers +/// + +/// The CXL.Cache and CXL.Memory Architectural register definitions +/// Based on section 7.2.2 of CXL Base Specification Rev. 1.1 +///@{ + +#define CXL_CAPABILITY_HEADER_OFFSET 0 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // b= it 0..15 + UINT32 CxlCapabilityVersion : 4; // b= it 16..19 + UINT32 CxlCacheMemVersion : 4; // b= it 20..23 + UINT32 ArraySize : 8; // b= it 24..31 + } Bits; + UINT32 Uint32; +} CXL_CAPABILITY_HEADER; + +#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // b= it 0..15 + UINT32 CxlCapabilityVersion : 4; // b= it 16..19 + UINT32 CxlRasCapabilityPointer : 12; // b= it 20..31 + } Bits; + UINT32 Uint32; +} CXL_RAS_CAPABILITY_HEADER; + +#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // b= it 0..15 + UINT32 CxlCapabilityVersion : 4; // b= it 16..19 + UINT32 CxlSecurityCapabilityPointer : 12; // b= it 20..31 + } Bits; + UINT32 Uint32; +} CXL_SECURITY_CAPABILITY_HEADER; + +#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // b= it 0..15 + UINT32 CxlCapabilityVersion : 4; // b= it 16..19 + UINT32 CxlLinkCapabilityPointer : 12; // b= it 20..31 + } Bits; + UINT32 Uint32; +} CXL_LINK_CAPABILITY_HEADER; + +typedef union { + struct { + UINT32 CacheDataParity : 1; // b= it 0..0 + UINT32 CacheAddressParity : 1; // b= it 1..1 + UINT32 CacheByteEnableParity : 1; // b= it 2..2 + UINT32 CacheDataEcc : 1; // b= it 3..3 + UINT32 MemDataParity : 1; // b= it 4..4 + UINT32 MemAddressParity : 1; // b= it 5..5 + UINT32 MemByteEnableParity : 1; // b= it 6..6 + UINT32 MemDataEcc : 1; // b= it 7..7 + UINT32 ReInitThreshold : 1; // b= it 8..8 + UINT32 RsvdEncodingViolation : 1; // b= it 9..9 + UINT32 PoisonReceived : 1; // b= it 10..10 + UINT32 ReceiverOverflow : 1; // b= it 11..11 + UINT32 Reserved : 20; // b= it 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_STATUS; + +typedef union { + struct { + UINT32 CacheDataParityMask : 1; // b= it 0..0 + UINT32 CacheAddressParityMask : 1; // b= it 1..1 + UINT32 CacheByteEnableParityMask : 1; // b= it 2..2 + UINT32 CacheDataEccMask : 1; // b= it 3..3 + UINT32 MemDataParityMask : 1; // b= it 4..4 + UINT32 MemAddressParityMask : 1; // b= it 5..5 + UINT32 MemByteEnableParityMask : 1; // b= it 6..6 + UINT32 MemDataEccMask : 1; // b= it 7..7 + UINT32 ReInitThresholdMask : 1; // b= it 8..8 + UINT32 RsvdEncodingViolationMask : 1; // b= it 9..9 + UINT32 PoisonReceivedMask : 1; // b= it 10..10 + UINT32 ReceiverOverflowMask : 1; // b= it 11..11 + UINT32 Reserved : 20; // b= it 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_MASK; + +typedef union { + struct { + UINT32 CacheDataParitySeverity : 1; // b= it 0..0 + UINT32 CacheAddressParitySeverity : 1; // b= it 1..1 + UINT32 CacheByteEnableParitySeverity : 1; // b= it 2..2 + UINT32 CacheDataEccSeverity : 1; // b= it 3..3 + UINT32 MemDataParitySeverity : 1; // b= it 4..4 + UINT32 MemAddressParitySeverity : 1; // b= it 5..5 + UINT32 MemByteEnableParitySeverity : 1; // b= it 6..6 + UINT32 MemDataEccSeverity : 1; // b= it 7..7 + UINT32 ReInitThresholdSeverity : 1; // b= it 8..8 + UINT32 RsvdEncodingViolationSeverity : 1; // b= it 9..9 + UINT32 PoisonReceivedSeverity : 1; // b= it 10..10 + UINT32 ReceiverOverflowSeverity : 1; // b= it 11..11 + UINT32 Reserved : 20; // b= it 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY; + +typedef union { + struct { + UINT32 CacheDataEcc : 1; // b= it 0..0 + UINT32 MemoryDataEcc : 1; // b= it 1..1 + UINT32 CrcThreshold : 1; // b= it 2..2 + UINT32 RetryThreshold : 1; // b= it 3..3 + UINT32 CachePoisonReceived : 1; // b= it 4..4 + UINT32 MemoryPoisonReceived : 1; // b= it 5..5 + UINT32 PhysicalLayerError : 1; // b= it 6..6 + UINT32 Reserved : 25; // b= it 7..31 + } Bits; + UINT32 Uint32; +} CXL_CORRECTABLE_ERROR_STATUS; + +typedef union { + struct { + UINT32 CacheDataEccMask : 1; // b= it 0..0 + UINT32 MemoryDataEccMask : 1; // b= it 1..1 + UINT32 CrcThresholdMask : 1; // b= it 2..2 + UINT32 RetryThresholdMask : 1; // b= it 3..3 + UINT32 CachePoisonReceivedMask : 1; // b= it 4..4 + UINT32 MemoryPoisonReceivedMask : 1; // b= it 5..5 + UINT32 PhysicalLayerErrorMask : 1; // b= it 6..6 + UINT32 Reserved : 25; // b= it 7..31 + } Bits; + UINT32 Uint32; +} CXL_CORRECTABLE_ERROR_MASK; + +typedef union { + struct { + UINT32 FirstErrorPointer : 4; // b= it 0..3 + UINT32 Reserved1 : 5; // b= it 4..8 + UINT32 MultipleHeaderRecordingCapability : 1; // b= it 9..9 + UINT32 Reserved2 : 3; // b= it 10..12 + UINT32 PoisonEnabled : 1; // b= it 13..13 + UINT32 Reserved3 : 18; // b= it 14..31 + } Bits; + UINT32 Uint32; +} CXL_ERROR_CAPABILITIES_AND_CONTROL; + +typedef struct { + CXL_1_1_UNCORRECTABLE_ERROR_STATUS HeaderLog[= 16]; +} CXL_HEADER_LOG; + +typedef struct { + CXL_1_1_UNCORRECTABLE_ERROR_STATUS Uncorrecta= bleErrorStatus; // offset 0 + CXL_1_1_UNCORRECTABLE_ERROR_MASK Uncorrecta= bleErrorMask; // offset 4 + CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY Uncorrecta= bleErrorSeverity; // offset 8 + CXL_CORRECTABLE_ERROR_STATUS Correctabl= eErrorStatus; // offset 12 + CXL_CORRECTABLE_ERROR_MASK Correctabl= eErrorMask; // offset 16 + CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapab= ilitiesAndControl; // offset 20 + CXL_HEADER_LOG HeaderLog;= // offset 24 +} CXL_1_1_RAS_CAPABILITY_STRUCTURE; + +typedef union { + struct { + UINT32 DeviceTrustLevel : 2; // b= it 0..1 + UINT32 Reserved : 30; // b= it 2..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_SECURITY_POLICY; + +typedef struct { + CXL_1_1_SECURITY_POLICY SecurityPo= licy; +} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE; + +typedef union { + struct { + UINT64 CxlLinkVersionSupported : 4; // b= it 0..3 + UINT64 CxlLinkVersionReceived : 4; // b= it 4..7 + UINT64 LlrWrapValueSupported : 8; // b= it 8..15 + UINT64 LlrWrapValueReceived : 8; // b= it 16..23 + UINT64 NumRetryReceived : 5; // b= it 24..28 + UINT64 NumPhyReinitReceived : 5; // b= it 29..33 + UINT64 WrPtrReceived : 8; // b= it 34..41 + UINT64 EchoEseqReceived : 8; // b= it 42..49 + UINT64 NumFreeBufReceived : 8; // b= it 50..57 + UINT64 Reserved : 6; // b= it 58..63 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_CAPABILITY; + +typedef union { + struct { + UINT16 LlReset : 1; // b= it 0..0 + UINT16 LlInitStall : 1; // b= it 1..1 + UINT16 LlCrdStall : 1; // b= it 2..2 + UINT16 InitState : 2; // b= it 3..4 + UINT16 LlRetryBufferConsumed : 8; // b= it 5..12 + UINT16 Reserved : 3; // b= it 13..15 + } Bits; + UINT16 Uint16; +} CXL_LINK_LAYER_CONTROL_AND_STATUS; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // b= it 0..9 + UINT64 CacheRspCredits : 10; // b= it 10..19 + UINT64 CacheDataCredits : 10; // b= it 20..29 + UINT64 MemReqRspCredits : 10; // b= it 30..39 + UINT64 MemDataCredits : 10; // b= it 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_RX_CREDIT_CONTROL; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // b= it 0..9 + UINT64 CacheRspCredits : 10; // b= it 10..19 + UINT64 CacheDataCredits : 10; // b= it 20..29 + UINT64 MemReqRspCredits : 10; // b= it 30..39 + UINT64 MemDataCredits : 10; // b= it 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // b= it 0..9 + UINT64 CacheRspCredits : 10; // b= it 10..19 + UINT64 CacheDataCredits : 10; // b= it 20..29 + UINT64 MemReqRspCredits : 10; // b= it 30..39 + UINT64 MemDataCredits : 10; // b= it 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_TX_CREDIT_STATUS; + +typedef union { + struct { + UINT32 AckForceThreshold : 8; // b= it 0..7 + UINT32 AckFLushRetimer : 10; // b= it 8..17 + } Bits; + UINT32 Uint32; +} CXL_LINK_LAYER_ACK_TIMER_CONTROL; + +typedef union { + struct { + UINT32 MdhDisable : 1; // b= it 0..0 + UINT32 Reserved : 31; // b= it 1..31 + } Bits; + UINT32 Uint32; +} CXL_LINK_LAYER_DEFEATURE; + +typedef struct { + CXL_LINK_LAYER_CAPABILITY LinkLayerC= apability; // offset 0 + CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerC= ontrolStatus; // offset 8 + CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerR= xCreditControl; // offset 10 + CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerR= xCreditReturnStatus; // offset 18 + CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerT= xCreditStatus; // offset 26 + CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerA= ckTimerControl; // offset 34 + CXL_LINK_LAYER_DEFEATURE LinkLayerD= efeature; // offset 38 +} CXL_1_1_LINK_CAPABILITY_STRUCTURE; + +#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180 +typedef union { + struct { + UINT32 Reserved1 : 4; // b= it 0..3 + UINT32 WeightedRoundRobinArbitrationWeight : 4; // b= it 4..7 + UINT32 Reserved2 : 24; // b= it 8..31 + } Bits; + UINT32 Uint32; +} CXL_IO_ARBITRATION_CONTROL; + +#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0 +typedef union { + struct { + UINT32 Reserved1 : 4; // b= it 0..3 + UINT32 WeightedRoundRobinArbitrationWeight : 4; // b= it 4..7 + UINT32 Reserved2 : 24; // b= it 8..31 + } Bits; + UINT32 Uint32; +} CXL_CACHE_MEMORY_ARBITRATION_CONTROL; +///@} + +typedef union { + struct { + UINT64 RcrbEnable : 1; // b= it 0..0 + UINT64 Reserved : 12; // b= it 1..12 + UINT64 RcrbBaseAddress : 51; // b= it 13..63 + } Bits; + UINT64 Uint64; +} CXL_RCRB_BASE; + +#pragma pack() + +#endif diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/Industr= yStandard/Pci.h index 8ed96b992a..86da00d4ed 100644 --- a/MdePkg/Include/IndustryStandard/Pci.h +++ b/MdePkg/Include/IndustryStandard/Pci.h @@ -12,6 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include =20 #endif --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#56068): https://edk2.groups.io/g/devel/message/56068 Mute This Topic: https://groups.io/mt/72449750/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 07:12:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+56069+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+56069+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1584810474; cv=none; d=zohomail.com; s=zohoarc; b=mLU/RBMtPaWihWkRA53vyxTTJZ3APVjTc5yCCb34E87lKqEO0SK/u4Ii1IqdLYpXWwt5nnUNumKBS7NkoQME3WVDSPzQxPZLXWjNeGB48RN2pD0wZ1Pj1LtBrMoUPqPcfbJWY8xyXUN1C4J9NVqH5tQtAydXwwDupV4hCYWKSN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584810474; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=CgFXV0MYPsZCkyblLGQsc4u1BhpDX7CIH1LvwledQps=; b=H1b889QGFg6efpdIvvJaxf3AjzSqIX9L02RJdp9k7TVt1jFWQfwVjUU8RC3yv3NXP3Dw0FOz+BRLdOC8A2XNHz7K1KiO+9zqi4XhdfWH2C6tSewmiW2zFnYA+TTj12jDJvdfb7TzuBC1uqI0QDffGme1RNcnhHumyZnnX9z0Hyc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+56069+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1584810474006305.9431976907547; Sat, 21 Mar 2020 10:07:54 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id upLBYY1788612xGUQs2nHF5m; Sat, 21 Mar 2020 10:07:53 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web10.12336.1584810469766332861 for ; Sat, 21 Mar 2020 10:07:53 -0700 IronPort-SDR: Wsl3Cb0OaSHG5Gq7ONXJpN7s1f7a1L22WUxc3UIqOssQZpobdKBsWitZIHy8gZOxPLHCsZQkI3 LLaqR5sdDRoA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2020 10:07:52 -0700 IronPort-SDR: DdJkMINCsoR/Hx1WabfdtExaBb3a/HcTiM30DMYolnrBznH+jA+dKfwVEHqS6cmt470lZoeiyI B97oFiFsIQGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,289,1580803200"; d="scan'208";a="234811110" X-Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.37]) by orsmga007.jf.intel.com with ESMTP; 21 Mar 2020 10:07:51 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao Subject: =?UTF-8?B?W2VkazItZGV2ZWxdIFtQQVRDSCBWMiAyLzJdIO+7v01kZVBrZy1JbmR1c3RyeVN0YW5kYXJkOiBDWEwgMS4xIEJhc2UgU3BlY2lmaWNhdGlvbiByZWdpc3RlcnM=?= Date: Sat, 21 Mar 2020 22:37:26 +0530 Message-Id: <20200321170726.9760-3-ashraf.javeed@intel.com> In-Reply-To: <20200321170726.9760-1-ashraf.javeed@intel.com> References: <20200321170726.9760-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: gCvwwyyin1LsZKnny0toudxDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1584810473; bh=gYUy04kxi3Sgi0UnqhGJ0Mkc9Kgyy2bwC1j2gUn96rM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=dz1QjbJGWbr3zhaWJdrovyQ3mU+vXEhMrmHY+atFZHige6oHJxU3MFR6Sc4kJEgvJ7A +dwOqkOH0Enjk29Gulw4ZLPJfxgXcdXVn5MXsvlknnnVWkuko5jLx2uyFLLI09IiKLjgU ATTlheLJoAZHODNz5RZtF58/Z7ugGniO51A= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2611 Introducing the Cxl.h as the main header file to support all versions of CXL Base Specification register definitions. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao --- MdePkg/Include/IndustryStandard/Cxl.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/Industr= yStandard/Cxl.h new file mode 100644 index 0000000000..d945fcbda2 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl.h @@ -0,0 +1,18 @@ +/** @file + Support for the latest CXL standard + + The main header to reference all versions of CXL Base specification regi= sters + from the MDE + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CXL_H_ +#define _CXL_H_ + +#include + +#endif + --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#56069): https://edk2.groups.io/g/devel/message/56069 Mute This Topic: https://groups.io/mt/72449752/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-