From nobody Wed May 8 10:56:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55639+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55639+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583572218; cv=none; d=zohomail.com; s=zohoarc; b=HHJZLc/HZF6U/JzaV0vKd36PCvYhanRpyeyH5eoSKJiWqECasAmwJLgTFmewkN5OMPHpXKP3V2px6dH52xW3FPG+4b9pziR90KwPW0dhuMXHi7nx8nYRql8RSaKGU/wW+C9vcYNRJFEH5AYFmaogZB9eWllgkho9hg88aq5bCkY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583572218; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=D7WTK+No1Il8VJEK0FChHDTudQWZfgdcLt9nTqUXze0=; b=KSMl0amsE8+wjpZdjfK8TgvO7k7US37S+FMnOl7XbR9ZUjVY8oipVwnHH/grtpjFLA8+DirSoT5paaTS39zVHn2V+qIr8/9AHFqPdVMnCTptI82ygJc9UmXrkKQ/cfxqRUvgJ/6TLp2KvmQA3wLrY0s4uBA0QJ8ikrfkDSRs4ww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55639+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583572218046248.29138916518366; Sat, 7 Mar 2020 01:10:18 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id hCBRYY1788612xxmK2ScPMq7; Sat, 07 Mar 2020 01:10:17 -0800 X-Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web10.11042.1583572217031546124 for ; Sat, 07 Mar 2020 01:10:17 -0800 X-Received: by mail-wm1-f67.google.com with SMTP id n8so917441wmc.4 for ; Sat, 07 Mar 2020 01:10:16 -0800 (PST) X-Gm-Message-State: V18nZ2JVZVhvBIF2kZbAQp4bx1787277AA= X-Google-Smtp-Source: ADFU+vs3IPz3d8KHhU64TbjFqhw+wUtjXnU4KIEejTMi5XjKEAQrInPEyYpPbDEcZ9ZudZIF+hFZwg== X-Received: by 2002:a05:600c:2241:: with SMTP id a1mr8810338wmm.59.1583572214996; Sat, 07 Mar 2020 01:10:14 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id i204sm17088429wma.44.2020.03.07.01.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Mar 2020 01:10:14 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 1/2] ArmPkg/ArmMmuLib AARCH64: drop pointless page table memory type check Date: Sat, 7 Mar 2020 10:10:07 +0100 Message-Id: <20200307091008.14918-2-ard.biesheuvel@linaro.org> In-Reply-To: <20200307091008.14918-1-ard.biesheuvel@linaro.org> References: <20200307091008.14918-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583572217; bh=Ko7DJ2Kw0D/UoSABu4SapZ7fhpWJcajXHpGrIF55Djc=; h=Cc:Date:From:Reply-To:Subject:To; b=Mgx9vAuwlWiaC/eDacOb5HH8WiZNkwE9+0uhcwU3JjXD1aO0XlFeiwxOZ+YInvxxD2O 5uyUhb/a37b8Mgu4j14MtEXpUYk+RKd0lXHOgmil0OgKDSwomL74A41dJKPIJOKosLVqf RKOwFf6cWCKiHWifJKxMXfW//LfRXKM8K2c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is the AARCH64 counterpart of commit 1f3b1eb3082206e4, to remove a pointless check against the memory type of the allocations that the page tables happened to land in. On ArmV8, we use writeback cacheable exclusively for all memory. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 221175ca6535..f2eec7191328 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -497,7 +497,6 @@ ArmConfigureMmu ( ) { VOID* TranslationTable; - UINT32 TranslationTableAttribute; UINT64 MaxAddress; UINTN T0SZ; UINTN RootTableEntryCount; @@ -618,18 +617,7 @@ ArmConfigureMmu ( RootTableEntryCount * sizeof(UINT64)); ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); =20 - TranslationTableAttribute =3D TT_ATTR_INDX_INVALID; while (MemoryTable->Length !=3D 0) { - - DEBUG_CODE_BEGIN (); - // Find the memory attribute for the Translation Table - if ((UINTN)TranslationTable >=3D MemoryTable->PhysicalBase && - (UINTN)TranslationTable + EFI_PAGE_SIZE <=3D MemoryTable->Physic= alBase + - MemoryTable->Len= gth) { - TranslationTableAttribute =3D MemoryTable->Attributes; - } - DEBUG_CODE_END (); - Status =3D FillTranslationTable (TranslationTable, MemoryTable); if (EFI_ERROR (Status)) { goto FREE_TRANSLATION_TABLE; @@ -637,9 +625,6 @@ ArmConfigureMmu ( MemoryTable++; } =20 - ASSERT (TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE_WRI= TE_BACK || - TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE_NON= SECURE_WRITE_BACK); - ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMOR= Y) | // mapped to EFI_MEMORY_UC MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMA= L_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMA= L_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55639): https://edk2.groups.io/g/devel/message/55639 Mute This Topic: https://groups.io/mt/71792475/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 8 10:56:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55640+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55640+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583572219; cv=none; d=zohomail.com; s=zohoarc; b=MsAiv2+RCyGwXfLqvEFeQQJvf4nlQeH7s46UjcXM7WF5fQdHfkL7SABpEXcDx6hR9aYpsM4XtyQLugx0We7vAoO9OkKyupiE2URcZVXxRudifFcsFlTuY0nFX1nL+8oflsYEUSQC7PZscpyTkl+QithYzRCsFSs7u0ELAoMHFJ8= ARC-Message-Signature: i=1; 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Sat, 07 Mar 2020 01:10:18 -0800 X-Received: by mail-wm1-f65.google.com with SMTP id p9so4946842wmc.2 for ; Sat, 07 Mar 2020 01:10:18 -0800 (PST) X-Gm-Message-State: OD4VNC5XqyIrcBzwElvptbbmx1787277AA= X-Google-Smtp-Source: ADFU+vvEH9SvKkqbM/EKjUOjKHSSOCKImc0ji7pA0cRUFoW5tJ1Ac1cbu6N8JSgUeJq5x2SVmnLD2A== X-Received: by 2002:a1c:a9cf:: with SMTP id s198mr8540780wme.115.1583572216505; Sat, 07 Mar 2020 01:10:16 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id i204sm17088429wma.44.2020.03.07.01.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Mar 2020 01:10:15 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 2/2] ArmPkg/ArmMmuLib AARCH64: cosmetic fixups Date: Sat, 7 Mar 2020 10:10:08 +0100 Message-Id: <20200307091008.14918-3-ard.biesheuvel@linaro.org> In-Reply-To: <20200307091008.14918-1-ard.biesheuvel@linaro.org> References: <20200307091008.14918-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583572219; bh=WcOA+LVDQIfl2HkzUruVXinBA1QCzzkQCMOaFu2irS0=; h=Cc:Date:From:Reply-To:Subject:To; b=cAMlZA0pv8doBBlXUKhEH69wJkqrd+EDmr/2i1goXcMwLDQKqj9V/CGZM/9PfRWvmdM fnCpQrpmbKvFJkRDkLMOjJH9p8hobNJoVvw86q168eIm9hv7YSazgihUTf3Izah7PWrDk /4KXQHn+V+jNVvqLo/JB59Yj23i5wZYHYks= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some cosmetic fixups to the AArch64 MMU code: - reflow overly long lines unless it hurts legibility - add/remove whitespace according to the [de facto] coding style - use camel case for goto labels Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 56 +++++++++++++------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index f2eec7191328..a43d468b73ca 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -47,7 +47,7 @@ ArmMemoryAttributeToPageAttribute ( return TT_ATTR_INDX_MEMORY_NON_CACHEABLE; =20 default: - ASSERT(0); + ASSERT (0); case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE: if (ArmReadCurrentEL () =3D=3D AARCH64_EL2) @@ -78,7 +78,9 @@ PageAttributeToGcdAttribute ( GcdAttributes =3D EFI_MEMORY_WB; break; default: - DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%l= X not supported.\n", PageAttributes)); + DEBUG ((DEBUG_ERROR, + "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", + PageAttributes)); ASSERT (0); // The Global Coherency Domain (GCD) value is defined as a bit set. // Returning 0 means no attribute has been set. @@ -86,13 +88,14 @@ PageAttributeToGcdAttribute ( } =20 // Determine protection attributes - if (((PageAttributes & TT_AP_MASK) =3D=3D TT_AP_NO_RO) || ((PageAttribut= es & TT_AP_MASK) =3D=3D TT_AP_RO_RO)) { + if (((PageAttributes & TT_AP_MASK) =3D=3D TT_AP_NO_RO) || + ((PageAttributes & TT_AP_MASK) =3D=3D TT_AP_RO_RO)) { // Read only cases map to write-protect GcdAttributes |=3D EFI_MEMORY_RO; } =20 // Process eXecute Never attribute - if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) !=3D 0 ) { + if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) !=3D 0) { GcdAttributes |=3D EFI_MEMORY_XP; } =20 @@ -503,7 +506,7 @@ ArmConfigureMmu ( UINT64 TCR; EFI_STATUS Status; =20 - if(MemoryTable =3D=3D NULL) { + if (MemoryTable =3D=3D NULL) { ASSERT (MemoryTable !=3D NULL); return EFI_INVALID_PARAMETER; } @@ -544,7 +547,9 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) { TCR |=3D TCR_PS_256TB; } else { - DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not s= upported by this MMU configuration.\n", MaxAddress)); + DEBUG ((DEBUG_ERROR, + "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MM= U configuration.\n", + MaxAddress)); ASSERT (0); // Bigger than 48-bit memory space are not supported return EFI_UNSUPPORTED; } @@ -566,7 +571,9 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) { TCR |=3D TCR_IPS_256TB; } else { - DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not s= upported by this MMU configuration.\n", MaxAddress)); + DEBUG ((DEBUG_ERROR, + "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MM= U configuration.\n", + MaxAddress)); ASSERT (0); // Bigger than 48-bit memory space are not supported return EFI_UNSUPPORTED; } @@ -596,9 +603,12 @@ ArmConfigureMmu ( if (TranslationTable =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; } - // We set TTBR0 just after allocating the table to retrieve its location= from the subsequent - // functions without needing to pass this value across the functions. Th= e MMU is only enabled - // after the translation tables are populated. + // + // We set TTBR0 just after allocating the table to retrieve its location= from + // the subsequent functions without needing to pass this value across the + // functions. The MMU is only enabled after the translation tables are + // populated. + // ArmSetTTBR0 (TranslationTable); =20 if (TranslationTableBase !=3D NULL) { @@ -606,7 +616,7 @@ ArmConfigureMmu ( } =20 if (TranslationTableSize !=3D NULL) { - *TranslationTableSize =3D RootTableEntryCount * sizeof(UINT64); + *TranslationTableSize =3D RootTableEntryCount * sizeof (UINT64); } =20 // @@ -614,21 +624,29 @@ ArmConfigureMmu ( // when populating the page tables. // InvalidateDataCacheRange (TranslationTable, - RootTableEntryCount * sizeof(UINT64)); - ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); + RootTableEntryCount * sizeof (UINT64)); + ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64)); =20 while (MemoryTable->Length !=3D 0) { Status =3D FillTranslationTable (TranslationTable, MemoryTable); if (EFI_ERROR (Status)) { - goto FREE_TRANSLATION_TABLE; + goto FreeTranslationTable; } MemoryTable++; } =20 - ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMOR= Y) | // mapped to EFI_MEMORY_UC - MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMA= L_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC - MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMA= L_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT - MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_M= EMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB + // + // EFI_MEMORY_UC =3D=3D> MAIR_ATTR_DEVICE_MEMORY + // EFI_MEMORY_WC =3D=3D> MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE + // EFI_MEMORY_WT =3D=3D> MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH + // EFI_MEMORY_WB =3D=3D> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK + // + ArmSetMAIR ( + MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY)= | + MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_= NON_CACHEABLE) | + MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_= WRITE_THROUGH) | + MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_= WRITE_BACK) + ); =20 ArmDisableAlignmentCheck (); ArmEnableStackAlignmentCheck (); @@ -638,7 +656,7 @@ ArmConfigureMmu ( ArmEnableMmu (); return EFI_SUCCESS; =20 -FREE_TRANSLATION_TABLE: +FreeTranslationTable: FreePages (TranslationTable, 1); return Status; } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55640): https://edk2.groups.io/g/devel/message/55640 Mute This Topic: https://groups.io/mt/71792476/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-