From nobody Wed May 1 05:13:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55603+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55603+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583511185; cv=none; d=zohomail.com; s=zohoarc; b=U3ewFggOdVDavAx2M9VqWdvUfFYL4S4YyATq1gR3v20oWOKYVDdovftu2upXlMmuUe2U5kcWUvrzLCQsE2zjI34bX8AJV5fxnKjZhXKQRytjLWZhBveRG1By7NIMgn2B0XbFfNV407Dhp0NxQ26AShKlFLcmEJj/YU76BbiawNc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583511185; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=6NUOmHMzuvDt53ZPOqdc9pCHVVA/V+DFVeC/p1O1COA=; b=NTtdZDlIVPFTddSkGRiizq9sfKQpy2Xphr5QgHMIyFygNUFok6ag2/KLl20V67F3i/JKCZvHwatPkot1+rBWBCt9G0NZugz4k3Wx6wfA8GmRXe4+j5pHHny0CQ4PBw1gy1VFjaMsKCk1yMpOtIYb8oVObDwdB7Nf4ASVNUFyALs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55603+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583511185422242.9739874001849; Fri, 6 Mar 2020 08:13:05 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id IulVYY1788612xn3gTH2Tq9c; Fri, 06 Mar 2020 08:13:05 -0800 X-Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.groups.io with SMTP id smtpd.web10.14956.1583511184070558812 for ; Fri, 06 Mar 2020 08:13:04 -0800 X-Received: by mail-wm1-f53.google.com with SMTP id p9so3079532wmc.2 for ; Fri, 06 Mar 2020 08:13:03 -0800 (PST) X-Gm-Message-State: P8Sc2cYaUHFLfKuAjBp1RqFTx1787277AA= X-Google-Smtp-Source: ADFU+vtQUXx80xrfJ9DHZS9g5r0J7ugdHHZ7ubCfVNfDhaga/MqtDDS90SMIkV/dcZNoC8tOIor/Uw== X-Received: by 2002:a05:600c:54f:: with SMTP id k15mr4599999wmc.96.1583511181584; Fri, 06 Mar 2020 08:13:01 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id f8sm6745287wmf.20.2020.03.06.08.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2020 08:12:59 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v3 1/2] ArmPkg/ArmMmuLib AARCH64: rewrite page table code Date: Fri, 6 Mar 2020 17:12:45 +0100 Message-Id: <20200306161246.6392-2-ard.biesheuvel@linaro.org> In-Reply-To: <20200306161246.6392-1-ard.biesheuvel@linaro.org> References: <20200306161246.6392-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583511185; bh=tXBgI+O0W6IP996bfrd/P8HRck/goRJy/ixpwnmbLww=; h=Cc:Date:From:Reply-To:Subject:To; b=WQblmB96xLyGDRLQDGp3rRb3IGsGrfRfGy9NqekQKC72AMRHZmfDg899UwZZJtVXxNF sc7GpaaUxNdIV0VpHMFb7Ngx6u96YZR8Qo6VoJqXGYMDWJm+h0ZgUcZLqRc7QykqG5wgB 7A7dETaiOT7sK+vofNTWjvoPKhllIJ6ONKA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Replace the slightly overcomplicated page table management code with a simplified, recursive implementation that should be far easier to reason about. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 332 +++++++------------- 1 file changed, 108 insertions(+), 224 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 204e33c75f95..e36594fea3ad 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -121,14 +121,16 @@ GetRootTranslationTableInfo ( =20 STATIC VOID -ReplaceLiveEntry ( +ReplaceTableEntry ( IN UINT64 *Entry, IN UINT64 Value, - IN UINT64 RegionStart + IN UINT64 RegionStart, + IN BOOLEAN IsLiveBlockMapping ) { - if (!ArmMmuEnabled ()) { + if (!ArmMmuEnabled () || !IsLiveBlockMapping) { *Entry =3D Value; + ArmUpdateTranslationTableEntry (Entry, (VOID *)(UINTN)RegionStart); } else { ArmReplaceLiveTranslationEntry (Entry, Value, RegionStart); } @@ -165,229 +167,132 @@ LookupAddresstoRootTable ( } =20 STATIC -UINT64* -GetBlockEntryListFromAddress ( - IN UINT64 *RootTable, - IN UINT64 RegionStart, - OUT UINTN *TableLevel, - IN OUT UINT64 *BlockEntrySize, - OUT UINT64 **LastBlockEntry +EFI_STATUS +UpdateRegionMappingRec ( + IN UINT64 RegionStart, + IN UINT64 RegionEnd, + IN UINT64 AttributeSetMask, + IN UINT64 AttributeClearMask, + IN UINT64 *PageTable, + IN UINTN Level ) { - UINTN RootTableLevel; - UINTN RootTableEntryCount; - UINT64 *TranslationTable; - UINT64 *BlockEntry; - UINT64 *SubTableBlockEntry; - UINT64 BlockEntryAddress; - UINTN BaseAddressAlignment; - UINTN PageLevel; - UINTN Index; - UINTN IndexLevel; - UINTN T0SZ; - UINT64 Attributes; - UINT64 TableAttributes; - - // Initialize variable - BlockEntry =3D NULL; - - // Ensure the parameters are valid - if (!(TableLevel && BlockEntrySize && LastBlockEntry)) { - ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); - return NULL; - } - - // Ensure the Region is aligned on 4KB boundary - if ((RegionStart & (SIZE_4KB - 1)) !=3D 0) { - ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); - return NULL; - } - - // Ensure the required size is aligned on 4KB boundary and not 0 - if ((*BlockEntrySize & (SIZE_4KB - 1)) !=3D 0 || *BlockEntrySize =3D=3D = 0) { - ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); - return NULL; - } - - T0SZ =3D ArmGetTCR () & TCR_T0SZ_MASK; - // Get the Table info from T0SZ - GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount= ); - - // If the start address is 0x0 then we use the size of the region to ide= ntify the alignment - if (RegionStart =3D=3D 0) { - // Identify the highest possible alignment for the Region Size - BaseAddressAlignment =3D LowBitSet64 (*BlockEntrySize); - } else { - // Identify the highest possible alignment for the Base Address - BaseAddressAlignment =3D LowBitSet64 (RegionStart); - } - - // Identify the Page Level the RegionStart must belong to. Note that Pag= eLevel - // should be at least 1 since block translations are not supported at le= vel 0 - PageLevel =3D MAX (3 - ((BaseAddressAlignment - 12) / 9), 1); - - // If the required size is smaller than the current block size then we n= eed to go to the page below. - // The PageLevel was calculated on the Base Address alignment but did no= t take in account the alignment - // of the allocation size - while (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) { - // It does not fit so we need to go a page level above - PageLevel++; - } - - // - // Get the Table Descriptor for the corresponding PageLevel. We need to = decompose RegionStart to get appropriate entries - // - - TranslationTable =3D RootTable; - for (IndexLevel =3D RootTableLevel; IndexLevel <=3D PageLevel; IndexLeve= l++) { - BlockEntry =3D (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, In= dexLevel, RegionStart); - - if ((IndexLevel !=3D 3) && ((*BlockEntry & TT_TYPE_MASK) =3D=3D TT_TYP= E_TABLE_ENTRY)) { - // Go to the next table - TranslationTable =3D (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIP= TION_TABLE); - - // If we are at the last level then update the last level to next le= vel - if (IndexLevel =3D=3D PageLevel) { - // Enter the next level - PageLevel++; - } - } else if ((*BlockEntry & TT_TYPE_MASK) =3D=3D TT_TYPE_BLOCK_ENTRY) { - // If we are not at the last level then we need to split this BlockE= ntry - if (IndexLevel !=3D PageLevel) { - // Retrieve the attributes from the block entry - Attributes =3D *BlockEntry & TT_ATTRIBUTES_MASK; - - // Convert the block entry attributes into Table descriptor attrib= utes - TableAttributes =3D TT_TABLE_AP_NO_PERMISSION; - if (Attributes & TT_NS) { - TableAttributes =3D TT_TABLE_NS; + UINTN BlockShift; + UINT64 BlockMask; + UINT64 BlockEnd; + UINT64 *Entry; + UINT64 EntryValue; + VOID *TranslationTable; + EFI_STATUS Status; + + ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) =3D=3D 0); + + BlockShift =3D (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ; + BlockMask =3D MAX_UINT64 >> BlockShift; + + DEBUG ((DEBUG_VERBOSE, "%a(%d): %llx - %llx set %lx clr %lx\n", __FUNCTI= ON__, + Level, RegionStart, RegionEnd, AttributeSetMask, AttributeClearMask)); + + for (; RegionStart < RegionEnd; RegionStart =3D BlockEnd) { + BlockEnd =3D MIN (RegionEnd, (RegionStart | BlockMask) + 1); + Entry =3D &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_CO= UNT - 1)]; + + // + // If RegionStart or BlockEnd is not aligned to the block size at this + // level, we will have to create a table mapping in order to map less + // than a block, and recurse to create the block or page entries at + // the next level. No block mappings are allowed at all at level 0, + // so in that case, we have to recurse unconditionally. + // + if (Level =3D=3D 0 || ((RegionStart | BlockEnd) & BlockMask) !=3D 0) { + ASSERT (Level < 3); + + if ((*Entry & TT_TYPE_MASK) !=3D TT_TYPE_TABLE_ENTRY) { + // + // No table entry exists yet, so we need to allocate a page table + // for the next level. + // + TranslationTable =3D AllocatePages (1); + if (TranslationTable =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; } =20 - // Get the address corresponding at this entry - BlockEntryAddress =3D RegionStart; - BlockEntryAddress =3D BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LE= VEL(IndexLevel); - // Shift back to right to set zero before the effective address - BlockEntryAddress =3D BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LE= VEL(IndexLevel); - - // Set the correct entry type for the next page level - if ((IndexLevel + 1) =3D=3D 3) { - Attributes |=3D TT_TYPE_BLOCK_ENTRY_LEVEL3; + if ((*Entry & TT_TYPE_MASK) =3D=3D TT_TYPE_BLOCK_ENTRY) { + // + // We are splitting an existing block entry, so we have to popul= ate + // the new table with the attributes of the block entry it repla= ces. + // + Status =3D UpdateRegionMappingRec ( + RegionStart & ~BlockMask, + (RegionStart | BlockMask) + 1, + *Entry & TT_ATTRIBUTES_MASK, + 0, + TranslationTable, + Level + 1); + if (EFI_ERROR (Status)) { + return Status; + } } else { - Attributes |=3D TT_TYPE_BLOCK_ENTRY; + ZeroMem (TranslationTable, EFI_PAGE_SIZE); } + } else { + TranslationTable =3D (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOC= K_ENTRY); + } =20 - // Create a new translation table - TranslationTable =3D AllocatePages (1); - if (TranslationTable =3D=3D NULL) { - return NULL; - } - - // Populate the newly created lower level table - SubTableBlockEntry =3D TranslationTable; - for (Index =3D 0; Index < TT_ENTRY_COUNT; Index++) { - *SubTableBlockEntry =3D Attributes | (BlockEntryAddress + (Index= << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1))); - SubTableBlockEntry++; - } + // + // Recurse to the next level + // + Status =3D UpdateRegionMappingRec ( + RegionStart, + BlockEnd, + AttributeSetMask, + AttributeClearMask, + TranslationTable, + Level + 1); + if (EFI_ERROR (Status)) { + return Status; + } =20 - // Fill the BlockEntry with the new TranslationTable - ReplaceLiveEntry (BlockEntry, - (UINTN)TranslationTable | TableAttributes | TT_TYPE_TABLE_ENTRY, - RegionStart); + if ((*Entry & TT_TYPE_MASK) !=3D TT_TYPE_TABLE_ENTRY) { + ReplaceTableEntry (Entry, + (UINT64)TranslationTable | TT_TYPE_TABLE_ENTRY, + RegionStart, + (*Entry & TT_TYPE_MASK) =3D=3D TT_TYPE_BLOCK_ENTRY); } } else { - if (IndexLevel !=3D PageLevel) { - // - // Case when we have an Invalid Entry and we are at a page level a= bove of the one targetted. - // + EntryValue =3D (*Entry & AttributeClearMask) | AttributeSetMask; + EntryValue |=3D RegionStart; + EntryValue |=3D (Level =3D=3D 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3 + : TT_TYPE_BLOCK_ENTRY; =20 - // Create a new translation table - TranslationTable =3D AllocatePages (1); - if (TranslationTable =3D=3D NULL) { - return NULL; - } - - ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64)); - - // Fill the new BlockEntry with the TranslationTable - *BlockEntry =3D ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIP= TION_TABLE) | TT_TYPE_TABLE_ENTRY; - } + ReplaceTableEntry (Entry, EntryValue, RegionStart, FALSE); } } - - // Expose the found PageLevel to the caller - *TableLevel =3D PageLevel; - - // Now, we have the Table Level we can get the Block Size associated to = this table - *BlockEntrySize =3D TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel); - - // The last block of the root table depends on the number of entry in th= is table, - // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table. - *LastBlockEntry =3D TT_LAST_BLOCK_ADDRESS(TranslationTable, - (PageLevel =3D=3D RootTableLevel) ? RootTableEntryCount : TT_ENTRY_C= OUNT); - - return BlockEntry; + return EFI_SUCCESS; } =20 STATIC EFI_STATUS UpdateRegionMapping ( - IN UINT64 *RootTable, - IN UINT64 RegionStart, - IN UINT64 RegionLength, - IN UINT64 Attributes, - IN UINT64 BlockEntryMask + IN UINT64 RegionStart, + IN UINT64 RegionSize, + IN UINT64 AttributeSetMask, + IN UINT64 AttributeClearMask ) { - UINT32 Type; - UINT64 *BlockEntry; - UINT64 *LastBlockEntry; - UINT64 BlockEntrySize; - UINTN TableLevel; + UINTN RootTableLevel; + UINTN T0SZ; =20 - // Ensure the Length is aligned on 4KB boundary - if ((RegionLength =3D=3D 0) || ((RegionLength & (SIZE_4KB - 1)) !=3D 0))= { - ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + if ((RegionStart & EFI_PAGE_MASK) !=3D 0 || (RegionSize & EFI_PAGE_MASK)= !=3D 0) { return EFI_INVALID_PARAMETER; } =20 - do { - // Get the first Block Entry that matches the Virtual Address and also= the information on the Table Descriptor - // such as the size of the Block Entry and the address of the last Blo= ckEntry of the Table Descriptor - BlockEntrySize =3D RegionLength; - BlockEntry =3D GetBlockEntryListFromAddress (RootTable, RegionStart, &= TableLevel, &BlockEntrySize, &LastBlockEntry); - if (BlockEntry =3D=3D NULL) { - // GetBlockEntryListFromAddress() return NULL when it fails to alloc= ate new pages from the Translation Tables - return EFI_OUT_OF_RESOURCES; - } + T0SZ =3D ArmGetTCR () & TCR_T0SZ_MASK; + GetRootTranslationTableInfo (T0SZ, &RootTableLevel, NULL); =20 - if (TableLevel !=3D 3) { - Type =3D TT_TYPE_BLOCK_ENTRY; - } else { - Type =3D TT_TYPE_BLOCK_ENTRY_LEVEL3; - } - - do { - // Fill the Block Entry with attribute and output block address - *BlockEntry &=3D BlockEntryMask; - *BlockEntry |=3D (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attri= butes | Type; - - ArmUpdateTranslationTableEntry (BlockEntry, (VOID *)RegionStart); - - // Go to the next BlockEntry - RegionStart +=3D BlockEntrySize; - RegionLength -=3D BlockEntrySize; - BlockEntry++; - - // Break the inner loop when next block is a table - // Rerun GetBlockEntryListFromAddress to avoid page table memory leak - if (TableLevel !=3D 3 && BlockEntry <=3D LastBlockEntry && - (*BlockEntry & TT_TYPE_MASK) =3D=3D TT_TYPE_TABLE_ENTRY) { - break; - } - } while ((RegionLength >=3D BlockEntrySize) && (BlockEntry <=3D LastBl= ockEntry)); - } while (RegionLength !=3D 0); - - return EFI_SUCCESS; + return UpdateRegionMappingRec (RegionStart, RegionStart + RegionSize, + AttributeSetMask, AttributeClearMask, ArmGetTTBR0BaseAddress (), + RootTableLevel); } =20 STATIC @@ -398,7 +303,6 @@ FillTranslationTable ( ) { return UpdateRegionMapping ( - RootTable, MemoryRegion->VirtualBase, MemoryRegion->Length, ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | = TT_AF, @@ -455,8 +359,6 @@ ArmSetMemoryAttributes ( IN UINT64 Attributes ) { - EFI_STATUS Status; - UINT64 *TranslationTable; UINT64 PageAttributes; UINT64 PageAttributeMask; =20 @@ -473,19 +375,11 @@ ArmSetMemoryAttributes ( TT_PXN_MASK | TT_XN_MASK); } =20 - TranslationTable =3D ArmGetTTBR0BaseAddress (); - - Status =3D UpdateRegionMapping ( - TranslationTable, + return UpdateRegionMapping ( BaseAddress, Length, PageAttributes, PageAttributeMask); - if (EFI_ERROR (Status)) { - return Status; - } - - return EFI_SUCCESS; } =20 STATIC @@ -497,17 +391,7 @@ SetMemoryRegionAttribute ( IN UINT64 BlockEntryMask ) { - EFI_STATUS Status; - UINT64 *RootTable; - - RootTable =3D ArmGetTTBR0BaseAddress (); - - Status =3D UpdateRegionMapping (RootTable, BaseAddress, Length, Attribut= es, BlockEntryMask); - if (EFI_ERROR (Status)) { - return Status; - } - - return EFI_SUCCESS; + return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryM= ask); } =20 EFI_STATUS --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55603): https://edk2.groups.io/g/devel/message/55603 Mute This Topic: https://groups.io/mt/71776543/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 05:13:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55604+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55604+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583511187; cv=none; d=zohomail.com; s=zohoarc; b=Il82hdRim+Ro7oc2+vD97NDjzsXzpyq4P+eHrLz7dz0h14LeSIH5UcHC934AX6VR+4SMcDJSNpgz1TpMh9pOsY+eQBKfYfiFwbtswTKEmrRGHAtcjLkzw2GU8/Ozg07ODFl34VisN/QRe0rkst5l43+R/4C9ldIHVuScO7lQWVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583511187; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=QMz55OA8WZPq+atqDYouEpqaG9Pc87c1+M2H4QxagmE=; b=hf3nUQLZ8CC3lAO6AoJT9yxY1qtKJTny7YjW0GX5t/nXxCNgoghVjxj1Pdib1ebNn5YeSfWLGo2p/95rYp95R1sg2Xxj3Xs2bjvKuhE+YFVbEUuRH9IrBD2AnBwTIvo0J19fSOYUV7pYojAsSxyGKmsHaLM5eymxebAxeHpjEEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55604+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583511187373490.3094850521079; Fri, 6 Mar 2020 08:13:07 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id h32UYY1788612xRBgPWipbfW; Fri, 06 Mar 2020 08:13:06 -0800 X-Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by mx.groups.io with SMTP id smtpd.web09.14942.1583511186276050110 for ; Fri, 06 Mar 2020 08:13:06 -0800 X-Received: by mail-wr1-f67.google.com with SMTP id v4so3020817wrs.8 for ; Fri, 06 Mar 2020 08:13:06 -0800 (PST) X-Gm-Message-State: GUua4yTHaIoLKs463HfbFy29x1787277AA= X-Google-Smtp-Source: ADFU+vtrQEllC+JaTtpu0D+5b/UURPPnVdKEehfEkA9TUBxrtvxxt8D+0ue9yxrqQ+KgKxzw6+TUSw== X-Received: by 2002:a5d:424e:: with SMTP id s14mr4983144wrr.226.1583511184400; Fri, 06 Mar 2020 08:13:04 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id f8sm6745287wmf.20.2020.03.06.08.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2020 08:13:02 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v3 2/2] ArmPkg/ArmMmuLib AARCH64: invalidate page tables before populating them Date: Fri, 6 Mar 2020 17:12:46 +0100 Message-Id: <20200306161246.6392-3-ard.biesheuvel@linaro.org> In-Reply-To: <20200306161246.6392-1-ard.biesheuvel@linaro.org> References: <20200306161246.6392-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583511186; bh=E/Du2aU6vHBuh4vjK8rEzIWCZVZSvYQ1MDBdWKKe3cc=; h=Cc:Date:From:Reply-To:Subject:To; b=kQFjFBPmtnlb9P9owlIXiiTbEGniwEh79Blj0YdO+wsHdgThaC1Ogg3shQa1luvaP1+ QNIrzwd3SW0y0gJzmIR0FLtw9vFEkcdgOvNioh6KQnkpGlt3EH1aopSDjGxF57iItf6y3 X1Ncbsc38/+x4b0WDC5dfdfB5WaZVSCXcbI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As it turns out, ARMv8 also permits accesses made with the MMU and caches off to hit in the caches, so to ensure that any modifications we make before enabling the MMU are visible afterwards as well, we should invalidate page tables right after allocation like we do now on ARM, if the MMU is still disabled at that point. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index e36594fea3ad..10ca8bac6a3f 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -217,6 +217,14 @@ UpdateRegionMappingRec ( return EFI_OUT_OF_RESOURCES; } =20 + if (!ArmMmuEnabled ()) { + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, EFI_PAGE_SIZE); + } + if ((*Entry & TT_TYPE_MASK) =3D=3D TT_TYPE_BLOCK_ENTRY) { // // We are splitting an existing block entry, so we have to popul= ate @@ -581,6 +589,12 @@ ArmConfigureMmu ( *TranslationTableSize =3D RootTableEntryCount * sizeof(UINT64); } =20 + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, + RootTableEntryCount * sizeof(UINT64)); ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); =20 TranslationTableAttribute =3D TT_ATTR_INDX_INVALID; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55604): https://edk2.groups.io/g/devel/message/55604 Mute This Topic: https://groups.io/mt/71776545/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-