From nobody Tue Feb 10 14:33:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55492+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55492+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583402443; cv=none; d=zohomail.com; s=zohoarc; b=R4AiaScUBXyI+xBvWIEWF2wgmfJXZme/9LEXC13iKjFbEdWk6X9DEP2Qicl9aa0CpWEKYWGRLsCzKo97HTmxNsKPUJ4uf/oxg/RzKjtE9l/uPNqvgyxpS0DvhdGbwhiwj42/tnzpezbwKJc6LYdgeja6O2MqzV44KesVVusqlCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583402443; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=wDQwJVHkfEBYx8n/rfLwbJ7qJ+CU3h47SKCYtU8whBQ=; b=d/PpEctHzdj6MZPRztkO9WxQvjLaBaWJe3ElOvbOkGiOxJmUTHlR+v6xJ+WqDN1SMe2qyvQ6kWTORIbAHbZXEV9bIzuhmY4ErnVGFL89gAsbTLDZFcfwDxW+kFpTBythoS5Jo5tr6g2qrtjpNWQVM3Qtdo4g5PgMHhTNpkV6nQA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55492+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583402443417372.87204664403566; Thu, 5 Mar 2020 02:00:43 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id NJFDYY1788612xuqvBKozMfp; Thu, 05 Mar 2020 02:00:41 -0800 X-Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web12.10245.1583402440379152661 for ; Thu, 05 Mar 2020 02:00:40 -0800 X-Received: by mail-wm1-f67.google.com with SMTP id i9so5493271wml.4 for ; Thu, 05 Mar 2020 02:00:40 -0800 (PST) X-Gm-Message-State: AJgk3xNQga4TXyJeAP4KQeKZx1787277AA= X-Google-Smtp-Source: ADFU+vvcF1pjbLTXRrdzG9dgZ8hg5kmprhirZLjHC1RUR5uLoDObzaj0A7pbsy1FwTj3pP/ZUpAkQA== X-Received: by 2002:a1c:e206:: with SMTP id z6mr8193615wmg.141.1583402437437; Thu, 05 Mar 2020 02:00:37 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id g206sm8569051wme.46.2020.03.05.02.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 02:00:36 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 2/2] ArmPkg/ArmMmuLib ARM: invalidate page tables as they are allocated Date: Thu, 5 Mar 2020 11:00:30 +0100 Message-Id: <20200305100030.20048-3-ard.biesheuvel@linaro.org> In-Reply-To: <20200305100030.20048-1-ard.biesheuvel@linaro.org> References: <20200305100030.20048-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583402441; bh=7xPY05ha/+MEUHVNKe6CCx3u92gTMEIVyPb5GBB9X3g=; h=Cc:Date:From:Reply-To:Subject:To; b=GSluOfs4v/03J1DPtgWO+WdN1/U8/tlItiBXTOjMFtgOt8zaCnxyxSZ/GDEwjGg/Tb+ eP/5TCL215iM29lIkM+FJZQcq6spShW75ch2vs0/RbC2k8xvQtpB9gxYyzq1xq+WzF0B3 PY+d6/HHMQcPK9i7cP1YyAQeoAANQDy7QzA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Instead of performing two cache invalidations for each section entry that gets updated, perform the first invalidation, which is intended to clean the page tables from caches on systems where cache hits are permitted with the MMU and caches off. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 33 +++++++++++--------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index 0800ef560d89..11a1e704beab 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -147,6 +147,13 @@ PopulateLevel2PageTable ( =20 BaseSectionAddress =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEn= try); =20 + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables + // + InvalidateDataCacheRange ((VOID *)TranslationTable, + TRANSLATION_TABLE_PAGE_SIZE); + // Populate the new Level2 Page Table for the section PageEntry =3D (UINT32*)TranslationTable; for (Index =3D 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { @@ -166,6 +173,12 @@ PopulateLevel2PageTable ( TranslationTable =3D (UINTN)AllocateAlignedPages ( EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_= SIZE), TRANSLATION_TABLE_PAGE_ALIGNMENT); + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables + // + InvalidateDataCacheRange ((VOID *)TranslationTable, + TRANSLATION_TABLE_PAGE_SIZE); ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE); =20 *SectionEntry =3D (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_= ADDRESS_MASK) | @@ -179,13 +192,6 @@ PopulateLevel2PageTable ( =20 ASSERT (FirstPageOffset + Pages <=3D TRANSLATION_TABLE_PAGE_COUNT); =20 - // - // Invalidate once to prevent page table updates to hit in the - // caches inadvertently. - // - InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset, - RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)); - for (Index =3D 0; Index < Pages; Index++) { *PageEntry++ =3D TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | = PageAttributes; PhysicalBase +=3D TT_DESCRIPTOR_PAGE_SIZE; @@ -268,14 +274,6 @@ FillTranslationTable ( SectionEntry =3D TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(Translat= ionTable, MemoryRegion->VirtualBase); =20 while (RemainLength !=3D 0) { - // - // Ensure that the assignment of the page table entry will not hit - // in the cache. Whether this could occur is IMPLEMENTATION DEFINED - // and thus permitted by the ARMv7 architecture. - // - ArmInvalidateDataCacheEntryByMVA ((UINTN)SectionEntry); - ArmDataSynchronizationBarrier (); - if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE =3D=3D 0 && RemainLength >=3D TT_DESCRIPTOR_SECTION_SIZE) { // Case: Physical address aligned on the Section Size (1MB) && the l= ength @@ -348,6 +346,11 @@ ArmConfigureMmu ( *TranslationTableSize =3D TRANSLATION_TABLE_SECTION_SIZE; } =20 + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables + // + InvalidateDataCacheRange (TranslationTable, TRANSLATION_TABLE_SECTION_SI= ZE); ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); =20 // By default, mark the translation table as belonging to a uncached reg= ion --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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