From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55431+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55431+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345577; cv=none; d=zohomail.com; s=zohoarc; b=jQbo7Vv7OY3segGlBt+idrLCvDLF45bQ+ovhtx6u1prMVAJM9+YkuljNjKN6BlwBMyeXnaZN+EwfnM3+KO/ZCCbU5K5qdVXD+4VchKtGxQUf1vsxIoBnDiqG5IrwmJx4M/FY4Zl57YQmkcIrxPi884NcCiywSgEuUTr8t8JEBWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345577; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=aU2FkVO7NYxJbHBjxsEF36PrWbSLJ8SPDCl34TWikEg=; b=apdFv1lXd9yOFpYqkGpHQh3OydWPHhCsF/P+i5JdQhZHNhBqt86MTE9oBhTWE704fX01PmX0oiMv41OwItxOxvbmx0r+GcbOZAXxjuwFBdLcUIZqVmWmwGGqTU9BGDXsznMGLi9EwdwNceppvoi/yKl7rsZ18Q7Oqh3eGBOFMB0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55431+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583345577249409.45105013554326; Wed, 4 Mar 2020 10:12:57 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id PDkqYY1788612xD1UrOdnFDH; Wed, 04 Mar 2020 10:12:56 -0800 X-Received: from mail-ot1-f66.google.com (mail-ot1-f66.google.com [209.85.210.66]) by mx.groups.io with SMTP id smtpd.web11.15495.1583345576444419604 for ; Wed, 04 Mar 2020 10:12:56 -0800 X-Received: by mail-ot1-f66.google.com with SMTP id x97so2962918ota.6 for ; Wed, 04 Mar 2020 10:12:56 -0800 (PST) X-Gm-Message-State: V0ExTnW0Cf8YAacqFERUxdytx1787277AA= X-Google-Smtp-Source: ADFU+vs02CVNvn6t+VbjOI4dS7LUAqsKMHoaYyFGkJqDHP/hrVLQ22GhezXO3Ti0JYvMcItGyjEIhQ== X-Received: by 2002:a05:6830:19ec:: with SMTP id t12mr1821677ott.161.1583345575145; Wed, 04 Mar 2020 10:12:55 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:12:54 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 1/9] ArmPlatformPkg/PrePi: replace set/way cache ops with by-VA ones Date: Wed, 4 Mar 2020 19:12:38 +0100 Message-Id: <20200304181246.23513-2-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345576; bh=4URkmwXFJ7zhmiaqf98F+Bj6pKQ2Fw1oH+wAFS3S0Ac=; h=Cc:Date:From:Reply-To:Subject:To; b=W62Vztb4A4DJKsCDjZyW288rWhpHGB8nqtmV+rW+37YrtzM7zRV+YzC0CrKP7NW3cmT nmyKM0aIuZugZY+yayH9m9SzHZm+5YJAuUfCFRTmZXatAsOWgFi4m4WcHEtCXfNuhk9GJ d1NC3NBDD4GwK6XrOKS8fLy1bl3dirzztSo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cache maintenance operations by set/way are only intended to be used in the context of on/offlining a core, while it has been taken out of the coherency domain. Any use intended to ensure that the contents of the cache have made it to main memory is unreliable, since cacheline migration and non-architected system caches may cause these contents to linger elsewhere, without being visible in main memory once the MMU and caches are disabled. In KVM on Linux, there are horrid hacks in place to ensure that such set/way operations are trapped, and replaced with a single by-VA clean/invalidate of the entire guest VA space once the MMU state changes, which can be costly, and is unnecessary if we manage the caches a bit more carefully, and perform maintenance by virtual address only. So let's get rid of the call to ArmInvalidateDataCache () in the PrePeiCore startup code, and instead, invalidate the UEFI memory region by virtual address, which is the only memory region we will be touching with the caches and MMU both disabled and enabled. (This will lead to data corruption if data written with the MMU off is shadowed by clean, stale cachelines that stick around when the MMU is enabled again.) Signed-off-by: Ard Biesheuvel Acked-by: Laszlo Ersek Tested-By: Pete Batard Reviewed-by: Leif Lindholm --- ArmPlatformPkg/PrePi/PeiMPCore.inf | 1 + ArmPlatformPkg/PrePi/PeiUniCore.inf | 1 + ArmPlatformPkg/PrePi/PrePi.c | 8 +++++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiM= PCore.inf index 9c5da0d42a7b..053f9fd9e616 100644 --- a/ArmPlatformPkg/PrePi/PeiMPCore.inf +++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf @@ -37,6 +37,7 @@ [Packages] =20 [LibraryClasses] BaseLib + CacheMaintenanceLib DebugLib DebugAgentLib ArmLib diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/Pei= UniCore.inf index ee9b05b25337..78d218ae09ca 100644 --- a/ArmPlatformPkg/PrePi/PeiUniCore.inf +++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf @@ -37,6 +37,7 @@ [Packages] =20 [LibraryClasses] BaseLib + CacheMaintenanceLib DebugLib DebugAgentLib ArmLib diff --git a/ArmPlatformPkg/PrePi/PrePi.c b/ArmPlatformPkg/PrePi/PrePi.c index 2bb144958139..254fb331733e 100644 --- a/ArmPlatformPkg/PrePi/PrePi.c +++ b/ArmPlatformPkg/PrePi/PrePi.c @@ -8,6 +8,7 @@ =20 #include =20 +#include #include #include #include @@ -178,8 +179,6 @@ CEntryPoint ( =20 // Data Cache enabled on Primary core when MMU is enabled. ArmDisableDataCache (); - // Invalidate Data cache - ArmInvalidateDataCache (); // Invalidate instruction cache ArmInvalidateInstructionCache (); // Enable Instruction Caches on all cores. @@ -200,6 +199,10 @@ CEntryPoint ( =20 // If not primary Jump to Secondary Main if (ArmPlatformIsPrimaryCore (MpId)) { + + InvalidateDataCacheRange ((VOID *)UefiMemoryBase, + FixedPcdGet32(PcdSystemMemoryUefiRegionSize)= ); + // Goto primary Main. PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp); } else { @@ -209,4 +212,3 @@ CEntryPoint ( // DXE Core should always load and never return ASSERT (FALSE); } - --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55431): https://edk2.groups.io/g/devel/message/55431 Mute This Topic: https://groups.io/mt/71732154/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55432+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55432+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345579; cv=none; d=zohomail.com; s=zohoarc; b=DrQ+OixAMv4pN43U3AEliew27LAO42apemsgvyUE3CKvbiSrIJ3n+r7fTOCHqvuU56XnNqGzKDalqO5/iYPpQF0M06nCupww27+/wfRHaZ84UnnQ+fzpXYib8Hq9oW4rPj1qG414Ah3zlE8zgQShdrJRKdWw5z8AXyZppJmzv5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345579; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=UFXrPXq3+VmTJy9IrAbB6jnPmgpOh83oCEf5fkN9YwA=; b=kONaDu9yS1BIbBTkMsQ6j0XwNF1DjuQmzqZGQjnrsSuXGPy7o6mhdsYtdBrnwHsnDImjV8SS/Ei5opebmZ9sigyTJA1NDrhQavCLXF3lAv6D/aT42KeUt4H+Oxb2aHyCc2RsyNDZECUqv+5tMvqmvWUYx3bQ3wPAylMpBxHmMBY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55432+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583345579294688.1109700455041; Wed, 4 Mar 2020 10:12:59 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id QCUMYY1788612xBXtDTQBQdd; Wed, 04 Mar 2020 10:12:58 -0800 X-Received: from mail-ot1-f67.google.com (mail-ot1-f67.google.com [209.85.210.67]) by mx.groups.io with SMTP id smtpd.web12.15674.1583345578405159375 for ; Wed, 04 Mar 2020 10:12:58 -0800 X-Received: by mail-ot1-f67.google.com with SMTP id v19so2961795ote.8 for ; Wed, 04 Mar 2020 10:12:58 -0800 (PST) X-Gm-Message-State: CJZqUDf8ih0WNYYcgCy8fncnx1787277AA= X-Google-Smtp-Source: ADFU+vtv141AXlwCZYDnFznzaCEf8TMlUbLh4IJboA8oDVO79kHreiI/sxDnyse/ZXv8FH33M7cWsg== X-Received: by 2002:a05:6830:186:: with SMTP id q6mr3286138ota.10.1583345577150; Wed, 04 Mar 2020 10:12:57 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:12:56 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 2/9] ArmPkg/ArmMmuLib ARM: remove dummy constructor Date: Wed, 4 Mar 2020 19:12:39 +0100 Message-Id: <20200304181246.23513-3-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345578; bh=I+pgEZ6xcj+rSW9KI5fGQ7ZLlWtNHNj4W75Vqatt2wQ=; h=Cc:Date:From:Reply-To:Subject:To; b=RL6rg1n7zyCq7k4c7n1/Dkgn6VgAJygtmkBSjVQr+dVfsZ+1IGxiJcuRGmyW6aVN2pa j09x3/xrymPaYdUmzStHqVptiLGSdTcUqMGBTLe0Ac4eDtu41HDDLjVl5a6FZG8nWwDPm k7KjECKcOHVX9ChX8OxxyNL//2GJ/0/+xro= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the CONSTRUCTOR define in the .INF AARCH64 only, so we can drop the empty stub that exists for ARM. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 9 --------- ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 ++ 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index 74ac31de98cc..a6601258bee0 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -830,12 +830,3 @@ ArmClearMemoryRegionReadOnly ( { return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); } - -RETURN_STATUS -EFIAPI -ArmMmuBaseLibConstructor ( - VOID - ) -{ - return RETURN_SUCCESS; -} diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar= mMmuLib/ArmMmuBaseLib.inf index 5028a955afac..3dfe68ba48a6 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -14,6 +14,8 @@ [Defines] MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D ArmMmuLib + +[Defines.AARCH64] CONSTRUCTOR =3D ArmMmuBaseLibConstructor =20 [Sources.AARCH64] --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55432): https://edk2.groups.io/g/devel/message/55432 Mute This Topic: https://groups.io/mt/71732155/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55433+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55433+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345582; cv=none; d=zohomail.com; s=zohoarc; b=jX+yLJ2DeRQ+rPSIY0KvTm6+CQagfj2iSlCHgqydlwmBO7lsuhyrTs/z06Gd3GVOXle7WBAScPjdyYCgCSjhm9Tua9nQr0f8390ZCZiTHoYLw4FZnPUYr/usOuxTwa9VpY2q3exKCCGcOXw0gXXst8e+1kBF95vtlCqNS52MUQY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345582; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=GERftb44fbEuOcoTa+ir3pGZOk3SZyniJF4NFP7+cZs=; b=E4ncC35HLy556D9l7Mgd9R0PPM/J5ezJPS9mTktvD4pDVstoIFPTwvCYpi0pKUhlam/AedhSXrLwmkPA4htIU36q3nz3z/zbkrA+t13PMs2E8JUvXsbyPeY2OlLSwtq9+YpSVA86YHDlpjnrTNujxq2QcHMm5vgacJQWsSgxrxI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55433+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583345582575384.81717291058226; Wed, 4 Mar 2020 10:13:02 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id YNjSYY1788612x2irXsl46lk; Wed, 04 Mar 2020 10:13:02 -0800 X-Received: from mail-ot1-f41.google.com (mail-ot1-f41.google.com [209.85.210.41]) by mx.groups.io with SMTP id smtpd.web09.15594.1583345581458169441 for ; Wed, 04 Mar 2020 10:13:01 -0800 X-Received: by mail-ot1-f41.google.com with SMTP id x97so2963136ota.6 for ; Wed, 04 Mar 2020 10:13:01 -0800 (PST) X-Gm-Message-State: dP9hRiFqwX3u35A5zIb3RTeIx1787277AA= X-Google-Smtp-Source: ADFU+vtP/TWe1tDRkhOOyLA4WSGkCEEnM5A0IPwstG/lGRcYNEJoqbULNxD1Feoo4v4HSByFOaRDdA== X-Received: by 2002:a9d:6c9:: with SMTP id 67mr3503801otx.363.1583345579547; Wed, 04 Mar 2020 10:12:59 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:12:58 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 3/9] ArmPkg/ArmMmuLib ARM: split ArmMmuLibCore.c into core and update code Date: Wed, 4 Mar 2020 19:12:40 +0100 Message-Id: <20200304181246.23513-4-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345582; bh=Cb2oj5L12ndGqqAxxtuI8yTBluuZXFdTeWCSg3mWwK4=; h=Cc:Date:From:Reply-To:Subject:To; b=PvA4c4Hufa3Nn2QWnKLJ6fDKTN3LajGtmIIwIgLkRoHtIvzZw3VNhRVaplAc1+GRdHp MrD2nuXKglp2qdDt7s0vXdk8TeLClFNAkLsr8V7i9wAQkI+t4ujw6gf9JPMrSSUohpYao qSb1PG12IBW+aHkZUncHjGhiEE8Q0kHNwYk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Unlike the AArch64 implementation of ArmMmuLib, which combines the initial page table population code with the code that runs at later stages to manage permission attributes in the page tables, ARM uses two completely separate sets of routines for this. Since ArmMmuLib is a static library, we can prevent duplication of this code between different users, which usually only need one or the other. (Note that LTO should also achieve the same.) This also makes it easier to reason about modifying the cache maintenance handling, and replace the set/way ops with by-VA ops, since the code that performs the set/way ops only executes when the MMU is still off. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c | 32 ++ ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 434 ------------------- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 435 ++++++++++++++++++++ ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 + 4 files changed, 469 insertions(+), 434 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Libra= ry/ArmMmuLib/Arm/ArmMmuLibConvert.c new file mode 100644 index 000000000000..e3b02a9fba57 --- /dev/null +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c @@ -0,0 +1,32 @@ +/** @file +* File managing the MMU for ARMv7 architecture +* +* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include + +#include + +UINT32 +ConvertSectionAttributesToPageAttributes ( + IN UINT32 SectionAttributes, + IN BOOLEAN IsLargePage + ) +{ + UINT32 PageAttributes; + + PageAttributes =3D 0; + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionA= ttributes, IsLargePage); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes,= IsLargePage); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes); + + return PageAttributes; +} diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index a6601258bee0..aca7a37facac 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -31,15 +31,6 @@ #define ID_MMFR0_SHR_IMP_HW_COHERENT 1 #define ID_MMFR0_SHR_IGNORED 0xf =20 -#define __EFI_MEMORY_RWX 0 // no restrictions - -#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \ - EFI_MEMORY_WC | \ - EFI_MEMORY_WT | \ - EFI_MEMORY_WB | \ - EFI_MEMORY_UCE | \ - EFI_MEMORY_WP) - UINTN EFIAPI ArmReadIdMmfr0 ( @@ -52,24 +43,6 @@ ArmHasMpExtensions ( VOID ); =20 -UINT32 -ConvertSectionAttributesToPageAttributes ( - IN UINT32 SectionAttributes, - IN BOOLEAN IsLargePage - ) -{ - UINT32 PageAttributes; - - PageAttributes =3D 0; - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionA= ttributes, IsLargePage); - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes); - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes,= IsLargePage); - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes); - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes); - - return PageAttributes; -} - STATIC BOOLEAN PreferNonshareableMemory ( @@ -423,410 +396,3 @@ ArmConfigureMmu ( ArmEnableMmu(); return RETURN_SUCCESS; } - -STATIC -EFI_STATUS -ConvertSectionToPages ( - IN EFI_PHYSICAL_ADDRESS BaseAddress - ) -{ - UINT32 FirstLevelIdx; - UINT32 SectionDescriptor; - UINT32 PageTableDescriptor; - UINT32 PageDescriptor; - UINT32 Index; - - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - volatile ARM_PAGE_TABLE_ENTRY *PageTable; - - DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)Base= Address)); - - // Obtain page table base - FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); - - // Calculate index into first level translation table for start of modif= ication - FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_= DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // Get section attributes and convert to page attributes - SectionDescriptor =3D FirstLevelTable[FirstLevelIdx]; - PageDescriptor =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttribut= esToPageAttributes (SectionDescriptor, FALSE); - - // Allocate a page table for the 4KB entries (we use up a full page even= though we only need 1KB) - PageTable =3D (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1); - if (PageTable =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - // Write the page table entries out - for (Index =3D 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { - PageTable[Index] =3D TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (In= dex << 12)) | PageDescriptor; - } - - // Formulate page table entry, Domain=3D0, NS=3D0 - PageTableDescriptor =3D (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGE= TABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; - - // Write the page table entry out, replacing section entry - FirstLevelTable[FirstLevelIdx] =3D PageTableDescriptor; - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -UpdatePageEntries ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *FlushTlbs OPTIONAL - ) -{ - EFI_STATUS Status; - UINT32 EntryValue; - UINT32 EntryMask; - UINT32 FirstLevelIdx; - UINT32 Offset; - UINT32 NumPageEntries; - UINT32 Descriptor; - UINT32 p; - UINT32 PageTableIndex; - UINT32 PageTableEntry; - UINT32 CurrentPageTableEntry; - VOID *Mva; - - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - volatile ARM_PAGE_TABLE_ENTRY *PageTable; - - Status =3D EFI_SUCCESS; - - // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) - // EntryValue: values at bit positions specified by EntryMask - EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK; - if (Attributes & EFI_MEMORY_XP) { - EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN; - } else { - EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE; - } - - // Although the PI spec is unclear on this, the GCD guarantees that only - // one Attribute bit is set at a time, so the order of the conditionals = below - // is irrelevant. If no memory attribute is specified, we preserve whate= ver - // memory type is set in the page tables, and update the permission attr= ibutes - // only. - if (Attributes & EFI_MEMORY_UC) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // map to strongly ordered - EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // T= EX[2:0] =3D 0, C=3D0, B=3D0 - } else if (Attributes & EFI_MEMORY_WC) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // map to normal non-cachable - EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX = [2:0]=3D 001 =3D 0x2, B=3D0, C=3D0 - } else if (Attributes & EFI_MEMORY_WT) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // write through with no-allocate - EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC= ; // TEX [2:0] =3D 0, C=3D1, B=3D0 - } else if (Attributes & EFI_MEMORY_WB) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // write back (with allocate) - EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // T= EX [2:0] =3D 001, C=3D1, B=3D1 - } else if (Attributes & CACHE_ATTRIBUTE_MASK) { - // catch unsupported memory type attributes - ASSERT (FALSE); - return EFI_UNSUPPORTED; - } - - if (Attributes & EFI_MEMORY_RO) { - EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RO_RO; - } else { - EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RW_RW; - } - - // Obtain page table base - FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); - - // Calculate number of 4KB page table entries to change - NumPageEntries =3D Length / TT_DESCRIPTOR_PAGE_SIZE; - - // Iterate for the number of 4KB pages to change - Offset =3D 0; - for(p =3D 0; p < NumPageEntries; p++) { - // Calculate index into first level translation table for page table v= alue - - FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Off= set) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // Read the descriptor from the first level page table - Descriptor =3D FirstLevelTable[FirstLevelIdx]; - - // Does this descriptor need to be converted from section entry to 4K = pages? - if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) { - Status =3D ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT); - if (EFI_ERROR(Status)) { - // Exit for loop - break; - } - - // Re-read descriptor - Descriptor =3D FirstLevelTable[FirstLevelIdx]; - if (FlushTlbs !=3D NULL) { - *FlushTlbs =3D TRUE; - } - } - - // Obtain page table base address - PageTable =3D (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(= Descriptor); - - // Calculate index into the page table - PageTableIndex =3D ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_= MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; - ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); - - // Get the entry - CurrentPageTableEntry =3D PageTable[PageTableIndex]; - - // Mask off appropriate fields - PageTableEntry =3D CurrentPageTableEntry & ~EntryMask; - - // Mask in new attributes and/or permissions - PageTableEntry |=3D EntryValue; - - if (CurrentPageTableEntry !=3D PageTableEntry) { - Mva =3D (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT)); - - // Only need to update if we are changing the entry - PageTable[PageTableIndex] =3D PageTableEntry; - ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], = Mva); - } - - Status =3D EFI_SUCCESS; - Offset +=3D TT_DESCRIPTOR_PAGE_SIZE; - - } // End first level translation table loop - - return Status; -} - -STATIC -EFI_STATUS -UpdateSectionEntries ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes - ) -{ - EFI_STATUS Status =3D EFI_SUCCESS; - UINT32 EntryMask; - UINT32 EntryValue; - UINT32 FirstLevelIdx; - UINT32 NumSections; - UINT32 i; - UINT32 CurrentDescriptor; - UINT32 Descriptor; - VOID *Mva; - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - - // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) - // EntryValue: values at bit positions specified by EntryMask - - // Make sure we handle a section range that is unmapped - EntryMask =3D TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN= _MASK | - TT_DESCRIPTOR_SECTION_AP_MASK; - EntryValue =3D TT_DESCRIPTOR_SECTION_TYPE_SECTION; - - // Although the PI spec is unclear on this, the GCD guarantees that only - // one Attribute bit is set at a time, so the order of the conditionals = below - // is irrelevant. If no memory attribute is specified, we preserve whate= ver - // memory type is set in the page tables, and update the permission attr= ibutes - // only. - if (Attributes & EFI_MEMORY_UC) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // map to strongly ordered - EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; /= / TEX[2:0] =3D 0, C=3D0, B=3D0 - } else if (Attributes & EFI_MEMORY_WC) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // map to normal non-cachable - EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // T= EX [2:0]=3D 001 =3D 0x2, B=3D0, C=3D0 - } else if (Attributes & EFI_MEMORY_WT) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // write through with no-allocate - EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_AL= LOC; // TEX [2:0] =3D 0, C=3D1, B=3D0 - } else if (Attributes & EFI_MEMORY_WB) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // write back (with allocate) - EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; /= / TEX [2:0] =3D 001, C=3D1, B=3D1 - } else if (Attributes & CACHE_ATTRIBUTE_MASK) { - // catch unsupported memory type attributes - ASSERT (FALSE); - return EFI_UNSUPPORTED; - } - - if (Attributes & EFI_MEMORY_RO) { - EntryValue |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; - } else { - EntryValue |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; - } - - if (Attributes & EFI_MEMORY_XP) { - EntryValue |=3D TT_DESCRIPTOR_SECTION_XN_MASK; - } - - // obtain page table base - FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); - - // calculate index into first level translation table for start of modif= ication - FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_= DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // calculate number of 1MB first level entries this applies to - NumSections =3D Length / TT_DESCRIPTOR_SECTION_SIZE; - - // iterate through each descriptor - for(i=3D0; i (UINT64)MAX_ADDRESS) { - return EFI_UNSUPPORTED; - } - - Length =3D MIN (Length, (UINT64)MAX_ADDRESS - BaseAddress + 1); - if (Length =3D=3D 0) { - return EFI_SUCCESS; - } - - FlushTlbs =3D FALSE; - while (Length > 0) { - if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE =3D=3D 0) && - Length >=3D TT_DESCRIPTOR_SECTION_SIZE) { - - ChunkLength =3D Length - Length % TT_DESCRIPTOR_SECTION_SIZE; - - DEBUG ((DEBUG_PAGE, - "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n", - BaseAddress, ChunkLength, Attributes)); - - Status =3D UpdateSectionEntries (BaseAddress, ChunkLength, Attribute= s); - - FlushTlbs =3D TRUE; - } else { - - // - // Process page by page until the next section boundary, but only if - // we have more than a section's worth of area to deal with after th= at. - // - ChunkLength =3D TT_DESCRIPTOR_SECTION_SIZE - - (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE); - if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) { - ChunkLength =3D Length; - } - - DEBUG ((DEBUG_PAGE, - "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n", - BaseAddress, ChunkLength, Attributes)); - - Status =3D UpdatePageEntries (BaseAddress, ChunkLength, Attributes, - &FlushTlbs); - } - - if (EFI_ERROR (Status)) { - break; - } - - BaseAddress +=3D ChunkLength; - Length -=3D ChunkLength; - } - - if (FlushTlbs) { - ArmInvalidateTlb (); - } - return Status; -} - -EFI_STATUS -ArmSetMemoryRegionNoExec ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP); -} - -EFI_STATUS -ArmClearMemoryRegionNoExec ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); -} - -EFI_STATUS -ArmSetMemoryRegionReadOnly ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO); -} - -EFI_STATUS -ArmClearMemoryRegionReadOnly ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); -} diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Librar= y/ArmMmuLib/Arm/ArmMmuLibUpdate.c new file mode 100644 index 000000000000..3dafe1d964cd --- /dev/null +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -0,0 +1,435 @@ +/** @file +* File managing the MMU for ARMv7 architecture +* +* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#define __EFI_MEMORY_RWX 0 // no restrictions + +#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \ + EFI_MEMORY_WC | \ + EFI_MEMORY_WT | \ + EFI_MEMORY_WB | \ + EFI_MEMORY_UCE | \ + EFI_MEMORY_WP) + +STATIC +EFI_STATUS +ConvertSectionToPages ( + IN EFI_PHYSICAL_ADDRESS BaseAddress + ) +{ + UINT32 FirstLevelIdx; + UINT32 SectionDescriptor; + UINT32 PageTableDescriptor; + UINT32 PageDescriptor; + UINT32 Index; + + volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; + volatile ARM_PAGE_TABLE_ENTRY *PageTable; + + DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)Base= Address)); + + // Obtain page table base + FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); + + // Calculate index into first level translation table for start of modif= ication + FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_= DESCRIPTOR_SECTION_BASE_SHIFT; + ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); + + // Get section attributes and convert to page attributes + SectionDescriptor =3D FirstLevelTable[FirstLevelIdx]; + PageDescriptor =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttribut= esToPageAttributes (SectionDescriptor, FALSE); + + // Allocate a page table for the 4KB entries (we use up a full page even= though we only need 1KB) + PageTable =3D (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1); + if (PageTable =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // Write the page table entries out + for (Index =3D 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { + PageTable[Index] =3D TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (In= dex << 12)) | PageDescriptor; + } + + // Formulate page table entry, Domain=3D0, NS=3D0 + PageTableDescriptor =3D (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGE= TABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; + + // Write the page table entry out, replacing section entry + FirstLevelTable[FirstLevelIdx] =3D PageTableDescriptor; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +UpdatePageEntries ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + OUT BOOLEAN *FlushTlbs OPTIONAL + ) +{ + EFI_STATUS Status; + UINT32 EntryValue; + UINT32 EntryMask; + UINT32 FirstLevelIdx; + UINT32 Offset; + UINT32 NumPageEntries; + UINT32 Descriptor; + UINT32 p; + UINT32 PageTableIndex; + UINT32 PageTableEntry; + UINT32 CurrentPageTableEntry; + VOID *Mva; + + volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; + volatile ARM_PAGE_TABLE_ENTRY *PageTable; + + Status =3D EFI_SUCCESS; + + // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) + // EntryValue: values at bit positions specified by EntryMask + EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK; + if (Attributes & EFI_MEMORY_XP) { + EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN; + } else { + EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE; + } + + // Although the PI spec is unclear on this, the GCD guarantees that only + // one Attribute bit is set at a time, so the order of the conditionals = below + // is irrelevant. If no memory attribute is specified, we preserve whate= ver + // memory type is set in the page tables, and update the permission attr= ibutes + // only. + if (Attributes & EFI_MEMORY_UC) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; + // map to strongly ordered + EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // T= EX[2:0] =3D 0, C=3D0, B=3D0 + } else if (Attributes & EFI_MEMORY_WC) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; + // map to normal non-cachable + EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX = [2:0]=3D 001 =3D 0x2, B=3D0, C=3D0 + } else if (Attributes & EFI_MEMORY_WT) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; + // write through with no-allocate + EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC= ; // TEX [2:0] =3D 0, C=3D1, B=3D0 + } else if (Attributes & EFI_MEMORY_WB) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; + // write back (with allocate) + EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // T= EX [2:0] =3D 001, C=3D1, B=3D1 + } else if (Attributes & CACHE_ATTRIBUTE_MASK) { + // catch unsupported memory type attributes + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + if (Attributes & EFI_MEMORY_RO) { + EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RO_RO; + } else { + EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RW_RW; + } + + // Obtain page table base + FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); + + // Calculate number of 4KB page table entries to change + NumPageEntries =3D Length / TT_DESCRIPTOR_PAGE_SIZE; + + // Iterate for the number of 4KB pages to change + Offset =3D 0; + for(p =3D 0; p < NumPageEntries; p++) { + // Calculate index into first level translation table for page table v= alue + + FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Off= set) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; + ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); + + // Read the descriptor from the first level page table + Descriptor =3D FirstLevelTable[FirstLevelIdx]; + + // Does this descriptor need to be converted from section entry to 4K = pages? + if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) { + Status =3D ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT); + if (EFI_ERROR(Status)) { + // Exit for loop + break; + } + + // Re-read descriptor + Descriptor =3D FirstLevelTable[FirstLevelIdx]; + if (FlushTlbs !=3D NULL) { + *FlushTlbs =3D TRUE; + } + } + + // Obtain page table base address + PageTable =3D (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(= Descriptor); + + // Calculate index into the page table + PageTableIndex =3D ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_= MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; + ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); + + // Get the entry + CurrentPageTableEntry =3D PageTable[PageTableIndex]; + + // Mask off appropriate fields + PageTableEntry =3D CurrentPageTableEntry & ~EntryMask; + + // Mask in new attributes and/or permissions + PageTableEntry |=3D EntryValue; + + if (CurrentPageTableEntry !=3D PageTableEntry) { + Mva =3D (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT)); + + // Only need to update if we are changing the entry + PageTable[PageTableIndex] =3D PageTableEntry; + ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], = Mva); + } + + Status =3D EFI_SUCCESS; + Offset +=3D TT_DESCRIPTOR_PAGE_SIZE; + + } // End first level translation table loop + + return Status; +} + +STATIC +EFI_STATUS +UpdateSectionEntries ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UINT32 EntryMask; + UINT32 EntryValue; + UINT32 FirstLevelIdx; + UINT32 NumSections; + UINT32 i; + UINT32 CurrentDescriptor; + UINT32 Descriptor; + VOID *Mva; + volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; + + // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) + // EntryValue: values at bit positions specified by EntryMask + + // Make sure we handle a section range that is unmapped + EntryMask =3D TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN= _MASK | + TT_DESCRIPTOR_SECTION_AP_MASK; + EntryValue =3D TT_DESCRIPTOR_SECTION_TYPE_SECTION; + + // Although the PI spec is unclear on this, the GCD guarantees that only + // one Attribute bit is set at a time, so the order of the conditionals = below + // is irrelevant. If no memory attribute is specified, we preserve whate= ver + // memory type is set in the page tables, and update the permission attr= ibutes + // only. + if (Attributes & EFI_MEMORY_UC) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; + // map to strongly ordered + EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; /= / TEX[2:0] =3D 0, C=3D0, B=3D0 + } else if (Attributes & EFI_MEMORY_WC) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; + // map to normal non-cachable + EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // T= EX [2:0]=3D 001 =3D 0x2, B=3D0, C=3D0 + } else if (Attributes & EFI_MEMORY_WT) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; + // write through with no-allocate + EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_AL= LOC; // TEX [2:0] =3D 0, C=3D1, B=3D0 + } else if (Attributes & EFI_MEMORY_WB) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; + // write back (with allocate) + EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; /= / TEX [2:0] =3D 001, C=3D1, B=3D1 + } else if (Attributes & CACHE_ATTRIBUTE_MASK) { + // catch unsupported memory type attributes + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + if (Attributes & EFI_MEMORY_RO) { + EntryValue |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; + } else { + EntryValue |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; + } + + if (Attributes & EFI_MEMORY_XP) { + EntryValue |=3D TT_DESCRIPTOR_SECTION_XN_MASK; + } + + // obtain page table base + FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); + + // calculate index into first level translation table for start of modif= ication + FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_= DESCRIPTOR_SECTION_BASE_SHIFT; + ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); + + // calculate number of 1MB first level entries this applies to + NumSections =3D Length / TT_DESCRIPTOR_SECTION_SIZE; + + // iterate through each descriptor + for(i=3D0; i (UINT64)MAX_ADDRESS) { + return EFI_UNSUPPORTED; + } + + Length =3D MIN (Length, (UINT64)MAX_ADDRESS - BaseAddress + 1); + if (Length =3D=3D 0) { + return EFI_SUCCESS; + } + + FlushTlbs =3D FALSE; + while (Length > 0) { + if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE =3D=3D 0) && + Length >=3D TT_DESCRIPTOR_SECTION_SIZE) { + + ChunkLength =3D Length - Length % TT_DESCRIPTOR_SECTION_SIZE; + + DEBUG ((DEBUG_PAGE, + "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n", + BaseAddress, ChunkLength, Attributes)); + + Status =3D UpdateSectionEntries (BaseAddress, ChunkLength, Attribute= s); + + FlushTlbs =3D TRUE; + } else { + + // + // Process page by page until the next section boundary, but only if + // we have more than a section's worth of area to deal with after th= at. + // + ChunkLength =3D TT_DESCRIPTOR_SECTION_SIZE - + (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE); + if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) { + ChunkLength =3D Length; + } + + DEBUG ((DEBUG_PAGE, + "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n", + BaseAddress, ChunkLength, Attributes)); + + Status =3D UpdatePageEntries (BaseAddress, ChunkLength, Attributes, + &FlushTlbs); + } + + if (EFI_ERROR (Status)) { + break; + } + + BaseAddress +=3D ChunkLength; + Length -=3D ChunkLength; + } + + if (FlushTlbs) { + ArmInvalidateTlb (); + } + return Status; +} + +EFI_STATUS +ArmSetMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP); +} + +EFI_STATUS +ArmClearMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); +} + +EFI_STATUS +ArmSetMemoryRegionReadOnly ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO); +} + +EFI_STATUS +ArmClearMemoryRegionReadOnly ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); +} diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar= mMmuLib/ArmMmuBaseLib.inf index 3dfe68ba48a6..2a7e7147958c 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -23,7 +23,9 @@ [Sources.AARCH64] AArch64/ArmMmuLibReplaceEntry.S =20 [Sources.ARM] + Arm/ArmMmuLibConvert.c Arm/ArmMmuLibCore.c + Arm/ArmMmuLibUpdate.c Arm/ArmMmuLibV7Support.S |GCC Arm/ArmMmuLibV7Support.asm |RVCT =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55433): https://edk2.groups.io/g/devel/message/55433 Mute This Topic: https://groups.io/mt/71732157/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55434+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55434+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345583; cv=none; d=zohomail.com; s=zohoarc; b=mORXMllNDJrVw14qV981tkJHl2xJSb/LE7GiWQsyf3kRPntfiCpR8FeyIrsknal095QaprGNFHK+TSpWpn49clCSYgssaz7BHcpSKgAuRQVFXaat8Lmjs0s770Vgxwn9WZYT6oLjXg6g4sRWajToIKz8S0ADjgySyXOHOlB9Qno= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345583; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=a78uo3o5juChx1chQv3UzMitXLDN3DoBa6uRsOiX16A=; b=dQ2g2vy0JyARtCWjJP7jCkO9QnZ7ilL9O5zNYEgwRHPwU1XNpXQ8OmjMsPVdvY5q7sNdqQ+yS8aIJREZ7xGJk5uukHyIlkX76H68HXKuem3NNcUMZmb7Rzz1o8cEdyDLL6ywjtMRUcx/t6oF9/b8h+r5Skjcw5Jzy9JT71GI+uA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55434+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15833455835521014.6388995796599; Wed, 4 Mar 2020 10:13:03 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id IzbyYY1788612xdF3uIOEsBe; Wed, 04 Mar 2020 10:13:03 -0800 X-Received: from mail-ot1-f66.google.com (mail-ot1-f66.google.com [209.85.210.66]) by mx.groups.io with SMTP id smtpd.web09.15595.1583345582735178851 for ; Wed, 04 Mar 2020 10:13:02 -0800 X-Received: by mail-ot1-f66.google.com with SMTP id b3so2976450otp.4 for ; Wed, 04 Mar 2020 10:13:02 -0800 (PST) X-Gm-Message-State: 4thb50y4nk53Gs6CfT6Vi8Snx1787277AA= X-Google-Smtp-Source: ADFU+vsYr2sZJZCkcuY92vdKeEERGzEt5VOWeyxHCQ5rHmwKoumW+VkJi5BukrlcXwArZkmLmLWY+A== X-Received: by 2002:a05:6830:1ca:: with SMTP id r10mr3294968ota.319.1583345581612; Wed, 04 Mar 2020 10:13:01 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:13:00 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 4/9] ArmPkg/ArmMmuLib ARM: cache-invalidate initial page table entries Date: Wed, 4 Mar 2020 19:12:41 +0100 Message-Id: <20200304181246.23513-5-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345583; bh=0Uo37rCFuT1imDF21zez8d5hcyN9s/nU87GThu0Dtlo=; h=Cc:Date:From:Reply-To:Subject:To; b=HptXNIb0P+cRcOuOjVG3g9azulr9vgUbMzCJSvC8+pF/PTqtVDJdo9DRpYcc78PJ2w9 ZW9M94VmiI5CTotbLDMIEyfub7I42cqKdsNljNB5QvFZP9ClZFPad+dQ5QQM8ZNbBdF2x LGBciGGVc9BnHr13TZ1M9C0yRf3/gZ2HLcA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the ARM version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if set/way operations were the appropriate method to achieve this, doing an invalidate-all first and then populating the page table entries creates a window where page table entries could be loaded speculatively into the caches before we modify them, and shadow the new values that we write there. So let's get rid of the blanket clean/invalidate operations, and instead, invalidate each section entry before and after it is updated (to address all the little corner cases that the ARMv7 spec permits), and invalidate sets of level 2 entries in blocks, using the generic invalidation routine from CacheMaintenanceLib On ARMv7, cache maintenance may be required also when the MMU is enabled, in case the page table walker is not cache coherent. However, the code being updated here is guaranteed to run only when the MMU is still off, and so we can disregard the case when the MMU and caches are on. Since the MMU and D-cache are already off when we reach this point, we can drop the MMU and D-cache disables as well. Maintenance of the I-cache is unnecessary, since we are not modifying any code, and the installed mapping is guaranteed to be 1:1. This means we can also leave it enabled while the page table population code is running. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 55 +++++++++++++++----- 1 file changed, 41 insertions(+), 14 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index aca7a37facac..7c7cad2c3d9d 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -178,11 +178,25 @@ PopulateLevel2PageTable ( =20 ASSERT (FirstPageOffset + Pages <=3D TRANSLATION_TABLE_PAGE_COUNT); =20 + // + // Invalidate once to prevent page table updates to hit in the + // caches inadvertently. + // + InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset, + RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)); + for (Index =3D 0; Index < Pages; Index++) { *PageEntry++ =3D TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | = PageAttributes; PhysicalBase +=3D TT_DESCRIPTOR_PAGE_SIZE; } =20 + // + // Invalidate again to ensure that any line fetches that may have occurr= ed + // [speculatively] since the previous invalidate are evicted again. + // + ArmDataMemoryBarrier (); + InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset, + RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)); } =20 STATIC @@ -253,11 +267,28 @@ FillTranslationTable ( SectionEntry =3D TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(Translat= ionTable, MemoryRegion->VirtualBase); =20 while (RemainLength !=3D 0) { + // + // Ensure that the assignment of the page table entry will not hit + // in the cache. Whether this could occur is IMPLEMENTATION DEFINED + // and thus permitted by the ARMv7 architecture. + // + ArmInvalidateDataCacheEntryByMVA ((UINTN)SectionEntry); + ArmDataSynchronizationBarrier (); + if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE =3D=3D 0 && RemainLength >=3D TT_DESCRIPTOR_SECTION_SIZE) { // Case: Physical address aligned on the Section Size (1MB) && the l= ength // is greater than the Section Size - *SectionEntry++ =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase)= | Attributes; + *SectionEntry =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) |= Attributes; + + // + // Issue a DMB to ensure that the page table entry update made it to + // memory before we issue the invalidate, otherwise, a subsequent + // speculative fetch could observe the old value. + // + ArmDataMemoryBarrier (); + ArmInvalidateDataCacheEntryByMVA ((UINTN)SectionEntry++); + PhysicalBase +=3D TT_DESCRIPTOR_SECTION_SIZE; RemainLength -=3D TT_DESCRIPTOR_SECTION_SIZE; } else { @@ -267,9 +298,17 @@ FillTranslationTable ( // Case: Physical address aligned on the Section Size (1MB) && the l= ength // does not fill a section // Case: Physical address NOT aligned on the Section Size (1MB) - PopulateLevel2PageTable (SectionEntry++, PhysicalBase, PageMapLength, + PopulateLevel2PageTable (SectionEntry, PhysicalBase, PageMapLength, MemoryRegion->Attributes); =20 + // + // Issue a DMB to ensure that the page table entry update made it to + // memory before we issue the invalidate, otherwise, a subsequent + // speculative fetch could observe the old value. + // + ArmDataMemoryBarrier (); + ArmInvalidateDataCacheEntryByMVA ((UINTN)SectionEntry++); + // If it is the last entry if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) { break; @@ -349,18 +388,6 @@ ArmConfigureMmu ( } } =20 - ArmCleanInvalidateDataCache (); - ArmInvalidateInstructionCache (); - - ArmDisableDataCache (); - ArmDisableInstructionCache(); - // TLBs are also invalidated when calling ArmDisableMmu() - ArmDisableMmu (); - - // Make sure nothing sneaked into the cache - ArmCleanInvalidateDataCache (); - ArmInvalidateInstructionCache (); - ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TAB= LE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F))); =20 // --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55434): https://edk2.groups.io/g/devel/message/55434 Mute This Topic: https://groups.io/mt/71732159/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55435+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55435+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345585; cv=none; d=zohomail.com; s=zohoarc; b=EbUugw6AszXaBMtyUdIITdG44L48VN9Bf8q64MGvYbbeophCmcazAejUvMHQRQrbmSH0CqdF5zCiB5Uzdkv2G1DwXWpNL+JfmAmbHSPDYzEpgOIZSvfCIvyaZFqVtIkjeUCenP6R0viDjv+wpQNzfYQdbBgs0isA0eV2Obf/Lm0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345585; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=oMTv4YEtnUXEUbJHYMOe7V9CZzKCbzb3+gtl+mvgqwU=; b=gxsVVKeOebXQaiY7UAHHsaoE4vgbsvQpIrbLrwP8at0ehNI5d2a88hPbtEz3wuGjVT5j4f7mX+c8hfgYOHjxr7NTfeAk3kcmEH8zIhD3H95qGhOly4YDlhic1mUqcMr/qX1WNYWyLGlMOcBrwsnSooRsIXjRxSoeVEhJOnyWXYs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55435+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583345585729455.9912173912204; Wed, 4 Mar 2020 10:13:05 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ehwKYY1788612xo4HF7Q4Dbq; Wed, 04 Mar 2020 10:13:05 -0800 X-Received: from mail-oi1-f196.google.com (mail-oi1-f196.google.com [209.85.167.196]) by mx.groups.io with SMTP id smtpd.web11.15498.1583345584796986499 for ; Wed, 04 Mar 2020 10:13:04 -0800 X-Received: by mail-oi1-f196.google.com with SMTP id c1so3082300oiy.2 for ; Wed, 04 Mar 2020 10:13:04 -0800 (PST) X-Gm-Message-State: 3ykeGb46GSTr5txTuv43NVQOx1787277AA= X-Google-Smtp-Source: ADFU+vuzWg3qT3SO5U6SxH9olxwm3I6BNHTVxOQvnydOvRd15ffNHNGUAhe3vszeP2zk6T8+CZj9Jg== X-Received: by 2002:aca:af49:: with SMTP id y70mr2729712oie.92.1583345583696; Wed, 04 Mar 2020 10:13:03 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:13:02 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 5/9] ArmPkg/ArmMmuLib AARCH64: cache-invalidate initial page table entries Date: Wed, 4 Mar 2020 19:12:42 +0100 Message-Id: <20200304181246.23513-6-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345585; bh=aRTvRwUGYdRI7yoATtnEWhvW2VKi720JrGZAzJV4zLk=; h=Cc:Date:From:Reply-To:Subject:To; b=U+LnFt/x86Svy/b605HOTQI5ObwxmJJVRRQbku+EDOzPsEr3K/epBZe1I0Psz33Vdse 8urLnDP+G5idafevNPFRXbtBmqS2Y+Z7x1J5GPKtZINF3haAHE2aBqZBKqAo4O+Qg2SIT XzeJN6L+cFYibjs4n7OasedYrWkrSs0Wql4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the AARCH64 version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if set/way operations were the appropriate method to achieve this, doing an invalidate-all first and then populating the page table entries creates a window where page table entries could be loaded speculatively into the caches before we modify them, and shadow the new values that we write there. So let's get rid of the blanket clean/invalidate operations, and instead, update ArmUpdateTranslationTableEntry () to invalidate each page table entry *after* it is written if the MMU is still disabled at this point. On ARMv8, it is guaranteed that memory accesses done by the page table walker are cache coherent, and so we can ignore the case where the MMU is on. Since the MMU and D-cache are already off when we reach this point, we can drop the MMU and D-cache disables as well. Maintenance of the I-cache is unnecessary, since we are not modifying any code, and the installed mapping is guaranteed to be 1:1. This means we can also leave it enabled while the page table population code is running. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 9 ++++++++- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 9 --------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library= /ArmLib/AArch64/ArmLibSupport.S index 1adf960377a2..f744cd6738b9 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -13,6 +13,8 @@ .set DAIF_RD_FIQ_BIT, (1 << 6) .set DAIF_RD_IRQ_BIT, (1 << 7) =20 +.set SCTLR_ELx_M_BIT_POS, (0) + ASM_FUNC(ArmReadMidr) mrs x0, midr_el1 // Read from Main ID Register (MIDR) ret @@ -122,11 +124,16 @@ ASM_FUNC(ArmUpdateTranslationTableEntry) lsr x1, x1, #12 EL1_OR_EL2_OR_EL3(x0) 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1 + mrs x2, sctlr_el1 b 4f 2: tlbi vae2, x1 // TLB Invalidate VA , EL2 + mrs x2, sctlr_el2 b 4f 3: tlbi vae3, x1 // TLB Invalidate VA , EL3 -4: dsb nsh + mrs x2, sctlr_el3 +4: tbnz x2, SCTLR_ELx_M_BIT_POS, 5f + dc ivac, x0 // invalidate in Dcache if MMU is still o= ff +5: dsb nsh isb ret =20 diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index e8f5c69e3136..204e33c75f95 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -699,15 +699,6 @@ ArmConfigureMmu ( =20 ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); =20 - // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs - ArmDisableMmu (); - ArmDisableDataCache (); - ArmDisableInstructionCache (); - - // Make sure nothing sneaked into the cache - ArmCleanInvalidateDataCache (); - ArmInvalidateInstructionCache (); - TranslationTableAttribute =3D TT_ATTR_INDX_INVALID; while (MemoryTable->Length !=3D 0) { =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55435): https://edk2.groups.io/g/devel/message/55435 Mute This Topic: https://groups.io/mt/71732161/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55436+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55436+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345588; cv=none; d=zohomail.com; s=zohoarc; b=PVPfzOX7KR8hw86j57Z/63MktaIoequ/xuEeE+YOCHs/EKtMzkPOtaP/KozwMOGsJj6t2XDaGD+cugH7lK7Qi217t7y4VazbxwWJdF0cZqr3aGKuEdsISnT2G9p1gS/LwI5zzYWosEc3BWl0kQ4bOyYrI5M3zkAGx+IOicpfuYQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345588; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=qrBFuzg6IMG/Aqwxly5JguTkunGQfGRE+/QyLreZC+Y=; b=igNVs12JlCFSPLCP3o5no+GcwtZF0Uv5frGvNbTbwulCTMJT0gOvi9SNWY8SiEpWEOe6Ni8NGzRp+Vpt6vrLHptyGi1r+fjfIevc0H8TA6Z6y1M5QEObJYUZ/vn3lS/Bk7LPhYaomJlXdiTpIsSH1K1chKqEADDp4cd9sutcMzc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55436+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583345588650605.664624577375; Wed, 4 Mar 2020 10:13:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4agOYY1788612xkCTvoZF1u1; Wed, 04 Mar 2020 10:13:08 -0800 X-Received: from mail-oi1-f195.google.com (mail-oi1-f195.google.com [209.85.167.195]) by mx.groups.io with SMTP id smtpd.web12.15679.1583345587027770705 for ; Wed, 04 Mar 2020 10:13:07 -0800 X-Received: by mail-oi1-f195.google.com with SMTP id c1so3082453oiy.2 for ; Wed, 04 Mar 2020 10:13:06 -0800 (PST) X-Gm-Message-State: WdyI7E1gNES6qyuI7hciWtaJx1787277AA= X-Google-Smtp-Source: ADFU+vv7klHkcQs5eAeT2PMTFds8Tl0enV7t5XucJJ3SWVwXMIYhIyVn/IORNm0CkP5c6wfTnS3LAw== X-Received: by 2002:aca:1903:: with SMTP id l3mr2553092oii.178.1583345585989; Wed, 04 Mar 2020 10:13:05 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.13.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:13:04 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 6/9] ArmPkg/ArmLib: move set/way helper functions into private header Date: Wed, 4 Mar 2020 19:12:43 +0100 Message-Id: <20200304181246.23513-7-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345588; bh=nLrSKPQz9JLA5WBs4eLkL3pUbKeWK/BG8Zsl46yob+8=; h=Cc:Date:From:Reply-To:Subject:To; b=WIyMmbNt1uS3FUtCBWCdpHweAMmhNGSmHlxW6/6hu6oa3GiNYqL7zxMrq/l/n1SIXil VkH9KJekxkEU7dagdvLQabfL0as6ChQrC+lF2zqTTCi3cORuRYeFhvvpKPOFcrB/a4T2/ XZzogV8jJJz+m020CsDI2I8knyAThyf1pK4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The clean/invalidate helper functions that operate on a single cache line identified by set, way and level in a special, architected format are only used by the implementations of the clean/invalidate routines that operate on the entire cache hierarchy, as exposed by ArmLib. The latter routines will be deprecated soon, so move the helpers out of ArmLib.h and into a private header so they are safe from abuse. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Include/Library/ArmLib.h | 18 ------------------ ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h | 18 ++++++++++++++++++ ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h | 18 ++++++++++++++++++ 3 files changed, 36 insertions(+), 18 deletions(-) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index e76a46d5f4ce..5a27b7c2fc27 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -211,24 +211,6 @@ ArmCleanInvalidateDataCacheEntryByMVA ( IN UINTN Address ); =20 -VOID -EFIAPI -ArmInvalidateDataCacheEntryBySetWay ( - IN UINTN SetWayFormat - ); - -VOID -EFIAPI -ArmCleanDataCacheEntryBySetWay ( - IN UINTN SetWayFormat - ); - -VOID -EFIAPI -ArmCleanInvalidateDataCacheEntryBySetWay ( - IN UINTN SetWayFormat - ); - VOID EFIAPI ArmEnableDataCache ( diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.h index ab9bcf553c4d..b2c8a8ea0b84 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h @@ -17,5 +17,23 @@ AArch64AllDataCachesOperation ( IN AARCH64_CACHE_OPERATION DataCacheOperation ); =20 +VOID +EFIAPI +ArmInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + #endif // __AARCH64_LIB_H__ =20 diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h b/ArmPkg/Library/ArmLib/A= rm/ArmV7Lib.h index c52fb9a1b484..93183e67230e 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h @@ -30,5 +30,23 @@ ArmV7AllDataCachesOperation ( IN ARM_V7_CACHE_OPERATION DataCacheOperation ); =20 +VOID +EFIAPI +ArmInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + #endif // __ARM_V7_LIB_H__ =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55436): https://edk2.groups.io/g/devel/message/55436 Mute This Topic: https://groups.io/mt/71732164/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55437+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55437+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345591; cv=none; d=zohomail.com; s=zohoarc; b=KW+CodWHR+juhT/GwFxG7oJ2tYgZtLW81FPlyWvtcLYz/FXN/aQMuUroPUKG3fHKUyQExRbm0MO2NwBqRBnUR1x++L+hkhhWZgd/kCX0vzC0DTUWQ6uheVtLVuC6A1B8FBXwzp8+d9vVYI0IKu2UlllEbenFPawx1Dy4onGIO6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345591; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=HfYgWvlyAX0raKeEWZQZzxcH4Ts09rwgZ3ABsIMOc7E=; b=ibpxWQJlsi9e+eJsQdgQSmx3brm7X1MPjBwDLz97DHPV8nKUext4V8q72f7Q9hEg76W+1iGGRJ4BPlagCs9SeeI5ucvzTbsxBzaPsbkHbe22YW34sZRnqkzH6TtsIcx0WW3ycWW5ieIzVtFzzlKOoYuqccTXltAPFtZcn0cXWVM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55437+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15833455911971006.3753590023141; Wed, 4 Mar 2020 10:13:11 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9avCYY1788612xtPn7YLfuQo; Wed, 04 Mar 2020 10:13:10 -0800 X-Received: from mail-ot1-f68.google.com (mail-ot1-f68.google.com [209.85.210.68]) by mx.groups.io with SMTP id smtpd.web11.15501.1583345590024092813 for ; Wed, 04 Mar 2020 10:13:10 -0800 X-Received: by mail-ot1-f68.google.com with SMTP id v19so2962398ote.8 for ; Wed, 04 Mar 2020 10:13:09 -0800 (PST) X-Gm-Message-State: 7X7ev2wx526rV3IYm4IsBB22x1787277AA= X-Google-Smtp-Source: ADFU+vtE6dwhWYAbsNQ5jjUjbe0+NVFOGskiq6AKpEkDodKagHIsGNyToH/Y+gBSEOGUjgaTaJ31Aw== X-Received: by 2002:a05:6830:1e09:: with SMTP id s9mr3199627otr.149.1583345588531; Wed, 04 Mar 2020 10:13:08 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:13:07 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 7/9] ArmPkg/ArmLib: clean up library includes Date: Wed, 4 Mar 2020 19:12:44 +0100 Message-Id: <20200304181246.23513-8-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345590; bh=yQGJoQT4S+URfRsl8gKizvtrGmOXyAA9VqlbG92HNR0=; h=Cc:Date:From:Reply-To:Subject:To; b=GBr4DHDPdkVy9kc42c3qazhsdfsASuAGzT+ZBtp9RE9/5J0aLvfjmN3Ma0S2DmZCdcJ iedEjlpSBfKCzsN+ZvDe1bvtxuk9AiV89r9I4U1oqRK+u59Bw0/wf6POiqAjzWlLj2yeS 6STDf4bRid7SEKlVelUlOVtIJpAMbkBvEn8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Suspiciously, ArmLib's INF does not contain a [LibraryClasses] section at all, but it turns out that all the library includes it contains (except for ArmLib.h itself) are actually bogus so let's just drop all of them. While at it, replace with the more accurate for a BASE type module, and put the includes in a consistent order. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 9 +++++---- ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c | 10 ++++++---- ArmPkg/Library/ArmLib/ArmLib.c | 2 -- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.c index 0ed8dae9a4b0..924bf48020e0 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -7,11 +7,12 @@ =20 **/ =20 -#include -#include +#include + #include -#include -#include + +#include + #include "AArch64Lib.h" #include "ArmLibPrivate.h" =20 diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c b/ArmPkg/Library/ArmLib/A= rm/ArmV7Lib.c index 38516d4f1b87..5d93aa6e0b8c 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c @@ -6,11 +6,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ -#include -#include + +#include + #include -#include -#include + +#include + #include "ArmV7Lib.h" #include "ArmLibPrivate.h" =20 diff --git a/ArmPkg/Library/ArmLib/ArmLib.c b/ArmPkg/Library/ArmLib/ArmLib.c index c682c3ab6339..3905d02c5e7e 100644 --- a/ArmPkg/Library/ArmLib/ArmLib.c +++ b/ArmPkg/Library/ArmLib/ArmLib.c @@ -10,8 +10,6 @@ #include =20 #include -#include -#include =20 #include "ArmLibPrivate.h" =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55437): https://edk2.groups.io/g/devel/message/55437 Mute This Topic: https://groups.io/mt/71732165/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55438+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55438+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345592; cv=none; d=zohomail.com; s=zohoarc; b=P1U5pvAaHaJdBIjMdnn7tuNr5Ghbvp7qW3asv4i1h9vQ1aVImFCpdQZZYxpAS62oPa5dWNzg7KM6iRBsUk6cwoDmkOLlBjm+3Neivic7ES2XIN602flqK+uuEo/mOuiMACeEZTFyrWhA/cjyUusLY4W2dvkw9mxnUsWM/SsRXR8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345592; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=29D0cg7TRYEyRr7YqD5dYe6v/m4Ph3NYaYI2PdoU2so=; b=JwTmk8dsX0TN2J0haPd7RJ2MjEra2tP15eA2L8YsHdevhH3PESrbJzx9Z2++gYbIwIHiXXILIvJD06DctFINbLdKqrciHVBT7qIiM1lsVWURJbMzZoizFdvMQk4W9iqBkbIBFgBcuwcAYiCy4RbFFP0iMhNEwgE9Uq1ge9MKj8k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55438+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583345592318585.8757476887378; Wed, 4 Mar 2020 10:13:12 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6mnEYY1788612xiDBQhEko51; Wed, 04 Mar 2020 10:13:12 -0800 X-Received: from mail-ot1-f50.google.com (mail-ot1-f50.google.com [209.85.210.50]) by mx.groups.io with SMTP id smtpd.web12.15682.1583345591574306569 for ; Wed, 04 Mar 2020 10:13:11 -0800 X-Received: by mail-ot1-f50.google.com with SMTP id 66so2944533otd.9 for ; Wed, 04 Mar 2020 10:13:11 -0800 (PST) X-Gm-Message-State: 6hi889TrFfhcRf7ptvOzk1tUx1787277AA= X-Google-Smtp-Source: ADFU+vti4R4g5yBQyEfLoxcwZq0ejGB3TwmtvWGY/guNyQMbXDmba8h3zcO40c/N0UaqVB4rZOtVpQ== X-Received: by 2002:a9d:6648:: with SMTP id q8mr3417892otm.105.1583345590581; Wed, 04 Mar 2020 10:13:10 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:13:09 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 8/9] ArmPkg/ArmLib: remove bogus protocol declaration Date: Wed, 4 Mar 2020 19:12:45 +0100 Message-Id: <20200304181246.23513-9-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345592; bh=muq1GkKI7FSLtPTCDmNooY3igZWXK9sr1FYX+1MDOjs=; h=Cc:Date:From:Reply-To:Subject:To; b=jTLwjOcPU3GJDttFHKUrosnbv17kBK6WpEETF01zz5/mSC1565DsgzcmFd1IEOSLkqb /ptTetthBTaSlYWPouizYr6kRxn47T3flNhnEVsqW8Hazh+grPBKLy8aYcmRTdgF2qjJB LCwku/IsgK4h2i8YQTMd59KG8Qr+At2ubn8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ArmLib is a BASE type library, which should not depend or even be aware on DXE type protocols. So drop the reference to gEfiCpuArchProtocolGuid. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/ArmBaseLib.inf | 3 --- 1 file changed, 3 deletions(-) diff --git a/ArmPkg/Library/ArmLib/ArmBaseLib.inf b/ArmPkg/Library/ArmLib/A= rmBaseLib.inf index 5e70990872f2..106a09f821e1 100644 --- a/ArmPkg/Library/ArmLib/ArmBaseLib.inf +++ b/ArmPkg/Library/ArmLib/ArmBaseLib.inf @@ -48,8 +48,5 @@ [Packages] ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec =20 -[Protocols] - gEfiCpuArchProtocolGuid - [FeaturePcd.ARM] gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55438): https://edk2.groups.io/g/devel/message/55438 Mute This Topic: https://groups.io/mt/71732166/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 27 23:48:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55439+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55439+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583345594; cv=none; d=zohomail.com; s=zohoarc; b=Kn64VIDyky80xaHN6LiIVcnRGEifDI5jnRO4QLMm/1JHc+ub4LcdmUmTj46taRa2J1bb2VFRq0RaTmv13VMexKxNytyXtXN7L23U3vhAvEn6GQif5BPSqgBX/EBgpqrOs4lw3MqnS6lz4wIh9uaqJQB02w+gkxIFNo8ytmKb6Ro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583345594; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=IyzUwZhRXf8ytcrCVSmQkbBti6hh+u9xLwX7h1lbKPY=; b=chBrOf7CumEu2X+5rqTVX8eEVai9khOUhTrNpKlmAe2GPFGw0G1ozxJTNAXmDWBCUy/okKOKTQcbJfYR3L+72TYrdmKaNni0sKxJnOjwzKxVW151l8rSSkUsBNl83PKbcWan4wZ6DIVPXLAxhZMoMPx6/NVK02nuWOv0u4Euc/k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55439+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15833455947245.270236231844137; Wed, 4 Mar 2020 10:13:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id YZo2YY1788612xjbz1lnFirk; Wed, 04 Mar 2020 10:13:14 -0800 X-Received: from mail-ot1-f66.google.com (mail-ot1-f66.google.com [209.85.210.66]) by mx.groups.io with SMTP id smtpd.web11.15502.1583345593566510654 for ; Wed, 04 Mar 2020 10:13:13 -0800 X-Received: by mail-ot1-f66.google.com with SMTP id v22so2937645otq.11 for ; Wed, 04 Mar 2020 10:13:13 -0800 (PST) X-Gm-Message-State: 3RMWeOUgCOlxwGgfsX7vkL70x1787277AA= X-Google-Smtp-Source: ADFU+vueXbtsc1EH0wG6B9ckzIXT86CaRgD4ihxxClOOj9FxdseQWDnoY++xZgRQaEqV7sv75Y1oLA== X-Received: by 2002:a05:6830:16c8:: with SMTP id l8mr3335971otr.2.1583345592526; Wed, 04 Mar 2020 10:13:12 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:13:11 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 9/9] ArmPkg/ArmLib: ASSERT on set/way cache ops being used with MMU on Date: Wed, 4 Mar 2020 19:12:46 +0100 Message-Id: <20200304181246.23513-10-ard.biesheuvel@linaro.org> In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583345594; bh=5y09hrkjUlOZFe0/egXmteYc9QMn5g82nPh7DhpQVRk=; h=Cc:Date:From:Reply-To:Subject:To; b=J8yDzTk/HdRw3gSEqfbv6vzDAvGPafqmIn1TrjAOePzCZjKbm1I/XJ54TGtG+f8Zgae 41rORm2zH8OkveWD2YmFs9XzFmhbRQRDXpA2AN9PmuxpQuOWJVMLcrnLUSD12Tugs4fWS qJuwolknTwxRxXPyQ9pbVbx3eXjI1wn4Zag= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On ARMv7 and up, doing cache maintenance by set/way is only permitted in the context of on/offlining a core, and any other uses should be avoided. Add ASSERT()s in the right place to ensure that any uses with the MMU enabled are caught in DEBUG builds. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 7 +++++++ ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c | 7 +++++++ ArmPkg/Library/ArmLib/ArmBaseLib.inf | 3 +++ 3 files changed, 17 insertions(+) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.c index 924bf48020e0..3fbd591192e2 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -10,6 +10,7 @@ #include =20 #include +#include =20 #include =20 @@ -41,6 +42,8 @@ ArmInvalidateDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay); } @@ -51,6 +54,8 @@ ArmCleanInvalidateDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay); } @@ -61,6 +66,8 @@ ArmCleanDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay); } diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c b/ArmPkg/Library/ArmLib/A= rm/ArmV7Lib.c index 5d93aa6e0b8c..2c4a23e1a1b2 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c @@ -10,6 +10,7 @@ #include =20 #include +#include =20 #include =20 @@ -41,6 +42,8 @@ ArmInvalidateDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay); } @@ -51,6 +54,8 @@ ArmCleanInvalidateDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay); } @@ -61,6 +66,8 @@ ArmCleanDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay); } diff --git a/ArmPkg/Library/ArmLib/ArmBaseLib.inf b/ArmPkg/Library/ArmLib/A= rmBaseLib.inf index 106a09f821e1..f61c71b673d1 100644 --- a/ArmPkg/Library/ArmLib/ArmBaseLib.inf +++ b/ArmPkg/Library/ArmLib/ArmBaseLib.inf @@ -44,6 +44,9 @@ [Sources.AARCH64] AArch64/AArch64Support.S AArch64/AArch64ArchTimerSupport.S =20 +[LibraryClasses] + DebugLib + [Packages] ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55439): https://edk2.groups.io/g/devel/message/55439 Mute This Topic: https://groups.io/mt/71732167/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-