From nobody Mon May 6 00:57:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55029+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55029+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582824336; cv=none; d=zohomail.com; s=zohoarc; b=KU7RESW40jU3ciIGwkwDC5I730AbfzL0h/2WftSk95yMnDxAKcBf1qnBsiYbqKNGPPLbanvao6SgK25x6g8l9iYFf1976qWrblAFZYQjQA4LJWi0crKpsZRSLyXaPDZIDkWG1hE8uGjQs483g64rpdcYXfdMcsSDEtnMVpoSGKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582824336; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=tsOpeo7cOBIwsjKIYtkZByv6A5gvvUwSrE2w47sKc64=; b=VM83OorzTNJVO2Aqw4kJavtbU1kgG/NhslALSQj30cZaihLvx2lVAY6wVGrQvqC9vJ9dmhM4QoKMnlBmiSAYLxtpl3HPlaMR1NtP3zR24lHWcGpYgsMhmuqL+B+LmIf7NV7ywhN6HeEONtoepbQRBLEWCb0yQwuEu63PiwD4hvk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55029+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582824336948177.5164978944381; Thu, 27 Feb 2020 09:25:36 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 25s9YY1788612xx7F15lmTx3; Thu, 27 Feb 2020 09:25:35 -0800 X-Received: from mga04.intel.com (mga04.intel.com []) by mx.groups.io with SMTP id smtpd.web12.7477.1582824332223573542 for ; Thu, 27 Feb 2020 09:25:35 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2020 09:25:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,492,1574150400"; d="scan'208";a="261560337" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by fmsmga004.fm.intel.com with ESMTP; 27 Feb 2020 09:25:33 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCHv3 1/5] MdeModulePkg/SdMmcPciHcDxe: Enhance driver traces Date: Thu, 27 Feb 2020 18:25:22 +0100 Message-Id: <20200227172526.5876-2-mateusz.albecki@intel.com> In-Reply-To: <20200227172526.5876-1-mateusz.albecki@intel.com> References: <20200227172526.5876-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: ze6YGVQQU5WQVeOJEIV0sfiCx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582824335; bh=Vd3Q27Za9Ryt+eFX7KZpT9QirezPDq+0VHn2fkyfF8Q=; h=Cc:Date:From:Reply-To:Subject:To; b=NbZtqlTIjghH6tLO0YZl0KeYtgXu6QN6C77SYL3mgs41tpXXlztcDzvXFsFpt5OS6kW tDguAT3rTsvsQNi6daaGYTbk06MC4CFKClo5PXNeSXIaATVO1QfhGta8/k0/HqkHAe+0C LPlvoBJjrCVYxr1Lwf5DUKnDFkvcnaYvn8c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To allow for easier debug of failing commands we have added a capability to print TRB and command packet when we start execution of the TRB(on DEBUG_VERBOSE level) and when the TRB failed to execute correctly(on DEBUG_ERROR level). Additionally we will also print error interrupt status and interrupt status register on failed SD command. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu Tested-by: Hao A Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 87 ++++++++++++++++++++= ++++ 1 file changed, 87 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 43626fff48..71cf5a78f9 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -1645,6 +1645,82 @@ BuildAdmaDescTable ( return EFI_SUCCESS; } =20 +/** + Prints the contents of the command packet to the debug port. + + @param[in] DebugLevel Debug level at which the packet should be printed. + @param[in] Packet Pointer to packet to print. +**/ +VOID +SdMmcPrintPacket ( + IN UINT32 DebugLevel, + IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet + ) +{ + if (Packet =3D=3D NULL) { + return; + } + + DEBUG ((DebugLevel, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n")); + if (Packet->SdMmcCmdBlk !=3D NULL) { + DEBUG ((DebugLevel, "Command index: %d, argument: %X\n", Packet->SdMmc= CmdBlk->CommandIndex, Packet->SdMmcCmdBlk->CommandArgument)); + DEBUG ((DebugLevel, "Command type: %d, response type: %d\n", Packet->S= dMmcCmdBlk->CommandType, Packet->SdMmcCmdBlk->ResponseType)); + } + if (Packet->SdMmcStatusBlk !=3D NULL) { + DEBUG ((DebugLevel, "Response 0: %X, 1: %X, 2: %X, 3: %X\n", + Packet->SdMmcStatusBlk->Resp0, + Packet->SdMmcStatusBlk->Resp1, + Packet->SdMmcStatusBlk->Resp2, + Packet->SdMmcStatusBlk->Resp3 + )); + } + DEBUG ((DebugLevel, "Timeout: %ld\n", Packet->Timeout)); + DEBUG ((DebugLevel, "InDataBuffer: %p\n", Packet->InDataBuffer)); + DEBUG ((DebugLevel, "OutDataBuffer: %p\n", Packet->OutDataBuffer)); + DEBUG ((DebugLevel, "InTransferLength: %d\n", Packet->InTransferLength)); + DEBUG ((DebugLevel, "OutTransferLength: %d\n", Packet->OutTransferLength= )); + DEBUG ((DebugLevel, "TransactionStatus: %r\n", Packet->TransactionStatus= )); +} + +/** + Prints the contents of the TRB to the debug port. + + @param[in] DebugLevel Debug level at which the TRB should be printed. + @param[in] Trb Pointer to the TRB structure. +**/ +VOID +SdMmcPrintTrb ( + IN UINT32 DebugLevel, + IN SD_MMC_HC_TRB *Trb + ) +{ + if (Trb =3D=3D NULL) { + return; + } + + DEBUG ((DebugLevel, "Printing SD_MMC_HC_TRB\n")); + DEBUG ((DebugLevel, "Slot: %d\n", Trb->Slot)); + DEBUG ((DebugLevel, "BlockSize: %d\n", Trb->BlockSize)); + DEBUG ((DebugLevel, "Data: %p\n", Trb->Data)); + DEBUG ((DebugLevel, "DataLen: %d\n", Trb->DataLen)); + DEBUG ((DebugLevel, "Read: %d\n", Trb->Read)); + DEBUG ((DebugLevel, "DataPhy: %lX\n", Trb->DataPhy)); + DEBUG ((DebugLevel, "DataMap: %p\n", Trb->DataMap)); + DEBUG ((DebugLevel, "Mode: %d\n", Trb->Mode)); + DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode)); + DEBUG ((DebugLevel, "Event: %p\n", Trb->Event)); + DEBUG ((DebugLevel, "Started: %d\n", Trb->Started)); + DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout)); + DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries)); + DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc)); + DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc)); + DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc)); + DEBUG ((DebugLevel, "AdmaMap: %p\n", Trb->AdmaMap)); + DEBUG ((DebugLevel, "AdmaPages: %X\n", Trb->AdmaPages)); + + SdMmcPrintPacket (DebugLevel, Trb->Packet); +} + /** Create a new TRB for the SD/MMC cmd request. =20 @@ -2236,6 +2312,10 @@ SdMmcCheckAndRecoverErrors ( return Status; } =20 + DEBUG ((DEBUG_ERROR, "Error reported by SDHCI\n")); + DEBUG ((DEBUG_ERROR, "Interrupt status =3D %X\n", IntStatus)); + DEBUG ((DEBUG_ERROR, "Error interrupt status =3D %X\n", ErrIntStatus)); + // // If the data timeout error is reported // but data transfer is signaled as completed we @@ -2439,6 +2519,13 @@ Done: =20 if (Status !=3D EFI_NOT_READY) { SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "TRB failed with %r\n", Status)); + SdMmcPrintTrb (DEBUG_ERROR, Trb); + } else { + DEBUG ((DEBUG_VERBOSE, "TRB success\n")); + SdMmcPrintTrb (DEBUG_VERBOSE, Trb); + } } =20 return Status; --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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View/Reply Online (#55029): https://edk2.groups.io/g/devel/message/55029 Mute This Topic: https://groups.io/mt/71591179/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 00:57:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55030+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55030+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582824339; cv=none; d=zohomail.com; s=zohoarc; b=QXfhHkk/BJDOgcRh9n7DFJA4+fCLpbwvqJmoYMQQ675/lmUSlZhROAsm8vo4mwUO1zBFAibSE7hsCmlBnr/5KBjsN/ezaDwFo5xspRuyki0wAF+CIY+MlW6J+PtXbMvOru9pOsm4gkhV8OU99Le2+YCv+9zi06k9LgpikwU4LD4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582824339; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=tVV/95xemXiy8SgWkOe0UaSi5XheuKwRJzYFTyVkYYA=; b=P1IPND9ZHVcorX8MwTvCN+hOMxtbctnSOXf0Meza/Rd9RxD9QvTOpR23lP4Y7kci3LadUB3a1CiObBTnEHcVba7XZi+xxEulD81EOLWFkOlKc+5SAf0053l8tVQf20qVPq0Kw7ugx5K22cRJMCCy6V4mguB+s53HywyXK7tVYHM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55030+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582824339953778.3050163206141; Thu, 27 Feb 2020 09:25:39 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id erIhYY1788612xLoffCIUImr; Thu, 27 Feb 2020 09:25:38 -0800 X-Received: from mga04.intel.com (mga04.intel.com []) by mx.groups.io with SMTP id smtpd.web12.7477.1582824332223573542 for ; Thu, 27 Feb 2020 09:25:38 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2020 09:25:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,492,1574150400"; d="scan'208";a="261560364" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by fmsmga004.fm.intel.com with ESMTP; 27 Feb 2020 09:25:36 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCHv3 2/5] MdeModulePkg/SdMmcPciHcDxe: Read response on command completion Date: Thu, 27 Feb 2020 18:25:23 +0100 Message-Id: <20200227172526.5876-3-mateusz.albecki@intel.com> In-Reply-To: <20200227172526.5876-1-mateusz.albecki@intel.com> References: <20200227172526.5876-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: VmKVMZTkNNcXSDEjA5G6eabGx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582824338; bh=tRQ8RxibSZdmqLRBWPISDv+2whgbyLG0wKZ9ohKXBfU=; h=Cc:Date:From:Reply-To:Subject:To; b=FHzzFC8MOd2PX90Ms8LDkh1fZzdNMQOtzr0YKjy9mZrnm/hw4pGM/A+8ZwwwqJuZRgs vmY7xqojpuUnD2rjBn1zJ0MAAtDPNbXBWxdqOC9WpffwNrINBAOhxwHVBGFORArenN4/3 Neheul2kQU7E7fieJtAOAHxC3H4Bn9EYblU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SdMmcPciHcDxe driver used to read response only after command and data transfer completed. According to SDHCI specification response data is ready after the command complete status is set by the host controller. Getting the response data early will help debugging the cases when command completed but data transfer timed out. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu Tested-by: Hao A Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 201 +++++++++++++++--= ---- 2 files changed, 144 insertions(+), 58 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h index 5bc3577ba2..15b7d12596 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h @@ -153,6 +153,7 @@ typedef struct { =20 EFI_EVENT Event; BOOLEAN Started; + BOOLEAN CommandComplete; UINT64 Timeout; UINT32 Retries; =20 diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 71cf5a78f9..205ec86032 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -1710,6 +1710,7 @@ SdMmcPrintTrb ( DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode)); DEBUG ((DebugLevel, "Event: %p\n", Trb->Event)); DEBUG ((DebugLevel, "Started: %d\n", Trb->Started)); + DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete)); DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout)); DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries)); DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc)); @@ -1760,6 +1761,7 @@ SdMmcCreateTrb ( Trb->Packet =3D Packet; Trb->Event =3D Event; Trb->Started =3D FALSE; + Trb->CommandComplete =3D FALSE; Trb->Timeout =3D Packet->Timeout; Trb->Retries =3D SD_MMC_TRB_RETRIES; Trb->Private =3D Private; @@ -2350,6 +2352,99 @@ SdMmcCheckAndRecoverErrors ( return ErrorStatus; } =20 +/** + Reads the response data into the TRB buffer. + This function assumes that caller made sure that + command has completed. + + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. + + @retval EFI_SUCCESS Response read successfully. + @retval Others Failed to get response. +**/ +EFI_STATUS +SdMmcGetResponse ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN SD_MMC_HC_TRB *Trb + ) +{ + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + UINT8 Index; + UINT32 Response[4]; + EFI_STATUS Status; + + Packet =3D Trb->Packet; + + if (Packet->SdMmcCmdBlk->CommandType =3D=3D SdMmcCommandTypeBc) { + return EFI_SUCCESS; + } + + for (Index =3D 0; Index < 4; Index++) { + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Trb->Slot, + SD_MMC_HC_RESPONSE + Index * 4, + TRUE, + sizeof (UINT32), + &Response[Index] + ); + if (EFI_ERROR (Status)) { + return Status; + } + } + CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response)); + + return EFI_SUCCESS; +} + +/** + Checks if the command completed. If the command + completed it gets the response and records the + command completion in the TRB. + + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. + @param[in] IntStatus Snapshot of the normal interrupt status register. + + @retval EFI_SUCCESS Command completed successfully. + @retval EFI_NOT_READY Command completion still pending. + @retval Others Command failed to complete. +**/ +EFI_STATUS +SdMmcCheckCommandComplete ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN SD_MMC_HC_TRB *Trb, + IN UINT16 IntStatus + ) +{ + UINT16 Data16; + EFI_STATUS Status; + + if ((IntStatus & BIT0) !=3D 0) { + Data16 =3D BIT0; + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Trb->Slot, + SD_MMC_HC_NOR_INT_STS, + FALSE, + sizeof (Data16), + &Data16 + ); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D SdMmcGetResponse (Private, Trb); + if (EFI_ERROR (Status)) { + return Status; + } + Trb->CommandComplete =3D TRUE; + return EFI_SUCCESS; + } + + return EFI_NOT_READY; +} + /** Check the TRB execution result. =20 @@ -2370,9 +2465,7 @@ SdMmcCheckTrbResult ( EFI_STATUS Status; EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; UINT16 IntStatus; - UINT32 Response[4]; UINT64 SdmaAddr; - UINT8 Index; UINT32 PioLength; =20 Packet =3D Trb->Packet; @@ -2400,6 +2493,54 @@ SdMmcCheckTrbResult ( goto Done; } =20 + // + // Tuning commands are the only ones that do not generate command + // complete interrupt. Process them here before entering the code + // that waits for command completion. + // + if (((Private->Slot[Trb->Slot].CardType =3D=3D EmmcCardType) && + (Packet->SdMmcCmdBlk->CommandIndex =3D=3D EMMC_SEND_TUNING_BLOCK)) = || + ((Private->Slot[Trb->Slot].CardType =3D=3D SdCardType) && + (Packet->SdMmcCmdBlk->CommandIndex =3D=3D SD_SEND_TUNING_BLOCK))) { + // + // When performing tuning procedure (Execute Tuning is set to 1) throu= gh PIO mode, + // wait Buffer Read Ready bit of Normal Interrupt Status Register to b= e 1. + // Refer to SD Host Controller Simplified Specification 3.0 figure 2-2= 9 for details. + // + if ((IntStatus & BIT5) =3D=3D BIT5) { + // + // Clear Buffer Read Ready interrupt at first. + // + IntStatus =3D BIT5; + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FAL= SE, sizeof (IntStatus), &IntStatus); + // + // Read data out from Buffer Port register + // + for (PioLength =3D 0; PioLength < Trb->DataLen; PioLength +=3D 4) { + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, = TRUE, 4, (UINT8*)Trb->Data + PioLength); + } + Status =3D EFI_SUCCESS; + goto Done; + } + } + + if (!Trb->CommandComplete) { + Status =3D SdMmcCheckCommandComplete (Private, Trb, IntStatus); + if (EFI_ERROR (Status)) { + goto Done; + } else { + // + // If the command doesn't require data transfer skip the transfer + // complete checking. + // + if ((Packet->SdMmcCmdBlk->CommandType !=3D SdMmcCommandTypeAdtc) && + (Packet->SdMmcCmdBlk->ResponseType !=3D SdMmcResponseTypeR1b) && + (Packet->SdMmcCmdBlk->ResponseType !=3D SdMmcResponseTypeR5b)) { + goto Done; + } + } + } + // // Check Transfer Complete bit is set or not. // @@ -2457,65 +2598,9 @@ SdMmcCheckTrbResult ( Trb->DataPhy =3D (UINT64)(UINTN)SdmaAddr; } =20 - if ((Packet->SdMmcCmdBlk->CommandType !=3D SdMmcCommandTypeAdtc) && - (Packet->SdMmcCmdBlk->ResponseType !=3D SdMmcResponseTypeR1b) && - (Packet->SdMmcCmdBlk->ResponseType !=3D SdMmcResponseTypeR5b)) { - if ((IntStatus & BIT0) =3D=3D BIT0) { - Status =3D EFI_SUCCESS; - goto Done; - } - } - - if (((Private->Slot[Trb->Slot].CardType =3D=3D EmmcCardType) && - (Packet->SdMmcCmdBlk->CommandIndex =3D=3D EMMC_SEND_TUNING_BLOCK)) = || - ((Private->Slot[Trb->Slot].CardType =3D=3D SdCardType) && - (Packet->SdMmcCmdBlk->CommandIndex =3D=3D SD_SEND_TUNING_BLOCK))) { - // - // When performing tuning procedure (Execute Tuning is set to 1) throu= gh PIO mode, - // wait Buffer Read Ready bit of Normal Interrupt Status Register to b= e 1. - // Refer to SD Host Controller Simplified Specification 3.0 figure 2-2= 9 for details. - // - if ((IntStatus & BIT5) =3D=3D BIT5) { - // - // Clear Buffer Read Ready interrupt at first. - // - IntStatus =3D BIT5; - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FAL= SE, sizeof (IntStatus), &IntStatus); - // - // Read data out from Buffer Port register - // - for (PioLength =3D 0; PioLength < Trb->DataLen; PioLength +=3D 4) { - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, = TRUE, 4, (UINT8*)Trb->Data + PioLength); - } - Status =3D EFI_SUCCESS; - goto Done; - } - } =20 Status =3D EFI_NOT_READY; Done: - // - // Get response data when the cmd is executed successfully. - // - if (!EFI_ERROR (Status)) { - if (Packet->SdMmcCmdBlk->CommandType !=3D SdMmcCommandTypeBc) { - for (Index =3D 0; Index < 4; Index++) { - Status =3D SdMmcHcRwMmio ( - Private->PciIo, - Trb->Slot, - SD_MMC_HC_RESPONSE + Index * 4, - TRUE, - sizeof (UINT32), - &Response[Index] - ); - if (EFI_ERROR (Status)) { - SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE); - return Status; - } - } - CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response)); - } - } =20 if (Status !=3D EFI_NOT_READY) { SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE); --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydz= ial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-31= 6 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata= i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wi= adomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiek= olwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by others is strictly prohibited. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55030): https://edk2.groups.io/g/devel/message/55030 Mute This Topic: https://groups.io/mt/71591180/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 00:57:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55031+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55031+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582824342; cv=none; d=zohomail.com; s=zohoarc; b=h9nF9N85hTAIbuYC/gW7AgdI2LEqUKs0bAhy4ZPbiQBNQOm2qU41R9phF9XvP8BJuJWya2x79gLKZwdVo8HUq2NCEkOu7K8Ix4UYzNtcDo3DD4ZMyPQPz0uqLB+gOgjLgfoPRRO2I6PdILs+fKMT5Bb8ilTLhixUMjh+pon/FVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582824342; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=EEMUvbMToVt/e8HOJw6c9Tk4Gy4O6c/W2eB1Kw3l6tU=; b=gAJekYmcN04IPsNPy2VwQewyqGlUeU4fEuCi7qcb5fpSVUxXz/cX5Qu8/HFJnhhFEhB9vIVLFrgWGf9Yi/TqbTnpyhuv5IU4F4fZSr9doiaMsPUoxIK79pgztoU7UdjdDM0Ik5OPS3dsFWNC3mfmhCbVT0o4NLNVExvK82Sle8Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55031+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582824342289898.7633662084055; Thu, 27 Feb 2020 09:25:42 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id bEeqYY1788612xYws4JAqBZ9; Thu, 27 Feb 2020 09:25:41 -0800 X-Received: from mga04.intel.com (mga04.intel.com []) by mx.groups.io with SMTP id smtpd.web12.7477.1582824332223573542 for ; Thu, 27 Feb 2020 09:25:40 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2020 09:25:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,492,1574150400"; d="scan'208";a="261560382" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by fmsmga004.fm.intel.com with ESMTP; 27 Feb 2020 09:25:39 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCHv3 3/5] MdeModulePkg/SdMmcPciHcDxe: Refactor data transfer completion Date: Thu, 27 Feb 2020 18:25:24 +0100 Message-Id: <20200227172526.5876-4-mateusz.albecki@intel.com> In-Reply-To: <20200227172526.5876-1-mateusz.albecki@intel.com> References: <20200227172526.5876-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: C3hE5phvHEOVlL9LYTy9iIXKx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582824341; bh=VdLUQO/qKfjiFWLcAmqVb8Ww4/e8PGLh2oVGyYi4z/w=; h=Cc:Date:From:Reply-To:Subject:To; b=KU7j6pxXe/a0wRlMFQrvJkEFd5p8HaBAB63HSD95iPFYYXyj96z35nWlr0nYOEdPIIW weT52WZEUymwrORMeu3eJZMafLgtPV98a5y4AC+RDyutVmMOmf4KT0y7u9QOEs/h7wwwc b6ofH/0X2xgeTDz7gNKPh6nBvXRAVilSkVg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch refactors the way in which the driver will check the data transfer completion. Data transfer related functionalities have been moved to separate function. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu Tested-by: Hao A Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 181 ++++++++++++++-----= ---- 1 file changed, 112 insertions(+), 69 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 205ec86032..bb699027e3 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -2445,6 +2445,112 @@ SdMmcCheckCommandComplete ( return EFI_NOT_READY; } =20 +/** + Update the SDMA address on the SDMA buffer boundary interrupt. + + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. + + @retval EFI_SUCCESS Updated SDMA buffer address. + @retval Others Failed to update SDMA buffer address. +**/ +EFI_STATUS +SdMmcUpdateSdmaAddress ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN SD_MMC_HC_TRB *Trb + ) +{ + UINT64 SdmaAddr; + EFI_STATUS Status; + + SdmaAddr =3D SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUN= DARY); + + if (Private->ControllerVersion[Trb->Slot] >=3D SD_MMC_HC_CTRL_VER_400) { + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Trb->Slot, + SD_MMC_HC_ADMA_SYS_ADDR, + FALSE, + sizeof (UINT64), + &SdmaAddr + ); + } else { + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Trb->Slot, + SD_MMC_HC_SDMA_ADDR, + FALSE, + sizeof (UINT32), + &SdmaAddr + ); + } + + if (EFI_ERROR (Status)) { + return Status; + } + + Trb->DataPhy =3D (UINT64)(UINTN)SdmaAddr; + return EFI_SUCCESS; +} + +/** + Checks if the data transfer completed and performs any actions + neccessary to continue the data transfer such as SDMA system + address fixup or PIO data transfer. + + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. + @param[in] IntStatus Snapshot of the normal interrupt status register. + + @retval EFI_SUCCESS Data transfer completed successfully. + @retval EFI_NOT_READY Data transfer completion still pending. + @retval Others Data transfer failed to complete. +**/ +EFI_STATUS +SdMmcCheckDataTransfer ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN SD_MMC_HC_TRB *Trb, + IN UINT16 IntStatus + ) +{ + UINT16 Data16; + EFI_STATUS Status; + + if ((IntStatus & BIT1) !=3D 0) { + Data16 =3D BIT1; + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Trb->Slot, + SD_MMC_HC_NOR_INT_STS, + FALSE, + sizeof (Data16), + &Data16 + ); + return Status; + } + + if ((Trb->Mode =3D=3D SdMmcSdmaMode) && ((IntStatus & BIT3) !=3D 0)) { + Data16 =3D BIT3; + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Trb->Slot, + SD_MMC_HC_NOR_INT_STS, + FALSE, + sizeof (Data16), + &Data16 + ); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D SdMmcUpdateSdmaAddress (Private, Trb); + if (EFI_ERROR (Status)) { + return Status; + } + } + + return EFI_NOT_READY; +} + /** Check the TRB execution result. =20 @@ -2465,7 +2571,6 @@ SdMmcCheckTrbResult ( EFI_STATUS Status; EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; UINT16 IntStatus; - UINT64 SdmaAddr; UINT32 PioLength; =20 Packet =3D Trb->Packet; @@ -2528,80 +2633,18 @@ SdMmcCheckTrbResult ( Status =3D SdMmcCheckCommandComplete (Private, Trb, IntStatus); if (EFI_ERROR (Status)) { goto Done; - } else { - // - // If the command doesn't require data transfer skip the transfer - // complete checking. - // - if ((Packet->SdMmcCmdBlk->CommandType !=3D SdMmcCommandTypeAdtc) && - (Packet->SdMmcCmdBlk->ResponseType !=3D SdMmcResponseTypeR1b) && - (Packet->SdMmcCmdBlk->ResponseType !=3D SdMmcResponseTypeR5b)) { - goto Done; - } } } =20 - // - // Check Transfer Complete bit is set or not. - // - if ((IntStatus & BIT1) =3D=3D BIT1) { - goto Done; - } - - // - // Check if DMA interrupt is signalled for the SDMA transfer. - // - if ((Trb->Mode =3D=3D SdMmcSdmaMode) && ((IntStatus & BIT3) =3D=3D BIT3)= ) { - // - // Clear DMA interrupt bit. - // - IntStatus =3D BIT3; - Status =3D SdMmcHcRwMmio ( - Private->PciIo, - Trb->Slot, - SD_MMC_HC_NOR_INT_STS, - FALSE, - sizeof (IntStatus), - &IntStatus - ); - if (EFI_ERROR (Status)) { - goto Done; - } - // - // Update SDMA Address register. - // - SdmaAddr =3D SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BO= UNDARY); - - if (Private->ControllerVersion[Trb->Slot] >=3D SD_MMC_HC_CTRL_VER_400)= { - Status =3D SdMmcHcRwMmio ( - Private->PciIo, - Trb->Slot, - SD_MMC_HC_ADMA_SYS_ADDR, - FALSE, - sizeof (UINT64), - &SdmaAddr - ); - } else { - Status =3D SdMmcHcRwMmio ( - Private->PciIo, - Trb->Slot, - SD_MMC_HC_SDMA_ADDR, - FALSE, - sizeof (UINT32), - &SdmaAddr - ); - } - - if (EFI_ERROR (Status)) { - goto Done; - } - Trb->DataPhy =3D (UINT64)(UINTN)SdmaAddr; + if (Packet->SdMmcCmdBlk->CommandType =3D=3D SdMmcCommandTypeAdtc || + Packet->SdMmcCmdBlk->ResponseType =3D=3D SdMmcResponseTypeR1b || + Packet->SdMmcCmdBlk->ResponseType =3D=3D SdMmcResponseTypeR5b) { + Status =3D SdMmcCheckDataTransfer (Private, Trb, IntStatus); + } else { + Status =3D EFI_SUCCESS; } =20 - - Status =3D EFI_NOT_READY; Done: - if (Status !=3D EFI_NOT_READY) { SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE); if (EFI_ERROR (Status)) { --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydz= ial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-31= 6 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata= i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wi= adomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiek= olwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by others is strictly prohibited. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55031): https://edk2.groups.io/g/devel/message/55031 Mute This Topic: https://groups.io/mt/71591182/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 00:57:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55032+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55032+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582824344; cv=none; d=zohomail.com; s=zohoarc; b=DDgffL+6LCXB7CRJkA17U1pxkPZUCXIlZCzHNuqPsDp1M35JLR/Wm2b1wLgfHLxks9qGSfZr/ej5zoh7AI/Glh2TXXG+U00yrmr4kK6fcHpXpJl+PipjAOBjBPn0ZcvZtMck0eZwBtTfSRWh0zgCmZD55yR6USmvbVLHUjBoa8Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582824344; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=IVSuVysrFIWm89CYMHNCRMoy6oz1tqS+kJxsCp+rPZ0=; b=ghFOGiaoaN29g+0Nw9B2ZoA5Tt3wYRE2UFxF9yrDsmioTTUudnvy8Spkd6TLjroDRd66t4OJlf+/llrMbyL/qhdgrvd5jS0Cxy7iSMxTlfn4C+ypWcW1oGA6pk1NHrfZnD/yRe6KmFW0zgbf1YmiPlAB3eRG2hjgiU2l+1RrkNI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55032+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582824344877505.4466475998579; Thu, 27 Feb 2020 09:25:44 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id PrknYY1788612xMm72uJcSEo; Thu, 27 Feb 2020 09:25:43 -0800 X-Received: from mga04.intel.com (mga04.intel.com []) by mx.groups.io with SMTP id smtpd.web12.7477.1582824332223573542 for ; Thu, 27 Feb 2020 09:25:43 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2020 09:25:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,492,1574150400"; d="scan'208";a="261560425" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by fmsmga004.fm.intel.com with ESMTP; 27 Feb 2020 09:25:41 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCHv3 4/5] MdeModulePkg/SdMmcPciHcDxe: Do not map memory for non DMA transfer Date: Thu, 27 Feb 2020 18:25:25 +0100 Message-Id: <20200227172526.5876-5-mateusz.albecki@intel.com> In-Reply-To: <20200227172526.5876-1-mateusz.albecki@intel.com> References: <20200227172526.5876-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: yssu2nkCRisRkqmhxKlRPurUx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582824343; bh=0kyQref1y5oXRoKH0aQky60LDoJYRPrcLVP3nV3no40=; h=Cc:Date:From:Reply-To:Subject:To; b=mdarAqyG4OLsWZ8Od56mzkGYeW3I9GG1A+JyRVtEPlfA0q/WFSnLl+SjvQ9X6d6p2Z+ OA+dmLAZ/SLCezSPZp7nlOu4NBkt8shYjmX0wGyvXia2cai3VCpBOEujN2KKq3zavmbxS hnZLcgIB1TFavuQm8FCnGuZGUVVuFD92fmM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Driver code used to map memory for DMA transfer even if host doesn't support DMA. This is causing memory corruption when driver transfers data using PIO. This change refactors the code to skip call to PciIo->Map for non DMA transfers. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu Tested-by: Hao A Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 88 ++++++++++++++++----= ---- 1 file changed, 61 insertions(+), 27 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index bb699027e3..422862577e 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -1722,6 +1722,62 @@ SdMmcPrintTrb ( SdMmcPrintPacket (DebugLevel, Trb->Packet); } =20 +/** + Sets up host memory to allow DMA transfer. + + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance. + @param[in] Slot The slot number of the SD card to send the command t= o. + @param[in] Packet A pointer to the SD command data structure. + + @retval EFI_SUCCESS Memory has been mapped for DMA transfer. + @retval Others Memory has not been mapped. +**/ +EFI_STATUS +SdMmcSetupMemoryForDmaTransfer ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN SD_MMC_HC_TRB *Trb + ) +{ + EFI_PCI_IO_PROTOCOL_OPERATION Flag; + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN MapLength; + EFI_STATUS Status; + + if (Trb->Read) { + Flag =3D EfiPciIoOperationBusMasterWrite; + } else { + Flag =3D EfiPciIoOperationBusMasterRead; + } + + PciIo =3D Private->PciIo; + if (Trb->Data !=3D NULL && Trb->DataLen !=3D 0) { + MapLength =3D Trb->DataLen; + Status =3D PciIo->Map ( + PciIo, + Flag, + Trb->Data, + &MapLength, + &Trb->DataPhy, + &Trb->DataMap + ); + if (EFI_ERROR (Status) || (Trb->DataLen !=3D MapLength)) { + return EFI_BAD_BUFFER_SIZE; + } + } + + if (Trb->Mode =3D=3D SdMmcAdma32bMode || + Trb->Mode =3D=3D SdMmcAdma64bV3Mode || + Trb->Mode =3D=3D SdMmcAdma64bV4Mode) { + Status =3D BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]); + if (EFI_ERROR (Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} + /** Create a new TRB for the SD/MMC cmd request. =20 @@ -1746,9 +1802,6 @@ SdMmcCreateTrb ( SD_MMC_HC_TRB *Trb; EFI_STATUS Status; EFI_TPL OldTpl; - EFI_PCI_IO_PROTOCOL_OPERATION Flag; - EFI_PCI_IO_PROTOCOL *PciIo; - UINTN MapLength; =20 Trb =3D AllocateZeroPool (sizeof (SD_MMC_HC_TRB)); if (Trb =3D=3D NULL) { @@ -1791,29 +1844,6 @@ SdMmcCreateTrb ( (Packet->SdMmcCmdBlk->CommandIndex =3D=3D SD_SEND_TUNING_BLOCK))) { Trb->Mode =3D SdMmcPioMode; } else { - if (Trb->Read) { - Flag =3D EfiPciIoOperationBusMasterWrite; - } else { - Flag =3D EfiPciIoOperationBusMasterRead; - } - - PciIo =3D Private->PciIo; - if (Trb->DataLen !=3D 0) { - MapLength =3D Trb->DataLen; - Status =3D PciIo->Map ( - PciIo, - Flag, - Trb->Data, - &MapLength, - &Trb->DataPhy, - &Trb->DataMap - ); - if (EFI_ERROR (Status) || (Trb->DataLen !=3D MapLength)) { - Status =3D EFI_BAD_BUFFER_SIZE; - goto Error; - } - } - if (Trb->DataLen =3D=3D 0) { Trb->Mode =3D SdMmcNoData; } else if (Private->Capability[Slot].Adma2 !=3D 0) { @@ -1831,12 +1861,16 @@ SdMmcCreateTrb ( if (Private->ControllerVersion[Slot] >=3D SD_MMC_HC_CTRL_VER_410) { Trb->AdmaLengthMode =3D SdMmcAdmaLen26b; } - Status =3D BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]= ); + Status =3D SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb); if (EFI_ERROR (Status)) { goto Error; } } else if (Private->Capability[Slot].Sdma !=3D 0) { Trb->Mode =3D SdMmcSdmaMode; + Status =3D SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb); + if (EFI_ERROR (Status)) { + goto Error; + } } else { Trb->Mode =3D SdMmcPioMode; } --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydz= ial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-31= 6 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata= i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wi= adomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiek= olwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by others is strictly prohibited. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55032): https://edk2.groups.io/g/devel/message/55032 Mute This Topic: https://groups.io/mt/71591184/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 00:57:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55033+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55033+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582824350; cv=none; d=zohomail.com; s=zohoarc; b=cm5jwFn9mMMCyaMokiu6akeWnbwGIq+eJAoxH5pr0n/f9RaO+zg5fNG9SpvazNTFg+xdNR8hcKVRvGu4a+ndF6Y3zGbvlVz+m3xAAUZNvYsxAW81NqMp4tqq/LMV4qg2NeVkwkuPOAUIUw1yYFIEWB7ygXlOP49cP9yYgOUmil8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582824350; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=ih2ClbciK9e0eV/LT4moRet7AGoJdyejudZR3ATT+Cw=; b=mJkv/r/LEGJjUcZ0EHrhFzzU1b4itANn9lNDxJB/XPo049rAp8UInuNGn7u38UhPoyLwQpQ1rGTUwqspp73OmyUmP71WABX88J/MK2I+ao7GiDG8eWo3KsqVfHzzUD4ZErUB/LK2zjKOvnFFQtRsh73GnoTIoheoOO+tjwgzcK4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55033+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582824350813348.8758716400225; Thu, 27 Feb 2020 09:25:50 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id crQZYY1788612xN000cN32W7; Thu, 27 Feb 2020 09:25:49 -0800 X-Received: from mga04.intel.com (mga04.intel.com []) by mx.groups.io with SMTP id smtpd.web12.7477.1582824332223573542 for ; Thu, 27 Feb 2020 09:25:45 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2020 09:25:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,492,1574150400"; d="scan'208";a="261560472" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by fmsmga004.fm.intel.com with ESMTP; 27 Feb 2020 09:25:44 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCHv3 5/5] MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode Date: Thu, 27 Feb 2020 18:25:26 +0100 Message-Id: <20200227172526.5876-6-mateusz.albecki@intel.com> In-Reply-To: <20200227172526.5876-1-mateusz.albecki@intel.com> References: <20200227172526.5876-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: KsoLINwxeEg5434lWtJc8SXBx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582824349; bh=4MU7DwwQuu53NhRetl/DfPZ7fV7XY9s1DMCp1nmG+y8=; h=Cc:Date:From:Reply-To:Subject:To; b=OB+6ueFXCcLyn61whC5iRY+9i5P+AwUKb7rYpm+TgEKcIFUwyib/uQFFtIH0bzSYbyB BLpqgF8QwoPVFceDCV1V00iVbqoOZvVXRgmRiLApfxUMRn2R2uEpSOQV8lL1ae9V5wgbe H+qYw6mWv5aO9qauBc47tzGS6iRTet9xAxI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Current driver does not support PIO transfer mode for commands other then tuning. This change adds the code to transfer PIO data. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu Tested-by: Hao A Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 3 + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 132 +++++++++++++++++= ---- 2 files changed, 114 insertions(+), 21 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h index 15b7d12596..fd89306fab 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h @@ -157,6 +157,9 @@ typedef struct { UINT64 Timeout; UINT32 Retries; =20 + BOOLEAN PioModeTransferCompleted; + UINT32 PioBlockIndex; + SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc; SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc; SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc; diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 422862577e..497ac08355 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -1713,6 +1713,8 @@ SdMmcPrintTrb ( DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete)); DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout)); DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries)); + DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", Trb->PioModeTransf= erCompleted)); + DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex)); DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc)); DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc)); DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc)); @@ -1817,6 +1819,8 @@ SdMmcCreateTrb ( Trb->CommandComplete =3D FALSE; Trb->Timeout =3D Packet->Timeout; Trb->Retries =3D SD_MMC_TRB_RETRIES; + Trb->PioModeTransferCompleted =3D FALSE; + Trb->PioBlockIndex =3D 0; Trb->Private =3D Private; =20 if ((Packet->InTransferLength !=3D 0) && (Packet->InDataBuffer !=3D NULL= )) { @@ -2479,6 +2483,104 @@ SdMmcCheckCommandComplete ( return EFI_NOT_READY; } =20 +/** + Transfers data from card using PIO method. + + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. + @param[in] IntStatus Snapshot of the normal interrupt status register. + + @retval EFI_SUCCESS PIO transfer completed successfully. + @retval EFI_NOT_READY PIO transfer completion still pending. + @retval Others PIO transfer failed to complete. +**/ +EFI_STATUS +SdMmcTransferDataWithPio ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN SD_MMC_HC_TRB *Trb, + IN UINT16 IntStatus + ) +{ + EFI_STATUS Status; + UINT16 Data16; + UINT32 BlockCount; + EFI_PCI_IO_PROTOCOL_WIDTH Width; + UINTN Count; + + BlockCount =3D (Trb->DataLen / Trb->BlockSize); + if (Trb->DataLen % Trb->BlockSize !=3D 0) { + BlockCount +=3D 1; + } + + if (Trb->PioBlockIndex >=3D BlockCount) { + return EFI_SUCCESS; + } + + switch (Trb->BlockSize % sizeof (UINT32)) { + case 0: + Width =3D EfiPciIoWidthFifoUint32; + Count =3D Trb->BlockSize / sizeof (UINT32); + break; + case 2: + Width =3D EfiPciIoWidthFifoUint16; + Count =3D Trb->BlockSize / sizeof (UINT16); + break; + case 1: + case 3: + default: + Width =3D EfiPciIoWidthFifoUint8; + Count =3D Trb->BlockSize; + break; + } + + if (Trb->Read) { + if ((IntStatus & BIT5) =3D=3D 0) { + return EFI_NOT_READY; + } + Data16 =3D BIT5; + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE= , sizeof (Data16), &Data16); + + Status =3D Private->PciIo->Mem.Read ( + Private->PciIo, + Width, + Trb->Slot, + SD_MMC_HC_BUF_DAT_PORT, + Count, + (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * Trb->PioBlock= Index)) + ); + if (EFI_ERROR (Status)) { + return Status; + } + Trb->PioBlockIndex++; + } else { + if ((IntStatus & BIT4) =3D=3D 0) { + return EFI_NOT_READY; + } + Data16 =3D BIT4; + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE= , sizeof (Data16), &Data16); + + Status =3D Private->PciIo->Mem.Write ( + Private->PciIo, + Width, + Trb->Slot, + SD_MMC_HC_BUF_DAT_PORT, + Count, + (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * Trb->PioBlock= Index)) + ); + if (EFI_ERROR (Status)) { + return Status; + } + Trb->PioBlockIndex++; + } + + if (Trb->PioBlockIndex >=3D BlockCount) { + Trb->PioModeTransferCompleted =3D TRUE; + return EFI_SUCCESS; + } else { + return EFI_NOT_READY; + } +} + /** Update the SDMA address on the SDMA buffer boundary interrupt. =20 @@ -2563,6 +2665,13 @@ SdMmcCheckDataTransfer ( return Status; } =20 + if (Trb->Mode =3D=3D SdMmcPioMode && !Trb->PioModeTransferCompleted) { + Status =3D SdMmcTransferDataWithPio (Private, Trb, IntStatus); + if (EFI_ERROR (Status)) { + return Status; + } + } + if ((Trb->Mode =3D=3D SdMmcSdmaMode) && ((IntStatus & BIT3) !=3D 0)) { Data16 =3D BIT3; Status =3D SdMmcHcRwMmio ( @@ -2605,7 +2714,6 @@ SdMmcCheckTrbResult ( EFI_STATUS Status; EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; UINT16 IntStatus; - UINT32 PioLength; =20 Packet =3D Trb->Packet; // @@ -2641,26 +2749,8 @@ SdMmcCheckTrbResult ( (Packet->SdMmcCmdBlk->CommandIndex =3D=3D EMMC_SEND_TUNING_BLOCK)) = || ((Private->Slot[Trb->Slot].CardType =3D=3D SdCardType) && (Packet->SdMmcCmdBlk->CommandIndex =3D=3D SD_SEND_TUNING_BLOCK))) { - // - // When performing tuning procedure (Execute Tuning is set to 1) throu= gh PIO mode, - // wait Buffer Read Ready bit of Normal Interrupt Status Register to b= e 1. - // Refer to SD Host Controller Simplified Specification 3.0 figure 2-2= 9 for details. - // - if ((IntStatus & BIT5) =3D=3D BIT5) { - // - // Clear Buffer Read Ready interrupt at first. - // - IntStatus =3D BIT5; - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FAL= SE, sizeof (IntStatus), &IntStatus); - // - // Read data out from Buffer Port register - // - for (PioLength =3D 0; PioLength < Trb->DataLen; PioLength +=3D 4) { - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, = TRUE, 4, (UINT8*)Trb->Data + PioLength); - } - Status =3D EFI_SUCCESS; - goto Done; - } + Status =3D SdMmcTransferDataWithPio (Private, Trb, IntStatus); + goto Done; } =20 if (!Trb->CommandComplete) { --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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