From nobody Fri May 3 12:28:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54847+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54847+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582711446; cv=none; d=zohomail.com; s=zohoarc; b=i1SVrsOzDoQpy1fXr/cwtQPph9xY/vT/5vSYzpN0rX3MzUye6Oxdy5/aiaQHImRQLO+LXPCZysp2NTCvvZKHHl3n9peRzu7QzIlFciU71QNCyQBL6BE6vjA11PhWvv0BYoaeUTqRbJvq+73tRLob2JwVi8jl+h5Lcz5r+rFcrx0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582711446; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=iqRtl5766bppSV1u/qpWqZ9OMHCJIuwpPbpBdqE79tY=; b=NZqjAQcHdOz4jPFkj0dFh0saf8R6fQGPQleTtf+muL41Ka1Siu1ieMhFk+wCtuaRpdcvfGbs7Hb5/X9Rtz09UuJNa2pchysYWOP+Wc/85Pwq8RG2OhfrRVv4jKeASAzqEHkz4rCkajPC5y4kXZE1P9QVYuirHmT5aV1ufvkNHd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54847+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582711446741773.1440593245459; Wed, 26 Feb 2020 02:04:06 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id nuaeYY1788612xGH1cvc0yGj; Wed, 26 Feb 2020 02:04:04 -0800 X-Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.groups.io with SMTP id smtpd.web10.6068.1582711443863747283 for ; Wed, 26 Feb 2020 02:04:04 -0800 X-Received: by mail-wm1-f66.google.com with SMTP id i10so3066150wmd.1 for ; Wed, 26 Feb 2020 02:04:03 -0800 (PST) X-Gm-Message-State: G9wMje0dlLndGhN894a3fnhMx1787277AA= X-Google-Smtp-Source: APXvYqybYWNcdr7ETfkWi7U+8ZiskilAQGfCe8BmDWUeNeAcAeVkJTicUEucZPL8gX19C/Mt7kkSZg== X-Received: by 2002:a1c:3b07:: with SMTP id i7mr4436594wma.57.1582711442149; Wed, 26 Feb 2020 02:04:02 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id b10sm2559159wrw.61.2020.02.26.02.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 02:04:01 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, lersek@redhat.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 1/6] ArmPkg/ArmMmuLib ARM: remove dummy constructor Date: Wed, 26 Feb 2020 11:03:48 +0100 Message-Id: <20200226100353.31962-2-ard.biesheuvel@linaro.org> In-Reply-To: <20200226100353.31962-1-ard.biesheuvel@linaro.org> References: <20200226100353.31962-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582711444; bh=6nvrR0zCkUa8KXBjXA8lkgOKWxpPxgCtlsVZ9nNrvPY=; h=Cc:Date:From:Reply-To:Subject:To; b=UF3oIu5XJeL5+1IoFxYtbMesR6g4QFkY4M7Hc7XgUQ2082m3/RG71Y24EG9fR5c+6a9 GGBdreEZXB6ZwuEGHJKIpuKazoTBv0pCcouaCeY/enfY8nXwg9VAlvhAIk0CjLJIVVqzT I/O6QzyabYEu487vVrN8yMmjHAS29c54OGU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the CONSTRUCTOR define in the .INF AARCH64 only, so we can drop the empty stub that exists for ARM. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 9 --------- ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 ++ 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index 74ac31de98cc..a6601258bee0 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -830,12 +830,3 @@ ArmClearMemoryRegionReadOnly ( { return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); } - -RETURN_STATUS -EFIAPI -ArmMmuBaseLibConstructor ( - VOID - ) -{ - return RETURN_SUCCESS; -} diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar= mMmuLib/ArmMmuBaseLib.inf index 5028a955afac..3dfe68ba48a6 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -14,6 +14,8 @@ [Defines] MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D ArmMmuLib + +[Defines.AARCH64] CONSTRUCTOR =3D ArmMmuBaseLibConstructor =20 [Sources.AARCH64] --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54847): https://edk2.groups.io/g/devel/message/54847 Mute This Topic: https://groups.io/mt/71562845/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:28:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54848+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54848+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582711448; cv=none; d=zohomail.com; s=zohoarc; b=DbiBfx5qy919FW5eKnR69ZvxZ4xUnuD9+UJXUCpdmj3ObbUWYGfWy6u66fggMrWh+MQJ9mXqKNNgUStKzRUrogfpNtMV97fx68MgCEnOTT3nU+VOUIo2R0BQFMVtekCv8S2tyYobBZiITSw2VXk2H+b8EQS8I+YP44GvjWIKHys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582711448; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=2OWZ+iY7CDHFWqMBvnCyV/FvMs4KadSJ8ucx1OHixP0=; b=VISF2Wu0EjfNUpsEsimBXNWFl5PV9b3u2u54gn8XRYyC3U3oJerb7GUgxVy58ssP6YJkp1irlghGISDdaV5NyiHVAG/lkl7ftHn7dscowMlJKqIBLmzpx1fn0FOI+Pn2/mWfnWyTvz+BujA4aQLOjmfckh5tuG/MtSnYx0R8/tM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54848+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582711448421490.56408945737894; Wed, 26 Feb 2020 02:04:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id mN5ZYY1788612xUnjpobe6o3; Wed, 26 Feb 2020 02:04:07 -0800 X-Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.groups.io with SMTP id smtpd.web11.5826.1582711446599248182 for ; Wed, 26 Feb 2020 02:04:07 -0800 X-Received: by mail-wr1-f43.google.com with SMTP id m16so2147006wrx.11 for ; Wed, 26 Feb 2020 02:04:06 -0800 (PST) X-Gm-Message-State: 2PzCrtLfKoDO1CNr1UnZpOC3x1787277AA= X-Google-Smtp-Source: APXvYqyz3qvb3k76mHuidfAC4Tf1e+4je9CLGmtbHgF9W5dXnXeVVd6APFHGdEO/ngVH0qZ8lBXUdw== X-Received: by 2002:a5d:69c6:: with SMTP id s6mr4433930wrw.32.1582711443886; Wed, 26 Feb 2020 02:04:03 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id b10sm2559159wrw.61.2020.02.26.02.04.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 02:04:02 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, lersek@redhat.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 2/6] ArmPkg/ArmMmuLib ARM: split ArmMmuLibCore.c into core and update code Date: Wed, 26 Feb 2020 11:03:49 +0100 Message-Id: <20200226100353.31962-3-ard.biesheuvel@linaro.org> In-Reply-To: <20200226100353.31962-1-ard.biesheuvel@linaro.org> References: <20200226100353.31962-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582711447; bh=VbRH4UEbmgbPN9vzrMOQMSgl5EkufIq5X8JjwPXcIUo=; h=Cc:Date:From:Reply-To:Subject:To; b=dCWGcng6vV1YVipmp7aBTyBQQJklH+GLSgFts4O5ljUWkU8aWcxeRBEcky45a7NQSa/ TQ+NCoiFx8ptdx+CHjFqxISDl7CojRfPndeOGc3VvkCI9BNGwz5h2T+YsxPCFlvVemzKb hMQX0TjgZH0xVZevSIN8orB0u3rssEEMLPY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Unlike the AArch64 implementation of ArmMmuLib, which combines the initial page table population code with the code that runs at later stages to manage permission attributes in the page tables, ARM uses two completely separate sets of routines for this. Since ArmMmuLib is a static library, we can prevent duplication of this code between different users, which usually only need one or the other. (Note that LTO should also achieve the same.) This also makes it easier to reason about modifying the cache maintenance handling, and replace the set/way ops with by-VA ops, since the code that performs the set/way ops only executes when the MMU is still off. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c | 32 ++ ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 434 ------------------- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 435 ++++++++++++++++++++ ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 + 4 files changed, 469 insertions(+), 434 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Libra= ry/ArmMmuLib/Arm/ArmMmuLibConvert.c new file mode 100644 index 000000000000..e3b02a9fba57 --- /dev/null +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c @@ -0,0 +1,32 @@ +/** @file +* File managing the MMU for ARMv7 architecture +* +* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include + +#include + +UINT32 +ConvertSectionAttributesToPageAttributes ( + IN UINT32 SectionAttributes, + IN BOOLEAN IsLargePage + ) +{ + UINT32 PageAttributes; + + PageAttributes =3D 0; + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionA= ttributes, IsLargePage); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes,= IsLargePage); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes); + + return PageAttributes; +} diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index a6601258bee0..aca7a37facac 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -31,15 +31,6 @@ #define ID_MMFR0_SHR_IMP_HW_COHERENT 1 #define ID_MMFR0_SHR_IGNORED 0xf =20 -#define __EFI_MEMORY_RWX 0 // no restrictions - -#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \ - EFI_MEMORY_WC | \ - EFI_MEMORY_WT | \ - EFI_MEMORY_WB | \ - EFI_MEMORY_UCE | \ - EFI_MEMORY_WP) - UINTN EFIAPI ArmReadIdMmfr0 ( @@ -52,24 +43,6 @@ ArmHasMpExtensions ( VOID ); =20 -UINT32 -ConvertSectionAttributesToPageAttributes ( - IN UINT32 SectionAttributes, - IN BOOLEAN IsLargePage - ) -{ - UINT32 PageAttributes; - - PageAttributes =3D 0; - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionA= ttributes, IsLargePage); - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes); - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes,= IsLargePage); - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes); - PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes); - - return PageAttributes; -} - STATIC BOOLEAN PreferNonshareableMemory ( @@ -423,410 +396,3 @@ ArmConfigureMmu ( ArmEnableMmu(); return RETURN_SUCCESS; } - -STATIC -EFI_STATUS -ConvertSectionToPages ( - IN EFI_PHYSICAL_ADDRESS BaseAddress - ) -{ - UINT32 FirstLevelIdx; - UINT32 SectionDescriptor; - UINT32 PageTableDescriptor; - UINT32 PageDescriptor; - UINT32 Index; - - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - volatile ARM_PAGE_TABLE_ENTRY *PageTable; - - DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)Base= Address)); - - // Obtain page table base - FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); - - // Calculate index into first level translation table for start of modif= ication - FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_= DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // Get section attributes and convert to page attributes - SectionDescriptor =3D FirstLevelTable[FirstLevelIdx]; - PageDescriptor =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttribut= esToPageAttributes (SectionDescriptor, FALSE); - - // Allocate a page table for the 4KB entries (we use up a full page even= though we only need 1KB) - PageTable =3D (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1); - if (PageTable =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - // Write the page table entries out - for (Index =3D 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { - PageTable[Index] =3D TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (In= dex << 12)) | PageDescriptor; - } - - // Formulate page table entry, Domain=3D0, NS=3D0 - PageTableDescriptor =3D (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGE= TABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; - - // Write the page table entry out, replacing section entry - FirstLevelTable[FirstLevelIdx] =3D PageTableDescriptor; - - return EFI_SUCCESS; -} - -STATIC -EFI_STATUS -UpdatePageEntries ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *FlushTlbs OPTIONAL - ) -{ - EFI_STATUS Status; - UINT32 EntryValue; - UINT32 EntryMask; - UINT32 FirstLevelIdx; - UINT32 Offset; - UINT32 NumPageEntries; - UINT32 Descriptor; - UINT32 p; - UINT32 PageTableIndex; - UINT32 PageTableEntry; - UINT32 CurrentPageTableEntry; - VOID *Mva; - - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - volatile ARM_PAGE_TABLE_ENTRY *PageTable; - - Status =3D EFI_SUCCESS; - - // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) - // EntryValue: values at bit positions specified by EntryMask - EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK; - if (Attributes & EFI_MEMORY_XP) { - EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN; - } else { - EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE; - } - - // Although the PI spec is unclear on this, the GCD guarantees that only - // one Attribute bit is set at a time, so the order of the conditionals = below - // is irrelevant. If no memory attribute is specified, we preserve whate= ver - // memory type is set in the page tables, and update the permission attr= ibutes - // only. - if (Attributes & EFI_MEMORY_UC) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // map to strongly ordered - EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // T= EX[2:0] =3D 0, C=3D0, B=3D0 - } else if (Attributes & EFI_MEMORY_WC) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // map to normal non-cachable - EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX = [2:0]=3D 001 =3D 0x2, B=3D0, C=3D0 - } else if (Attributes & EFI_MEMORY_WT) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // write through with no-allocate - EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC= ; // TEX [2:0] =3D 0, C=3D1, B=3D0 - } else if (Attributes & EFI_MEMORY_WB) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // write back (with allocate) - EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // T= EX [2:0] =3D 001, C=3D1, B=3D1 - } else if (Attributes & CACHE_ATTRIBUTE_MASK) { - // catch unsupported memory type attributes - ASSERT (FALSE); - return EFI_UNSUPPORTED; - } - - if (Attributes & EFI_MEMORY_RO) { - EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RO_RO; - } else { - EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RW_RW; - } - - // Obtain page table base - FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); - - // Calculate number of 4KB page table entries to change - NumPageEntries =3D Length / TT_DESCRIPTOR_PAGE_SIZE; - - // Iterate for the number of 4KB pages to change - Offset =3D 0; - for(p =3D 0; p < NumPageEntries; p++) { - // Calculate index into first level translation table for page table v= alue - - FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Off= set) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // Read the descriptor from the first level page table - Descriptor =3D FirstLevelTable[FirstLevelIdx]; - - // Does this descriptor need to be converted from section entry to 4K = pages? - if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) { - Status =3D ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT); - if (EFI_ERROR(Status)) { - // Exit for loop - break; - } - - // Re-read descriptor - Descriptor =3D FirstLevelTable[FirstLevelIdx]; - if (FlushTlbs !=3D NULL) { - *FlushTlbs =3D TRUE; - } - } - - // Obtain page table base address - PageTable =3D (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(= Descriptor); - - // Calculate index into the page table - PageTableIndex =3D ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_= MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; - ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); - - // Get the entry - CurrentPageTableEntry =3D PageTable[PageTableIndex]; - - // Mask off appropriate fields - PageTableEntry =3D CurrentPageTableEntry & ~EntryMask; - - // Mask in new attributes and/or permissions - PageTableEntry |=3D EntryValue; - - if (CurrentPageTableEntry !=3D PageTableEntry) { - Mva =3D (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT)); - - // Only need to update if we are changing the entry - PageTable[PageTableIndex] =3D PageTableEntry; - ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], = Mva); - } - - Status =3D EFI_SUCCESS; - Offset +=3D TT_DESCRIPTOR_PAGE_SIZE; - - } // End first level translation table loop - - return Status; -} - -STATIC -EFI_STATUS -UpdateSectionEntries ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes - ) -{ - EFI_STATUS Status =3D EFI_SUCCESS; - UINT32 EntryMask; - UINT32 EntryValue; - UINT32 FirstLevelIdx; - UINT32 NumSections; - UINT32 i; - UINT32 CurrentDescriptor; - UINT32 Descriptor; - VOID *Mva; - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - - // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) - // EntryValue: values at bit positions specified by EntryMask - - // Make sure we handle a section range that is unmapped - EntryMask =3D TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN= _MASK | - TT_DESCRIPTOR_SECTION_AP_MASK; - EntryValue =3D TT_DESCRIPTOR_SECTION_TYPE_SECTION; - - // Although the PI spec is unclear on this, the GCD guarantees that only - // one Attribute bit is set at a time, so the order of the conditionals = below - // is irrelevant. If no memory attribute is specified, we preserve whate= ver - // memory type is set in the page tables, and update the permission attr= ibutes - // only. - if (Attributes & EFI_MEMORY_UC) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // map to strongly ordered - EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; /= / TEX[2:0] =3D 0, C=3D0, B=3D0 - } else if (Attributes & EFI_MEMORY_WC) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // map to normal non-cachable - EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // T= EX [2:0]=3D 001 =3D 0x2, B=3D0, C=3D0 - } else if (Attributes & EFI_MEMORY_WT) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // write through with no-allocate - EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_AL= LOC; // TEX [2:0] =3D 0, C=3D1, B=3D0 - } else if (Attributes & EFI_MEMORY_WB) { - // modify cacheability attributes - EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // write back (with allocate) - EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; /= / TEX [2:0] =3D 001, C=3D1, B=3D1 - } else if (Attributes & CACHE_ATTRIBUTE_MASK) { - // catch unsupported memory type attributes - ASSERT (FALSE); - return EFI_UNSUPPORTED; - } - - if (Attributes & EFI_MEMORY_RO) { - EntryValue |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; - } else { - EntryValue |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; - } - - if (Attributes & EFI_MEMORY_XP) { - EntryValue |=3D TT_DESCRIPTOR_SECTION_XN_MASK; - } - - // obtain page table base - FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); - - // calculate index into first level translation table for start of modif= ication - FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_= DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // calculate number of 1MB first level entries this applies to - NumSections =3D Length / TT_DESCRIPTOR_SECTION_SIZE; - - // iterate through each descriptor - for(i=3D0; i (UINT64)MAX_ADDRESS) { - return EFI_UNSUPPORTED; - } - - Length =3D MIN (Length, (UINT64)MAX_ADDRESS - BaseAddress + 1); - if (Length =3D=3D 0) { - return EFI_SUCCESS; - } - - FlushTlbs =3D FALSE; - while (Length > 0) { - if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE =3D=3D 0) && - Length >=3D TT_DESCRIPTOR_SECTION_SIZE) { - - ChunkLength =3D Length - Length % TT_DESCRIPTOR_SECTION_SIZE; - - DEBUG ((DEBUG_PAGE, - "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n", - BaseAddress, ChunkLength, Attributes)); - - Status =3D UpdateSectionEntries (BaseAddress, ChunkLength, Attribute= s); - - FlushTlbs =3D TRUE; - } else { - - // - // Process page by page until the next section boundary, but only if - // we have more than a section's worth of area to deal with after th= at. - // - ChunkLength =3D TT_DESCRIPTOR_SECTION_SIZE - - (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE); - if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) { - ChunkLength =3D Length; - } - - DEBUG ((DEBUG_PAGE, - "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n", - BaseAddress, ChunkLength, Attributes)); - - Status =3D UpdatePageEntries (BaseAddress, ChunkLength, Attributes, - &FlushTlbs); - } - - if (EFI_ERROR (Status)) { - break; - } - - BaseAddress +=3D ChunkLength; - Length -=3D ChunkLength; - } - - if (FlushTlbs) { - ArmInvalidateTlb (); - } - return Status; -} - -EFI_STATUS -ArmSetMemoryRegionNoExec ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP); -} - -EFI_STATUS -ArmClearMemoryRegionNoExec ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); -} - -EFI_STATUS -ArmSetMemoryRegionReadOnly ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO); -} - -EFI_STATUS -ArmClearMemoryRegionReadOnly ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); -} diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Librar= y/ArmMmuLib/Arm/ArmMmuLibUpdate.c new file mode 100644 index 000000000000..3dafe1d964cd --- /dev/null +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -0,0 +1,435 @@ +/** @file +* File managing the MMU for ARMv7 architecture +* +* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#define __EFI_MEMORY_RWX 0 // no restrictions + +#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \ + EFI_MEMORY_WC | \ + EFI_MEMORY_WT | \ + EFI_MEMORY_WB | \ + EFI_MEMORY_UCE | \ + EFI_MEMORY_WP) + +STATIC +EFI_STATUS +ConvertSectionToPages ( + IN EFI_PHYSICAL_ADDRESS BaseAddress + ) +{ + UINT32 FirstLevelIdx; + UINT32 SectionDescriptor; + UINT32 PageTableDescriptor; + UINT32 PageDescriptor; + UINT32 Index; + + volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; + volatile ARM_PAGE_TABLE_ENTRY *PageTable; + + DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)Base= Address)); + + // Obtain page table base + FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); + + // Calculate index into first level translation table for start of modif= ication + FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_= DESCRIPTOR_SECTION_BASE_SHIFT; + ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); + + // Get section attributes and convert to page attributes + SectionDescriptor =3D FirstLevelTable[FirstLevelIdx]; + PageDescriptor =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttribut= esToPageAttributes (SectionDescriptor, FALSE); + + // Allocate a page table for the 4KB entries (we use up a full page even= though we only need 1KB) + PageTable =3D (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1); + if (PageTable =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // Write the page table entries out + for (Index =3D 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { + PageTable[Index] =3D TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (In= dex << 12)) | PageDescriptor; + } + + // Formulate page table entry, Domain=3D0, NS=3D0 + PageTableDescriptor =3D (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGE= TABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; + + // Write the page table entry out, replacing section entry + FirstLevelTable[FirstLevelIdx] =3D PageTableDescriptor; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +UpdatePageEntries ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + OUT BOOLEAN *FlushTlbs OPTIONAL + ) +{ + EFI_STATUS Status; + UINT32 EntryValue; + UINT32 EntryMask; + UINT32 FirstLevelIdx; + UINT32 Offset; + UINT32 NumPageEntries; + UINT32 Descriptor; + UINT32 p; + UINT32 PageTableIndex; + UINT32 PageTableEntry; + UINT32 CurrentPageTableEntry; + VOID *Mva; + + volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; + volatile ARM_PAGE_TABLE_ENTRY *PageTable; + + Status =3D EFI_SUCCESS; + + // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) + // EntryValue: values at bit positions specified by EntryMask + EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK; + if (Attributes & EFI_MEMORY_XP) { + EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN; + } else { + EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE; + } + + // Although the PI spec is unclear on this, the GCD guarantees that only + // one Attribute bit is set at a time, so the order of the conditionals = below + // is irrelevant. If no memory attribute is specified, we preserve whate= ver + // memory type is set in the page tables, and update the permission attr= ibutes + // only. + if (Attributes & EFI_MEMORY_UC) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; + // map to strongly ordered + EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // T= EX[2:0] =3D 0, C=3D0, B=3D0 + } else if (Attributes & EFI_MEMORY_WC) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; + // map to normal non-cachable + EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX = [2:0]=3D 001 =3D 0x2, B=3D0, C=3D0 + } else if (Attributes & EFI_MEMORY_WT) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; + // write through with no-allocate + EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC= ; // TEX [2:0] =3D 0, C=3D1, B=3D0 + } else if (Attributes & EFI_MEMORY_WB) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; + // write back (with allocate) + EntryValue |=3D TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // T= EX [2:0] =3D 001, C=3D1, B=3D1 + } else if (Attributes & CACHE_ATTRIBUTE_MASK) { + // catch unsupported memory type attributes + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + if (Attributes & EFI_MEMORY_RO) { + EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RO_RO; + } else { + EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RW_RW; + } + + // Obtain page table base + FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); + + // Calculate number of 4KB page table entries to change + NumPageEntries =3D Length / TT_DESCRIPTOR_PAGE_SIZE; + + // Iterate for the number of 4KB pages to change + Offset =3D 0; + for(p =3D 0; p < NumPageEntries; p++) { + // Calculate index into first level translation table for page table v= alue + + FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Off= set) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; + ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); + + // Read the descriptor from the first level page table + Descriptor =3D FirstLevelTable[FirstLevelIdx]; + + // Does this descriptor need to be converted from section entry to 4K = pages? + if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) { + Status =3D ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT); + if (EFI_ERROR(Status)) { + // Exit for loop + break; + } + + // Re-read descriptor + Descriptor =3D FirstLevelTable[FirstLevelIdx]; + if (FlushTlbs !=3D NULL) { + *FlushTlbs =3D TRUE; + } + } + + // Obtain page table base address + PageTable =3D (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(= Descriptor); + + // Calculate index into the page table + PageTableIndex =3D ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_= MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; + ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); + + // Get the entry + CurrentPageTableEntry =3D PageTable[PageTableIndex]; + + // Mask off appropriate fields + PageTableEntry =3D CurrentPageTableEntry & ~EntryMask; + + // Mask in new attributes and/or permissions + PageTableEntry |=3D EntryValue; + + if (CurrentPageTableEntry !=3D PageTableEntry) { + Mva =3D (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT)); + + // Only need to update if we are changing the entry + PageTable[PageTableIndex] =3D PageTableEntry; + ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], = Mva); + } + + Status =3D EFI_SUCCESS; + Offset +=3D TT_DESCRIPTOR_PAGE_SIZE; + + } // End first level translation table loop + + return Status; +} + +STATIC +EFI_STATUS +UpdateSectionEntries ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UINT32 EntryMask; + UINT32 EntryValue; + UINT32 FirstLevelIdx; + UINT32 NumSections; + UINT32 i; + UINT32 CurrentDescriptor; + UINT32 Descriptor; + VOID *Mva; + volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; + + // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) + // EntryValue: values at bit positions specified by EntryMask + + // Make sure we handle a section range that is unmapped + EntryMask =3D TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN= _MASK | + TT_DESCRIPTOR_SECTION_AP_MASK; + EntryValue =3D TT_DESCRIPTOR_SECTION_TYPE_SECTION; + + // Although the PI spec is unclear on this, the GCD guarantees that only + // one Attribute bit is set at a time, so the order of the conditionals = below + // is irrelevant. If no memory attribute is specified, we preserve whate= ver + // memory type is set in the page tables, and update the permission attr= ibutes + // only. + if (Attributes & EFI_MEMORY_UC) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; + // map to strongly ordered + EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; /= / TEX[2:0] =3D 0, C=3D0, B=3D0 + } else if (Attributes & EFI_MEMORY_WC) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; + // map to normal non-cachable + EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // T= EX [2:0]=3D 001 =3D 0x2, B=3D0, C=3D0 + } else if (Attributes & EFI_MEMORY_WT) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; + // write through with no-allocate + EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_AL= LOC; // TEX [2:0] =3D 0, C=3D1, B=3D0 + } else if (Attributes & EFI_MEMORY_WB) { + // modify cacheability attributes + EntryMask |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; + // write back (with allocate) + EntryValue |=3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; /= / TEX [2:0] =3D 001, C=3D1, B=3D1 + } else if (Attributes & CACHE_ATTRIBUTE_MASK) { + // catch unsupported memory type attributes + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + if (Attributes & EFI_MEMORY_RO) { + EntryValue |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; + } else { + EntryValue |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; + } + + if (Attributes & EFI_MEMORY_XP) { + EntryValue |=3D TT_DESCRIPTOR_SECTION_XN_MASK; + } + + // obtain page table base + FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); + + // calculate index into first level translation table for start of modif= ication + FirstLevelIdx =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_= DESCRIPTOR_SECTION_BASE_SHIFT; + ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); + + // calculate number of 1MB first level entries this applies to + NumSections =3D Length / TT_DESCRIPTOR_SECTION_SIZE; + + // iterate through each descriptor + for(i=3D0; i (UINT64)MAX_ADDRESS) { + return EFI_UNSUPPORTED; + } + + Length =3D MIN (Length, (UINT64)MAX_ADDRESS - BaseAddress + 1); + if (Length =3D=3D 0) { + return EFI_SUCCESS; + } + + FlushTlbs =3D FALSE; + while (Length > 0) { + if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE =3D=3D 0) && + Length >=3D TT_DESCRIPTOR_SECTION_SIZE) { + + ChunkLength =3D Length - Length % TT_DESCRIPTOR_SECTION_SIZE; + + DEBUG ((DEBUG_PAGE, + "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n", + BaseAddress, ChunkLength, Attributes)); + + Status =3D UpdateSectionEntries (BaseAddress, ChunkLength, Attribute= s); + + FlushTlbs =3D TRUE; + } else { + + // + // Process page by page until the next section boundary, but only if + // we have more than a section's worth of area to deal with after th= at. + // + ChunkLength =3D TT_DESCRIPTOR_SECTION_SIZE - + (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE); + if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) { + ChunkLength =3D Length; + } + + DEBUG ((DEBUG_PAGE, + "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n", + BaseAddress, ChunkLength, Attributes)); + + Status =3D UpdatePageEntries (BaseAddress, ChunkLength, Attributes, + &FlushTlbs); + } + + if (EFI_ERROR (Status)) { + break; + } + + BaseAddress +=3D ChunkLength; + Length -=3D ChunkLength; + } + + if (FlushTlbs) { + ArmInvalidateTlb (); + } + return Status; +} + +EFI_STATUS +ArmSetMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP); +} + +EFI_STATUS +ArmClearMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); +} + +EFI_STATUS +ArmSetMemoryRegionReadOnly ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO); +} + +EFI_STATUS +ArmClearMemoryRegionReadOnly ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ) +{ + return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX); +} diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar= mMmuLib/ArmMmuBaseLib.inf index 3dfe68ba48a6..2a7e7147958c 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -23,7 +23,9 @@ [Sources.AARCH64] AArch64/ArmMmuLibReplaceEntry.S =20 [Sources.ARM] + Arm/ArmMmuLibConvert.c Arm/ArmMmuLibCore.c + Arm/ArmMmuLibUpdate.c Arm/ArmMmuLibV7Support.S |GCC Arm/ArmMmuLibV7Support.asm |RVCT =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54848): https://edk2.groups.io/g/devel/message/54848 Mute This Topic: https://groups.io/mt/71562846/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:28:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54849+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54849+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582711448; cv=none; d=zohomail.com; s=zohoarc; b=JuaVip9PRC0wDL+7bfpO8eKjpYmuZ6Ii/9+GNl/5D34bKsgbEUX2abYhtSitQs+hvlggFUT01IySh+S9zGRImgf9SfvoJPc/HB9E7faBVmcgF9zeCGokXOUpCpZfh2EI9ymmOyoeDM0IQvgEcDp59MEoO2+449WwkWrJn7OSJK0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582711448; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=subjxenveaBrKqVTFWSKqsbnhF5e9seppbKagca4M1E=; b=AcEu7T1l2gHXhQK04aRWs1IzlOonn3o3mxstm6iaSPNTljzBqmH0mN7uZKzqKI4lH2W9IKkb6cvKCdWuIWwGl1BxcDJDO1TDGV4v1i1cwp7YpyG6rT9N/P61pYWPuMRrvrVNIy+LsD4Gs+Z2pMjIT7gNoPgEo0wiSobhIz0lXSM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54849+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582711448801922.272819249307; Wed, 26 Feb 2020 02:04:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id bZqrYY1788612xT3O6OFbhBl; Wed, 26 Feb 2020 02:04:07 -0800 X-Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by mx.groups.io with SMTP id smtpd.web11.5827.1582711446972002162 for ; Wed, 26 Feb 2020 02:04:07 -0800 X-Received: by mail-wr1-f67.google.com with SMTP id z15so2215285wrl.1 for ; Wed, 26 Feb 2020 02:04:06 -0800 (PST) X-Gm-Message-State: WKdwok0CSpJdkeQBfyvr2drVx1787277AA= X-Google-Smtp-Source: APXvYqwLTCGG1uM4PWXI+S69KaqdPTCiMsjA5+EQSMe4914PWY6Jfb/63RJMpja58eMHFxP7CWPKCg== X-Received: by 2002:adf:e481:: with SMTP id i1mr4957181wrm.158.1582711445248; Wed, 26 Feb 2020 02:04:05 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id b10sm2559159wrw.61.2020.02.26.02.04.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 02:04:04 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, lersek@redhat.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 3/6] ArmPkg/ArmMmuLib ARM: cache-invalidate initial page table entries Date: Wed, 26 Feb 2020 11:03:50 +0100 Message-Id: <20200226100353.31962-4-ard.biesheuvel@linaro.org> In-Reply-To: <20200226100353.31962-1-ard.biesheuvel@linaro.org> References: <20200226100353.31962-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582711447; bh=q0MT9RSv7cr7I0+JsOxzj3xJhx4Dbvz6wlLDywfYPzY=; h=Cc:Date:From:Reply-To:Subject:To; b=UmeBgxJksdAbz8W+ADig2fTsZjJr2KPnIE5mFXwTZVV4f3hGJXpXXTBS7DmYPpCBGmR 70rqjnGRzL3DaZzDfAGFl01QF8fhKhARX2wh8cytZMdooxFncY9RY//tBS9Ji5XfNOh2Z uzVJ6Z5JbKqj8ZDx4oaSPVJr0VSB8/dRD4c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the ARM version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if set/way operations were the appropriate method to achieve this, doing an invalidate-all first and then populating the page table entries creates a window where page table entries could be loaded speculatively into the caches before we modify them, and shadow the new values that we write there. So let's get rid of the blanket clean/invalidate operations, and instead, update ArmUpdateTranslationTableEntry () to invalidate each page table entry *after* it is written if the MMU is still disabled at this point. On ARMv7, cache maintenance may be required also when the MMU is enabled, in case the page table walker is not cache coherent. However, the code being updated here is guaranteed to run only when the MMU is still off, and so we can disregard the case when the MMU and caches are on. Since the MMU and D-cache are already off when we reach this point, we can drop the MMU and D-cache disables as well. Maintenance of the I-cache is unnecessary, since we are not modifying any code, and the installed mapping is guaranteed to be 1:1. This means we can also leave it enabled while the page table population code is running. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 25 +++++++++----------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index aca7a37facac..c5906b4310cc 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -183,6 +183,8 @@ PopulateLevel2PageTable ( PhysicalBase +=3D TT_DESCRIPTOR_PAGE_SIZE; } =20 + InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset, + RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)); } =20 STATIC @@ -257,7 +259,11 @@ FillTranslationTable ( RemainLength >=3D TT_DESCRIPTOR_SECTION_SIZE) { // Case: Physical address aligned on the Section Size (1MB) && the l= ength // is greater than the Section Size - *SectionEntry++ =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase)= | Attributes; + *SectionEntry =3D TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) |= Attributes; + + ArmDataSynchronizationBarrier (); + ArmInvalidateDataCacheEntryByMVA ((UINTN)SectionEntry++); + PhysicalBase +=3D TT_DESCRIPTOR_SECTION_SIZE; RemainLength -=3D TT_DESCRIPTOR_SECTION_SIZE; } else { @@ -267,9 +273,12 @@ FillTranslationTable ( // Case: Physical address aligned on the Section Size (1MB) && the l= ength // does not fill a section // Case: Physical address NOT aligned on the Section Size (1MB) - PopulateLevel2PageTable (SectionEntry++, PhysicalBase, PageMapLength, + PopulateLevel2PageTable (SectionEntry, PhysicalBase, PageMapLength, MemoryRegion->Attributes); =20 + ArmDataSynchronizationBarrier (); + ArmInvalidateDataCacheEntryByMVA ((UINTN)SectionEntry++); + // If it is the last entry if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) { break; @@ -349,18 +358,6 @@ ArmConfigureMmu ( } } =20 - ArmCleanInvalidateDataCache (); - ArmInvalidateInstructionCache (); - - ArmDisableDataCache (); - ArmDisableInstructionCache(); - // TLBs are also invalidated when calling ArmDisableMmu() - ArmDisableMmu (); - - // Make sure nothing sneaked into the cache - ArmCleanInvalidateDataCache (); - ArmInvalidateInstructionCache (); - ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TAB= LE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F))); =20 // --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54849): https://edk2.groups.io/g/devel/message/54849 Mute This Topic: https://groups.io/mt/71562847/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:28:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54850+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54850+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582711450; cv=none; d=zohomail.com; s=zohoarc; b=MIZXOHvgq/Evr+ops2x3VaYaV40fNUwg5UZvug9LxEbjGHFzFt3cNpp0G+aao4eRmPwURjM5eQABD+DJ1J+fQ2+vJvBPKU90xtDVoNlKk4wQZ7ei/K4FIM9h6Ou/LCrC2aUrpCJuqktzx54sNyDL74qBCfSzQWQh4crrMubErI0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582711450; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=C5GLJaBi6QtCi6gERnjYCTaF+7RBp3s8VkEb9qmfew4=; b=dziXkNNCMHXos8vSTjw3sH0qa8FtgdlUdb+6SsyHdLKP4e7mCLFGuk4OtDEoGaWyLlAebmDol/II7n8xGm8mvTP8AELxttC3xHybFE4J2u0tbrrU3SOX1wfJkhgs3/i2L87bpHvpVgexe4Wn+hVNcgsP7ZlbOUWs+wecPC0z9rs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54850+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582711450147799.6277816185029; Wed, 26 Feb 2020 02:04:10 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Ec4oYY1788612xWbFKEtrPs9; Wed, 26 Feb 2020 02:04:09 -0800 X-Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by mx.groups.io with SMTP id smtpd.web12.5891.1582711448503960332 for ; Wed, 26 Feb 2020 02:04:08 -0800 X-Received: by mail-wr1-f65.google.com with SMTP id j7so2129504wrp.13 for ; Wed, 26 Feb 2020 02:04:08 -0800 (PST) X-Gm-Message-State: hMQH3yhsQ9wuxoJxQSyZdCQUx1787277AA= X-Google-Smtp-Source: APXvYqzqnkveVQCGExq5jKvxsLuh2LEWagFhfqdzZnJSqVkR7VcPlX+Fv+Huvnxxb/NnVzd1Kv+yFA== X-Received: by 2002:a05:6000:192:: with SMTP id p18mr4560335wrx.218.1582711446622; Wed, 26 Feb 2020 02:04:06 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id b10sm2559159wrw.61.2020.02.26.02.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 02:04:05 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, lersek@redhat.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 4/6] ArmPkg/ArmMmuLib AARCH64: cache-invalidate initial page table entries Date: Wed, 26 Feb 2020 11:03:51 +0100 Message-Id: <20200226100353.31962-5-ard.biesheuvel@linaro.org> In-Reply-To: <20200226100353.31962-1-ard.biesheuvel@linaro.org> References: <20200226100353.31962-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582711449; bh=k0TesOd86ezSg4u+FIu7paEMw9+nqN2DQgTNbOKDp24=; h=Cc:Date:From:Reply-To:Subject:To; b=cRAJWGsgoNF6LH56eC5LKJvnhFcP48heycFA6AUtP4TpOrc7L8KqZcRIDpST5aFFZOR 0hcFFWlgXBNWqDaFaAMJnS1tmOD3OY0N4BjFAb1Im8ITAETMlVuXoYXbUftC4iNWuzwgK PRrO5VgFjZ5ZoMDzbPx/t5+iQBLh4qRzN0o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the AARCH64 version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if set/way operations were the appropriate method to achieve this, doing an invalidate-all first and then populating the page table entries creates a window where page table entries could be loaded speculatively into the caches before we modify them, and shadow the new values that we write there. So let's get rid of the blanket clean/invalidate operations, and instead, update ArmUpdateTranslationTableEntry () to invalidate each page table entry *after* it is written if the MMU is still disabled at this point. On ARMv8, it is guaranteed that memory accesses done by the page table walker are cache coherent, and so we can ignore the case where the MMU is on. Since the MMU and D-cache are already off when we reach this point, we can drop the MMU and D-cache disables as well. Maintenance of the I-cache is unnecessary, since we are not modifying any code, and the installed mapping is guaranteed to be 1:1. This means we can also leave it enabled while the page table population code is running. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 9 ++++++++- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 9 --------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library= /ArmLib/AArch64/ArmLibSupport.S index 1adf960377a2..f744cd6738b9 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -13,6 +13,8 @@ .set DAIF_RD_FIQ_BIT, (1 << 6) .set DAIF_RD_IRQ_BIT, (1 << 7) =20 +.set SCTLR_ELx_M_BIT_POS, (0) + ASM_FUNC(ArmReadMidr) mrs x0, midr_el1 // Read from Main ID Register (MIDR) ret @@ -122,11 +124,16 @@ ASM_FUNC(ArmUpdateTranslationTableEntry) lsr x1, x1, #12 EL1_OR_EL2_OR_EL3(x0) 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1 + mrs x2, sctlr_el1 b 4f 2: tlbi vae2, x1 // TLB Invalidate VA , EL2 + mrs x2, sctlr_el2 b 4f 3: tlbi vae3, x1 // TLB Invalidate VA , EL3 -4: dsb nsh + mrs x2, sctlr_el3 +4: tbnz x2, SCTLR_ELx_M_BIT_POS, 5f + dc ivac, x0 // invalidate in Dcache if MMU is still o= ff +5: dsb nsh isb ret =20 diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index e8f5c69e3136..204e33c75f95 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -699,15 +699,6 @@ ArmConfigureMmu ( =20 ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); =20 - // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs - ArmDisableMmu (); - ArmDisableDataCache (); - ArmDisableInstructionCache (); - - // Make sure nothing sneaked into the cache - ArmCleanInvalidateDataCache (); - ArmInvalidateInstructionCache (); - TranslationTableAttribute =3D TT_ATTR_INDX_INVALID; while (MemoryTable->Length !=3D 0) { =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54850): https://edk2.groups.io/g/devel/message/54850 Mute This Topic: https://groups.io/mt/71562849/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:28:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54851+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54851+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582711452; cv=none; d=zohomail.com; s=zohoarc; b=MInmw15hlgfVZf8jfDr3N2AWDUNxCu/3JBFzP6lWwQ2wqGdMO5f832Nbk7x4DQkJDww1o31gYK/pweuN4tJF3azwzyYGzuYgwFZF8e250hGZqfhxMDEqLHuoS0x5lHRaf8h1SaIhI63ZQuZNe/9GJYWFw4V2NIgNDhYbiIQs1xI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582711452; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=0zWk5flajbrRaxZDyxcLm9ZO5Cd87a4apYORi7RxqbU=; b=NzFumvxtS4Mj26oOlhhlLXPpQW4z1JGQEw2kEi0szdim3C2XdZIZLUBmFuPyODQt8C0fxf4VAHJgG/OwKu5CxUFA9ujakl9CwIZ3Qwpc7ORixAG6ZvViotrJ73ETPjTEPul1qXpEW8CFJyfM3l8z+r5uWSjcAV0mCbx3aOy9xjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54851+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582711452571226.22389856126813; Wed, 26 Feb 2020 02:04:12 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id YFhuYY1788612xXOIGeNoCS2; Wed, 26 Feb 2020 02:04:11 -0800 X-Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.groups.io with SMTP id smtpd.web11.5828.1582711450753344352 for ; Wed, 26 Feb 2020 02:04:11 -0800 X-Received: by mail-wr1-f68.google.com with SMTP id p18so2158331wre.9 for ; Wed, 26 Feb 2020 02:04:10 -0800 (PST) X-Gm-Message-State: 4gRWO8zA1lA6hq7oojmSfUjix1787277AA= X-Google-Smtp-Source: APXvYqyqBzmZDmt60C4I7uGzvCEoHglildL8npGIOdfLIyf54CMApEXURNXoLdd/P8LroRki5f7EZw== X-Received: by 2002:adf:f244:: with SMTP id b4mr4637677wrp.413.1582711448991; Wed, 26 Feb 2020 02:04:08 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id b10sm2559159wrw.61.2020.02.26.02.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 02:04:07 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, lersek@redhat.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 5/6] ArmPkg/ArmLib: move set/way helper functions into private header Date: Wed, 26 Feb 2020 11:03:52 +0100 Message-Id: <20200226100353.31962-6-ard.biesheuvel@linaro.org> In-Reply-To: <20200226100353.31962-1-ard.biesheuvel@linaro.org> References: <20200226100353.31962-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582711451; bh=yXE3155pPSK+qDOl4/40bnB9M+Ofl48oXrv0ZKUtl20=; h=Cc:Date:From:Reply-To:Subject:To; b=QT2U6q6vmaZZRiYbGBpVjHGhBWNkuE1i2e4o+0Iv7FTino4DS/NkbaKQzyo1DrTU0Db iKB3E6AquuF5bcn6wVvm9RU/P/t8nYSpP6wTLcdlAlvj1dGjMWFWJu02LZ9pfhddKi7l6 S+BIDyKIfBc3+b+GJcSG1Jbf7U0UXOtrJBA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The clean/invalidate helper functions that operate on a single cache line identified by set, way and level in a special, architected format are only used by the implementations of the clean/invalidate routines that operate on the entire cache hierarchy, as exposed by ArmLib. The latter routines will be deprecated soon, so move the helpers out of ArmLib.h and into a private header so they are safe from abuse. Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Library/ArmLib.h | 18 ------------------ ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h | 18 ++++++++++++++++++ ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h | 18 ++++++++++++++++++ 3 files changed, 36 insertions(+), 18 deletions(-) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index e76a46d5f4ce..5a27b7c2fc27 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -211,24 +211,6 @@ ArmCleanInvalidateDataCacheEntryByMVA ( IN UINTN Address ); =20 -VOID -EFIAPI -ArmInvalidateDataCacheEntryBySetWay ( - IN UINTN SetWayFormat - ); - -VOID -EFIAPI -ArmCleanDataCacheEntryBySetWay ( - IN UINTN SetWayFormat - ); - -VOID -EFIAPI -ArmCleanInvalidateDataCacheEntryBySetWay ( - IN UINTN SetWayFormat - ); - VOID EFIAPI ArmEnableDataCache ( diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.h index ab9bcf553c4d..b2c8a8ea0b84 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h @@ -17,5 +17,23 @@ AArch64AllDataCachesOperation ( IN AARCH64_CACHE_OPERATION DataCacheOperation ); =20 +VOID +EFIAPI +ArmInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + #endif // __AARCH64_LIB_H__ =20 diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h b/ArmPkg/Library/ArmLib/A= rm/ArmV7Lib.h index c52fb9a1b484..93183e67230e 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h @@ -30,5 +30,23 @@ ArmV7AllDataCachesOperation ( IN ARM_V7_CACHE_OPERATION DataCacheOperation ); =20 +VOID +EFIAPI +ArmInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + +VOID +EFIAPI +ArmCleanInvalidateDataCacheEntryBySetWay ( + IN UINTN SetWayFormat + ); + #endif // __ARM_V7_LIB_H__ =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54851): https://edk2.groups.io/g/devel/message/54851 Mute This Topic: https://groups.io/mt/71562851/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:28:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54852+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54852+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582711454; cv=none; d=zohomail.com; s=zohoarc; b=oLYnQNSTv/0NRaGG2i6lqv0M5g6GAH1sMaDm8DPzwo+Fe6OxvDPkcHbMpwM7/XH5cg/GAXTU6OeL1JHbf2HhLJzH7Fkh9jdu0syWOCwuZW9gVv6RtkQpwEfpLpW+Hh77pjrj4w8soWDsh0uPMfHD1XNmK2PiwGS3+CDKz0yXw5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582711454; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=YUTbDIUsXigh7f8hM1MmtEoX1vnT6RMuv/gxO0FvwRA=; b=Ogus00HYSZTmDjwQZ79Vlhym3ADdPvMtYLYCKbmYcsTwNmARyGH9xss9/WjRghjk9RUMaDtg6Mt0WzecHTH0jBmj39AVE3STelCM3L4yT0gf99Cooncx4jkuJwW3VwQHmvbs9moj12cxiNg9UgL8UlpG5zhx0+F094ZPIWcNN7M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54852+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582711454156897.0589499478127; Wed, 26 Feb 2020 02:04:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id oB0xYY1788612xGBgtXTd8vf; Wed, 26 Feb 2020 02:04:13 -0800 X-Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by mx.groups.io with SMTP id smtpd.web10.6070.1582711452323966753 for ; Wed, 26 Feb 2020 02:04:12 -0800 X-Received: by mail-wr1-f67.google.com with SMTP id r17so50317wrj.7 for ; Wed, 26 Feb 2020 02:04:12 -0800 (PST) X-Gm-Message-State: GYvhHfaHQ4SLUVM03JcdtxyWx1787277AA= X-Google-Smtp-Source: APXvYqz8/RDCbSoto4tymIoX8LxKWGGBrGmqQAll6a5FIWg+dZbj78mgBPxnW0geaIP8cneC5NU37g== X-Received: by 2002:a5d:6406:: with SMTP id z6mr4561779wru.294.1582711450343; Wed, 26 Feb 2020 02:04:10 -0800 (PST) X-Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id b10sm2559159wrw.61.2020.02.26.02.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2020 02:04:09 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, lersek@redhat.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH 6/6] ArmPkg/ArmLib: deprecate set/way cache maintenance routines Date: Wed, 26 Feb 2020 11:03:53 +0100 Message-Id: <20200226100353.31962-7-ard.biesheuvel@linaro.org> In-Reply-To: <20200226100353.31962-1-ard.biesheuvel@linaro.org> References: <20200226100353.31962-1-ard.biesheuvel@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582711453; bh=g5ZjYrPpj5bAr4ijqLOrrSk7+sfOhhSzXA07FrKb66c=; h=Cc:Date:From:Reply-To:Subject:To; b=wDA8HldcduZNPQMPx+maSCq5FBq2rZlnJkGiScc0VE2YipAyifzNIhX9f3GYQUFLzwH puL6Snxbh1wfZW5ImdwSmpPkkIV5Z1KKqx/oQdgq8KvdNnP/BbqPkb8MU0dAN7VGDWIKF x0q16Ni66nwHXU15Wu47lLRK8PhzdG2SY7g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cache maintenance on ARMv7 systems and up should be done by virtual address if the purpose is to manage the cached state of contents of memory. Set/way operations are only intended to maintain the caches themselves, e.g., to ensure that the contents of dirty cachelines are brought to main memory before the core is powered off entirely. UEFI on ARM is typically not involved in the latter at all, and any cache maintenance it does is to ensure that the memory it occupies and modifies remains in a consistent state with respect to the caches. So let's deprecate the set/way routines now that we have removed all uses of it in the core code. Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Library/ArmLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 5a27b7c2fc27..8330339302ca 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -156,6 +156,8 @@ ArmIsMpCore ( VOID ); =20 +#ifndef DISABLE_NEW_DEPRECATED_INTERFACES + VOID EFIAPI ArmInvalidateDataCache ( @@ -169,6 +171,8 @@ ArmCleanInvalidateDataCache ( VOID ); =20 +#endif + VOID EFIAPI ArmCleanDataCache ( --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54852): https://edk2.groups.io/g/devel/message/54852 Mute This Topic: https://groups.io/mt/71562852/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-