From nobody Mon Apr 29 09:03:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54789+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54789+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582643178; cv=none; d=zohomail.com; s=zohoarc; b=e7jSmIASkj0+t5Sz8AxDh1W7RhH+YvOTOHuhM18IkhciDL+b5qwH6FIKZuWOVuY8p5Ap0zKYs6oPcFTSXZn0fDR4diQxYVqOtpKxBN39VEw4wCgs/S4gVas4/miJOSldluKbY9qcYb04Ka00qr7uyE0A5SkxeiVx9Klg644GkAM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582643178; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=+LImCP7/NwK81IH8PT0cLqKUrJYl0QUc4Xvk32DpipM=; b=eQUL09C/gkt3MCnHc2uaBQqPfz+5JUvaHRVV2VscnQ27yWclj94qsMk3Ydc2xpu84fma6LF9qGQLxIsOc9tmZ45zN3qRPAO7wyOLKHNFQFh3CTDsKiokZ95H8gfLJT+Zo4qYi1uher2WGVILjXtU7XmX3haiTuSVocoTa0BSn3g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54789+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582643178387639.6319769638247; Tue, 25 Feb 2020 07:06:18 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id n3u1YY1788612xYou62J9VRU; Tue, 25 Feb 2020 07:06:17 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web12.5689.1582643176864161371 for ; Tue, 25 Feb 2020 07:06:16 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Feb 2020 07:06:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,484,1574150400"; d="scan'208";a="260722811" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by fmsmga004.fm.intel.com with ESMTP; 25 Feb 2020 07:06:13 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCHv2 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency Date: Tue, 25 Feb 2020 16:05:53 +0100 Message-Id: <20200225150553.6040-2-mateusz.albecki@intel.com> In-Reply-To: <20200225150553.6040-1-mateusz.albecki@intel.com> References: <20200225150553.6040-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: oviAnSjG64I6gUH1cUz9TUCKx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582643177; bh=HfsJmpTAmrMfBloiNQeAkJnuaix43qQ7DK1xdgimzJs=; h=Cc:Date:From:Reply-To:Subject:To; b=B9NkmALCrGwrLE75t4/OkXhI4ueJD5pdNiaGIm9Fg443yzv0t9y/q9XFcpMXnsP009k sGNW+9AYATQuujTurd5sjeSK1rKIBJhihCayhDMoOJyw1PBJNjQ3j7mNFbCgaW54z4Hlt BXUKA0SCervmFNK93DGt7imuK040gfYALb4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1140 To avoid stability issues on some designs the driver will now send SEND_STATUS at previous, lower, frequency when upgrading the bus timing. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 88 ++++++++++++++++--= ---- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 2 +- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 + 4 files changed, 69 insertions(+), 24 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg= /Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c index 776c0e796c..8b5f8e8ee7 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c @@ -558,6 +558,43 @@ EmmcTuningClkForHs200 ( return EFI_DEVICE_ERROR; } =20 +/** + Check the SWITCH operation status. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL inst= ance. + @param[in] Slot The slot number on which command should be sent. + @param[in] Rca The relative device address. + + @retval EFI_SUCCESS The SWITCH finished siccessfully. + @retval others The SWITCH failed. +**/ +EFI_STATUS +EmmcCheckSwitchStatus ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 Slot, + IN UINT16 Rca + ) +{ + EFI_STATUS Status; + UINT32 DevStatus; + + Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails with %r= \n", Status)); + return Status; + } + + // + // Check the switch operation is really successful or not. + // + if ((DevStatus & BIT7) !=3D 0) { + DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch operation fail= s as DevStatus is 0x%08x\n", DevStatus)); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + /** Switch the bus width to specified width. =20 @@ -591,7 +628,6 @@ EmmcSwitchBusWidth ( UINT8 Index; UINT8 Value; UINT8 CmdSet; - UINT32 DevStatus; =20 // // Write Byte, the Value field is written into the byte pointed by Index. @@ -617,18 +653,10 @@ EmmcSwitchBusWidth ( return Status; } =20 - Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); + Status =3D EmmcCheckSwitchStatus (PassThru, Slot, Rca); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n"= , Status)); return Status; } - // - // Check the switch operation is really successful or not. - // - if ((DevStatus & BIT7) !=3D 0) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation fails a= s DevStatus is 0x%08x\n", DevStatus)); - return EFI_DEVICE_ERROR; - } =20 Status =3D SdMmcHcSetBusWidth (PciIo, Slot, BusWidth); =20 @@ -669,9 +697,9 @@ EmmcSwitchBusTiming ( UINT8 Index; UINT8 Value; UINT8 CmdSet; - UINT32 DevStatus; SD_MMC_HC_PRIVATE_DATA *Private; UINT8 HostCtrl1; + BOOLEAN DelaySendStatus; =20 Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); // @@ -695,7 +723,7 @@ EmmcSwitchBusTiming ( Value =3D 0; break; default: - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d\= n)", BusTiming)); + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d)= \n", BusTiming)); return EFI_INVALID_PARAMETER; } =20 @@ -724,6 +752,26 @@ EmmcSwitchBusTiming ( return Status; } =20 + // + // For cases when we switch bus timing to higher mode from current we wa= nt to + // send SEND_STATUS at current, lower, frequency then the target frequen= cy to avoid + // stability issues. It has been observed that some designs are unable t= o process the + // SEND_STATUS at higher frequency during switch to HS200 @200MHz irresp= ective of the number of retries + // and only running the clock tuning is able to make them work at target= frequency. + // + // For cases when we are downgrading the frequency and current high freq= uency is invalid + // we have to first change the frequency to target frequency and then se= nd the SEND_STATUS. + // + if (Private->Slot[Slot].CurrentFreq < (ClockFreq * 1000)) { + Status =3D EmmcCheckSwitchStatus (PassThru, Slot, Rca); + if (EFI_ERROR (Status)) { + return Status; + } + DelaySendStatus =3D FALSE; + } else { + DelaySendStatus =3D TRUE; + } + // // Convert the clock freq unit from MHz to KHz. // @@ -732,17 +780,11 @@ EmmcSwitchBusTiming ( return Status; } =20 - Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Send status fails with %r\n= ", Status)); - return Status; - } - // - // Check the switch operation is really successful or not. - // - if ((DevStatus & BIT7) !=3D 0) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: The switch operation fails = as DevStatus is 0x%08x\n", DevStatus)); - return EFI_DEVICE_ERROR; + if (DelaySendStatus) { + Status =3D EmmcCheckSwitchStatus (PassThru, Slot, Rca); + if (EFI_ERROR (Status)) { + return Status; + } } =20 return Status; diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c index b18ff3e972..57f4cf329a 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c @@ -28,7 +28,7 @@ EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding =3D { NULL }; =20 -#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, \ +#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0, \ {EDKII_SD_MMC_BUS_WIDTH_IGNORE,\ EDKII_SD_MMC_CLOCK_FREQ_IGNORE,\ {EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE}}} diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h index 5bc3577ba2..bb3d38482f 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h @@ -83,6 +83,7 @@ typedef struct { BOOLEAN MediaPresent; BOOLEAN Initialized; SD_MMC_CARD_TYPE CardType; + UINT64 CurrentFreq; EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters; } SD_MMC_HC_SLOT; =20 diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 43626fff48..7971196a25 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -931,6 +931,8 @@ SdMmcHcClockSupply ( } } =20 + Private->Slot[Slot].CurrentFreq =3D ClockFreq; + return Status; } =20 --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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