From nobody Thu May 2 13:20:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54713+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54713+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582298265; cv=none; d=zohomail.com; s=zohoarc; b=fcVox5+GyIN53BAE4z4m+pfaFOGl39KOd0zirkcjmOXlWiPizua5yAnx2TZGU3V3M8u7v/m9asNYCCjp2ht5G1PmrCwicAn4K8ecR7EZ+tN/WnP24JZLiL80Yna5E2+oMeWEXnAj7SDqufbokp+QFnZ1Di4LPnFe204vxhkE30s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582298265; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=jMemrjcPs+F2FghQIdoDRnopzDUD5b2id/Ns45Goo7k=; b=IwEtJ1chIf3KTOKw8nFwtWtm0ekXAOsGOQxXBOSO2Vrdf/zYCs8vaksiV+7Ujt6TXSNGoC+HCCGJFzesujYzc+8CdYjJaNlvRc88lfc3FxTKpIYjXo0LeaLFRIOsnBWfhuxpmtR5e5F3VKuglrLBz0bhwJ9OA3Y9ar4Cu95ZN8g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54713+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 158229826592673.84500308235056; Fri, 21 Feb 2020 07:17:45 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id kkHlYY1788612x310YFU5V6E; Fri, 21 Feb 2020 07:17:45 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.9795.1582298265141393727 for ; Fri, 21 Feb 2020 07:17:45 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Feb 2020 07:17:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,468,1574150400"; d="scan'208";a="225240902" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by orsmga007.jf.intel.com with ESMTP; 21 Feb 2020 07:17:42 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency Date: Fri, 21 Feb 2020 16:17:19 +0100 Message-Id: <20200221151719.4248-2-mateusz.albecki@intel.com> In-Reply-To: <20200221151719.4248-1-mateusz.albecki@intel.com> References: <20200221151719.4248-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: YDp74MnHK2SaYdg3gBGyFqC3x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582298265; bh=m276TH8qogl40nZOggOoxA+i1QOFlHaeWFNQ4olGuQU=; h=Cc:Date:From:Reply-To:Subject:To; b=t0ikwwm8ZTJ6B3l+iQk8TYDyPHkKpSA2HbAF8mpU8MjB8yT03M703rAO4YkAz+aomlg ikWkRj/nD16xq23Y3MKWHNfjW5ChznajL+YHQ5sby/7aMMWM/UYsTzMSMR1rCEdjh05lp 5RdJiz67H8A/wjjXxyCPMc+1UsI+wDW3H+0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1140 To avoid stability issues on some designs the driver will now send SEND_STATUS at previous, lower, frequency when upgrading the bus timing. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 124 +++++++++++++++++= ---- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 2 +- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 1 + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 + 4 files changed, 105 insertions(+), 24 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg= /Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c index 776c0e796c..c2ebd37623 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c @@ -558,6 +558,41 @@ EmmcTuningClkForHs200 ( return EFI_DEVICE_ERROR; } =20 +/** + Check the SWITCH operation status. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL inst= ance. + + @retval EFI_SUCCESS The SWITCH finished siccessfully. + @retval others The SWITCH failed. +**/ +EFI_STATUS +EmmcCheckSwitchStatus ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 Slot, + IN UINT16 Rca + ) +{ + EFI_STATUS Status; + UINT32 DevStatus; + + Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails with %r= \n", Status)); + return Status; + } + + // + // Check the switch operation is really successful or not. + // + if ((DevStatus & BIT7) !=3D 0) { + DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch operation fail= s as DevStatus is 0x%08x\n", DevStatus)); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + /** Switch the bus width to specified width. =20 @@ -591,7 +626,6 @@ EmmcSwitchBusWidth ( UINT8 Index; UINT8 Value; UINT8 CmdSet; - UINT32 DevStatus; =20 // // Write Byte, the Value field is written into the byte pointed by Index. @@ -617,24 +651,53 @@ EmmcSwitchBusWidth ( return Status; } =20 - Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); + Status =3D EmmcCheckSwitchStatus (PassThru, Slot, Rca); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n"= , Status)); return Status; } - // - // Check the switch operation is really successful or not. - // - if ((DevStatus & BIT7) !=3D 0) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation fails a= s DevStatus is 0x%08x\n", DevStatus)); - return EFI_DEVICE_ERROR; - } =20 Status =3D SdMmcHcSetBusWidth (PciIo, Slot, BusWidth); =20 return Status; } =20 +/** + Checks if given clock frequency is supported on + given bus timing. + + @param[in] ClockFreq Clock frequency to check in KHz. + @param[in] BusTiming Bus timing against which frequency will be compare= d. + + @retval TRUE Frequency is valid for given bus timing. + @retval FALSE Frequency is invalid for given bus timing. +**/ +BOOLEAN +EmmcIsFrequencySupportedOnBusTiming ( + IN UINT64 ClockFreq, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + UINT32 MaxFreq; + + switch (BusTiming) { + case SdMmcMmcLegacy: + MaxFreq =3D 26000; + break; + case SdMmcMmcHsSdr: + case SdMmcMmcHsDdr: + MaxFreq =3D 52000; + break; + case SdMmcMmcHs200: + case SdMmcMmcHs400: + MaxFreq =3D 200000; + break; + default: + return FALSE; + } + + return (ClockFreq <=3D MaxFreq); +} + /** Switch the bus timing and clock frequency. =20 @@ -669,9 +732,9 @@ EmmcSwitchBusTiming ( UINT8 Index; UINT8 Value; UINT8 CmdSet; - UINT32 DevStatus; SD_MMC_HC_PRIVATE_DATA *Private; UINT8 HostCtrl1; + BOOLEAN DelaySendStatus; =20 Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); // @@ -695,7 +758,7 @@ EmmcSwitchBusTiming ( Value =3D 0; break; default: - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d\= n)", BusTiming)); + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d)= \n", BusTiming)); return EFI_INVALID_PARAMETER; } =20 @@ -724,6 +787,27 @@ EmmcSwitchBusTiming ( return Status; } =20 + // + // For cases when we switch bus timing to higher mode from current we wa= nt to + // send SEND_STATUS at current, lower, frequency then the target frequen= cy to avoid + // stability issues. It has been observed that some designs are unable t= o process the + // SEND_STATUS at higher frequency during switch to HS200 @200MHz irresp= ective of the number of retries + // and only running the clock tuning is able to make them work on target= frequency. + // + // For cases when we are downgrading the frequency and current high freq= uency is invalid + // we have to first change the frequency to target frequency and then se= nd the SEND_STATUS. + // + if (EmmcIsFrequencySupportedOnBusTiming (Private->Slot[Slot].CurrentFreq= , BusTiming) && + (Private->Slot[Slot].CurrentFreq < (ClockFreq * 1000))) { + Status =3D EmmcCheckSwitchStatus (PassThru, Slot, Rca); + if (EFI_ERROR (Status)) { + return Status; + } + DelaySendStatus =3D FALSE; + } else { + DelaySendStatus =3D TRUE; + } + // // Convert the clock freq unit from MHz to KHz. // @@ -732,17 +816,11 @@ EmmcSwitchBusTiming ( return Status; } =20 - Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Send status fails with %r\n= ", Status)); - return Status; - } - // - // Check the switch operation is really successful or not. - // - if ((DevStatus & BIT7) !=3D 0) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: The switch operation fails = as DevStatus is 0x%08x\n", DevStatus)); - return EFI_DEVICE_ERROR; + if (DelaySendStatus) { + Status =3D EmmcCheckSwitchStatus (PassThru, Slot, Rca); + if (EFI_ERROR (Status)) { + return Status; + } } =20 return Status; diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c index b18ff3e972..57f4cf329a 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c @@ -28,7 +28,7 @@ EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding =3D { NULL }; =20 -#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, \ +#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, 0, \ {EDKII_SD_MMC_BUS_WIDTH_IGNORE,\ EDKII_SD_MMC_CLOCK_FREQ_IGNORE,\ {EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE}}} diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h index 5bc3577ba2..bb3d38482f 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h @@ -83,6 +83,7 @@ typedef struct { BOOLEAN MediaPresent; BOOLEAN Initialized; SD_MMC_CARD_TYPE CardType; + UINT64 CurrentFreq; EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters; } SD_MMC_HC_SLOT; =20 diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 43626fff48..7971196a25 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -931,6 +931,8 @@ SdMmcHcClockSupply ( } } =20 + Private->Slot[Slot].CurrentFreq =3D ClockFreq; + return Status; } =20 --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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