From nobody Mon May 6 06:38:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54579+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54579+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582037645806909.8144584214693; Tue, 18 Feb 2020 06:54:05 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id cL5yYY1788612xB9QGIegl8a; Tue, 18 Feb 2020 06:54:05 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.4945.1582037644559411810 for ; Tue, 18 Feb 2020 06:54:04 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Feb 2020 06:54:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,456,1574150400"; d="scan'208";a="268781406" X-Received: from kesakkit-desk2.gar.corp.intel.com ([10.66.253.115]) by fmsmga002.fm.intel.com with ESMTP; 18 Feb 2020 06:54:02 -0800 From: "Kathappan Esakkithevar" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Deepika Kethi Reddy , Prince Agyeman Subject: [edk2-devel] [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Date: Tue, 18 Feb 2020 20:23:42 +0530 Message-Id: <20200218145343.11820-2-kathappan.esakkithevar@intel.com> In-Reply-To: <20200218145343.11820-1-kathappan.esakkithevar@intel.com> References: <20200218145343.11820-1-kathappan.esakkithevar@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kathappan.esakkithevar@intel.com X-Gm-Message-State: JBOmU3alfLYminjqpCbdyw2Jx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582037645; bh=d+3/g9ko0Sf1dWoUb52D+vYFCpy8loXeRNM5FSsbj3c=; h=Cc:Date:From:Reply-To:Subject:To; b=bKz/lczNLNp0jgtpxP5Vdm+LQoLS885oFg+ymEdlBhEkJQLXzV3CWGAySfytW6CqpF8 qJV7+/ic/1a0vhICWR6lSfS2G5o46Hh4PpVlw7KiGfqy3G703X0K+ATLEQyZL3BXnBTxh La8b94KbPn2VzHSFVPUYkLuks9/sfkN/sU8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280 Adds CPU model, SA Device ID, PCH SKU ID for Cometlake U V1. Key files =3D=3D=3D=3D=3D=3D=3D=3D=3D * CpuReg.h - Add CPU Family Model support. * SaRegsHostBridge.h - Add SA Device ID support. * MrcInterface.h - Add CPU Family Model support in MRC. * PchRegsLpcCnl.h - Add PCH SKU ID support. Signed-off-by: Kathappan Esakkithevar Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Deepika Kethi Reddy Cc: Prince Agyeman Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone Reviewed-by: Sai Chaganty --- .../Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h | 5 ++++- .../PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c | 18 ++++++++++++++= +++- .../Pch/Include/Register/PchRegsLpcCnl.h | 3 ++- .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c | 5 ++++- .../SystemAgent/Include/Register/SaRegsHostBridge.h | 5 ++++- .../MemoryInit/Include/Coffeelake/MrcInterface.h | 5 +++-- 6 files changed, 34 insertions(+), 7 deletions(-) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h index 68f2c019e2..4b9ce8d4d3 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h @@ -9,7 +9,7 @@ - Definitions beginning with "S_" are register sizes - Definitions beginning with "N_" are the bit position =20 - Copyright (c) 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -181,6 +181,7 @@ #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0 #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0 #define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670 +#define CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT 0x000A0660 =20 #ifndef STALL_ONE_MICRO_SECOND #define STALL_ONE_MICRO_SECOND 1 @@ -206,6 +207,7 @@ typedef enum { EnumCpuCflUltUlx =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX, EnumCpuCflDtHalo =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO, EnumCpuCnlDtHalo =3D CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO, + EnumCpuCmlUlt =3D CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT, EnumCpuMax =3D CPUID_FULL_FAMILY_MODEL } CPU_FAMILY; =20 @@ -256,6 +258,7 @@ typedef enum { /// typedef enum { EnumCflCpu =3D 0, + EnumCmlCpu, EnumCpuUnknownGeneration =3D 255 } CPU_GENERATION; #endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPla= tformLib/CpuPlatformLibrary.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Libr= ary/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c index 18f2028fa9..702a10c9d8 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLi= b/CpuPlatformLibrary.c +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLi= b/CpuPlatformLibrary.c @@ -1,7 +1,7 @@ /** @file CPU Platform Lib implementation. =20 - Copyright (c) 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -80,6 +80,15 @@ GetCpuSku ( CpuDid =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_= BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID)); =20 switch (CpuFamilyModel) { + case CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT: + switch (CpuDid) { + case V_SA_DEVICE_ID_CML_ULT_1: // CML ULT + case V_SA_DEVICE_ID_CML_ULT_2: // CML ULT + case V_SA_DEVICE_ID_CML_ULT_3: // CML ULT + CpuType =3D EnumCpuUlt; + break; + } + break; case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX: switch (CpuDid) { case V_SA_DEVICE_ID_KBL_MB_ULT_1: // KBL ULT OPI @@ -87,6 +96,9 @@ GetCpuSku ( case V_SA_DEVICE_ID_CFL_ULT_2: // CFL ULT case V_SA_DEVICE_ID_CFL_ULT_3: // CFL ULT case V_SA_DEVICE_ID_CFL_ULT_4: // CFL ULT + case V_SA_DEVICE_ID_CML_ULT_1: // CML ULT + case V_SA_DEVICE_ID_CML_ULT_2: // CML ULT + case V_SA_DEVICE_ID_CML_ULT_3: // CML ULT CpuType =3D EnumCpuUlt; break; =20 @@ -378,6 +390,10 @@ GetCpuGeneration ( CpuGeneration =3D EnumCflCpu; break; =20 + case EnumCpuCmlUlt: + CpuGeneration =3D EnumCmlCpu; + break; + default: CpuGeneration =3D EnumCpuUnknownGeneration; ASSERT (FALSE); diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sLpcCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs= LpcCnl.h index 74789a87ce..e8a18cac3e 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl= .h +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl= .h @@ -21,7 +21,7 @@ - Registers / bits of new devices introduced in a PCH generation will be= just named as "_PCH_" without [generation_name] inserted. =20 - Copyright (c) 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -31,6 +31,7 @@ =20 #define V_LPC_CFG_DID_CNL_H 0xA300 #define V_LPC_CFG_DID_CNL_LP 0x9D80 +#define V_LPC_CFG_DID_CML_LP 0x0280 =20 // // PCH-LP Device IDs diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInf= oLib/PchInfoLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDx= eSmmPchInfoLib/PchInfoLibCnl.c index 431b1470c2..da6479f212 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pc= hInfoLibCnl.c +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pc= hInfoLibCnl.c @@ -4,7 +4,7 @@ All function in this library is available for PEI, DXE, and SMM, But do not support UEFI RUNTIME environment call. =20 - Copyright (c) 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -37,6 +37,9 @@ PchSeriesFromLpcDid ( case V_LPC_CFG_DID_CNL_LP: return PCH_LP; =20 + case V_LPC_CFG_DID_CML_LP: + return PCH_LP; + default: return PCH_UNKNOWN_SERIES; } diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsHostBridge.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/Register/SaRegsHostBridge.h index 2cc0e5be68..67bbf13d77 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sHostBridge.h +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sHostBridge.h @@ -15,7 +15,7 @@ - Registers / bits of new devices introduced in a SA generation will be = just named as "_SA_" without [generation_name] inserted. =20 - Copyright (c) 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -112,6 +112,9 @@ #define V_SA_DEVICE_ID_CFL_ULT_4 0x3E35 ///< CoffeeLake Mobile (C= FL-U 2+(1 or 2)) SA DID #define V_SA_DEVICE_ID_CFL_ULT_6 0x3ECC ///< CoffeeLake Mobile (C= FL-U 2+3e) SA DID =20 +#define V_SA_DEVICE_ID_CML_ULT_1 0x9B51 ///< CometLake (CML-U 6+2)= SA DID +#define V_SA_DEVICE_ID_CML_ULT_2 0x9B61 ///< CometLake (CML-U 4+2)= SA DID +#define V_SA_DEVICE_ID_CML_ULT_3 0x9B71 ///< CometLake (CML-U 2+2)= SA DID // // CoffeeLake CPU Desktop SA Device IDs B0:D0:F0 // diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Incl= ude/Coffeelake/MrcInterface.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAg= ent/MemoryInit/Include/Coffeelake/MrcInterface.h index 635906cc2b..b9b390cc71 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Cof= feelake/MrcInterface.h +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Cof= feelake/MrcInterface.h @@ -1,7 +1,7 @@ /** @file This file includes all the data structures that the MRC considers "globa= l data". =20 - Copyright (c) 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -477,7 +477,8 @@ typedef enum { /// typedef enum { cmCFL_ULX_ULT =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX, ///< Co= ffeelake ULT/ULX - cmCFL_DT_HALO =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO ///< Co= ffeelake DT/Halo + cmCFL_DT_HALO =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO, ///< Co= ffeelake DT/Halo + cmCML_ULX_ULT =3D CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT ///< Co= metlake ULT/ULX } MrcCpuModel; =20 /// --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54579): https://edk2.groups.io/g/devel/message/54579 Mute This Topic: https://groups.io/mt/71372343/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 06:38:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54580+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54580+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1582037654500993.555968330414; Tue, 18 Feb 2020 06:54:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id OjkTYY1788612xjOVCaEYAwa; Tue, 18 Feb 2020 06:54:14 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.4973.1582037653601015547 for ; Tue, 18 Feb 2020 06:54:13 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Feb 2020 06:54:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,456,1574150400"; d="scan'208";a="268781453" X-Received: from kesakkit-desk2.gar.corp.intel.com ([10.66.253.115]) by fmsmga002.fm.intel.com with ESMTP; 18 Feb 2020 06:54:11 -0800 From: "Kathappan Esakkithevar" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Deepika Kethi Reddy , Prince Agyeman Subject: [edk2-devel] [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg Date: Tue, 18 Feb 2020 20:23:43 +0530 Message-Id: <20200218145343.11820-3-kathappan.esakkithevar@intel.com> In-Reply-To: <20200218145343.11820-1-kathappan.esakkithevar@intel.com> References: <20200218145343.11820-1-kathappan.esakkithevar@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kathappan.esakkithevar@intel.com X-Gm-Message-State: P9e3XFlBJOSiE59q80QMOXHDx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1582037654; bh=SONCoNbNXlydOToZnE8ieyveZTUBxd/MloKYk0bB4rE=; h=Cc:Date:From:Reply-To:Subject:To; b=YO/ef6zRWmzu3s5yGibJQaSDgNi9HD0NIapsgiV10S7owehsjjmfnMrbFXz1SvzHYOF y+z88qme3jdYkMA3SHJoVz6Y50fsV5Y1VUhP0eUSzvwu9icz7INjc2FKS7yr+LUybmD+f naV958tt7zJ05bNFIbD1lBktWaOll9unKDE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280 This change adds the configuration to enable build for CometlakeURvp. Also it updates Cometlake U Rvp details to the Readme.md. Signed-off-by: Kathappan Esakkithevar Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Deepika Kethi Reddy Cc: Prince Agyeman Reviewed-by: Chasel Chiu --- Platform/Intel/Readme.md | 11 +++++++++++ Platform/Intel/build.cfg | 3 ++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 02d9517d19..b5ad8ed5fe 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -56,6 +56,7 @@ A UEFI firmware implementation using MinPlatformPkg is co= nstructed using the fol * The `KabylakeOpenBoardPkg` contains board implementations for Kaby Lake = systems. * The `SimicsOpenBoardPkg` contains board implementations for the Simics h= ardware simulator. * The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey= Lake systems. +* The `CometlakeOpenBoardPkg` contains board implementations for Comet Lak= e systems. =20 ### **Supported Hardware** =20 @@ -67,6 +68,7 @@ A UEFI firmware implementation using MinPlatformPkg is co= nstructed using the fol ----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| | RVP 3 | Sky Lake, Kaby Lake, Kaby Lake R= efresh | KabylakeOpenBoardPkg | KabylakeRvp3 | | WHL-U DDR4 RVP | Whiskey Lake = | WhiskeylakeOpenBoardPkg | WhiskeylakeURvp | +| CML-U LPDDR3 RVP | COmet Lake V1 = | CometlakeOpenBoardPkg | CometlakeURvp | =20 *Note: RVP =3D Reference and Validation Platform* =20 @@ -237,6 +239,11 @@ return back to the minimum platform caller. | | | |---build_config.cfg: Whiskeyla= keURvp specific build | | | settings = environment variables. | | | + | | |------CometlakeOpenBoardPkg + | | | |------CometlakeURvp + | | | |---build_config.cfg: Cometlake= URvp specific build + | | | settings = environment variables. + | | | |------FSP =20 @@ -257,6 +264,10 @@ return back to the minimum platform caller. 1. This firmware project has only been tested booting to Microsoft Windows= 10 x64 with AHCI mode and Integrated Graphic Device. =20 +**CometlakeOpenBoardPkg** +1. This firmware project has been tested booting to Microsoft Windows 10 x= 64 with AHCI mode and External Graphic Device. +2. This firmware project has been also tested booting to Ubuntu 17.10 with= AHCI mode and Integrated Graphic Device. + ### **Package Builds** =20 In some cases, such as BoardModulePkg, a package may provide a set of func= tionality that is included in other diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index 86a9115021..5bc1dea43c 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -1,7 +1,7 @@ # @ build.cfg # This is the main/default build configuration file # -# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # =20 @@ -58,3 +58,4 @@ BoardX58Ich10 =3D SimicsOpenBoardPkg/BoardX58Ich10/build_= config.cfg GalagoPro3 =3D KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg KabylakeRvp3 =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg WhiskeylakeURvp =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.c= fg +CometlakeURvp =3D CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54580): https://edk2.groups.io/g/devel/message/54580 Mute This Topic: https://groups.io/mt/71372347/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-