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From: "Kathappan Esakkithevar" <kathappan.esakkithevar@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
Chasel Chiu <chasel.chiu@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>,
Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 1/7] CometlakeOpenBoardPkg:
Add package and headers
Date: Wed, 12 Feb 2020 00:42:35 +0530
Message-Id: <20200211191241.53188-2-kathappan.esakkithevar@intel.com>
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280
Create the CometlakeOpenBoardPkg to provide board support code. The
package may support Cometlake boards. The package serves as a board
support package in the EDK II Minimum Platform design. Silicon support
for this package is provided in CometLakeFspBinPkg in the FSP repository
and CoffeelakeSiliconPkg in the edk2-platforms repository.
Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../Tbt/Include/Library/DxeCheckIommuSupportLib.h | 43 +
.../Features/Tbt/Include/Library/DxeTbtPolicyLib.h | 49 +
.../Tbt/Include/Library/DxeTbtSecurityLib.h | 131 ++
.../Tbt/Include/Library/PeiCheckIommuSupportLib.h | 21 +
.../Features/Tbt/Include/Library/PeiTbtPolicyLib.h | 43 +
.../Tbt/Include/Library/PeiTbtTaskDispatchLib.h | 61 +
.../Features/Tbt/Include/Library/TbtCommonLib.h | 261 +++
.../Features/Tbt/Include/Ppi/PeiTbtPolicy.h | 31 +
.../Tbt/Include/Private/Library/PeiDTbtInitLib.h | 130 ++
.../Include/Private/Library/PeiTbtCommonInitLib.h | 51 +
.../Tbt/Include/Protocol/DisableBmeProtocol.h | 36 +
.../Features/Tbt/Include/Protocol/DxeTbtPolicy.h | 137 ++
.../Features/Tbt/Include/Protocol/TbtNvsArea.h | 50 +
.../Features/Tbt/Include/TbtBoardInfo.h | 23 +
.../Features/Tbt/Include/TbtNvsAreaDef.h | 68 +
.../Tbt/Include/TbtPolicyCommonDefinition.h | 84 +
.../Include/Acpi/GlobalNvs.asl | 112 ++
.../Include/Acpi/GlobalNvsAreaDef.h | 118 ++
.../Include/AttemptUsbFirst.h | 51 +
.../Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h | 57 +
.../Include/FirwmareConfigurations.h | 20 +
.../CometlakeOpenBoardPkg/Include/GopConfigLib.h | 1766 ++++++++++++++++=
++++
.../CometlakeOpenBoardPkg/Include/IoExpander.h | 68 +
.../Include/Library/DxeCpuPolicyUpdateLib.h | 75 +
.../Include/Library/DxeMePolicyUpdateLib.h | 27 +
.../Include/Library/DxePchPolicyUpdateLib.h | 25 +
.../Include/Library/DxePolicyBoardConfigLib.h | 30 +
.../Include/Library/DxeSaPolicyUpdateLib.h | 25 +
.../Include/Library/FspPolicyInitLib.h | 29 +
.../Include/Library/GpioCheckConflictLib.h | 46 +
.../Include/Library/GpioExpanderLib.h | 123 ++
.../Include/Library/HdaVerbTableLib.h | 48 +
.../Include/Library/I2cAccessLib.h | 34 +
.../Include/Library/PeiPlatformLib.h | 40 +
.../Include/Library/PeiPolicyBoardConfigLib.h | 141 ++
.../Include/Library/PeiPolicyInitLib.h | 38 +
.../Include/Library/PlatformInitLib.h | 23 +
.../Include/PchHsioPtssTables.h | 51 +
.../Include/PcieDeviceOverrideTable.h | 106 ++
.../Intel/CometlakeOpenBoardPkg/Include/Platform.h | 33 +
.../Include/PlatformBoardId.h | 29 +
.../Include/Protocol/GlobalNvsArea.h | 47 +
.../Intel/CometlakeOpenBoardPkg/Include/Setup.h | 144 ++
.../Intel/CometlakeOpenBoardPkg/Include/SioRegs.h | 157 ++
.../Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec | 564 +++++++
45 files changed, 5246 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Library/DxeCheckIommuSupportLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Library/DxeTbtPolicyLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Library/DxeTbtSecurityLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Library/PeiCheckIommuSupportLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Library/PeiTbtPolicyLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Library/PeiTbtTaskDispatchLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Library/TbtCommonLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Ppi/PeiTbtPolicy.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Private/Library/PeiDTbtInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Private/Library/PeiTbtCommonInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Protocol/DisableBmeProtocol.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Protocol/DxeTbtPolicy.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Protocol/TbtNvsArea.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/TbtBoardInfo.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/TbtNvsAreaDef.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/TbtPolicyCommonDefinition.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/Globa=
lNvs.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/Globa=
lNvsAreaDef.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsb=
First.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareCo=
nfigurations.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigL=
ib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander=
.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Dx=
eCpuPolicyUpdateLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Dx=
eMePolicyUpdateLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Dx=
ePchPolicyUpdateLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Dx=
ePolicyBoardConfigLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Dx=
eSaPolicyUpdateLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Fs=
pPolicyInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Gp=
ioCheckConflictLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Gp=
ioExpanderLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Hd=
aVerbTableLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2=
cAccessLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Pe=
iPlatformLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Pe=
iPolicyBoardConfigLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Pe=
iPolicyInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Pl=
atformInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPts=
sTables.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDevice=
OverrideTable.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBo=
ardId.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/G=
lobalNvsArea.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Libr=
ary/DxeCheckIommuSupportLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Featur=
es/Tbt/Include/Library/DxeCheckIommuSupportLib.h
new file mode 100644
index 0000000000..d0ba236145
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Dxe=
CheckIommuSupportLib.h
@@ -0,0 +1,43 @@
+/** @file
+ Header file for the DxeCheckIommuSupport library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+#define _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
+/**
+ Detect ME FW and Board Type and return the result via IommuSkuCheck.
+
+ IommuSkuCheck
+ BIT0: Indicate system has a Corporate CSME firmware
+ BIT1: Indicate BIOS is running on a CML RVP
+ BIT2: Indicate BIOS is running on a CFL-H RVP
+ BIT3: Indicate BIOS is running on a CFL-S 8+2 RVP
+
+ @retval Return 0 means not support, otherwise value is defined by IommuS=
kuCheck
+**/
+UINT8
+DetectMeAndBoard (
+ VOID
+ );
+
+/**
+ DxeCheckIommuSupport
+
+ Only WHL/CFL-H/CFL-S 8+2 Crop SKUs support Iommu.
+ This function will save sku information to PcdIommuSkuCheck.
+ BIOS will use PcdIommuSkuCheck and other factors to set PcdVTdPolicyProp=
ertyMask on the next boot in PEI phase
+
+ This function might perform a system reset.
+**/
+EFI_STATUS
+EFIAPI
+DxeCheckIommuSupport (
+ VOID
+ );
+#endif // _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Libr=
ary/DxeTbtPolicyLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/I=
nclude/Library/DxeTbtPolicyLib.h
new file mode 100644
index 0000000000..0ebffd55ea
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Dxe=
TbtPolicyLib.h
@@ -0,0 +1,49 @@
+/** @file
+ Prototype of the DxeTbtPolicyLib library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_TBT_POLICY_LIB_H_
+#define _DXE_TBT_POLICY_LIB_H_
+
+
+/**
+ Install TBT Policy.
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b=
uffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallTbtPolicy (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Update Tbt Policy Callback.
+
+ @param[in] Event A pointer to the Event that triggered the callb=
ack.
+ @param[in] Context A pointer to private data registered with the c=
allback function.
+
+**/
+VOID
+EFIAPI
+UpdateTbtPolicyCallback (
+ VOID
+ );
+
+/**
+ Print DXE TBT Policy
+**/
+VOID
+TbtPrintDxePolicyConfig (
+ VOID
+ );
+#endif // _DXE_TBT_POLICY_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Libr=
ary/DxeTbtSecurityLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt=
/Include/Library/DxeTbtSecurityLib.h
new file mode 100644
index 0000000000..5468ff0bf4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Dxe=
TbtSecurityLib.h
@@ -0,0 +1,131 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_SECURITY_LIB_H_
+#define _TBT_SECURITY_LIB_H_
+
+#include <Protocol/Tcg2Protocol.h>
+#include <Protocol/AcpiTable.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/AslUpdateLib.h>
+#include <Library/UefiLib.h>
+#include <Uefi.h>
+#include <SetupVariable.h>
+#include <OemSetup.h>
+#include <DmaRemappingTable.h>
+#include <PcieRegs.h>
+#include <Tcg2ConfigNvData.h>
+#include <TbtPolicyCommonDefinition.h>
+#include <Library/TbtCommonLib.h>
+
+#define TBT_SECURITY_EVENT_STRING "DMA Protection Disabled"
+#define TBT_SECURITY_EVENT_STRING_LEN (sizeof (TBT_SECURITY_EV=
ENT_STRING) - 1)
+
+#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING "Security Level is Downg=
raded to 0"
+#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING_LEN (sizeof (TBT_SECURITY_LE=
VEL_DOWNGRADED_STRING) - 1)
+
+#define GET_TBT_SECURITY_MODE 0
+#define SET_TBT_SECURITY_MODE 1
+
+typedef struct {
+ UINT8 EnableVtd;
+ BOOLEAN SLDowngrade;
+} PCR7_DATA;
+
+/**
+ TBT Security ExtendPCR7 CallBackFunction
+ If the firmware/BIOS has an option to enable and disable DMA protections=
via a VT-d switch in BIOS options, then the shipping configuration must be=
with VT-d protection enabled.
+ On every boot where VT-d/DMA protection is disabled, or will be disabled=
, or configured to a lower security state, and a platform has a TPM enabled=
, then the platform SHALL extend an EV_EFI_ACTION event into PCR[7] before =
enabling external DMA.
+ The event string SHALL be "DMA Protection Disabled". The platform firmwa=
re MUST log this measurement in the event log using the string "DMA Protect=
ion Disabled" for the Event Data.
+ Measure and log launch of TBT Security, and extend the measurement resul=
t into a specific PCR.
+ Extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA. =
The event string SHALL be "DMA Protection Disabled". The platform firmware =
MUST log this measurement in the event log using the string "DMA Protection=
Disabled" for the Event Data.
+
+ @param[in] Event - A pointer to the Event that triggered the callbac=
k.
+ @param[in] Context - A pointer to private data registered with the cal=
lback function.
+**/
+VOID
+EFIAPI
+ExtendPCR7CallBackFunction (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+/**
+ TBT Security DisableBme CallBackFunction
+
+ BIOS will disable BME and tear down the Thunderbolt DMAR tables at ExitB=
ootServices
+ in order to hand off security of TBT hierarchies to the OS.
+ The BIOS is expected to either: Disable BME from power on till the OS st=
arts configuring the devices and enabling BME Enable BME only for devices t=
hat can be protected by VT-d in preboot environment,
+ but disable BME and tear down any Thunderbolt DMAR tables at ExitBootSer=
vices()
+
+ @param[in] Event - A pointer to the Event that triggered the callbac=
k.
+ @param[in] Context - A pointer to private data registered with the cal=
lback function.
+**/
+VOID
+EFIAPI
+TbtDisableBmeCallBackFunction (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+/**
+ TBT Security SetDmarOptIn CallBackFunction
+
+ A new security feature will be supported to protect against Physical DMA=
attacks over Thunderbolt connects.
+ In order to do this, they need a new flag added to the DMAR tables that =
a DMA is only permitted into RMRR at ExitBootServices(). With this flag av=
ailable, OS can then Bug Check if any DMA is requested outside of the RMRR =
before OS supported device drivers are started.
+ ReadyToBoot callback routine to update DMAR BIT2
+ Bit definition: DMA_CONTROL_GUARANTEE
+ If Set, the platform supports blocking all DMA outside of the regions de=
fined in the RMRR structures from ExitBootServices() until OS supported dev=
ice drivers are started.
+
+ @param[in] Event - A pointer to the Event that triggered the callbac=
k.
+ @param[in] Context - A pointer to private data registered with the cal=
lback function.
+**/
+VOID
+EFIAPI
+SetDmarOptInCallBackFunction (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+
+/**
+ The function install DisableBme protocol for TBT Shell validation
+**/
+VOID
+InstallDisableBmeProtocol (
+ VOID
+ );
+
+/**
+ Get or set Thunderbolt(TM) security mode
+
+ @param[in] DelayTime - The delay time after do ForcePwr
+ @param[in] SecurityMode - TBT Security Level
+ @param[in] Gpio3ForcePwrEn - Force GPIO to power on or not
+ @param[in] DTbtController - Enable/Disable DTbtController
+ @param[in] MaxControllerNumber - Number of contorller
+ @param[in] Action - 0 =3D get, 1 =3D set
+
+ @retval - Return security level
+**/
+UINT8
+EFIAPI
+GetSetSecurityMode (
+ IN UINTN DelayTime,
+ IN UINT8 SecurityMode,
+ IN UINT8 Gpio3ForcePwrEn,
+ IN UINT8 *DTbtController,
+ IN UINT8 MaxControllerNumber,
+ IN UINT8 Action
+);
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Libr=
ary/PeiCheckIommuSupportLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Featur=
es/Tbt/Include/Library/PeiCheckIommuSupportLib.h
new file mode 100644
index 0000000000..e069914cb4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Pei=
CheckIommuSupportLib.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for the PeiCheckIommuSupport library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+#define _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
+/**
+ Check Iommu Ability base on SKU type, CSME FW type, Vtd and setup option=
s.
+**/
+VOID
+PeiCheckIommuSupport (
+ VOID
+ );
+
+#endif // _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Libr=
ary/PeiTbtPolicyLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/I=
nclude/Library/PeiTbtPolicyLib.h
new file mode 100644
index 0000000000..498f684696
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Pei=
TbtPolicyLib.h
@@ -0,0 +1,43 @@
+/** @file
+ Prototype of the PeiTbtPolicyLib library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_TBT_POLICY_LIB_H_
+#define _PEI_TBT_POLICY_LIB_H_
+
+/**
+ Install Tbt Policy
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b=
uffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallPeiTbtPolicy (
+ VOID
+ );
+
+/**
+ Update PEI TBT Policy Callback
+**/
+VOID
+EFIAPI
+UpdatePeiTbtPolicyCallback (
+ VOID
+ );
+
+/**
+ Print PEI TBT Policy
+**/
+VOID
+EFIAPI
+TbtPrintPeiPolicyConfig (
+ VOID
+ );
+#endif // _DXE_TBT_POLICY_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Libr=
ary/PeiTbtTaskDispatchLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Features=
/Tbt/Include/Library/PeiTbtTaskDispatchLib.h
new file mode 100644
index 0000000000..b1370e4064
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Pei=
TbtTaskDispatchLib.h
@@ -0,0 +1,61 @@
+/** @file
+ PEI TBT Task Dispatch library Header file
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_TBT_TASK_DISPATCH_LIB_H__
+#define __PEI_TBT_TASK_DISPATCH_LIB_H__
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Ppi/PeiTbtPolicy.h>
+
+typedef
+EFI_STATUS
+(EFIAPI *TBT_TASK) (
+ PEI_TBT_POLICY *PeiTbtConfig
+);
+
+typedef enum {
+ TBT_NULL, ///< All policy flags turned off.
+ TBT_NORMAL =3D (1 << 0), ///< Execute TBT function on cold reset.
+ TBT_S3 =3D (1 << 1), ///< Execute TBT function on S3 exit.
+ TBT_S4 =3D (1 << 2), ///< Execute TBT function on S4 exit.
+ TBT_ALL =3D MAX_UINTN ///< Execute TBT function always.
+} TBT_BOOT_MODE;
+
+typedef struct {
+ TBT_TASK TbtTask; ///< Ptr to function to execute, with par=
ameter list.
+ TBT_BOOT_MODE TbtBootModeFlag; ///< Call table base on TbtBootModeFlag
+ CHAR8 *String; ///< Output string describing this task.
+} TBT_CALL_TABLE_ENTRY;
+
+/**
+ Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE
+**/
+TBT_BOOT_MODE
+TbtGetBootMode (
+ VOID
+);
+
+/**
+ TbtTaskDistpach: Dispatch the TBT tasks according to TBT_CALL_TABLE_ENTRY
+
+ @param[in] TBT_CALL_TABLE_ENTRY TbtCallTable
+
+**/
+VOID
+TbtTaskDistpach (
+ IN TBT_CALL_TABLE_ENTRY *TbtCallTable
+);
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Libr=
ary/TbtCommonLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Incl=
ude/Library/TbtCommonLib.h
new file mode 100644
index 0000000000..8d61d0623b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Tbt=
CommonLib.h
@@ -0,0 +1,261 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_COMMON_LIB_H_
+#define _TBT_COMMON_LIB_H_
+
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+
+#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_RP 0 // @todo : Update when on=
ce finalized
+#define DEFAULT_PCI_BUS_NUMBER_ITBT_RP 0
+#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_RP 0x07
+
+#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_DMA0 0
+#define DEFAULT_PCI_BUS_NUMBER_ITBT_DMA0 0
+#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_DMA0 0x0D
+#define DEFAULT_PCI_FUNCTION_NUMBER_ITBT_DMA0 0x02
+
+#define DTBT_CONTROLLER 0x00
+#define DTBT_TYPE_PCH 0x01
+#define DTBT_TYPE_PEG 0x02
+#define ITBT_CONTROLLER 0x80
+#define TBT2PCIE_ITBT_R 0xEC
+#define PCIE2TBT_ITBT_R 0xF0
+#define TBT2PCIE_DTBT_R 0x548
+#define PCIE2TBT_DTBT_R 0x54C
+
+#define INVALID_RP_CONTROLLER_TYPE 0xFF
+
+//
+// Thunderbolt FW OS capability
+//
+#define NO_OS_NATIVE_SUPPORT 0
+#define OS_NATIVE_SUPPORT_ONLY 1
+#define OS_NATIVE_SUPPORT_RTD3 2
+
+#define ITBT_SAVE_STATE_OFFSET BIT4 // Bits 4-7 is for ITBT (HIA0/1/2/Res=
erved)
+#define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 i=
s in use)
+/**
+Get Tbt2Pcie Register Offset
+
+@param[in] Type ITBT (0x80) or DTBT (0x00)
+@retval Register Register Variable
+**/
+
+#define GET_TBT2PCIE_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function=
, RegisterAddress) \
+ if (Type =3D=3D ITBT_CONTROLLER) { \
+ RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func=
tion, TBT2PCIE_ITBT_R); \
+ } else { \
+ RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func=
tion, TBT2PCIE_DTBT_R); \
+ }
+
+/**
+Get Pcie2Tbt Register Offset
+
+@param[in] Type ITBT (0x80) or DTBT (0x00)
+@retval Register Register Variable
+**/
+
+#define GET_PCIE2TBT_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function=
, RegisterAddress) \
+ if (Type =3D=3D ITBT_CONTROLLER) { \
+ RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func=
tion, PCIE2TBT_ITBT_R); \
+ } else { \
+ RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func=
tion, PCIE2TBT_DTBT_R); \
+ }
+
+#define PCIE2TBT_VLD_B BIT0
+#define TBT2PCIE_DON_R BIT0
+#define TBT_MAIL_BOX_DELAY (100*1000)
+#define TBT_5S_TIMEOUT 50
+#define TBT_1S_TIMEOUT 10
+#define TBT_3S_TIMEOUT 30
+
+#define PCIE2TBT_GO2SX (0x02 << 1)
+#define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1)
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1)
+#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1)
+#define PCIE2TBT_OS_UP (0x06 << 1)
+#define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1)
+#define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1)
+#define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1)
+#define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1)
+#define PCIE2TBT_BOOT_ON (0x18 << 1)
+#define PCIE2TBT_BOOT_OFF (0x19 << 1)
+#define PCIE2TBT_USB_ON (0x19 << 1)
+#define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1)
+#define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1)
+#define PCIE2TBT_POWER_CYCLE (0x1C << 1)
+#define PCIE2TBT_PREBOOTACL (0x1E << 1)
+#define CONNECT_TOPOLOGY_COMMAND (0x1F << 1)
+
+#define RESET_HR_BIT BIT0
+#define ENUMERATE_HR_BIT BIT1
+#ifndef AUTO
+#define AUTO 0x0
+#endif
+
+//
+//Thunder Bolt Device IDs
+//
+
+//
+// Alpine Ridge HR device IDs
+//
+#define AR_HR_2C 0x1576
+#define AR_HR_4C 0x1578
+#define AR_XHC 0x15B5
+#define AR_XHC_4C 0x15B6
+#define AR_HR_LP 0x15C0
+//
+// Alpine Ridge C0 HR device IDs
+//
+#define AR_HR_C0_2C 0x15DA
+#define AR_HR_C0_4C 0x15D3
+//
+// Titan Ridge HR device IDs
+//
+#define TR_HR_2C 0x15E7
+#define TR_HR_4C 0x15EA
+//
+//End of Thunderbolt(TM) Device IDs
+//
+
+typedef struct _DEV_ID {
+ UINT8 Segment;
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+} DEV_ID;
+
+//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf
+//@todo should refactor this to only be present in that driver
+//@todo also definitions like this should never be in a .h file anyway
+//@todo this is a quick hack to get things compiling for now
+#ifdef __GNUC__
+#pragma GCC diagnostic warning "-Wunused-variable"
+#endif
+
+/**
+Based on the Security Mode Selection, BIOS drives FORCE_PWR.
+
+@param[in] GpioNumber
+@param[in] Value
+**/
+VOID
+ForceDtbtPower(
+ IN UINT32 GpioNumber,
+ IN BOOLEAN Value
+);
+
+/**
+ Get Security Level.
+ @param[in] Type ITBT (0x80) or DTBT (0x00)
+ @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
+ @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
+ @param[in] Function Function number for HIA (ITBT) or Host Router (DTB=
T)
+ @param[in] Timeout Time out with 100 ms garnularity
+**/
+UINT8
+GetSecLevel (
+ IN BOOLEAN Type,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 Command,
+ IN UINT32 Timeout
+ );
+
+/**
+ Set Security Level.
+ @param[in] Data Security State
+ @param[in] Type ITBT (0x80) or DTBT (0x00)
+ @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
+ @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
+ @param[in] Function Function number for HIA (ITBT) or Host Router (DTB=
T)
+ @param[in] Timeout Time out with 100 ms garnularity
+**/
+BOOLEAN
+SetSecLevel (
+ IN UINT8 Data,
+ IN BOOLEAN Type,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 Command,
+ IN UINT32 Timeout
+ );
+
+/**
+Execute TBT Mail Box Command
+
+@param[in] Command TBT Command
+@param[in] Type ITBT (0x80) or DTBT (0x00)
+@param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
+@param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
+@param[in] Function Function number for HIA (ITBT) or Host Router (DTBT)
+@param[in] Timeout Time out with 100 ms garnularity
+@Retval true if command executes succesfully
+**/
+BOOLEAN
+TbtSetPcie2TbtCommand(
+ IN UINT8 Command,
+ IN BOOLEAN Type,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT32 Timeout
+);
+/**
+ Check connected TBT controller is supported or not by DeviceID
+
+ @param[in] DeviceID DeviceID of of TBT controller
+
+
+ @retval TRUE Valid DeviceID
+ @retval FALSE Invalid DeviceID
+**/
+
+BOOLEAN
+IsTbtHostRouter (
+ IN UINT16 DeviceID
+ );
+
+/**
+ Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Po=
rt physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device =
number.
+ @param[out] RpFun Return corresponding root port functio=
n number.
+
+ @retval EFI_SUCCESS Root port device and function is retri=
eved
+**/
+EFI_STATUS
+EFIAPI
+GetDTbtRpDevFun(
+ IN BOOLEAN Type,
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFunc
+ );
+
+/**
+ Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
+ @param[in] CommandOffsetAddress Tbt2Pcie Register Address
+ @param[in] TimeOut Time out with 100 ms garnularity
+ @param[in] Tbt2PcieDone Wait condition (wait for Bit to Cl=
ear/Set)
+ @param[out] *Tbt2PcieValue Function Register value
+**/
+BOOLEAN
+InternalWaitforCommandCompletion (
+ IN UINT64 CommandOffsetAddress,
+ IN UINT32 TimeOut,
+ IN BOOLEAN Tbt2PcieDone,
+ OUT UINT32 *Tbt2PcieValue
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Ppi/=
PeiTbtPolicy.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/=
Ppi/PeiTbtPolicy.h
new file mode 100644
index 0000000000..1d42c4c578
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtP=
olicy.h
@@ -0,0 +1,31 @@
+/** @file
+TBT PEI Policy
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_TBT_POLICY_H_
+#define _PEI_TBT_POLICY_H_
+
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(push, 1)
+
+#define PEI_TBT_POLICY_REVISION 1
+
+/**
+ TBT PEI configuration\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct _PEI_TBT_POLICY {
+ DTBT_COMMON_CONFIG DTbtCommonConfig; =
///< dTbt Common Configuration
+ DTBT_CONTROLLER_CONFIG DTbtControllerConfig [MAX_DTBT_CONTROLLER_NUMBER]=
; ///< dTbt Controller Configuration
+} PEI_TBT_POLICY;
+
+#pragma pack(pop)
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Priv=
ate/Library/PeiDTbtInitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Feature=
s/Tbt/Include/Private/Library/PeiDTbtInitLib.h
new file mode 100644
index 0000000000..450d183c7f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Lib=
rary/PeiDTbtInitLib.h
@@ -0,0 +1,130 @@
+/** @file
+ PEI DTBT Init Dispatch library Header file
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_DTBT_INIT_LIB_H__
+#define __PEI_DTBT_INIT_LIB_H__
+
+#include <Private/Library/PeiTbtCommonInitLib.h>
+#include <Library/PeiTbtTaskDispatchLib.h>
+
+extern TBT_CALL_TABLE_ENTRY DTbtCallTable[];
+
+/**
+ Get Thunderbolt(TM) (TBT) PEI Policy Data.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtGetPeiTbtPolicyData (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Toggle related GPIO pin for DTBT.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtToggleGPIO (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ set tPCH25 Timing to 10 ms for DTBT.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSetTPch25Timing (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Do ForcePower for DTBT Controller
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtForcePower (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Clear VGA Registers for DTBT.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtClearVgaRegisters (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Exectue Mail box command "Boot On".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtBootOn (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Exectue Mail box command "USB On".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtUsbOn (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Exectue Mail box command "Sx Exit".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSxExitFlow (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Priv=
ate/Library/PeiTbtCommonInitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Fe=
atures/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h
new file mode 100644
index 0000000000..aae88b2992
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Lib=
rary/PeiTbtCommonInitLib.h
@@ -0,0 +1,51 @@
+/** @file
+ PEI TBT Common Init Dispatch library Header file
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_TBT_COMMON_INIT_LIB_H__
+#define __PEI_TBT_COMMON_INIT_LIB_H__
+
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiTbtTaskDispatchLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TbtCommonLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/PmcLib.h>
+#include <PlatformNvRamHookLib.h>
+
+BOOLEAN
+IsHostRouterPresentBeforeSleep(
+IN UINT8 ControllerType,
+IN UINT8 Controller
+);
+
+VOID
+TbtSetSxMode(
+IN BOOLEAN Type,
+IN UINT8 Bus,
+IN UINT8 Device,
+IN UINT8 Function,
+IN UINT8 TbtBootOn
+);
+
+VOID
+TbtClearVgaRegisters(
+IN UINTN Segment,
+IN UINTN Bus,
+IN UINTN Device,
+IN UINTN Function
+);
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Prot=
ocol/DisableBmeProtocol.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/T=
bt/Include/Protocol/DisableBmeProtocol.h
new file mode 100644
index 0000000000..b64973db68
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Di=
sableBmeProtocol.h
@@ -0,0 +1,36 @@
+/** @file
+ Definitions for DisableBmeProtocol
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DISABLE_TBT_BME_PROTOCOL_H_
+#define _DISABLE_TBT_BME_PROTOCOL_H_
+
+typedef struct EFI_DISABLE_BME_PROTOCOL EFI_DISABLE_TBT_BME_PROTOCOL;
+
+/**
+ This is for disable TBT BME bit under shell environment
+
+ @param[in] Event - A pointer to the Event that triggered the callbac=
k.
+ @param[in] Context - A pointer to private data registered with the cal=
lback function.
+**/
+typedef
+VOID
+(EFIAPI *DISABLE_BUS_MASTER_ENABLE) (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+
+struct EFI_DISABLE_BME_PROTOCOL {
+ DISABLE_BUS_MASTER_ENABLE DisableBme;
+};
+
+extern EFI_GUID gDxeDisableTbtBmeProtocolGuid;
+
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Prot=
ocol/DxeTbtPolicy.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inc=
lude/Protocol/DxeTbtPolicy.h
new file mode 100644
index 0000000000..0528c5ea3d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Dx=
eTbtPolicy.h
@@ -0,0 +1,137 @@
+/** @file
+TBT DXE Policy
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_TBT_POLICY_H_
+#define _DXE_TBT_POLICY_H_
+
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(push, 1)
+
+#define DXE_TBT_POLICY_REVISION 1
+
+//
+// TBT Common Data Structure
+//
+typedef struct _TBT_COMMON_CONFIG{
+ /**
+ TBT Security Level
+ <b>0: SL0 No Security</b>, 1: SL1 User Authorization, 2: SL2 Secure Co=
nnect, 3: SL3 Display Port and USB
+ **/
+ UINT32 SecurityMode : 3;
+ /**
+ BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH=
GPIOs
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 Gpio5Filter : 1;
+ /**
+ WA for TR A0 OS_UP Command, it is only needed for TR A0 stepping
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TrA0OsupWa : 1;
+ /**
+ Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtWakeupSupport : 1;
+ /**
+ SMI TBT enumeration
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtHotSMI : 1;
+ /**
+ Notify PCIe RP after Hot-Plug/Hot-Unplug occurred.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtHotNotify : 1;
+ /**
+ CLK REQ for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtSetClkReq : 1;
+ /**
+ ASPM setting for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: L0s, 2: L1, 3: L0sL1
+ **/
+ UINT32 TbtAspm : 2;
+ /**
+ L1 SubState for for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: L1.1, 2: L1.1 & L1.2
+ **/
+ UINT32 TbtL1SubStates : 2;
+ /**
+ LTR for for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtLtr : 1;
+ /**
+ PTM for for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtPtm : 1;
+ /**
+ TBT Dynamic AC/DC L1.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtAcDcSwitch : 1;
+ /**
+ TBT RTD3 Support.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 Rtd3Tbt : 1;
+ /**
+ TBT ClkReq for RTD3 Flow.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 Rtd3TbtClkReq : 1;
+ /**
+ TBT Win10support for Tbt FW execution mode.
+ <b>0: Disabled</b>, 1: Native, 2: Native + RTD3
+ **/
+ UINT32 Win10Support : 2;
+ /**
+ TbtVtdBaseSecurity
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtVtdBaseSecurity: 1;
+ /**
+ Control Iommu behavior in pre-boot
+ <b>0: Disabled Iommu</b>, 1: Enable Iommu, Disable exception list, 2: =
Enable Iommu, Enable exception list
+ **/
+ UINT32 ControlIommu : 3;
+ UINT32 Rsvd0 : 8; ///< Reserved bits
+ UINT16 Rtd3TbtClkReqDelay;
+ UINT16 Rtd3TbtOffDelay;
+} TBT_COMMON_CONFIG;
+
+//
+// dTBT Resource Data Structure
+//
+typedef struct _DTBT_RESOURCE_CONFIG{
+ UINT8 DTbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe RP =
that connect to dTBT Host Router
+ UINT16 DTbtPcieMemRsvd; ///< Preserve MEM resource for PCIe RP =
that connect to dTBT Host Router
+ UINT8 DTbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM resource=
for PCIe RP that connect to dTBT Host Router
+ UINT16 DTbtPciePMemRsvd; ///< Preserve PMEM resource for PCIe RP=
that connect to dTBT Host Router
+ UINT8 DTbtPciePMemAddrRngMax; ///< Alignment of Preserve PMEM resourc=
e for PCIe RP that connect to dTBT Host Router
+ UINT8 Reserved[1]; ///< Reserved for DWORD alignment
+} DTBT_RESOURCE_CONFIG;
+
+/**
+ TBT DXE configuration\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct _DXE_TBT_POLICY_PROTOCOL {
+ TBT_COMMON_CONFIG TbtCommonConfig; =
///< Tbt Common Information
+ DTBT_RESOURCE_CONFIG DTbtResourceConfig[MAX_DTBT_CONTROLLER_NUMBER]; =
///< dTbt Resource Configuration
+} DXE_TBT_POLICY_PROTOCOL;
+
+#pragma pack(pop)
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Prot=
ocol/TbtNvsArea.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Inclu=
de/Protocol/TbtNvsArea.h
new file mode 100644
index 0000000000..c2a366f3b1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Tb=
tNvsArea.h
@@ -0,0 +1,50 @@
+/** @file
+ This file defines the TBT NVS Area Protocol.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_NVS_AREA_H_
+#define _TBT_NVS_AREA_H_
+
+//
+// Platform NVS Area definition
+//
+#include <TbtNvsAreaDef.h>
+
+//
+// Includes
+//
+#define TBT_NVS_DEVICE_ENABLE 1
+#define TBT_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+typedef struct _TBT_NVS_AREA_PROTOCOL TBT_NVS_AREA_PROTOCOL;
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gTbtNvsAreaProtocolGuid;
+
+/**
+ Making any TBT_NVS_AREA structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+ <b>Revision 1</b>: - Initial version.\n
+ <b>Revision 2</b>: - Adding TBT NVS AREA Revision, Deprecated DTbtCont=
rollerEn0, DTbtControllerEn1.\n
+**/
+#define TBT_NVS_AREA_REVISION 2
+
+//
+// Platform NVS Area Protocol
+//
+typedef struct _TBT_NVS_AREA_PROTOCOL {
+ TBT_NVS_AREA *Area;
+} TBT_NVS_AREA_PROTOCOL;
+
+#endif // _TBT_NVS_AREA_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtB=
oardInfo.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtB=
oardInfo.h
new file mode 100644
index 0000000000..e595867d37
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInf=
o.h
@@ -0,0 +1,23 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_INFO_GUID_H_
+#define _TBT_INFO_GUID_H_
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(1)
+//
+// TBT Info HOB
+//
+typedef struct _TBT_INFO_HOB {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ DTBT_COMMON_CONFIG DTbtCommonConfig; =
///< dTbt Common Configuration
+ DTBT_CONTROLLER_CONFIG DTbtControllerConfig [MAX_DTBT_CONTROLLER_NUMBER]=
; ///< dTbt Controller Configuration
+} TBT_INFO_HOB;
+#pragma pack()
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtN=
vsAreaDef.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Tbt=
NvsAreaDef.h
new file mode 100644
index 0000000000..e84a0abd94
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtNvsAreaD=
ef.h
@@ -0,0 +1,68 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ //
+ // Define TBT NVS Area operation region.
+ //
+
+#ifndef _TBT_NVS_AREA_DEF_H_
+#define _TBT_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+ UINT8 ThunderboltSmiFunction; ///< Offset 0 Th=
underbolt(TM) SMI Function Number
+ UINT8 ThunderboltHotSmi; ///< Offset 1 SM=
I on Hot Plug for TBT devices
+ UINT8 TbtWin10Support; ///< Offset 2 Tb=
tWin10Support
+ UINT8 TbtGpioFilter; ///< Offset 3 Gp=
io filter to detect USB Hotplug event
+ UINT8 ThunderboltHotNotify; ///< Offset 4 No=
tify on Hot Plug for TBT devices
+ UINT8 TbtSelector; ///< Offset 5 Th=
underbolt(TM) Root port selector
+ UINT8 WAKFinished; ///< Offset 6 WA=
K Finished
+ UINT8 DiscreteTbtSupport; ///< Offset 7 Th=
underbolt(TM) support
+ UINT8 TbtAcpiRemovalSupport; ///< Offset 8 Tb=
tAcpiRemovalSupport
+ UINT32 TbtFrcPwrEn; ///< Offset 9 Tb=
tFrcPwrEn
+ UINT32 TbtFrcPwrGpioNo0; ///< Offset 13 Tb=
tFrcPwrGpioNo
+ UINT8 TbtFrcPwrGpioLevel0; ///< Offset 17 Tb=
tFrcPwrGpioLevel
+ UINT32 TbtCioPlugEventGpioNo0; ///< Offset 18 Tb=
tCioPlugEventGpioNo
+ UINT32 TbtPcieRstGpioNo0; ///< Offset 22 Tb=
tPcieRstGpioNo
+ UINT8 TbtPcieRstGpioLevel0; ///< Offset 26 Tb=
tPcieRstGpioLevel
+ UINT8 CurrentDiscreteTbtRootPort; ///< Offset 27 Cu=
rrent Port that has plug event
+ UINT8 RootportSelected0; ///< Offset 28 Ro=
ot port Selected by the User
+ UINT8 RootportSelected0Type; ///< Offset 29 Ro=
ot port Type
+ UINT8 RootportSelected1; ///< Offset 30 Ro=
ot port Selected by the User
+ UINT8 RootportSelected1Type; ///< Offset 31 Ro=
ot port Type
+ UINT8 RootportEnabled0; ///< Offset 32 Ro=
ot port Enabled by the User
+ UINT8 RootportEnabled1; ///< Offset 33 Ro=
ot port Enabled by the User
+ UINT32 TbtFrcPwrGpioNo1; ///< Offset 34 Tb=
tFrcPwrGpioNo
+ UINT8 TbtFrcPwrGpioLevel1; ///< Offset 38 Tb=
tFrcPwrGpioLevel
+ UINT32 TbtCioPlugEventGpioNo1; ///< Offset 39 Tb=
tCioPlugEventGpioNo
+ UINT32 TbtPcieRstGpioNo1; ///< Offset 43 Tb=
tPcieRstGpioNo
+ UINT8 TbtPcieRstGpioLevel1; ///< Offset 47 Tb=
tPcieRstGpioLevel
+ UINT8 TBtCommonGpioSupport; ///< Offset 48 Se=
t if Single GPIO is used for Multi/Different Controller Hot plug support
+ UINT8 CurrentDiscreteTbtRootPortType; ///< Offset 49 Ro=
ot Port type for which SCI Triggered
+ UINT8 TrOsup; ///< Offset 50 Ti=
tan Ridge Osup command
+ UINT8 TbtAcDcSwitch; ///< Offset 51 TB=
T Dynamic AcDc L1
+ UINT8 DTbtControllerEn0; ///< Offset 52 DT=
btController0 is enabled or not. @deprecated since revision 2
+ UINT8 DTbtControllerEn1; ///< Offset 53 DT=
btController1 is enabled or not. @deprecated since revision 2
+ UINT8 TbtAspm; ///< Offset 54 AS=
PM setting for all the PCIe device in TBT daisy chain.
+ UINT8 TbtL1SubStates; ///< Offset 55 L1=
SubState for for all the PCIe device in TBT daisy chain.
+ UINT8 TbtSetClkReq; ///< Offset 56 CL=
K REQ for all the PCIe device in TBT daisy chain.
+ UINT8 TbtLtr; ///< Offset 57 LT=
R for for all the PCIe device in TBT daisy chain.
+ UINT8 TbtPtm; ///< Offset 58 PT=
M for for all the PCIe device in TBT daisy chain.
+ UINT8 TbtWakeupSupport; ///< Offset 59 Se=
nd Go2SxNoWake or GoSxWake according to TbtWakeupSupport
+ UINT16 Rtd3TbtOffDelay; ///< Offset 60 Rt=
d3TbtOffDelay TBT RTD3 Off Delay
+ UINT8 TbtSxWakeSwitchLogicEnable; ///< Offset 62 Tb=
tSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB=
at Sx entry point. HW logic is required.
+ UINT8 Rtd3TbtSupport; ///< Offset 63 En=
able Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup.
+ UINT8 Rtd3TbtClkReq; ///< Offset 64 En=
able TBT RTD3 CLKREQ mask.
+ UINT16 Rtd3TbtClkReqDelay; ///< Offset 65 TB=
T RTD3 CLKREQ mask delay.
+ //
+ // Revision Field:
+ //
+ UINT8 TbtRevision; ///< Offset 67 Re=
vison of TbtNvsArea
+} TBT_NVS_AREA;
+
+#pragma pack(pop)
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtP=
olicyCommonDefinition.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt=
/Include/TbtPolicyCommonDefinition.h
new file mode 100644
index 0000000000..ae9d4f7a76
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCo=
mmonDefinition.h
@@ -0,0 +1,84 @@
+/** @file
+TBT Policy Common definition.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_POLICY_COMMON_H_
+#define _TBT_POLICY_COMMON_H_
+
+#include <Library/GpioLib.h>
+#include <IndustryStandard/Pci22.h>
+
+#define MAX_DTBT_CONTROLLER_NUMBER 2
+
+#define TYPE_PCIE 0x01
+#define TYPE_PEG 0x02
+
+#pragma pack(push, 1)
+
+//
+// dTBT Force Power GPIO Data Structure
+//
+typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG {
+ GPIO_PAD GpioPad; ///< GPIO Pad Number
+ BOOLEAN GpioLevel; ///< 0 =3D Active Low; 1 =3D Act=
ive High
+ UINT8 Reserved[3]; ///< Reserved for DWORD alignment
+} DTBT_FORCE_POWER_GPIO_CONFIG;
+
+//
+// dTBT CIO Plug Event GPIO Data Structure
+//
+typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG {
+ GPIO_PAD GpioPad; ///< GPIO Pad Number
+ UINT32 AcpiGpeSignature; ///< AcpiPlatform driver will ch=
ange the XTBT method to the _Lxx or _Exx that we assign in this item.
+ BOOLEAN AcpiGpeSignaturePorting; ///< 0 =3D No porting required(f=
or 2-tier GPI GPE event architecture), 1 =3D Porting required(for 1-tier GP=
I GPE event architecture)
+ UINT8 Reserved[3]; ///< Reserved for DWORD alignment
+} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG;
+
+//
+// dTBT PCIE Reset GPIO Data Structure
+//
+typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG {
+ GPIO_PAD GpioPad; ///< GPIO Pad Number
+ BOOLEAN GpioLevel; ///< 0 =3D Active Low; 1 =3D Act=
ive High
+ UINT8 Reserved[3]; ///< Reserved for DWORD alignment
+} DTBT_PCIE_RESET_GPIO_CONFIG;
+
+//
+// dTBT Controller Data Structure
+//
+typedef struct _DTBT_CONTROLLER_CONFIG {
+ UINT8 DTbtControllerEn; ///< Enable/Disable DT=
btController.
+ UINT8 Type; ///< 01-Pcie RP, 02- P=
EG,Reserved. <Specific according to Board Design>
+ UINT8 PcieRpNumber; ///< RP Number/ PEG Po=
rt (0,1,2) that connecet to dTBT controller. <Specific according to Board D=
esign>
+ DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The GPIO pin that=
can force dTBT Power On. <Specific according to Board Design>
+ DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that=
can generate Hot-Plug event. <Specific according to Board Design>
+ DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO pin that=
is use to perform Reset when platform enters to Sx, it is required for pla=
tforms where PCI_RST pin connected to Tbt is controlled with GPIO <Specific=
according to Board Design>
+ GPIO_PAD PdResetGpioPad; ///< PD HRESET GPIO Pa=
d Number
+ GPIO_PAD PdSxEntryGpioPad; ///< PD SX Entry GPIO =
Pad Number
+ GPIO_PAD PdSxAckGpioPad; ///< PD SX Ack GPIO Pa=
d Number
+ UINT8 Reserved[1]; ///< Reserved for DWOR=
D alignment
+} DTBT_CONTROLLER_CONFIG;
+
+//
+// dTBT Controller Data Structure
+//
+typedef struct _DTBT_COMMON_CONFIG {
+ UINT8 TbtBootOn; ///< Send BootOn Mailbox =
command when TbtBootOn is enabled.
+ UINT8 TbtUsbOn; ///< Send UsbOn Mailbox c=
ommand when TbtBootOn is enabled.
+ UINT8 Gpio3ForcePwr; ///< Force GPIO to power =
on or not
+ UINT16 Gpio3ForcePwrDly; ///< The delay time after=
do ForcePwr
+ BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT contro=
llers share the same GPIO pin <Specific according to Board Design>
+ BOOLEAN PcieRstSupport; ///< 0 =3D Not Support, 1=
=3D Supported. it is required for platforms where PCI_RST pin connected to=
Tbt is controlled with GPIO
+ UINT8 SecurityMode; ///< 0: SL0 No Security, =
1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and U=
SB
+ UINT8 ControlIommu; ///< Control Iommu behavi=
or in pre-boot, 0: Disabled Iommu, 1: Enable Iommu, Disable exception list,=
2: Enable Iommu, Enable exception list
+ UINT8 Reserved[3]; ///< Reserved for DWORD a=
lignment
+} DTBT_COMMON_CONFIG;
+
+#pragma pack(pop)
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.as=
l b/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl
new file mode 100644
index 0000000000..4e0ff03f5f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl
@@ -0,0 +1,112 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Define a Global region of ACPI NVS Region that may be used for any
+ // type of implementation. The starting offset and size will be fixed
+ // up by the System BIOS during POST. Note that the Size must be a word
+ // in size to be fixed up correctly.
+
+ OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
+ Field(GNVS,AnyAcc,Lock,Preserve)
+ {
+ //
+ // Miscellaneous Dynamic Registers:
+ //
+ Offset(0), OSYS, 16, // Offset(0), Operating System
+ Offset(2), SMIF, 8, // Offset(2), SMI Function Call (ASL to SM=
I via I/O Trap)
+ Offset(3), P80D, 32, // Offset(3), Port 80 Debug Port Value
+ Offset(7), PWRS, 8, // Offset(7), Power State (AC Mode =3D 1)
+ //
+ // Thermal Policy Registers:
+ //
+ Offset(8), DTSE, 8, // Offset(8), Digital Thermal Sensor Enable
+ Offset(9), DTSF, 8, // Offset(9), DTS SMI Function Call
+ //
+ // CPU Identification Registers:
+ //
+ Offset(10), APIC, 8, // Offset(10), APIC Enabled by SBIOS (APIC =
Enabled =3D 1)
+ Offset(11), TCNT, 8, // Offset(11), Number of Enabled Threads
+ //
+ // PCIe Hot Plug
+ //
+ Offset(12), OSCC, 8, // Offset(12), PCIE OSC Control
+ Offset(13), NEXP, 8, // Offset(13), Native PCIE Setup Value
+ //
+ // Global Variables
+ //
+ Offset(14), DSEN, 8, // Offset(14), _DOS Display Support Flag.
+ Offset(15), GPIC, 8, // Offset(15), Global IOAPIC/8259 Interrupt=
Mode Flag.
+ Offset(16), L01C, 8, // Offset(16), Global L01 Counter.
+ Offset(17), LTR1, 8, // Offset(17), Latency Tolerance Reporting =
Enable
+ Offset(18), LTR2, 8, // Offset(18), Latency Tolerance Reporting =
Enable
+ Offset(19), LTR3, 8, // Offset(19), Latency Tolerance Reporting =
Enable
+ Offset(20), LTR4, 8, // Offset(20), Latency Tolerance Reporting =
Enable
+ Offset(21), LTR5, 8, // Offset(21), Latency Tolerance Reporting =
Enable
+ Offset(22), LTR6, 8, // Offset(22), Latency Tolerance Reporting =
Enable
+ Offset(23), LTR7, 8, // Offset(23), Latency Tolerance Reporting =
Enable
+ Offset(24), LTR8, 8, // Offset(24), Latency Tolerance Reporting =
Enable
+ Offset(25), LTR9, 8, // Offset(25), Latency Tolerance Reporting =
Enable
+ Offset(26), LTRA, 8, // Offset(26), Latency Tolerance Reporting =
Enable
+ Offset(27), LTRB, 8, // Offset(27), Latency Tolerance Reporting =
Enable
+ Offset(28), LTRC, 8, // Offset(28), Latency Tolerance Reporting =
Enable
+ Offset(29), LTRD, 8, // Offset(29), Latency Tolerance Reporting =
Enable
+ Offset(30), LTRE, 8, // Offset(30), Latency Tolerance Reporting =
Enable
+ Offset(31), LTRF, 8, // Offset(31), Latency Tolerance Reporting =
Enable
+ Offset(32), LTRG, 8, // Offset(32), Latency Tolerance Reporting =
Enable
+ Offset(33), LTRH, 8, // Offset(33), Latency Tolerance Reporting =
Enable
+ Offset(34), LTRI, 8, // Offset(34), Latency Tolerance Reporting =
Enable
+ Offset(35), LTRJ, 8, // Offset(35), Latency Tolerance Reporting =
Enable
+ Offset(36), LTRK, 8, // Offset(36), Latency Tolerance Reporting =
Enable
+ Offset(37), LTRL, 8, // Offset(37), Latency Tolerance Reporting =
Enable
+ Offset(38), LTRM, 8, // Offset(38), Latency Tolerance Reporting =
Enable
+ Offset(39), LTRN, 8, // Offset(39), Latency Tolerance Reporting =
Enable
+ Offset(40), LTRO, 8, // Offset(40), Latency Tolerance Reporting =
Enable
+ Offset(41), OBF1, 8, // Offset(41), Optimized Buffer Flush and F=
ill
+ Offset(42), OBF2, 8, // Offset(42), Optimized Buffer Flush and F=
ill
+ Offset(43), OBF3, 8, // Offset(43), Optimized Buffer Flush and F=
ill
+ Offset(44), OBF4, 8, // Offset(44), Optimized Buffer Flush and F=
ill
+ Offset(45), OBF5, 8, // Offset(45), Optimized Buffer Flush and F=
ill
+ Offset(46), OBF6, 8, // Offset(46), Optimized Buffer Flush and F=
ill
+ Offset(47), OBF7, 8, // Offset(47), Optimized Buffer Flush and F=
ill
+ Offset(48), OBF8, 8, // Offset(48), Optimized Buffer Flush and F=
ill
+ Offset(49), OBF9, 8, // Offset(49), Optimized Buffer Flush and F=
ill
+ Offset(50), OBFA, 8, // Offset(50), Optimized Buffer Flush and F=
ill
+ Offset(51), OBFB, 8, // Offset(51), Optimized Buffer Flush and F=
ill
+ Offset(52), OBFC, 8, // Offset(52), Optimized Buffer Flush and F=
ill
+ Offset(53), OBFD, 8, // Offset(53), Optimized Buffer Flush and F=
ill
+ Offset(54), OBFE, 8, // Offset(54), Optimized Buffer Flush and F=
ill
+ Offset(55), OBFF, 8, // Offset(55), Optimized Buffer Flush and F=
ill
+ Offset(56), OBFG, 8, // Offset(56), Optimized Buffer Flush and F=
ill
+ Offset(57), OBFH, 8, // Offset(57), Optimized Buffer Flush and F=
ill
+ Offset(58), OBFI, 8, // Offset(58), Optimized Buffer Flush and F=
ill
+ Offset(59), OBFJ, 8, // Offset(59), Optimized Buffer Flush and F=
ill
+ Offset(60), OBFK, 8, // Offset(60), Optimized Buffer Flush and F=
ill
+ Offset(61), OBFL, 8, // Offset(61), Optimized Buffer Flush and F=
ill
+ Offset(62), OBFM, 8, // Offset(62), Optimized Buffer Flush and F=
ill
+ Offset(63), OBFN, 8, // Offset(63), Optimized Buffer Flush and F=
ill
+ Offset(64), OBFO, 8, // Offset(64), Optimized Buffer Flush and F=
ill
+ Offset(65), RTD3, 8, // Offset(65), Runtime D3 support.
+ Offset(66), S0ID, 8, // Offset(66), Low Power S0 Idle Enable
+ Offset(67), GBSX, 8, // Offset(67), Virtual GPIO button Notify S=
leep State Change
+ Offset(68), PSCP, 8, // Offset(68), P-state Capping
+ Offset(69), P2ME, 8, // Offset(69), Ps2 Mouse Enable
+ Offset(70), P2MK, 8, // Offset(70), Ps2 Keyboard and Mouse Enable
+ //
+ // Driver Mode
+ //
+ Offset(71), GIRQ, 32, // Offset(71), GPIO IRQ
+ Offset(75), PLCS, 8, // Offset(75), set PL1 limit when entering =
CS
+ Offset(76), PLVL, 16, // Offset(76), PL1 limit value
+ Offset(78), PB1E, 8, // Offset(78), 10sec Power button support
+ Offset(79), ECR1, 8, // Offset(79), Pci Delay Optimization Ecr
+ Offset(80), TBTS, 8, // Offset(80), Thunderbolt(TM) support
+ Offset(81), TNAT, 8, // Offset(81), TbtNativeOsHotPlug
+ Offset(82), TBSE, 8, // Offset(82), Thunderbolt(TM) Root port se=
lector
+ Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port se=
lector
+ }
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAre=
aDef.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef=
.h
new file mode 100644
index 0000000000..6755554c08
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
@@ -0,0 +1,118 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Define a Global region of ACPI NVS Region that may be used for any
+ // type of implementation. The starting offset and size will be fixed
+ // up by the System BIOS during POST. Note that the Size must be a word
+ // in size to be fixed up correctly.
+
+
+#ifndef _GLOBAL_NVS_AREA_DEF_H_
+#define _GLOBAL_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+ //
+ // Miscellaneous Dynamic Registers:
+ //
+ UINT16 OperatingSystem; ///< Offset 0 Op=
erating System
+ UINT8 SmiFunction; ///< Offset 2 SM=
I Function Call (ASL to SMI via I/O Trap)
+ UINT32 Port80DebugValue; ///< Offset 3 Po=
rt 80 Debug Port Value
+ UINT8 PowerState; ///< Offset 7 Po=
wer State (AC Mode =3D 1)
+ //
+ // Thermal Policy Registers:
+ //
+ UINT8 EnableDigitalThermalSensor; ///< Offset 8 Di=
gital Thermal Sensor Enable
+ UINT8 DigitalThermalSensorSmiFunction; ///< Offset 9 DT=
S SMI Function Call
+ //
+ // CPU Identification Registers:
+ //
+ UINT8 ApicEnable; ///< Offset 10 AP=
IC Enabled by SBIOS (APIC Enabled =3D 1)
+ UINT8 ThreadCount; ///< Offset 11 Nu=
mber of Enabled Threads
+ //
+ // PCIe Hot Plug
+ //
+ UINT8 PcieOSCControl; ///< Offset 12 PC=
IE OSC Control
+ UINT8 NativePCIESupport; ///< Offset 13 Na=
tive PCIE Setup Value
+ //
+ // Global Variables
+ //
+ UINT8 DisplaySupportFlag; ///< Offset 14 _D=
OS Display Support Flag.
+ UINT8 InterruptModeFlag; ///< Offset 15 Gl=
obal IOAPIC/8259 Interrupt Mode Flag.
+ UINT8 L01Counter; ///< Offset 16 Gl=
obal L01 Counter.
+ UINT8 LtrEnable[24]; ///< Offset 17 La=
tency Tolerance Reporting Enable
+ ///< Offset 18 La=
tency Tolerance Reporting Enable
+ ///< Offset 19 La=
tency Tolerance Reporting Enable
+ ///< Offset 20 La=
tency Tolerance Reporting Enable
+ ///< Offset 21 La=
tency Tolerance Reporting Enable
+ ///< Offset 22 La=
tency Tolerance Reporting Enable
+ ///< Offset 23 La=
tency Tolerance Reporting Enable
+ ///< Offset 24 La=
tency Tolerance Reporting Enable
+ ///< Offset 25 La=
tency Tolerance Reporting Enable
+ ///< Offset 26 La=
tency Tolerance Reporting Enable
+ ///< Offset 27 La=
tency Tolerance Reporting Enable
+ ///< Offset 28 La=
tency Tolerance Reporting Enable
+ ///< Offset 29 La=
tency Tolerance Reporting Enable
+ ///< Offset 30 La=
tency Tolerance Reporting Enable
+ ///< Offset 31 La=
tency Tolerance Reporting Enable
+ ///< Offset 32 La=
tency Tolerance Reporting Enable
+ ///< Offset 33 La=
tency Tolerance Reporting Enable
+ ///< Offset 34 La=
tency Tolerance Reporting Enable
+ ///< Offset 35 La=
tency Tolerance Reporting Enable
+ ///< Offset 36 La=
tency Tolerance Reporting Enable
+ ///< Offset 37 La=
tency Tolerance Reporting Enable
+ ///< Offset 38 La=
tency Tolerance Reporting Enable
+ ///< Offset 39 La=
tency Tolerance Reporting Enable
+ ///< Offset 40 La=
tency Tolerance Reporting Enable
+ UINT8 ObffEnable[24]; ///< Offset 41 Op=
timized Buffer Flush and Fill
+ ///< Offset 42 Op=
timized Buffer Flush and Fill
+ ///< Offset 43 Op=
timized Buffer Flush and Fill
+ ///< Offset 44 Op=
timized Buffer Flush and Fill
+ ///< Offset 45 Op=
timized Buffer Flush and Fill
+ ///< Offset 46 Op=
timized Buffer Flush and Fill
+ ///< Offset 47 Op=
timized Buffer Flush and Fill
+ ///< Offset 48 Op=
timized Buffer Flush and Fill
+ ///< Offset 49 Op=
timized Buffer Flush and Fill
+ ///< Offset 50 Op=
timized Buffer Flush and Fill
+ ///< Offset 51 Op=
timized Buffer Flush and Fill
+ ///< Offset 52 Op=
timized Buffer Flush and Fill
+ ///< Offset 53 Op=
timized Buffer Flush and Fill
+ ///< Offset 54 Op=
timized Buffer Flush and Fill
+ ///< Offset 55 Op=
timized Buffer Flush and Fill
+ ///< Offset 56 Op=
timized Buffer Flush and Fill
+ ///< Offset 57 Op=
timized Buffer Flush and Fill
+ ///< Offset 58 Op=
timized Buffer Flush and Fill
+ ///< Offset 59 Op=
timized Buffer Flush and Fill
+ ///< Offset 60 Op=
timized Buffer Flush and Fill
+ ///< Offset 61 Op=
timized Buffer Flush and Fill
+ ///< Offset 62 Op=
timized Buffer Flush and Fill
+ ///< Offset 63 Op=
timized Buffer Flush and Fill
+ ///< Offset 64 Op=
timized Buffer Flush and Fill
+ UINT8 Rtd3Support; ///< Offset 65 Ru=
ntime D3 support.
+ UINT8 LowPowerS0Idle; ///< Offset 66 Lo=
w Power S0 Idle Enable
+ UINT8 VirtualGpioButtonSxBitmask; ///< Offset 67 Vi=
rtual GPIO button Notify Sleep State Change
+ UINT8 PstateCapping; ///< Offset 68 P-=
state Capping
+ UINT8 Ps2MouseEnable; ///< Offset 69 Ps=
2 Mouse Enable
+ UINT8 Ps2KbMsEnable; ///< Offset 70 Ps=
2 Keyboard and Mouse Enable
+ //
+ // Driver Mode
+ //
+ UINT32 GpioIrqRoute; ///< Offset 71 GP=
IO IRQ
+ UINT8 PL1LimitCS; ///< Offset 75 se=
t PL1 limit when entering CS
+ UINT16 PL1LimitCSValue; ///< Offset 76 PL=
1 limit value
+ UINT8 TenSecondPowerButtonEnable; ///< Offset 78 10=
sec Power button support
+ UINT8 PciDelayOptimizationEcr; ///< Offset 79 Pc=
i Delay Optimization Ecr
+ UINT8 TbtSupport; ///< Offset 80 Th=
underbolt(TM) support
+ UINT8 TbtNativeOsHotPlug; ///< Offset 81 Tb=
tNativeOsHotPlug
+ UINT8 TbtSelector; ///< Offset 82 Th=
underbolt(TM) Root port selector
+ UINT8 TbtSelector1; ///< Offset 83 Th=
underbolt(TM) Root port selector
+} EFI_GLOBAL_NVS_AREA;
+
+#pragma pack(pop)
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h=
b/Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h
new file mode 100644
index 0000000000..15c7853aa2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h
@@ -0,0 +1,51 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ATTEMPT_USB_FIRST_H_
+#define _ATTEMPT_USB_FIRST_H_
+
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO {
+ UINT8 RevisonId; // Structure Revision ID
+ UINT8 HotkeyTriggered; // Hot key status
+} ATTEMPT_USB_FIRST_HOTKEY_INFO;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_VARIABLE {
+ UINT8 UsbBootPrior;
+} ATTEMPT_USB_FIRST_VARIABLE;
+#pragma pack()
+
+//
+// Volatile variable definition for Attempt USB first features
+//
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE {
+ UINT8 RevisonId; // Structure Revision ID
+ UINT8 UsbFirstEnable; // Attempt USB First is enabled or not
+} ATTEMPT_USB_FIRST_RUNTIME_VARIABLE;
+#pragma pack()
+
+//
+// Volatile variable definition for third party Default Enabling via UEFI =
Variable.
+//
+#pragma pack(1)
+typedef struct _ENABLE_CUSTOM_DEFAULTS{
+ UINT32 EnableCustomDefaults;
+} ENABLE_CUSTOM_DEFAULTS;
+#pragma pack()
+
+#define COENG_DEFAULTS_UNKNOWN 0
+#define COENG_DEFAULTS_SUPPORTED 1
+#define COENG_DEFAULTS_VAR_EXITS 2
+#define COENG_DEFAULTS_VAR_SET 4
+#define COENG_DEFAULTS_AVAILABLE (COENG_DEFAULTS_SUPPORTED | COENG_DEFAULT=
S_VAR_EXITS |COENG_DEFAULTS_VAR_SET)
+
+extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid;
+extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid;
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h b/Platfo=
rm/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h
new file mode 100644
index 0000000000..23b58fa1a2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h
@@ -0,0 +1,57 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPUSMM_H_
+#define _CPUSMM_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CPUSMM_GUID { 0x90d93e09, 0x4e91, 0x4b3d, { 0x8c, 0x77, 0xc8, 0x2f=
, 0xf1, 0xe, 0x3c, 0x81 }}
+#define CPUSMM_SETUP_NAME L"CpuSmm"
+
+#pragma pack(1)
+typedef struct {
+ UINT8 CpuSmmMsrSaveStateEnable;
+ UINT8 CpuSmmCodeAccessCheckEnable;
+ UINT8 CpuSmmUseDelayIndication;
+ UINT8 CpuSmmUseBlockIndication;
+ UINT8 CpuSmmUseSmmEnableIndication;
+ UINT8 CpuSmmProcTraceEnable;
+} CPU_SMM;
+#pragma pack()
+
+#ifndef OFFSET_OF
+#ifdef __GNUC__
+#if __GNUC__ >=3D 4
+#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
+#endif
+#endif
+#endif
+
+#ifndef OFFSET_OF
+#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
+#endif
+
+#define VERIFY_OFFSET(TYPE, Field, Offset) extern UINT8 _VerifyOffset##TYP=
E##Field[(OFFSET_OF(TYPE, Field) =3D=3D Offset) / (OFFSET_OF(TYPE, Field) =
=3D=3D Offset)]
+
+//
+// If TpmSupport/MorStae isn't in this offset, build failure (0 size array=
or divided by 0) will be generated.
+// Platform DSC file maps the two field to HII PCD so the offset value is =
critical.
+//
+VERIFY_OFFSET (CPU_SMM, CpuSmmMsrSaveStateEnable, 0x0);
+VERIFY_OFFSET (CPU_SMM, CpuSmmCodeAccessCheckEnable, 0x1);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseDelayIndication, 0x2);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseBlockIndication, 0x3);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseSmmEnableIndication, 0x4);
+VERIFY_OFFSET (CPU_SMM, CpuSmmProcTraceEnable, 0x5);
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+#ifdef __cplusplus
+}
+#endif
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfigura=
tions.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfiguratio=
ns.h
new file mode 100644
index 0000000000..21598e85d4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfigurations.h
@@ -0,0 +1,20 @@
+/** @file
+ This header file provides definitions of firmware configuration.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FIRMWARE_CONFIGURATION_H_
+#define _FIRMWARE_CONFIGURATION_H_
+
+typedef enum {
+ FwConfigDefault =3D 0,
+ FwConfigProduction,
+ FwConfigTest,
+ FwConfigMax
+} FW_CONFIG;
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h b/=
Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h
new file mode 100644
index 0000000000..cbd325fce6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h
@@ -0,0 +1,1766 @@
+/** @file
+Header file for GOP Configuration Library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GOP_CONFIG_LIB_H_
+#define _GOP_CONFIG_LIB_H_
+
+#include <Library/DebugLib.h>
+#include <Uefi/UefiBaseType.h>
+#pragma pack(1)
+#define GOP_CONFIG_VBT_REVISION 0xC1
+
+#define ChildStruct_MAX 8 ///< Maximum numbe=
r of child structures in VBT
+#define CompressionStruct_MAX 2 ///< Maximum numbe=
r of compression parameter structures in VBT.
+#define NO_DEVICE 0x00 ///< Defines a nul=
l display class.
+#define DISPLAY_PORT_ONLY 0x68C6 ///< Defines a dis=
play class of Integrated Display Port Only
+#define DISPLAY_PORT_HDMI_DVI_COMPATIBLE 0x60D6 ///< Defines a dis=
play class of Integrated DisplayPort with HDMI/DVI Compatible
+#define DISPLAY_PORT_DVI_COMPATIBLE 0x68D6 ///< Defines a dis=
play class of Integrated DisplayPort with DVI Compatible
+#define HDMI_DVI 0x60D2 ///< Defines a dis=
play class of Integrated HDMI/DVI
+#define DVI_ONLY 0x68D2 ///< Defines a dis=
play class of Integrated DVI Only
+#define MIPI_ONLY 0x1400
+#define eDP_ONLY 0x1806 ///< Defines a dis=
play class of eDP only
+#define AUX_CHANNEL_A 0x40
+#define AUX_CHANNEL_B 0x10
+#define AUX_CHANNEL_C 0x20
+#define AUX_CHANNEL_D 0x30
+#define NO_PORT 0x00 ///< Defines a out=
put port NA
+#define HDMI_B 0x01 ///< Defines a out=
put port HDMI-B
+#define HDMI_C 0x02 ///< Defines a out=
put port HDMI-C
+#define HDMI_D 0x03 ///< Defines a out=
put port HDMI-D
+#define HDMI_F 0x0E ///< Defines a out=
put port HDMI-D
+#define DISPLAY_PORT_A 0x0A ///< Defines a out=
put port DisplayPort A
+#define DISPLAY_PORT_B 0x07 ///< Defines a out=
put port DisplayPort B
+#define DISPLAY_PORT_C 0x08 ///< Defines a out=
put port DisplayPort C
+#define DISPLAY_PORT_D 0x09 ///< Defines a out=
put port DisplayPort D
+#define DISPLAY_PORT_E 0x0B ///< Defines a out=
put port DisplayPort E
+#define DISPLAY_PORT_F 0x0D ///< Defines a out=
put port DisplayPort F
+#define PORT_MIPI_A 0x15 ///< Mipi Port A
+#define PORT_MIPI_C 0x17 ///< Mipi Port C
+
+typedef struct {
+ UINT16 Dclk; // DClk in 10 KHz
+ UINT8 HActive; // HActive [7:0]
+ UINT8 HBlank; // HBlank [7:0]
+ UINT8 HA_HB_UpperNibble; // Upper nibble =3D HActive [11:8]
+ UINT8 VActive; // VActive [7:0]
+ UINT8 VBlank; // VBlank [7:0]
+ UINT8 VA_VB_UpperNibble; // Upper nibble =3D VActive [11:8]
+ UINT8 HSyncOffset; // HSync offset from blank start L=
SB
+ UINT8 HPulseWidth; // HSync Pulse Width, LSB
+ UINT8 VsyncOffset_VpulseWidth_LSB; // Bits 7:4 =3D VSync offset [3:0]
+ UINT8 HSO_HSPW_V_High; // Bits 7:6 =3D HSync Offset [9:8]
+ UINT8 HorImageSize; // Horizontal Image Size
+ UINT8 VerImageSize; // Vertical Image Size
+ UINT8 HIS_VIS_High; // UpperLmtH_V Upper limits of H. =
and V. image size
+ UINT8 HBorder; // Horizontal Border
+ UINT8 VBorder; // Vertical Border
+ UINT8 Flags; // Flags
+} DTD_STRUCTURE; // 18 Bytes
+
+typedef struct {
+ UINT16 XRes;
+ UINT16 YRes;
+ UINT32 SerialNo;
+ UINT8 Week;
+ UINT8 Year;
+} PID_DATA; // 10 Bytes
+
+//
+// VBT Header
+//
+/**
+ This structure defines the VBT Header.
+**/
+typedef struct {
+ UINT8 Product_String[20]; ///< "$VBT_Cannonlake" is the product string
+ UINT16 Version_Num; ///< Defines the VBT Header version number.
+ UINT16 Header_Size; ///< Defines the size of VBT Header.
+ UINT16 Table_Size; ///< Defines the size of complete VBT.
+ UINT8 Checksum; ///< Defines the checksum of entire VBT
+ UINT8 Reserved1; ///< Reserved field 1 of 1 byte.
+ UINT32 Bios_Data_Offset; ///< Defines the offset of VBT Data block.
+ UINT32 Aim_Data_Offset[4]; ///< 4 reserved pointers to VBT data blocks.
+} VBT_HEADER;
+
+/**
+ This structure defines the VBT BIOS Data Block Header
+**/
+typedef struct {
+ UINT8 BDB_Signature[16]; ///< Defines the Bios Data Block signature "=
BIOS_DATA_BLOCK".
+ UINT16 BDB_Version; ///< Defines the VBT (data) version.
+ UINT16 BDB_Header_Size; ///< Defines the size of VBT Bios data block=
header.
+ UINT16 BDB_Size; ///< Defines the size of Bios data block.
+} VBT_BIOS_DATA_HEADER;
+
+/**
+ This structure defines the BMP Signon Message and Copyright Message Stru=
cture
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines Block ID : 254
+ UINT16 BlockSize; ///< Defines the size of BMP Signon block.
+
+ UINT16 Bmp_BIOS_Size; ///< Defines the BIOS size 32k/48k/64k.
+ UINT8 BIOS_Type; ///< Defines the type of BIOS desktop or mob=
ile.
+ UINT8 RelStatus; ///< Defines the release status of the curre=
nt GOP driver.
+ UINT8 BIOS_HW; ///< Defines the Hardware i.e. Cannonlake.
+ UINT8 INT_HW; ///< Defines the integrated hardware support=
ed eDP/HDMI/DP.
+ UINT8 Build_Number[4]; ///< Defines the build number string.
+ UINT8 SignOn[155]; ///< Defines the sign on message.
+ UINT8 CopyRight[61]; ///< Defines the copyright message.
+} BMP_STRUCTURE_SIGNON;
+
+/**
+ This structure defines the BMP General Bits
+**/
+typedef struct {
+ UINT16 bmp_BIOS_CS; ///< Defines the start of BIOS code segment
+ UINT8 bmp_DOS_Boot_Mode; ///< Defines the mode number to set when D=
OS is boot
+ UINT8 bmp_BW_Percent; ///< Set percentage of total memory BW
+ UINT8 bmp_Popup_Mem_Size; ///< Default Popup memory size in KB
+ UINT8 bmp_Resize_PCI_BIOS; ///< BIOS size granularity in 0.5 KB
+ UINT8 Switch_CRT_To_DDC2; ///< Obsolete field: Is the CRT already sw=
itched to DDC2
+ UINT8 bmp_Allow_Config; ///< Bit 1 : 1, Enable aspect ratio for DOS
+ ///< Bit 0 : 1, Allow boot to DVI even if =
it is not attached.
+} BMPGEN;
+
+/**
+ This structure defines Block 254 (BMP structure)
+**/
+typedef struct {
+ BMP_STRUCTURE_SIGNON bmp_Signon_Message; ///< Instance of signon an=
d copyright message structure
+ BMPGEN bmp_General_Bytes; ///< Instance of BMP Gener=
al Bits structure.
+} BLOCK254_BMP_Structure;
+
+/**
+ This structure defines Block 1 (General Bytes Definitions)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID (1)
+ UINT16 BlockSize; ///< Defines the size of General bytes definitio=
n block.
+
+ /**
+ BMP General Bit Definitions 1\n
+ Bit 7 =3D DVO A color flip bit
+ =3D 0, No DVO A color flip
+ =3D 1, Flip DVO A color
+ Bits 6:4 =3D Clear screen (CLS) after Signon
+ =3D 000, No CLS
+ =3D 001, 0.5 sec pause and then CLS
+ =3D 010, 1.0 sec pause and then CLS
+ =3D 011, 1.5 sec pause and then CLS
+ =3D 100, 2.0 sec pause and then CLS
+ =3D 101, 2.5 sec pause and then CLS
+ =3D 110, 3.0 sec pause and then CLS
+ =3D 111, 3.5 sec pause and then CLS
+ Bit 3 =3D 1 Enable Display Signon
+ Bit 2 =3D 1 Enable Flex-aim Support
+ Bits 1:0 =3D Flat panel fitting enabling
+ =3D 00, Centering
+ =3D 01, Reserved
+ =3D 10, Aspect scaling
+ =3D 11, Fullscreen
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 PanelFitterEnabling:2;
+ UINT8 FlexAimSupportEnable:1;
+ UINT8 DisplaySignonEnable:1;
+ UINT8 ClearScreenTime:3;
+ UINT8 DvoAColorFlipEnable:1;
+ } Bits;
+ } bmp_Bits_1;
+
+ /**
+ BMP General Bit Definitions\n
+ Bit 7 =3D Hot plug support
+ =3D 0, Hot plug disabled
+ =3D 1, Hot plug enabled
+ Bit 6 =3D Dynamic CD clock feature
+ =3D 0, Dynamic CD clock feature is disabled
+ =3D 1, Dynamic CD clock feature is enabled
+ Bit 5 =3D Underscan support for VGA timings
+ Bit 4 =3D Disable SSC in Dual Display Twin Mode. (This field is obsolete=
now. Kept for VBIOS only.)
+ =3D 0, No
+ =3D 1, Yes
+ Bit 3 =3D LFP power state on override by 5f64h,08h
+ =3D 0, No Override
+ =3D 1, Override
+ Bit 2 =3D Internal LVDS SSC frequency. (This field is obsolete now. Kept=
for VBIOS only.)
+ =3D 0, 96/120MHz
+ =3D 1, 100MHz
+ Bit 1 =3D internal LVDS SSC (Spread Spectrum Clock) (This field is obsol=
ete now. Kept for VBIOS only.)
+ =3D 0, Disabled
+ =3D 1, Enabled
+ Bit 0 =3D KvmrSessionEnable.
+ =3D 0, Disabled
+ =3D 1, Enabled
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 KvmrSessionEnable:1;
+ UINT8 Reserved_1:5;
+ UINT8 DynamicCdClockEnable:1;
+ UINT8 HotPlugEnable:1;
+ } Bits;
+ } bmp_Bits_2;
+
+ /**
+ BMP General Bit Definitions 3\n
+ Bit 7 =3D Ignore strap status
+ =3D 0 Do not ignore
+ =3D 1 Ignore
+ Bit 6 =3D Panel Timing algorithm
+ =3D 0 Preferred timings
+ =3D 1 Best fit timings
+ Bit 5 Copy iLFP DTD to SDVO LVDS DTD
+ =3D 0 Don't copy DTD
+ =3D 1 Copy DTD to
+ Bit 4 =3D VBIOS normal/extd. DT mode
+ =3D 0 Normal mode
+ =3D 1 DUAL mode
+ Bit 3 =3D FDI RX Polarity
+ =3D 0 Normal
+ =3D 1 Inverted
+ Bit 2 =3D Enable 180 Degree Rotation
+ =3D 0 Disable
+ =3D 1 Enable
+ Bit 1 =3D Single DVI-I connector for CRT and DVI display: Obsolete field
+ =3D 0 Disabled
+ =3D 1 Enabled
+ Bit 0 =3D Smooth Vision
+ =3D 0 Disabled
+ =3D 1 Enabled
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 Reserved1:1;
+ UINT8 SingleDviiCrtConnector:1;
+ UINT8 Enable180DegRotation:1;
+ UINT8 FdiRxPolarity:1;
+ UINT8 Reserved2:4;
+ } Bits;
+ } bmp_Bits_3;
+
+ UINT8 Reserved; ///< Reserved field. It was Legacy_Monitor_Detect =
in previous platforms.
+
+ /**
+ Integrated display device support\n
+ Bits 7:6 =3D Reserved
+ Bit 5 =3D DP SSC Dongle Enable/Disable
+ Bit 4 =3D DP SSC Frequency. (This field is obsolete now. Kept for VBIOS =
only.)
+ =3D 0, 96 MHz
+ =3D 1, 100 MHz
+ Bit 3 =3D DP SSC Enable
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 2 =3D Integrated EFP support
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 1 =3D Integrated TV support. (This field is obsolete now. Kept for V=
BIOS only.)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 0 =3D Integrated CRT support: Obsolete field
+ =3D 0, Disable
+ =3D 1, Enable
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 CrtSupported:1;
+ UINT8 TvSupported:1;
+ UINT8 EfpSupported:1;
+ UINT8 DpSscEnable:1;
+ UINT8 DpSscFrequency:1;
+ UINT8 DpDongleSscEnable:1;
+ UINT8 Reserved1:2;
+ } Bits;
+ } Int_Displays_Support;
+} VBT_GENERAL1_INFO;
+
+/**
+ This defines the Structure of PRD Boot Table Entry
+**/
+typedef struct {
+ UINT8 AttachBits; ///< Bitmap representing the displays attached cur=
rently.
+ UINT8 BootDev_PipeA; ///< Bitmap representing the display to boot on Pi=
pe A.
+ UINT8 BootDev_PipeB; ///< Bitmap representing the display to boot on Pi=
pe B.
+} PRD_TABLE;
+
+/**
+ This defines the structure of Block 254 (PRD Boot Table/Child Device Lis=
t)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID (254)
+ UINT16 BlockSize; ///< Defines the size of Block 254
+
+ PRD_TABLE PRDTable[16]; ///< Defines the Child devic=
e list for enumerating child handles.
+ UINT16 PRD_Boot_Table_Number_Of_Entries; ///< Number of entries in ch=
ild device list.
+} PRD_BOOT_TABLE;
+
+/**
+ This defines the Structure for a CHILD_STRUCT (used for all the displays=
).
+**/
+typedef struct {
+ UINT16 DeviceHandle; ///< Unique ID indicating the group of dis=
play device (LFP/EFP1/EFP2/EFP3/EFP4).
+ UINT16 DeviceClass; ///< Indicates the class of display device.
+ UINT8 I2CSpeed; ///< Defines the I2C speed to be used for =
I2C transaction.
+ /**
+ Defines the DP on board redriver configuration.
+ BIT[7] : Reserved
+ BIT[6] : Is On Board DP Redriver Present
+ 0 : No
+ 1 : Yes
+ BIT[5:3] : On Board Redriver VSwing Level
+ 0 : Level 0
+ 1 : Level 1
+ 2 : Level 2
+ 3 : Level 3
+ Others : Reserved
+ BIT[2:0] : On Board Redriver PreEmph Level
+ 0 : Level 0
+ 1 : Level 1
+ 2 : Level 2
+ 3 : Level 3
+ Others : Reserved
+ **/
+ union{
+ UINT8 Value;
+ struct {
+ UINT8 OnBoardPreEmphLevel:3;
+ UINT8 OnBoardVSwingLevel:3;
+ UINT8 OnBoardRedriverPresent:1;
+ UINT8 Reserved:1;
+ } Bits;
+ } DpOnBoardRedriver;
+
+ /**
+ Defines the DP on dock redriver configuration.
+ BIT[7] : Reserved
+ BIT[6] : Is On Dock DP Redriver Present
+ 0 : No
+ 1 : Yes
+ BIT[5:3] : On Dock Redriver VSwing Level
+ 0 : Level 0
+ 1 : Level 1
+ 2 : Level 2
+ 3 : Level 3
+ Others : Reserved
+ BIT[2:0] : On Dock Redriver PreEmph Level
+ 0 : Level 0
+ 1 : Level 1
+ 2 : Level 2
+ 3 : Level 3
+ Others : Reserved
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 OnDockPreEmphLevel:3;
+ UINT8 OnDockVSwingLevel:3;
+ UINT8 OnDockRedriverPresent:1;
+ UINT8 Reserved:1;
+ } Bits;
+ } DpOnDockRedriver;
+
+ /**
+
+ Defines the HDMI level shifter configuration.
+ BIT[7:5] : Hdmi Maximum data rate
+ BIT[4:0] : Hdmi Level shifter value
+
+ **/
+ union{
+ UINT8 Value;
+ struct {
+ UINT8 HdmiLevelShifterValue:5;
+ UINT8 HdmiMaxDataRateBits:3;
+ } Bits;
+ } HdmiLevelShifterConfig;
+
+ UINT16 EFPDTDBufferPointer; ///< Pointer to the DTD timing to be used =
in case of edidless EFP.
+
+ /**
+ Defines the first set of flags.
+ BIT[7-4] : Reserved
+ BIT[3] : Dual pipe ganged display support
+ 0 : Display uses a single pipe/port
+ 1 : Display uses two distinct pipes/ports.
+ BIT[2] : Compression Method Select
+ 0 : Compression using picture parameter set (PPS)
+ 1 : Compression using Capability parameter set (CPS)
+ BIT[1] : Compression enable/disable for this display.
+ 0 : Disabled
+ 1 : Enabled
+ BIT[0] : EDID less EFP Enable
+ 0 : Enable support for EDID less EFP.
+ 1 : Disable support for EDID less EFP.
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 EdidlessEfpEnable:1;
+ UINT8 CompressionEnable:1;
+ UINT8 CompressionMethod:1;
+ UINT8 IsDualPortEnabled:1;
+ UINT8 Reserved:4;
+ } Bits;
+ } Flags0;
+
+ /**
+ Defines the compression index field for the display.
+ BITS[7-4] : Reserved
+ BITS[3-0] : Compression Structure index in the block 55.
+ 0x0 : Index 0 in block 55
+ 0x1 : Index 1 in block 55
+ 0xF : Not Applicable.
+ Others : Reserved
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 IndexInBlock55:4;
+ UINT8 Reserved:4;
+ } Bits;
+ } CompressionStructureIndex;
+
+ UINT8 SlaveDdiPort; ///< The DVO port number of slave DDI to b=
e used in case Flags0[3] =3D 1.
+
+ UINT8 Reserved_1; ///< Reserved and might be used in other p=
latforms.
+ UINT16 AddInOffset; ///< Obsolete field.
+ UINT8 DVOPort; ///< Specifies the port number of the disp=
lay device represented in the device class.
+ UINT8 I2CBus; ///< Specifies the GMBUS or I2C pin pair f=
or add in card.
+ UINT8 SlaveAddr; ///< Specifies the I2C address of the add =
in card.
+ UINT8 DDCBus; ///< Specifies the GMBUS pin pair for EDID=
read.
+ UINT16 TimingInfoPtr; ///< Pointer to the buffer where VBIOS sto=
res the EDID of device.
+ UINT8 DVOCfg; ///< Obsolete field.
+
+ /**
+ Flags 1\n
+ Bits 7:5 : Reserved
+ Bit 4 : HPD Sense Invert
+ 0 : Invert not required (default)
+ 1 : Invert required
+ Bit 3 : IBoost feature enable/disable.
+ 0 : IBoost feature is disabled.
+ 1 : IBoost feature is enabled.
+ Bit 2 : Hdmi 2.0 Motherboard Downsuppotred options
+ 0 : Motherboard Down chip not supported
+ 1 : Motherboard Down Chip Supported on the Board
+ Bit 1 : Lane Reversal feature.
+ 0 : Disable
+ 1 : Enable
+ Bit 0 : DP/HDMI routed to dock.
+ 0 : Disable
+ 1 : Enable
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 DockablePort:1;
+ UINT8 EnableLaneReversal:1;
+ UINT8 OnBoardLsPconDonglePresent:1;
+ UINT8 IBoostEnable:1;
+ UINT8 IsHpdInverted:1;
+ UINT8 Reserved:3;
+ } Bits;
+ } Flags_1;
+
+ UINT8 Compatibility; ///< Compatibility is used in VBIOS only. =
It was used before device class was defined.
+ UINT8 AUX_Channel; ///< Specifies the aux channel to be used =
for display port devices.
+ UINT8 Dongle_Detect; ///< Indicates whether dongle detect is en=
abled or not.
+ UINT8 Capabilities; ///< Bits 1-0 indicate pipe capabilities w=
hether display can be used on one pipe or both the pipes.
+ UINT8 DVOWiring; ///< Obsolete field.
+ UINT8 MipiBridgeType; ///< MIPI bridge type
+ UINT16 DeviceClassExtension; ///< Obsolete.
+ UINT8 DVOFunction; ///< Obsolete.
+
+ /**
+ Flags 2
+ Bits 7:4 : DP Port trace length from silicon to output port on the board
+ 0 : Default RVP length
+ 1 : Short trace length
+ 2 : Long trace length
+ Bits 3:2 : Reserved
+ Bit 1 : Indicates whether this port is Thunderbolt port or not.
+ 0 : No
+ 1 : Yes
+ Bit 0 : DP 2 lane RCR# 1024829: USB type C to enable 2 lane DP displ=
ay
+ 0 : Disable
+ 1 : Enable
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 UsbTypeCDongleEnabled:1; ///< Indicates whether this port i=
s USB type C.
+ UINT8 IsThunderboltPort:1; ///< Indicates whether this port i=
s Thunderbolt. (ICL+)
+ UINT8 Reserved:2; ///< Reserved for future use.
+ UINT8 DpPortTraceLength:4; ///< Dp port trace length from sil=
icon to port.
+ } Bits;
+ } Flags_2;
+ UINT8 DP2XGpioIndex; ///< GPIO index number for the USB type C.
+ UINT16 DP2XGpioNumber; ///< GPIO number for USB type C.
+
+ /**
+ IBoost magnitude field.
+ Bits 7:4 : DP Boost magnitude
+ 0 : 1
+ 1 : 3
+ 2 : 7
+ Others : Reserved for CML.
+ Bits 3:0 : HDMI Boost magnitude
+ 0 : 1
+ 1 : 3
+ 2 : 7
+ Others : Reserved.
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 DpEdpBoostMagnitude:4;
+ UINT8 HdmiBoostMagnitude:4;
+ } Bits;
+ } BoostMagnitude;
+} CHILD_STRUCT;
+
+/**
+ This structure defines Block 2 (General Bytes Definitions)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 2.
+ UINT16 BlockSize; ///< Defines the size of VBT General Inf=
o 2 Block.
+
+ UINT8 bmp_CRT_DDC_GMBUS_Pin; ///< Obsolete field: Selects the C=
RT DDC GMBUS pin pair.
+ UINT8 bmp_DPMS_Bits; ///< BMP DPMS Bit Definitions.
+ UINT16 bmp_Boot_Dev_Bits; ///< BMP Boot Device Bit Definitio=
ns.
+ UINT8 SizeChild_Struct; ///< Size of the ChildStruc struct=
ure.
+
+ CHILD_STRUCT Child_Struct[ChildStruct_MAX]; ///< This array defines al=
l the supported child structures.
+} VBT_GENERAL2_INFO;
+
+/**
+ This defines the structure of Block 3 (Original Display Toggle List)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 3
+ UINT16 BlockSize; ///< Defines the size of Original Displa=
y Toggle List Block
+ UINT8 bmp_Display_Detect; ///< Display must be attached or not
+} BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST;
+
+/**
+ This defines structure of a pointer table.
+**/
+typedef struct {
+ UINT16 Offset; ///< Defines the offset of the table from start of=
BIOS Data block.
+ UINT16 Size; ///< Defines the size of an entry of the table.
+} BMP_TABLE_PTR;
+
+/**
+ This structure defines Block 252 (SBIOS Hooks and BMP Table Pointers).
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 252.
+ UINT16 BlockSize; ///< Defines the size of SBIOS Hooks b=
lock.
+ UINT8 SbiosHooks[18]; ///< This array defines a series of SB=
IOS hooks. Each entry represents one hook.
+ BMP_TABLE_PTR BmpTablePtr[26]; ///< This array defines pointers to al=
l the important tables in the VBT.
+} BLOCK252_SBIOS_Hook;
+
+/**
+ This defines the structure of MMIO boot table entry
+**/
+typedef struct {
+ UINT32 Register; ///< Defines the MMIO offset of the register.
+ UINT32 Value; ///< Defines the default value of the register.
+} MMIO_BOOT_TABLE;
+
+/**
+ This structure defines Block 6 (MMIO Register Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 6
+ UINT16 BlockSize; ///< Defines the size of MMIO Regi=
ster Table block.
+ UINT16 RegTableId; ///< Defines the ID for MMIO regis=
ter table (0xFFFC).
+ UINT8 AccessFlag; ///< Defines the flag for data acc=
ess size (02 for 4 byte read/write).
+ MMIO_BOOT_TABLE MMIOBootTable[14]; ///< Array containing the MMIO reg=
ister table.
+ UINT16 TableEnd; ///< Special value describing End =
of table (0xFFFF).
+} BLOCK06_MMIO_REG_TABLE;
+
+/**
+ This structure defines Block 7 (IO SW Flag Register Table)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines Block ID (7).
+ UINT16 BlockSize; ///< Defines the size of IO SW Flag register t=
able block.
+ UINT16 RegTableId; ///< Defines the ID for IO SW Flag register ta=
ble (0xFFFE).
+ UINT8 GRIndexRegLsb; ///< Defines the read/write size. Value is 0xC=
E meaning 1 byte without mask.
+ UINT8 IOSWFlagReg; ///< Defines the offset for the IO SW Flag reg=
ister.
+ UINT8 Value; ///< Defines the data/value for the register.
+ UINT16 TableEnd; ///< Special value describing the end of table=
(0xFFFF).
+} BLOCK07_IOSWFLAG_REG_TABLE;
+
+/**
+ This structure defines the entry of SWF table.
+**/
+typedef struct {
+ UINT32 Register; ///< Defines the MMIO offset of the SWF register.
+ UINT32 Value; ///< Defines the default value for the SWF register.
+} SWF_TABLE;
+
+/**
+ This defines the structure of Block 8 (MMIO SW Flag Block).
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 8.
+ UINT16 BlockSize; ///< Defines the size of MMIO SWF register table=
block.
+ UINT16 RegTableId; ///< Defines the ID for MMIO SWF register table =
(0xFFFC).
+ UINT8 AccessFlag; ///< Defines the data access size. Value is 0x02=
meaning 4 bytes read/write.
+ SWF_TABLE SWFTable[7]; ///< Array containing the MMIO SWF register tabl=
e.
+ UINT16 TableEnd; ///< Special value describing end of table (0xFF=
FF).
+} BLOCK08_MMIOSWFLAG_REG_TABLE;
+
+/**
+ This structure defines the PSR feature table entry.
+**/
+typedef struct {
+ UINT8 SRD_Enables; ///< Defines PSR features such as full link =
enable/disable and whether aux is required to wake up.
+ UINT8 SRD_WaitTimes; ///< Defines lines to wait before link stand=
by and idle frames to wait before SRD enable.
+ UINT16 SRD_TP1_WakeupTime; ///< TP 1 wake up time in multiples of 100.
+ UINT16 SRD_TP2_WakeupTime; ///< TP2/TP3 wake up time in multiples of 100
+} PSR_FEATURE_TABLE;
+
+/**
+ This defines the structure of Block 9 (PSR Features Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the block ID : 9
+ UINT16 BlockSize; ///< Defines the size of PSR Fea=
ture block.
+ PSR_FEATURE_TABLE PSRFeatureTable[16]; ///< Array containing the PSR Fe=
ature table.
+} BLOCK09_PSR_FEATURE;
+
+/**
+ This structure defines an entry of Mode Removal table.
+**/
+typedef struct {
+ UINT16 XRes; ///< X resolution of the mode.
+ UINT16 YRes; ///< Y resolution of the mode.
+ UINT8 Bpp; ///< Bits per pixel of the mode.
+ UINT16 RRate; ///< Refresh rate of the mode.
+ UINT8 RFlags; ///< Flags specifying display type and functional =
area where the mode is to be removed.
+ UINT16 PanelFlags; ///< Applicable to LFP only. Indicates which LFP p=
anels the mode is to be removed.
+} MODE_REMOVAL_TABLE_ENTRY;
+
+/**
+ This defines the structure of Block 10 (Mode Removal Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block I=
D : 10.
+ UINT16 BlockSize; ///< Defines the size of=
Mode Removal table block.
+ UINT8 EntrySize; ///< Defines the size of=
one entry of mode removal table.
+ MODE_REMOVAL_TABLE_ENTRY ModeRemovalTable[20]; ///< Array containing th=
e mode removal table.
+ UINT16 Terminator; ///< Special value indic=
ating end of mode removal table (0xFFFF).
+} BLOCK10_MODE_REMOVAL_TABLE;
+
+/**
+ This defines the structure of Block 12 (Driver Features Data Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 12
+ UINT16 BlockSize; ///< Defines the size of Driver featur=
es block.
+
+ /**
+ This field defines the various driver related bits:\n
+ Bit 7 =3D Use 00000110h ID for Primary LFP
+ =3D 0, No
+ =3D 1, Yes
+ Bit 6 =3D Enable/Disable Sprite in Clone Mode
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 5 =3D Driver INT 15h hook
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 4 =3D Dual View Zoom
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 3 =3D Hot Plug DVO
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 2 =3D Allow display switching when in Full Screen DOS.
+ =3D 0, Block Display Switching
+ =3D 1, Allow Display Switching
+ Bit 1 =3D Block display switching when DVD active
+ =3D 0, No Block Display Switching
+ =3D 1, Block Display Switching
+ Bit 0 =3D Boot device algorithm
+ =3D 0, OS Default
+ =3D 1, Driver Default
+ **/
+ UINT8 bmp_Driver_Bits;
+ UINT16 bmp_Driver_Boot_Mode_X; ///< X resolution of driver boot mode.
+ UINT16 bmp_Driver_Boot_Mode_Y; ///< Y resolution of driver boot mode.
+ UINT8 bmp_Driver_Boot_Mode_BPP; ///< Bits per pixel of driver boot mod=
e.
+ UINT8 bmp_Driver_Boot_Mode_RR; ///< Refresh rate of driver boot mode.
+
+ /**
+ This field defines the extended driver bits 1.\n
+ Bits [15:14] =3D Integrated HDMI configuration
+ =3D 00b, No Integrated HDMI
+ =3D 01b, Port-B Only
+ =3D 10b, Port-C Only
+ =3D 11b, Both Port-B and Port-C
+ Bits 13 =3D TV Hotplug
+ Bits [12:11] =3D LFP configuration
+ =3D 00b, No LVDS
+ =3D 01b, Integrated LVDS
+ =3D 10b, SDVO LVDS
+ =3D 11b, eDP
+ Bit 10 =3D Obsolete field: CRT hotplug
+ =3D 0, Disabled
+ =3D 1, Enabled (Default)
+ Bit 9 =3D SDVO device power down
+ =3D 0, Disabled (Default)
+ =3D 1, Enabled
+ Bit 8 =3D Preserve Aspect Ratio
+ =3D 0, Disabled (Default)
+ =3D 1, Enabled
+ Bit 7 =3D Display "Maintain Aspect Scaling" via CUI
+ =3D 0, No
+ =3D 1, Yes (Default)
+ Bit 6 =3D Sprite Display Assignment when Overlay is Active in Clone Mode:
+ =3D 0, Secondary
+ =3D 1, Primary
+ Bit 5 =3D Default Power Scheme user interface
+ =3D 0, CUI
+ =3D 1, 3rd Party Application
+ Bit 4 =3D NT 4.0 Dual Display Clone Support
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 3 =3D Default Render Clock Frequency
+ =3D 0, High Frequency
+ =3D 1, Low Frequency
+ Bit 2 =3D Dual-Frequency Graphics Technology
+ =3D 0, No
+ =3D 1, Yes
+ Bit 1 =3D Selective Mode Pruning
+ =3D 0, No
+ =3D 1, Yes
+ Bit 0 =3D Enable LFP as primary
+ =3D 0, Disable
+ =3D 1, Enable
+**/
+ UINT16 bmp_Ext_Driver_Bits;
+
+ /**
+ This defines the driver flags related to CUI Hot key.\n
+ Bits [7:3] - Reserved
+ Bit 2 =3D Display Subsystem Enable/Disable
+ =3D 0, Enable (default Value)
+ =3D 1, Disable
+ Bit 1 =3D Embedded Platform
+ =3D 0, False
+ =3D 1, True
+ Bit 0 =3D Define CUI HotK Displays Statically
+ =3D 0, No
+ =3D 1, Yes
+ **/
+ UINT8 bmp_Display_Detect_CUIHotK;
+
+ UINT16 bmp_Legacy_CRT_Max_X; ///< Obsolete field: Defines the l=
egacy CRT X resolution for driver boot mode.
+ UINT16 bmp_Legacy_CRT_Max_Y; ///< Obsolete field: Defines the l=
egacy CRT Y resolution for driver boot mode.
+ UINT8 bmp_Legacy_CRT_Max_RR; ///< Obsolete field: Defines the l=
egacy CRT refresh rate for driver boot mode.
+
+ /**
+ This field defines the extended driver bits 2.\n
+ Bits [7:1] - Reserved
+ Bit 0 =3D Enable Internal Source Termination for HDMI
+ =3D 0, External Termination
+ =3D 1, Internal Termination
+ **/
+ UINT8 bmp_Ext2_Driver_Bits;
+
+ UINT8 bmp_VBT_Customization_Version; ///< Defines the customized VBT =
version number.
+
+ /**
+ This field defines all the driver feature flags.\n
+ Bit 15 =3D PC Features Field's Validity
+ =3D 0, Invalid
+ =3D 1, Valid
+ Bit 14 =3D Hpd_wake - HPD events are routed to display driver when syste=
m is in S0ix/DC9
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 13 =3D Assertive Display Technology (ADT)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 12 =3D Dynamic Media Refresh Rate Switching (DMRRS)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 11 =3D Dynamic Frames Per Second (DFPS)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 10 =3D Intermediate Pixel Storage (IPS)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 9 =3D Panel Self Refresh (PSR)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 8 =3D Intel Turbo Boost Technology
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 7 =3D Graphics Power Modulation Technology (GPMT)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 6 =3D Graphics Render Standby (RS)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 5 =3D Intel Display Refresh Rate Switching (DRRS)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 4 =3D Intel Automatic Display Brightness (ADB)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 3 =3D DxgkDDI Backlight Control (DxgkDdiBLC)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 2 =3D Intel Display Power Saving Technology (DPST)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 1 =3D Intel Smart 2D Display Technology (S2DDT)
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 0 =3D Intel Rapid Memory Power Management (RMPM)
+ =3D 0, Disable
+ =3D 1, Enable
+ **/
+ UINT16 bmp_Driver_Feature_Flags;
+} BLOCK12_DRIVER_FEATURES;
+
+/**
+ This defines the structure of Block 13 (Driver Persistence Options)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 13
+ UINT16 BlockSize; ///< Defines the size of Driver Persiste=
nce options block.
+
+ /**
+ Defines the various persistence options.\n
+ Bits [15:10] - Reserved
+ Bit 9 =3D Docking Persistence Algorithm
+ =3D 0, OS Default
+ =3D 1, Driver Default
+ Bit 8 =3D DVO Hot Plug Persistence on Mode
+ Bit 7 =3D EDID Persistence on Mode
+ Bit 6 =3D Hot Key Persistence on Mode
+ =3D 0, No
+ =3D 1, Yes
+ Bit 5 =3D Hot Key Persistence on RestorePipe
+ =3D 0, No
+ =3D 1, Yes
+ Bit 4 =3D Hot Key Persistence on RefreshRate
+ =3D 0, No
+ =3D 1, Yes
+ Bit 3 =3D Hot Key Persistence on MDS/Twin
+ =3D 0, No
+ =3D 1, Yes
+ Bit 2 =3D Power Management Persistence Algorithm
+ =3D 0, OS Default
+ =3D 1, Driver Default
+ Bit 1 =3D Lid Switch Persistence Algorithm
+ =3D 0, OS Default
+ =3D 1, Driver Default
+ Bit 0 =3D Hot Key Persistence Algorithm
+ =3D 0, OS Default
+ =3D 1, Driver Default
+ **/
+ UINT16 PersistenceAlgorithm;
+
+ UINT8 PersistMaxconfig; ///< Maximum mode persistence configurat=
ions (10-200)
+} BLOCK13_DRIVER_PERSISTENCE;
+
+/**
+ This defines the structure of Block 17 (SV Bits)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defnies the unique Block ID : 17
+ UINT16 BlockSize; ///< Defines the size of SV Bits block.
+
+ /**
+ Bits [7:4] =3D Reserved
+ Bit3 =3D Allow VBlank/VblankScanline timeout hang
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit2 =3D Special GMBus support
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit1 =3D Skip program pipe timings when set VGA modes
+ =3D 0, Setmode skip DVO Update
+ =3D 1, Setmode updates DVO
+ Bit0 =3D Disable VGA fast arbiter
+ =3D 0, Enabled
+ =3D 1, Disabled
+ **/
+ UINT8 SvBits1;
+ UINT8 SvBits2; ///< Reserved for future use.
+ UINT8 SvBits3; ///< Reserved for future use.
+ UINT8 SvBits4; ///< Reserved for future use.
+ UINT8 SvBits5; ///< Reserved for future use.
+ UINT8 SvBits6; ///< Reserved for future use.
+ UINT8 SvBits7; ///< Reserved for future use.
+ UINT8 SvBits8; ///< Reserved for future use.
+} BLOCK17_SV_BITS;
+
+/**
+ This defines the structure of Block 18 (Driver Rotation)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 18
+ UINT16 BlockSize; ///< Defines the size of Driver Rota=
tion block.
+ UINT8 RotationFeatureSupport; ///< Rotation feature support field =
used by driver.
+ UINT8 Reserved1; ///< Reserved for future use.
+ UINT16 Reserved2; ///< Reserved for future use.
+ UINT32 Reserved3; ///< Reserved for future use.
+ UINT32 Reserved4; ///< Reserved for future use.
+} BLOCK18_DRIVER_ROTATION;
+
+/**
+ This structure defines an entry of OEM mode table.
+**/
+typedef struct {
+ /**
+ Mode Flags:
+ Bits[7:3] =3D Reserved
+ Bit 2 =3D Enable/disable this OEM mode in GOP driver.
+ Bit 1 =3D Enable/disable this mode in Driver
+ Bit 0 =3D Enable/disable this mode in VBIOS
+ **/
+ UINT8 ModeFlags;
+
+ /**
+ Display Device Flags:
+ Bit 7 =3D LFP2
+ Bit 6 =3D EFP2
+ Bit 5 =3D EFP3
+ Bit 4 =3D EFP4
+ Bit 3 =3D LFP
+ Bit 2 =3D EFP
+ Bit 1 =3D Rsvd
+ Bit 0 =3D Rsvd
+ **/
+ UINT8 DisplayFlags;
+ UINT16 XRes; ///< Defines the X resolution of the mode.
+ UINT16 YRes; ///< Defines the Y resolution of the mode.
+
+ /**
+ Defines the bits per pixel of the mode.
+ Bit 7:3 =3D Reserved
+ Bit 2 =3D 32 BPP
+ Bit 1 =3D 16 BPP
+ Bit 0 =3D 8 BPP
+ **/
+ UINT8 Bpp;
+ UINT8 RRate; ///< Defines the refresh rate of the mode.
+ DTD_STRUCTURE Dtd; ///< Defines the 18 byte timing config for the mod=
e.
+} OEM_MODE_ENTRY;
+
+/**
+ This defines the structure of Block 20 (OEM Mode Customization Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique block ID : 20
+ UINT16 BlockSize; ///< Defines the size of OEM customiza=
tion block.
+ UINT8 NumOfEntry; ///< Defines the number of entries in =
OEM Mode table.
+ UINT8 EntrySize; ///< Defines the size of one entry of =
OEM Mode table.
+ OEM_MODE_ENTRY OemModeTable[6]; ///< Array defining the OEM mode table.
+} BLOCK20_OEM_CUSTOMIZATION;
+
+/**
+ This defines the structure of Block 26 (TV options)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 26
+ UINT16 BlockSize; ///< Defines the size of TV Options bl=
ock.
+
+ /**
+ Defines the TV options:
+ Bit 15 =3D D-Conector Support
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 14 =3D Add 1776x1000 when 1080i is selected and add 1184x666 when =
720p is selected
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 13:12 Underscan/overscan for HDTV via DVI
+ =3D 00b, Enable Underscan and Overscan modes (Default)
+ =3D 01b, Enable only overscan modes
+ =3D 10b, Enable only underscan modes
+ Bits 11:2 =3D Reserved
+ Bit 1:0 =3D Underscan/overscan for HDTV via Component (YPrPb)
+ =3D 00b, Enable Underscan and Overscan modes (Default)
+ =3D 01b, Enable only overscan modes
+ =3D 10b, Enable only underscan modes
+ **/
+ UINT16 bmp_TV_Options_1;
+} BLOCK26_TV_OPTIONS;
+
+/**
+ This structure defines the eDP panel power sequencing parameters.
+**/
+typedef struct {
+ UINT16 T3; ///< Panel Power-Up Delay.
+ UINT16 T8; ///< Panel Power-On to backlight Enable Delay.
+ UINT16 T9; ///< Backlight-Off to Power-Down Delay.
+ UINT16 T10; ///< Power-Down Delay.
+ UINT16 T12; ///< Power Cycle Delay.
+} EDP_PWR_SEQ;
+
+/**
+ This structure defines the PWM<-->Backlight delays for a single eDP pane=
l.
+**/
+typedef struct {
+ UINT16 PwmOnToBacklightEnableDelay; ///< PWM on to backight enable=
delay.
+ UINT16 BacklightDisableToPwmOffDelay; ///< Backlight disable to PWM =
off delay.
+} EDP_PWM_BACKLIGHT_DELAYS;
+
+/**
+ This defines FLT parameters for a single eDP panel.
+ Bits[15:12] : VSwing level
+ 0 : 0.4V (default)
+ 1 : 0.6V
+ 2 : 0.8V
+ 3 : 1.2V
+ Others : Reserved
+ Bits[11:8] : Pre-emphasis level
+ 0 : no pre-emphasis (default)
+ 1 : 3.5dB
+ 2 : 6dB
+ 3 : 9.5dB
+ Others : Reserved
+ Bits[7:4] : Lane count (port width)
+ 0 : x1 mode (default)
+ 1 : x2 mode
+ 2 : Reserved
+ 3 : x4 mode
+ Others : Reserved
+ Bits[3:0] : data rate
+ 0 : 1.62 Gbps
+ 1 : 2.7 Gbps
+ 2 : 5.4 Gbps
+ Others : Reserved
+**/
+typedef union {
+ UINT16 Value;
+ struct {
+ UINT16 DataRate:4;
+ UINT16 LaneCount:4;
+ UINT16 PreEmphasisLevel:4;
+ UINT16 VSwingLevel:4;
+ } Bits;
+} EDP_FAST_LINK_TRAINING_PARAMS;
+
+/**
+ This defines Full link training parameters for a single eDP panel.
+ Bits[7:4] : VSwing level
+ 0 : 0.4V (default)
+ 1 : 0.6V
+ 2 : 0.8V
+ 3 : 1.2V
+ Others : Reserved
+ Bits[3:0] : Pre-emphasis level
+ 0 : no pre-emphasis (default)
+ 1 : 3.5dB
+ 2 : 6dB
+ 3 : 9.5dB
+ Others : Reserved
+**/
+typedef union {
+ UINT8 Value;
+ struct {
+ UINT8 PreEmphasisLevel:4;
+ UINT8 VSwingLevel:4;
+ } Bits;
+} EDP_FULL_LINK_TRAINING_PARAMS;
+
+/**
+ This defines the structure of Apical Parameters for a single eDP panel.
+**/
+typedef struct {
+ UINT32 PanelOui; ///< Apical IP specific field for Pane=
l OUI
+ UINT32 DPCDBaseAddress; ///< Apical IP specific field for DPCD=
Base address
+ UINT32 DPCDIrdidixControl0; ///< Apical IP specific field for DPCD=
Idridix Control 0
+ UINT32 DPCDOptionSelect; ///< Apical IP specific field for DPCD=
option select
+ UINT32 DPCDBacklight; ///< Apical IP specific field for DPCD=
backlight
+ UINT32 AmbientLight; ///< Apical IP specific field for Ambi=
ent light
+ UINT32 BacklightScale; ///< Apical IP specific field for back=
light scale
+} EDP_APICAL_PARAMS;
+
+/**
+ This defines the structure of Block 27 (eDP Display Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 27
+ UINT16 BlockSize; ///< Defines the size of eDP display VBT=
block.
+
+ EDP_PWR_SEQ eDP_PWR_SEQ[16]; ///< Array defining the panel power sequ=
encing for all 16 eDP panels.
+
+ /**
+ Defines the panel color depth in bits per pixel. 2 Bits for each Panel.
+ Bits[1:0] Panel color depth for Panel #1
+ =3D 00, 18bpp
+ =3D 01, 24bpp
+ =3D 10, 30bpp
+ =3D 11, 36bpp
+ **/
+ UINT32 eDP_Panel_Color_Depth;
+
+ /**
+ Array containing the FLT parameters of 16 eDP panels.
+ **/
+ EDP_FAST_LINK_TRAINING_PARAMS eDP_Fast_Link_Training_Params[16];
+
+ /**
+ This field defines the eDP sDRRS MSA Timing Delay for all 16 eDP panels.=
2 Bits for Each Panel.
+ Bits[1:0] for Panel #1
+ =3D 00, Line 1
+ =3D 01, Line 2
+ =3D 10, Line 3
+ =3D 11, Line 4
+ **/
+ UINT32 eDP_sDRRS_MSA_Delay;
+
+ /**
+ Defines the S3D feature enable/disable for all 16 eDP panels. 1 Bit for =
Each Panel.
+ Bits[0] for Panel #1
+ =3D 0, S3D disabled for this panel
+ =3D 1, S3D enabled for this panel
+ **/
+ UINT16 eDP_S3D_Feature;
+
+ /**
+ Defines the T3 optimization enable/disable for all 16 panels. 1 Bit for =
each panel.
+ Bits[0] =3D Panel #1
+ =3D 0, T3 optimization disabled for this panel
+ =3D 1, T3 optimization enabled for this panel
+ **/
+ UINT16 eDP_T3_Optmization;
+
+ /**
+ Defines the Edp vswing and pre-emphasis for all 16 panels. 4 Bits for Ea=
ch Panel
+ Bits[3:0] =3D Panel #1
+ =3D 0, Use table 1 for this panel.
+ =3D 1, Use table 2 for this panel.
+ **/
+ UINT64 VswingPreEmphasisTableNum;
+
+ /**
+ Defines the Edp fast link training support on all 16 panels. 1 Bit for E=
ach Panel
+ Bits[0] =3D Panel #1
+ =3D 0, FastLinkTraining feature is disabled for this panel
+ =3D 1, FastLinkTraining feature is enabled for this panel
+ **/
+ UINT16 EdpFastLinkTrainingSupportOnPanel;
+
+ /**
+ Defines whether the Set power state at DPCD 600h is to be done in eDP en=
able/disable sequence.
+ Bits[0] =3D Panel #1
+ =3D 0, Set power state at DPCD 600h feature is disabled for this panel
+ =3D 1, Set power state at DPCD 600h feature is enabled for this panel
+ **/
+ UINT16 SetPowerStateAtDPCD600h; //This is not used currently
+
+ /**
+ Array defining the PWM <--> Backlight related delays for 16 panels.
+ **/
+ EDP_PWM_BACKLIGHT_DELAYS eDP_Pwm_BackLight_Delays[16];
+
+ /**
+ Defines the Edp full link training support on all 16 panels. 1 Bit for E=
ach Panel.
+ \verbatim
+ Bits[0] : Panel #1
+ 0 : Initial vswing and pre-emphasis levels are not provided for Fu=
ll link training
+ 1 : Initial vswing and pre-emphasis levels are provided for Full l=
ink training
+ Bits 1 to 15 are for panel # 2 to 16.
+ \endverbatim
+ **/
+ UINT16 InitialFullLinkTrainingParamsProvidedInVbt;
+
+ /**
+ Array containing the initial Vswing and Pre-emphasis parameters for Fu=
ll link training.
+ **/
+ EDP_FULL_LINK_TRAINING_PARAMS eDP_Full_Link_Training_Params[16];
+
+ /**
+ Defines the Edp Apical assertive display IP support on all 16 panels. 1 =
Bit for Each Panel.
+ Bit 0 : Panel #1
+ 0 : Apical assertive display IP is disabled for this panel.
+ 1 : Apical assertive display IP is enabled for this panel.
+ Bits 1 to 15 are for panel # 2 to 16.
+ **/
+ UINT16 IsApicalAssertiveDisplayIpEnable;
+
+ /**
+ Array containing the Apical parameters for all 16 panels
+ **/
+ EDP_APICAL_PARAMS eDP_Apcial_Params[16];
+} BLOCK27_EDP_FEATURES;
+
+/**
+ This defines the structure of Block 28 (Edidless EFP support DTD timings)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the uniqu=
e Block ID : 28
+ UINT16 BlockSize; ///< Defines the size =
of Edidless EFP support block.
+ DTD_STRUCTURE Edidless_EFP_DTD_Struc[4]; ///< Array defining th=
e DTD timing for 3 EFP devices.
+} BLOCK28_EDIDLESS_EFP;
+
+/**
+This defines the structure of toggle list entry.
+**/
+typedef struct {
+ /**
+ Defines the display device selection for toggling
+ Bit 15 =3D EFP4.3 (Reserved for CML)
+ Bit 14 =3D EFP3.3
+ Bit 13 =3D EFP2.3
+ Bit 12 =3D EFP1.3
+ Bit 11 =3D EFP4.2 (Reserved for CML)
+ Bit 10 =3D EFP3.2
+ Bit 9 =3D EFP2.2
+ Bit 8 =3D EFP1.2
+ Bit 7 =3D LFP2
+ Bit 6 =3D EFP2
+ Bit 5 =3D EFP3
+ Bit 4 =3D EFP4
+ Bit 3 =3D LFP
+ Bit 2 =3D EFP
+ Bit 1 =3D TV
+ Bit 0 =3D CRT
+ **/
+ UINT16 DisplayDevice;
+} CNL_TOGGLE_LIST_ENTRY;
+
+/**
+ This defines the structure of Block 31 (Toggle Lists for Cannonlake)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Bl=
ock ID : 31
+ UINT16 BlockSize; ///< Defines the size of T=
oggle List Block.
+ UINT16 NumOfEntry1; ///< Defines the number of=
entries in toggle list 1.
+ UINT8 EntrySize1; ///< Defines the size of t=
oggle list entry present in list 1.
+ CNL_TOGGLE_LIST_ENTRY ToggleList1Entry[16]; ///< Array defining the to=
ggle list 1.
+ UINT16 NumOfEntry2; ///< Defines the number of=
entries in toggle list 2.
+ UINT8 EntrySize2; ///< Defines the size of t=
oggle list entry present in list 2.
+ CNL_TOGGLE_LIST_ENTRY ToggleList2Entry[8]; ///< Array defining the to=
ggle list 2.
+ UINT16 NumOfEntry3; ///< Defines the number of=
entries in toggle list 3.
+ UINT8 EntrySize3; ///< Defines the size of t=
oggle list entry present in list 3.
+ CNL_TOGGLE_LIST_ENTRY ToggleList3Entry[8]; ///< Array defining the to=
ggle list 3.
+ UINT16 NumOfEntry4; ///< Defines the number of=
entries in toggle list 4.
+ UINT8 EntrySize4; ///< Defines the size of t=
oggle list entry present in list 4.
+ CNL_TOGGLE_LIST_ENTRY ToggleList4Entry[8]; ///< Array defining the to=
ggle list 4.
+} BLOCK31_TOGGLE_LIST;
+
+/**
+ This defines the structure of Display device removal configuration entry.
+**/
+typedef struct {
+ /**
+ Defines the display device configuration to be removed.
+ Bit 15 =3D EFP4.3 (Reserved for CML)
+ Bit 14 =3D EFP3.3
+ Bit 13 =3D EFP2.3
+ Bit 12 =3D EFP1.3
+ Bit 11 =3D EFP4.2 (Reserved for CML)
+ Bit 10 =3D EFP3.2
+ Bit 9 =3D EFP2.2
+ Bit 8 =3D EFP1.2
+ Bit 7 =3D LFP2
+ Bit 6 =3D EFP2
+ Bit 5 =3D EFP3
+ Bit 4 =3D EFP4
+ Bit 3 =3D LFP
+ Bit 2 =3D EFP
+ Bit 1 =3D TV
+ Bit 0 =3D CRT
+ **/
+ UINT16 DisplayDeviceConfiguration;
+} CNL_DISPLAY_CONFIGURATION_ENTRY;
+
+/**
+ This defines the structure of Block 32 (Display removal configuration Bl=
ock)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the uni=
que Block ID =3D 32
+ UINT16 BlockSize; ///< Defines the siz=
e of Display removal configuration block.
+ UINT8 NumOfEntry; ///< Defines the num=
ber of entries in display removal configuraion table.
+ UINT8 EntrySize; ///< Defines the siz=
e of 1 entry in display removal configuration table.
+ CNL_DISPLAY_CONFIGURATION_ENTRY RemoveDisplayConfiguration[15]; =
///< Array defining the display removal configuration table.
+}BLOCK32_DISPLAY_CONFIGURATION_REMOVAL;
+
+/**
+ This defines the Local Flat panel basic details such as resolution and t=
he various registers.
+**/
+typedef struct {
+ UINT16 XRes; ///< X resolution of the panel.
+ UINT16 YRes; ///< Y resolution of the panel.
+ UINT32 LVDSDigDisReg; ///< MMIO offset of LFP digital display =
port register.
+ UINT32 LVDSDigDisVal; ///< Value of LFP digital display port r=
egister.
+ UINT32 OnSeqDelayReg; ///< MMIO offset of Panel power on seque=
ncing delay register.
+ UINT32 OnSeqDelayVal; ///< Value of Panel power on sequencing =
delay register.
+ UINT32 OffSeqDelayReg; ///< MMIO offset of Panel power off sequ=
encing delay register.
+ UINT32 OffSeqDelayVal; ///< Value of Panel power off sequencing=
delay register.
+ UINT32 CycleDelay_RefDivReg; ///< MMIO offset of Panel power cycle de=
lay and reference divider register.
+ UINT32 CycleDelay_RefDivVal; ///< Value of Panel power cycle delay an=
d reference divider register.
+ UINT16 Terminate; ///< Special value 0xFFFF indicating end=
of data.
+} FP_DATA;
+
+/**
+ This defines the structure consisting of all details for a single Local =
Flat panel.
+**/
+typedef struct {
+ FP_DATA FP_Data; ///< Instance of ::FP_DATA structure.
+ DTD_STRUCTURE DTD_Data; ///< Instance of ::DTD_STRUCTURE which conta=
ins the DTD timings for the panel.
+ PID_DATA PID_Data; ///< Instance of ::PID_DATA structure which =
contains panel related information used by driver.
+} LVDS_FP_TABLE;
+
+/**
+ This structure defines all the details regarding Backlight control for L=
FP.
+**/
+typedef struct {
+ /**
+ Defines the backlight features for the panel.
+ Bits 7:6 =3D GMBus Speed:
+ =3D 00, 100 KHz
+ =3D 01, 50 KHz
+ =3D 10, 400 KHz
+ =3D 11, 1 MHz
+ Bits 5:3 =3D Inverter GPIO Pins
+ =3D 0, None
+ =3D 1, I2C GPIO pins
+ =3D 2, Analog CRT DDC pins
+ =3D 3, DVI/LVDS DDC GPIO pins
+ =3D 5, sDVO I2C GPIO pins
+ Bit 2 =3D Inverter Polarity (i2c & PWM)
+ =3D 0, Normal (0 =3D Minimum brightness)
+ =3D 1, Inverted (0 =3D Maximum brightness)
+ Bits 1:0 =3D BLC Inverter Type
+ =3D 00, None/External
+ =3D 01, i2c
+ =3D 10, PWM
+ =3D 11, Reserved
+ **/
+ UINT8 BLC_Ftr;
+
+ UINT16 PWM_Freq; ///< PWM inverter frequency in KHz
+ UINT8 Min_Brightness; ///< Minimum brightness in the range 0-255
+ UINT8 I2C_Add; ///< I2C Inverter Slave Address
+ UINT8 I2C_Command; ///< I2C Inverter command code
+} BLC;
+
+/**
+ This defines the structure of Block 40 (LFP Features)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 40
+ UINT16 BlockSize; ///< Defines the size of LFP Features block.
+
+ UINT8 bmp_Panel_type; ///< Defines the panel type of LFP.
+ UINT8 Skip1; ///< Obsoleted.
+
+ /**
+ Capabilities byte:
+ Bit 15:7 =3D SW Workaround bits
+ Bit 6 =3D Panel EDID support
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 5 =3D Pixel dithering
+ =3D 0, Disable
+ =3D 1, Enable
+ Bit 4 =3D Panel Fitting ratio calc.
+ =3D 0 - Manual
+ =3D 1 - Automatic
+ Bit 3 =3D Panel Fitting Graphics mode
+ =3D 0, Bilinear
+ =3D 1, Enhanced
+ Bit 2 =3D Panel Fitting Text mode
+ =3D 0, Bilinear
+ =3D 1, Enhanced
+ Bit 1:0 =3D Panel Fitting Support
+ =3D 00, No panel fitting
+ =3D 01, Text panel fitting
+ =3D 10, GFX panel fitting
+ =3D 11, Text+GFX panel fitting
+ **/
+ UINT16 bmp_LVDS_Capabilities;
+
+ /**
+ Defines the channel type of LFP. 2 Bits for each Panel.
+ Bits [0:1] for Panel #1
+ =3D 00, Automatic (algorithm)
+ =3D 01, Single Channel
+ =3D 10, Dual Channel
+ =3D 11, Reserved
+ **/
+ UINT32 INT_LVDS_Panel_Channel_Bits;
+
+ UINT16 Enable_SSC_Bit; ///< LVDS Spread Spectrum Clock
+ UINT16 SSC_Freq_Bit; ///< LVDS Spread Spectrum Clock Frequency
+ UINT16 Disable_SSC_DDT_Bit; ///< Disable SSC in Dual Display Twin
+
+ /**
+ Defines the panel color depth. 1 Bits for each Panel.
+ Bits[0] for Panel #01
+ =3D 0, 18bpp
+ =3D 1, 24bpp
+ **/
+ UINT16 INT_Panel_Color_Depth;
+
+ /**
+ Defines the Panel type. 2 Bits for each Panel.
+ Bits [0:1] for Panel #1
+ =3D 00, Static DRRS
+ =3D 01, D2PO
+ =3D 10, Seamless
+ =3D 11, Reserved
+ **/
+ UINT32 DPS_Panel_Type_Bits;
+
+ /**
+ Defines the type of backlight control for the LFP. 2 bits for each Panel.
+ Bits [0:1] for Panel #1
+ =3D 00, Default
+ =3D 01, CCFL backlight
+ =3D 10, LED backlight
+ =3D 11, Reserved
+ **/
+ UINT32 BLT_Control_Type_Bits;
+ /**
+ Defines the LFP power enable flag in S0 state for all 16 panels. 1 Bit f=
or Each Panel.
+ Bits[0] : Panel #1
+ 0 : Do not keep LCDVCC on during S0 state.
+ 1 : Keep LCDVCC on during S0 state.
+ Bits 1 to 15 are for panel # 2 to 16.
+ **/
+ UINT16 LcdvccOnDuringS0State;
+} BLOCK40_LVDS_FEATURES;
+
+/**
+ This structure defines the second type of BMP table pointers.
+ This is used to store pointers to LFP Flat panel data, DTD and PID infor=
mation.
+**/
+typedef struct {
+ UINT16 Offset; ///< Offset of the table.
+ UINT8 Size; ///< Size of the table.
+} BMP_TABLE_TYPE2_PTR;
+
+/**
+ This structure defines a set of 3 pointers for LFP display.
+ These pointers point to FP data, DTD and PID information respectively.
+**/
+typedef struct {
+ BMP_TABLE_TYPE2_PTR FpTablePtr; ///< Pointer to FP Data of the LFP p=
anel.
+ BMP_TABLE_TYPE2_PTR DtdTablePtr; ///< Pointer to DTD of the LFP panel.
+ BMP_TABLE_TYPE2_PTR PidTablePtr; ///< Pointer to the PID data of the =
LFP panel.
+} LFP_TABLE_POINTERS;
+
+/**
+ This defines the structure of Block 41 (LFP Table Pointers for FPDATA, D=
TD and PID)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Bl=
ock ID:41
+ UINT16 BlockSize; ///< Defines the size of L=
FP Table Pointer Block.
+ UINT8 NumOfEntries; ///< Defines the number of=
entries in the Table.
+ LFP_TABLE_POINTERS LfpTablePointers[16]; ///< Array of ::LFP_TABLE_=
POINTERS for all 16 panels.
+ UINT16 LfpPanelNameTableOffset; ///< Offset of LFP panel n=
ames table.
+ UINT8 LfpPanelNameLength; ///< Length of a single LF=
P panel's name.
+} BLOCK41_LFP_TABLE_POINTERS;
+
+/**
+ This defines the structure of Block 42 (Complete LFP Panel Information)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique block ID :=
42
+ UINT16 BlockSize; ///< Defines the size of Complete =
LFP panel information for all 16 panels.
+ LVDS_FP_TABLE LVDS_FP_Table[16]; ///< Array of ::LVDS_FP_TABLE cont=
aining data of 16 panels.
+ UINT8 LFP_PANEL_NAMES[16][13];///< Array defining the panel name=
s for all 16 panels.
+
+ /**
+ 1 Bit for Each Panel
+ Bit0 =3D Scaling feature for panel 1.
+ =3D 0, Scaling feature is disabled for this panel.
+ =3D 1, Scaling feature is enabled for this panel.
+ **/
+ UINT16 EnableScaling; //This is not used currently
+
+ /**
+ Array defining DRRS minimum refresh rate. 1 Byte for Each Panel.
+ **/
+ UINT8 Seamless_DRRS_Min_RR[16];
+
+ /**
+ Array defining Pixel Overlap Count. 1 Byte for Each Panel.
+ **/
+ UINT8 PixelOverlapCount[16];
+} BLOCK42_LVDS_PANEL_INFO;
+
+typedef union {
+ /**
+ Backlight control parameters.\n
+ Bits 7:4 : PWM Controller Selection
+ 0 : Controller 0
+ 1 : Controller 1
+ 2 : Controller 2
+ 3 : Controller 3
+ Others : Reserved.
+ Bits 3:0 : PWM Source Selection
+ 0 : PMIC PWM
+ 1 : LPSS PWM
+ 2 : DISPLAY PWM
+ 3 : CABC PWM
+ Others : Reserved.
+ **/
+ UINT8 Value;
+ struct {
+ UINT8 PwmSourceSelection:4;
+ UINT8 PwmControllerSelection:4;
+ } Bits;
+} BKLT_CTRL_PARAMS;
+
+/**
+ This defines the structure of Block 43 (LFP Brightness Control)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block =
ID : 43
+ UINT16 BlockSize; ///< Defines the size of Brigh=
tness control block.
+
+ UINT8 SIZE_BLCStruc; ///< Defines the size of singl=
e entry in Backlight control table for LFP.
+ BLC BLC_Struct[16]; ///< Array defining the backli=
ght control for 16 LFP panels.
+ UINT8 Post_Brightness[16]; ///< Array defining the initia=
l brightness for all 16 panels.
+ BKLT_CTRL_PARAMS Brightness_Control[16]; ///< Array defining the bright=
ness control method for all 16 panels
+} BLOCK43_LVDS_BLC;
+
+/**
+ This defines the structure of Block 44 (LFP Power Conservation Features)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique block ID : 44
+ UINT16 BlockSize; ///< Defines the size of LFP Power Conservation =
Features block.
+ union {
+ /**
+ Bit[7] : ALS Enable/Disable
+ 0 - Disable
+ 1 - Enable
+ Bit[6] : Display LACE support
+ 0 - Not supported
+ 1 - Supported
+ Bit[5] : Default Display LACE enabled status
+ 0 - Disabled
+ 1 - Enabled
+ Bit[4] : Reserved
+ Bit[3:1] : Power conservation preference level.
+ 4 is default in a range of 1 to 6.
+ Bit[0] : Reserved
+ **/
+ UINT8 Value;
+ struct {
+ UINT8 Reserved:1;
+ UINT8 PwrConservation:3;
+ UINT8 Reserved_1:1;
+ UINT8 DefalutDisplayLaceEnable:1;
+ UINT8 DisplayLaceSupport:1;
+ UINT8 AlsEnable:1;
+ } Bits;
+ } LfpFeatureBits;
+
+ UINT16 AlsData[10]; ///< Defines the main ALS data.
+
+ union {
+ /**
+ Bit[7:3] : Reserved
+ Bit[2:0] : Aggressiveness Level Profile.
+ 000 - Minimum
+ 001 - Moderate
+ 010 - High
+ **/
+ UINT8 Value;
+ struct {
+ UINT8 AggressionProfileLevel:3;
+ UINT8 Reserved:5;
+ } Bits;
+ } LaceAggressivenessProfile; ///< Defines the LACE Aggressiveness Profile
+} BLOCK44_ALS;
+
+/**
+ This defines the structure of Black Frame Insertion table entry.
+**/
+typedef struct {
+ /**
+ BFI Features\n
+ Bit[7-2] : Reserved\n
+ Bit[1] : Enable Brightness control in CUI\n
+ Bit[0] : Enable BFI in driver
+ **/
+ UINT8 EnableBits;
+ UINT8 BrightnessNonBFI; ///< Brightness percentage in non BFI =
mode
+} BFI;
+
+/**
+ This defines the structure of Block 45 (Black Frame insertion Support fo=
r LFP)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 45
+ UINT16 BlockSize; ///< Defines the size of Black frame=
insertion support block.
+ UINT8 SIZE_BFIStruc; ///< Defines the size of 1 entry of =
black frame data.
+ BFI BFI_Struct[16]; ///< Array defining the data of blac=
k frame insertion for all 16 panels.
+} BLOCK45_BFI_SUPPORT;
+
+/**
+ This structure defines the chromaticity information for a single LFP pan=
el.
+**/
+typedef struct {
+ /**
+ Defines the chromaticity feature enable bits
+ Bits 7:2 =3D Reserved
+ Bit 1 =3D Override EDID values for chromaticity if enabled, Instead =
Use VBT values
+ =3D 0, Disable, Use the EDID values
+ =3D 1, Enable, Use the values from the VBT
+ Bit 0 =3D Enable chromaticity feature. EDID values will be used when=
this feature is enabled.
+ =3D 0, Disable
+ =3D 1, Enable
+ **/
+ UINT8 EnableBits;
+
+ UINT8 Red_Green_1; ///< Red/green chormaticity coordinates at E=
DID offset 19h
+ UINT8 Blue_White_1; ///< Blue/white chromatiity coordinates at E=
DID offset 1Ah
+ UINT8 Red_X1; ///< Red x coordinate at EDID offset 1Bh
+ UINT8 Red_Y1; ///< Red x coordinate at EDID offset 1Ch
+ UINT8 Green_X1; ///< Green x coordinate at EDID offset 1Dh
+ UINT8 Green_Y1; ///< Green x coordinate at EDID offset 1Eh
+ UINT8 Blue_X1; ///< Blue x coordinate at EDID offset 1Fh
+ UINT8 Blue_Y1; ///< Blue x coordinate at EDID offset 20h
+ UINT8 White_X1; ///< White x coordinate at EDID offset 21h
+ UINT8 White_Y1; ///< White x coordinate at EDID offset 22h
+} CHROMATICITY;
+
+/**
+ This structure defines the Luminance information for a single LFP panel.
+**/
+typedef struct {
+ /**
+ Defines the chromaticity feature enable bits
+ Bits 7:2 : Reserved
+ Bit 1 : Enable Gamma feature.
+ : if enabled, use gamma values from this block.
+ 0 : Disable
+ 1 : Enable
+ Bit 0 : Enable Luminance feature.
+ : if enabled, use values from this block.
+ 0 : Disable
+ 1 : Enable
+ **/
+ UINT8 EnableBits;
+ /**
+ Luminance info (refer DisplayID 2.0)
+ 2 byte value, encoded in IEEE 754 half-precision binary floating point=
format
+ **/
+ UINT16 MinLuminance; ///< Native minimum luminance
+ UINT16 MaxFullFrameLuminance; ///< Native maximum luminance (Full =
Frame)
+ UINT16 MaxLuminance; ///< Native Maximum Luminance (1% Re=
ctangular Coverage)
+ /**
+ Gamma EOTF
+ Gamma values range from 00h through FFh which will come from VBT.
+ Value shall define the gamma range, from 1.00 to 3.54.
+ Field Value =3D (Gamma (value from VBT) + 100) / 100
+
+ FFh =3D No gamma information shall be provided
+ **/
+ UINT8 Gamma;
+
+}LUMINANCE_AND_GAMMA;
+
+/**
+ This defines the structure of Block 46 (Chromaticity Support)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Bloc=
k ID : 46
+ UINT16 BlockSize; ///< Defines the size of Chr=
omaticity Block.
+ CHROMATICITY Chromaticity_Struct[16]; ///< Defines the chromaticit=
y information for all 16 panels.
+ LUMINANCE_AND_GAMMA Luminance_Gamma_Struct[16]; ///< Defines the lum=
ianance information for all 16 panels.
+} BLOCK46_CHROMATICITY_SUPPORT;
+
+/**
+ This defines the structure of Block 51 (Fixed Mode Set)
+**/
+typedef struct{
+ UINT8 BlockId; ///< Defines the unique block ID : 51.
+ UINT16 BlockSize; ///< Defines the size of Fixed mode set feat=
ure block.
+ UINT8 FeatureEnable; ///< Whether the fixed mode set feature is e=
nabled/disabled.
+ UINT32 XRes; ///< X resolution of the fixed mode.
+ UINT32 YRes; ///< Y resolution of the fixed mode.
+} BLOCK51_FIXED_MODE_SET;
+
+/**
+ This defines the Complete VBT Structure for generation purpose
+**/
+typedef struct {
+ VBT_HEADER VbtHeader;
+ VBT_BIOS_DATA_HEADER VbtBdbHeader;
+ BLOCK254_BMP_Structure Block254BMPStructure;
+ VBT_GENERAL1_INFO VbtGen1Info;
+ PRD_BOOT_TABLE PrdBootTable;
+ VBT_GENERAL2_INFO VbtGen2Info;
+ BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST Block03OriginalDisplayToggleLi=
st;
+ BLOCK252_SBIOS_Hook Block252SbiosHook;
+ BLOCK06_MMIO_REG_TABLE Block06MmioRegTable;
+ BLOCK07_IOSWFLAG_REG_TABLE Block07IoswflagRegTable;
+ BLOCK08_MMIOSWFLAG_REG_TABLE Block08MmioswflagRegTable;
+ BLOCK09_PSR_FEATURE Block09PsrFeature;
+ BLOCK10_MODE_REMOVAL_TABLE Block10ModeRemovalTable;
+ BLOCK12_DRIVER_FEATURES Block12DriverFeatures;
+ BLOCK13_DRIVER_PERSISTENCE Block13DriverPersistence;
+ BLOCK17_SV_BITS Block17SvBits;
+ BLOCK18_DRIVER_ROTATION Block18DriverRotation;
+ BLOCK20_OEM_CUSTOMIZATION Block20OemCustomization;
+ BLOCK26_TV_OPTIONS Block26TVOptions;
+ BLOCK27_EDP_FEATURES Block27EDPFeatures;
+ BLOCK28_EDIDLESS_EFP Block28EdidlessEFP;
+ BLOCK31_TOGGLE_LIST Block31ToggleList;
+ BLOCK32_DISPLAY_CONFIGURATION_REMOVAL Block32DisplayConfigurationRem=
oval;
+ BLOCK40_LVDS_FEATURES Block40LVDSFeatures;
+ BLOCK41_LFP_TABLE_POINTERS Block41LfpTablePointers;
+ BLOCK42_LVDS_PANEL_INFO Block42LvdsPanelInfo;
+ BLOCK43_LVDS_BLC Block43LVDSBlc;
+ BLOCK44_ALS Block44Als;
+ BLOCK46_CHROMATICITY_SUPPORT Block46ChromaticitySupport;
+ BLOCK51_FIXED_MODE_SET Block51FixedModeSet;
+} VBT_TABLE_DATA;
+
+#pragma pack()
+
+/**
+ This function will update the VBT checksum.
+
+ @param[in out] VbtPtr - Pointer to VBT table
+
+ @retval none
+**/
+VOID
+UpdateVbtChecksum(
+ VBT_TABLE_DATA *VbtPtr
+);
+
+/**
+ This function will update the VBT.
+
+ @param[in] VbtPtr - Pointer to VBT Table
+
+ @retval none
+**/
+VOID
+UpdateGopVbt (
+ IN VBT_TABLE_DATA *VbtPtr
+);
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h b/Pl=
atform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h
new file mode 100644
index 0000000000..fdb6b8eead
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h
@@ -0,0 +1,68 @@
+/** @file
+ GPIO definition table for CometlakeURvp
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IO_EXPANDER_H_
+#define _IO_EXPANDER_H_
+
+typedef struct {
+ UINT32 IoExpanderNumber : 1; // IO Expander Number (0/1)
+ UINT32 GpioPinNumber : 5; // GPIO Pin Number (0 to 23)
+ UINT32 GpioDirection : 1; // GPIO Pin Direction (Input/Output)
+ UINT32 GpioLevel : 1; // GPIO Pin Output Level (High/Low)
+ UINT32 GpioInversion : 1; // GPIO Pin Inversion (Enabled/Disabled)
+ UINT32 Reserved : 23; // Reserved
+} IO_EXPANDER_GPIO_CONFIG;
+
+//CML PCH LP GPIO Expander Number
+#define IO_EXPANDER_0 0
+#define IO_EXPANDER_1 1
+
+//CML PCH LP GPIO Pin Mapping
+#define IO_EXPANDER_GPIO_0 0 // P00
+#define IO_EXPANDER_GPIO_1 1 // P01
+#define IO_EXPANDER_GPIO_2 2 // P02
+#define IO_EXPANDER_GPIO_3 3 // P03
+#define IO_EXPANDER_GPIO_4 4 // P04
+#define IO_EXPANDER_GPIO_5 5 // P05
+#define IO_EXPANDER_GPIO_6 6 // P06
+#define IO_EXPANDER_GPIO_7 7 // P07
+#define IO_EXPANDER_GPIO_8 8 // P10
+#define IO_EXPANDER_GPIO_9 9 // P11
+#define IO_EXPANDER_GPIO_10 10 // P12
+#define IO_EXPANDER_GPIO_11 11 // P13
+#define IO_EXPANDER_GPIO_12 12 // P14
+#define IO_EXPANDER_GPIO_13 13 // P15
+#define IO_EXPANDER_GPIO_14 14 // P16
+#define IO_EXPANDER_GPIO_15 15 // P17
+#define IO_EXPANDER_GPIO_16 16 // P20
+#define IO_EXPANDER_GPIO_17 17 // P21
+#define IO_EXPANDER_GPIO_18 18 // P22
+#define IO_EXPANDER_GPIO_19 19 // P23
+#define IO_EXPANDER_GPIO_20 20 // P24
+#define IO_EXPANDER_GPIO_21 21 // P25
+#define IO_EXPANDER_GPIO_22 22 // P26
+#define IO_EXPANDER_GPIO_23 23 // P27
+
+//CML PCH LP GPIO Expander GPIO Direction
+#define IO_EXPANDER_GPIO_OUTPUT 0
+#define IO_EXPANDER_GPIO_INPUT 1
+
+//CML PCH LP GPIO Expaner GPIO Output Level
+#define IO_EXPANDER_GPO_LEVEL_LOW 0
+#define IO_EXPANDER_GPO_LEVEL_HIGH 1
+
+//CML PCH LP GPIO Expaner GPIO Inversion Status
+#define IO_EXPANDER_GPI_INV_DISABLED 0
+#define IO_EXPANDER_GPI_INV_ENABLED 1
+#define IO_EXPANDER_GPIO_RESERVED 0x00
+
+//GPIO Table Terminator
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCpuPol=
icyUpdateLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCp=
uPolicyUpdateLib.h
new file mode 100644
index 0000000000..a5dd731aa7
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpda=
teLib.h
@@ -0,0 +1,75 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_CPU_POLICY_UPDATE_LIB_H_
+#define _DXE_CPU_POLICY_UPDATE_LIB_H_
+
+#include <PiDxe.h>
+#include <PchAccess.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/CpuPolicyProtocol.h>
+
+/**
+
+ This function prints the CPU DXE phase policy.
+
+ @param[in] DxeCpuPolicy - CPU DXE Policy protocol
+
+**/
+VOID
+CpuDxePrintPolicyProtocol (
+ IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ );
+
+/**
+
+Routine Description:
+
+ This function updates Dxe Cpu Policy Protocol
+
+Arguments:
+
+ @param[in] DxeCpuPolicy The Cpu Policy protocol instance
+
+Returns:
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by th=
is driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to =
initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnor=
mally.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSiCpuPolicy (
+ IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ );
+
+/**
+
+ CpuInstallPolicyProtocol installs CPU Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please=
update and override
+ any setting before calling this function.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol=
instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b=
uffer
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMePoli=
cyUpdateLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMeP=
olicyUpdateLib.h
new file mode 100644
index 0000000000..a873446be3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMePolicyUpdat=
eLib.h
@@ -0,0 +1,27 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_ME_POLICY_UPDATE_LIB_H_
+#define _DXE_ME_POLICY_UPDATE_LIB_H_
+
+/**
+ Update the ME Policy Library
+
+ @param[in] DxeMePolicy The pointer to get ME Policy proto=
col instance
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this=
driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to in=
itialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnorma=
lly.
+
+**/
+EFI_STATUS
+UpdateDxeMePolicy (
+ IN OUT ME_POLICY_PROTOCOL *DxeMePolicy
+ );
+
+#endif // _DXE_ME_POLICY_UPDATE_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePchPol=
icyUpdateLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePc=
hPolicyUpdateLib.h
new file mode 100644
index 0000000000..fd451328bd
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePchPolicyUpda=
teLib.h
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_PCH_POLICY_UPDATE_LIB_H_
+#define _DXE_PCH_POLICY_UPDATE_LIB_H_
+
+/**
+ Get data for platform policy from setup options.
+
+ @param[in] PchPolicy The pointer to get PCH Policy protoco=
l instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxePchPolicy (
+ IN OUT PCH_POLICY_PROTOCOL *PchPolicy
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePolicy=
BoardConfigLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Dxe=
PolicyBoardConfigLib.h
new file mode 100644
index 0000000000..f73da06df4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePolicyBoardCo=
nfigLib.h
@@ -0,0 +1,30 @@
+/** @file
+ Header file for the DxePolicyBoardConfig Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_POLICY_BOARD_CONFIG_LIB_H_
+#define _DXE_POLICY_BOARD_CONFIG_LIB_H_
+
+#include <Protocol/MePolicy.h>
+#include <Protocol/SaPolicy.h>
+
+/**
+ This function performs DXE SA Policy update by board configuration.
+
+ @param[in, out] DxeSaPolicy DXE SA Policy
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicyBoardConfig (
+ IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaPoli=
cyUpdateLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaP=
olicyUpdateLib.h
new file mode 100644
index 0000000000..77ca6c3f2a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdat=
eLib.h
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_SA_POLICY_UPDATE_LIB_H_
+#define _DXE_SA_POLICY_UPDATE_LIB_H_
+
+/**
+ Get data for platform policy from setup options.
+
+ @param[in] SaPolicy The pointer to get SA Policy protocol =
instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicy (
+ IN OUT SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicy=
InitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicyI=
nitLib.h
new file mode 100644
index 0000000000..bfa0f0cf3e
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicyInitLib=
.h
@@ -0,0 +1,29 @@
+/** @file
+ Function prototype of FspPolicyInitLib.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FSP_POLICY_INIT_LIB_H_
+#define _FSP_POLICY_INIT_LIB_H_
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+VOID
+EFIAPI
+FspPolicyInitPreMem (
+ IN FSPM_UPD *FspmUpdDataPtr
+ );
+
+VOID
+EFIAPI
+FspPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+#endif // _FSP_POLICY_INIT_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCheck=
ConflictLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCh=
eckConflictLib.h
new file mode 100644
index 0000000000..19d16c1151
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCheckConflic=
tLib.h
@@ -0,0 +1,46 @@
+/** @file
+ Header file for check Gpio PadMode conflict.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_CHECK_CONFLICT_LIB_H_
+#define _GPIO_CHECK_CONFLICT_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <GpioConfig.h>
+#include <Library/GpioLib.h>
+
+extern EFI_GUID gGpioCheckConflictHobGuid;
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ UINT32 GpioPadMode:5;
+ UINT32 Reserved:27;
+} GPIO_PAD_MODE_INFO;
+
+/**
+ Check Gpio PadMode conflict and report it.
+**/
+VOID
+GpioCheckConflict (
+ VOID
+ );
+
+/**
+ This libaray will create one Hob for each Gpio config table
+ without PadMode is GpioHardwareDefault
+
+ @param[in] GpioDefinition Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+**/
+VOID
+CreateGpioCheckConflictHob (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ );
+
+#endif // _GPIO_CHECK_CONFLICT_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpan=
derLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpande=
rLib.h
new file mode 100644
index 0000000000..5bd00e21fc
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpanderLib.h
@@ -0,0 +1,123 @@
+/** @file
+ Support for IO expander TCA6424.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_EXPANDER_LIB_H_
+#define _GPIO_EXPANDER_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+/**
+ Set the Direction value for the given Expander Gpio pin.
+
+ This function is to Set the direction value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+**/
+VOID
+GpioExpSetDirection (
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Direction
+ );
+/**
+ Set the input value for the given Expander Gpio pin.
+
+ This function is to get the input value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+
+**/
+VOID
+GpioExpSetPolarity (
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Polarity
+ );
+/**
+ Set the Output value for the given Expander Gpio pin.
+
+ This function is to Set the Output value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+
+**/
+VOID
+GpioExpSetOutput (
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Value
+ );
+/**
+ Returns the data from register value giving in the input.
+
+ This function is to get the data from the Expander
+ Registers by following the I2C Protocol communication
+
+
+ @param[in] Bar0 Bar address of the SerialIo Controller
+ @param[in] Address Expander Value with in the Contoller
+ @param[in] Register Address of Input/Output/Configure/Polarity
+ registers with in the Expander
+
+ @retval UINT8 Value returned from the register
+**/
+UINT8
+GpioExpGetInput (
+ IN UINT8 Expander,
+ IN UINT8 Pin
+ );
+
+/**
+ Configures all registers of a single IO Expander in one go.
+
+ @param[in] Expander Expander number (0/1)
+ @param[in] Direction Bit-encoded direction values. BIT0 is for pin0, =
etc. 0=3Doutput, 1=3Dinput
+ @param[in] Polarity Bit-encoded input inversion values. BIT0 is for =
pin0, etc. 0=3Dnormal, 1=3Dinversion
+ @param[in] Output Bit-encoded output state, ignores polarity, only=
applicable if direction=3DINPUT. BIT0 is for pin0, etc. 0=3Dlow, 1=3Dhigh
+
+**/
+VOID
+GpioExpBulkConfig (
+ IN UINT8 Expander,
+ IN UINT32 Direction,
+ IN UINT32 Polarity,
+ IN UINT32 Output
+ );
+
+/**
+ Returns the Controller on which GPIO expander is present.
+
+ This function returns the Controller value
+
+ @param[out] Controller Pointer to a Controller value on
+ which I2C expander is configured.
+
+ @retval EFI_SUCCESS non.
+**/
+EFI_STATUS
+GpioExpGetController (
+ OUT UINT8 *Controller
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTa=
bleLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTabl=
eLib.h
new file mode 100644
index 0000000000..7e15e959a6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTableLib.h
@@ -0,0 +1,48 @@
+/** @file
+
+ Header file for the Intel HD Audio Verb Table library.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _HDA_VERB_TABLE_LIB_H_
+#define _HDA_VERB_TABLE_LIB_H_
+
+#include <ConfigBlock/HdAudioConfig.h>
+#include <Library/BaseLib.h>
+
+enum HDAUDIO_CODEC_SELECT {
+ PchHdaCodecPlatformOnboard =3D 0,
+ PchHdaCodecExternalKit =3D 1
+};
+
+/**
+ Add verb table function.
+ This function update the verb table number and verb table ptr of policy.
+
+ @param[in] HdAudioConfig HD Audio config block
+ @param[out] VerbTableEntryNum Number of verb table entries
+ @param[out] HdaVerbTablePtr Pointer to the verb table
+**/
+VOID
+AddPlatformVerbTables (
+ IN UINT8 CodecType,
+ OUT UINT8 *VerbTableEntryNum,
+ OUT UINT32 *HdaVerbTablePtr
+ );
+
+/**
+ HDA VerbTable init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+HdaVerbTableInit(
+ IN UINT16 BoardId
+ );
+
+#endif
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccess=
Lib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccessLib.h
new file mode 100644
index 0000000000..e1f00b6d96
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccessLib.h
@@ -0,0 +1,34 @@
+/** @file
+ Support for IO expander TCA6424.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _I2C_ACCESS_LIB_H_
+#define _I2C_ACCESS_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+#define WAIT_1_SECOND 1600000000 //1.6 * 10^9
+
+EFI_STATUS
+I2cWriteRead (
+ IN UINTN MmioBase,
+ IN UINT8 SlaveAddress,
+ IN UINT8 WriteLength,
+ IN UINT8 *WriteBuffer,
+ IN UINT8 ReadLength,
+ IN UINT8 *ReadBuffer,
+ IN UINT64 TimeBudget
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatfo=
rmLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatformL=
ib.h
new file mode 100644
index 0000000000..3443479a52
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatformLib.h
@@ -0,0 +1,40 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED 1
+
+typedef struct {
+ UINT8 Register;
+ UINT32 Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+ PCH_GPIO_DEV Use_Sel;
+ PCH_GPIO_DEV Use_Sel2;
+ PCH_GPIO_DEV Use_Sel3;
+ PCH_GPIO_DEV Io_Sel;
+ PCH_GPIO_DEV Io_Sel2;
+ PCH_GPIO_DEV Io_Sel3;
+ PCH_GPIO_DEV Lvl;
+ PCH_GPIO_DEV Lvl2;
+ PCH_GPIO_DEV Lvl3;
+ PCH_GPIO_DEV Inv;
+ PCH_GPIO_DEV Blink;
+ PCH_GPIO_DEV Rst_Sel;
+ PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicy=
BoardConfigLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/Pei=
PolicyBoardConfigLib.h
new file mode 100644
index 0000000000..7615461e1e
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyBoardCo=
nfigLib.h
@@ -0,0 +1,141 @@
+/** @file
+ Header file for the PeiPolicyBoardConfig Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_POLICY_BOARD_CONFIG_LIB_H_
+#define _PEI_POLICY_BOARD_CONFIG_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ This function performs PEI CPU Pre-Memory Policy update by board configu=
ration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ This function performs PEI ME Pre-Memory Policy update by board configur=
ation.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ This function performs PEI PCH Pre-Memory Policy update by board configu=
ration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ This function performs PEI SA Pre-Memory Policy update by board configur=
ation.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ This function performs PEI CPU Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs PEI ME Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs PEI PCH Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs PEI SA Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs PEI SI Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicy=
InitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyI=
nitLib.h
new file mode 100644
index 0000000000..ddcf839cfc
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyInitLib=
.h
@@ -0,0 +1,38 @@
+/** @file
+ Header file for the PolicyInitPei Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _POLICY_INIT_PEI_LIB_H_
+#define _POLICY_INIT_PEI_LIB_H_
+
+/**
+ Initialize Intel PEI Platform Policy
+
+ @param[in] FirmwareConfiguration It uses to skip specific policy init =
that depends
+ on the 'FirmwareConfiguration' varaib=
le.
+**/
+VOID
+EFIAPI
+PeiPolicyInitPreMem (
+ IN UINT8 FirmwareConfiguration
+ );
+
+/**
+ Initialize Intel PEI Platform Policy
+
+ @param[in] PeiServices General purpose services available to =
every PEIM.
+ @param[in] FirmwareConfiguration It uses to skip specific policy init t=
hat depends
+ on the 'FirmwareConfiguration' varaibl=
e.
+**/
+VOID
+EFIAPI
+PeiPolicyInit (
+// IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINT8 FirmwareConfiguration
+ );
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformI=
nitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformIni=
tLib.h
new file mode 100644
index 0000000000..25ed2679d2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformInitLib.h
@@ -0,0 +1,23 @@
+/** @file
+ Function prototype of PlatformInitLib.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INIT_LIB_H_
+#define _PLATFORM_INIT_LIB_H_
+
+VOID
+PlatformLateInit (
+ VOID
+ );
+
+VOID
+InitSerialPort (
+ VOID
+ );
+
+#endif // _PLATFORM_INIT_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables=
.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables.h
new file mode 100644
index 0000000000..3330a48e4d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables.h
@@ -0,0 +1,51 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef PCH_HSIO_PTSSTABLES_H_
+#define PCH_HSIO_PTSSTABLES_H_
+
+#include <PchAccess.h>
+
+///
+/// SATA PTSS Topology Types
+///
+typedef enum {
+ PchSataTopoUnknown =3D 0x00,
+ PchSataTopoIsata,
+ PchSataTopoDirectConnect,
+ PchSataTopoFlex,
+ PchSataTopoM2
+} PCH_SATA_TOPOLOGY;
+
+///
+/// PCIe PTSS Topology Types
+///
+typedef enum {
+ PchPcieTopoUnknown =3D 0x00,
+ PchPcieTopox1,
+ PchPcieTopox4,
+ PchPcieTopoSataE,
+ PchPcieTopoM2
+} PCH_PCIE_TOPOLOGY;
+
+///
+/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH.
+///
+typedef struct {
+ UINT8 LaneNum;
+ UINT8 PhyMode;
+ UINT16 Offset;
+ UINT32 Value;
+ UINT32 BitMask;
+} PCH_SBI_PTSS_HSIO_TABLE;
+
+typedef struct {
+ PCH_SBI_PTSS_HSIO_TABLE PtssTable;
+ UINT16 Topology;
+} HSIO_PTSS_TABLES;
+
+#endif // PCH_HSIO_PTSSTABLES_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrid=
eTable.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrideT=
able.h
new file mode 100644
index 0000000000..f8f32610d1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h
@@ -0,0 +1,106 @@
+/** @file
+ PCIe Device Override Table
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIE_DEVICE_OVERRIDE_TABLE_H_
+#define _PCIE_DEVICE_OVERRIDE_TABLE_H_
+
+#include <ConfigBlock/PcieRpConfig.h>
+#include <IndustryStandard/Pci22.h>
+
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_NETWORK_OTHER 0x80
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] =
=3D {
+ //
+ // Intel PRO/Wireless
+ //
+ { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel WiMAX/WiFi Link
+ //
+ { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, =
0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Crane Peak WLAN NIC
+ //
+ { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Crane Peak w/BT WLAN NIC
+ //
+ { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Kelsey Peak WiFi, WiMax
+ //
+ { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 105
+ //
+ { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 135
+ //
+ { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 2200
+ //
+ { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 2230
+ //
+ { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 6235
+ //
+ { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel CampPeak 2 Wifi
+ //
+ { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+ //
+ // Intel WilkinsPeak 1 Wifi
+ //
+ { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, =
0, 0 },
+ { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, =
0, 0 },
+ //
+ // Intel Wilkins Peak 2 Wifi
+ //
+ { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, =
0, 0 },
+ { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, =
0, 0 },
+ //
+ // Intel Wilkins Peak PF Wifi
+ //
+ { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP=
cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+
+ //
+ // End of Table
+ //
+ { 0 }
+};
+
+#endif
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h b/Plat=
form/Intel/CometlakeOpenBoardPkg/Include/Platform.h
new file mode 100644
index 0000000000..cabd0e167a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h
@@ -0,0 +1,33 @@
+/** @file
+ This header file provides platform specific definitions used
+ by other modules for platform specific initialization.
+ This is not suitable for consumption by ASL or VRF files.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_H_
+#define _PLATFORM_H_
+
+//#include "CommonDefinitions.h"
+#include "PchAccess.h"
+#include "SaAccess.h"
+
+//
+// Need minimum of 48MB during PEI phase for IAG and some buffer for boot.
+//
+#define PEI_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) =
// 80MB + 256MB
+#define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) =
// 80MB + 256MB
+
+#define FLASH_BLOCK_SIZE 0x10000
+
+#define CPU_EXTERNAL_CLOCK_FREQ 0x64
+#define CPU_FREQUENCY_MODE_100 0x64
+#define FREQUENCY_RESOLUTION_3182 0xc6e
+#define NDIVIDER_BASE_VALUE 0x19d
+#define MDIVIDER_VALUE_13 0xd
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h=
b/Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h
new file mode 100644
index 0000000000..9a4b156d5f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h
@@ -0,0 +1,29 @@
+/** @file
+Defines Platform BoardIds
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_BOARD_ID_H_
+#define _PLATFORM_BOARD_ID_H_
+
+#define FlavorUnknown 0x0
+#define FlavorMobile 0x1
+#define FlavorDesktop 0x2
+#define FlavorWorkstation 0x3
+#define FlavorUpServer 0x4
+#define FlavorEmbedded 0x5
+#define FlavorPlatformMax 0x6
+
+#define TypeUnknown 0x0
+#define TypeTrad 0x1
+#define TypeUltUlx 0x2
+
+#define BoardIdCometLakeULpddr3Rvp 0x1
+
+#define BoardIdUnknown1 0xffff
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNv=
sArea.h b/Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNvsAr=
ea.h
new file mode 100644
index 0000000000..ee927ae629
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,47 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xd=
c }
+
+#define GLOBAL_NVS_AREA_REVISION 16
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#include <Acpi/GlobalNvsAreaDef.h>
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+ EFI_GLOBAL_NVS_AREA *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h b/Platfor=
m/Intel/CometlakeOpenBoardPkg/Include/Setup.h
new file mode 100644
index 0000000000..00863d3fa0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h
@@ -0,0 +1,144 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SETUP__H__
+#define __SETUP__H__
+
+#ifndef MDEPKG_NDEBUG
+#define DEBUG_INTERFACE_FORM_ENABLE
+#endif // MDEPKG_NDEBUG
+//
+// Form class guid for the forms those will be showed on first front page.
+//
+#define FRONT_PAGE_GUID { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a,=
0xa3, 0xf, 0xdc, 0x4b, 0x44, 0x1e } }
+//
+// Form class guid for the forms those will be showed on boot maintenance =
manager menu.
+//
+#define BOOT_MAINTENANCE_GUID { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89, 0x8a,=
0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 } }
+
+// VFR common Definitions
+#define INVENTORY(Name,Value) \
+ text \
+ help =3D STRING_TOKEN(STR_EMPTY), \
+ text =3D Name, \
+ text =3D Value, \
+ flags =3D 0, \
+ key =3D 0;
+
+#define SUBTITLE(Text) subtitle text =3D Text;
+#define SEPARATOR SUBTITLE(STRING_TOKEN(STR_EMPTY))
+
+#define INTERACTIVE_TEXT(HelpToken, CaptionToken, ValueToken, Key)\
+ grayoutif TRUE;\
+ oneof varid =3D SETUP_DATA.InteractiveText,\
+ questionid =3D Key,\
+ prompt =3D CaptionToken,\
+ help =3D HelpToken,\
+ option text =3D ValueToken, value =3D 0, flags =3D INTERACTIVE =
| DEFAULT;\
+ refresh interval =3D 1 \
+ endoneof;\
+ endif;
+
+#define SUPPRESS_GRAYOUT_ENDIF endif; endif;
+#define DEFAULT_FLAG
+
+#define SYSTEM_ACCESS_KEY_ID 0xF000
+//
+// System Access defintions.
+//
+#define SYSTEM_ACCESS_GUID \
+ { 0xE770BB69, 0xBCB4, 0x4D04, { 0x9E, 0x97, 0x23, 0xFF, 0x94, 0x56, 0xFE,=
0xAC }}
+
+#define SYSTEM_PASSWORD_ADMIN 0
+#define SYSTEM_PASSWORD_USER 1
+#define ADMIN_PW_CLEAR 0
+#define ADMIN_PW_SET 1
+
+
+typedef struct _SYSTEM_ACCESS
+{
+ //
+ // Passwords
+ //
+ UINT8 Access;
+} SYSTEM_ACCESS;
+
+//
+// Record the password status.
+//
+typedef struct {
+ UINT8 AdminName;
+ UINT8 UserName;
+} EFI_PASSWORD_STATUS;
+
+//
+// Config Data
+//
+typedef struct {
+ UINT8 SerialDebug;
+ UINT8 SerialDebugBaudRate;
+ UINT8 RamDebugInterface;
+ UINT8 UartDebugInterface;
+ UINT8 Usb3DebugInterface;
+ UINT8 SerialIoDebugInterface;
+ UINT8 TraceHubDebugInterface;
+} DEBUG_CONFIG_DATA;
+
+//
+// Config Data Hob
+//
+#define DEBUG_CONFIG_DATA_HOB DEBUG_CONFIG_DATA
+
+//
+// Secure Boot Data
+//
+typedef struct{
+ UINT8 SecureBoot;
+} SECURE_BOOT_VARIABLE;
+
+#pragma pack()
+
+//
+// Varstore statement
+// Setup is EfiVarStore that is related to EFI variable with attribute 0x07
+// (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARI=
ABLE_RUNTIME_ACCESS)
+//
+#define SETUP_DATA_VARSTORE\
+ efivarstore SETUP_DATA, varid =3D 1,\
+ attribute =3D 0x7, name =3D Setup, guid =3D SETUP_GUID;
+#define SA_SETUP_VARSTORE\
+ efivarstore SA_SETUP, varid =3D 2,\
+ attribute =3D 0x7, name =3D SaSetup, guid =3D SA_SETUP_GUID;
+#define CPU_SETUP_VARSTORE\
+ efivarstore CPU_SETUP, varid =3D 3,\
+ attribute =3D 0x7, name =3D CpuSetup, guid =3D CPU_SETUP_GUID;
+#define ME_SETUP_VARSTORE\
+ efivarstore ME_SETUP, varid =3D 4,\
+ attribute =3D 0x7, name =3D MeSetup, guid =3D ME_SETUP_GUID;
+#define PCH_SETUP_VARSTORE\
+ efivarstore PCH_SETUP, varid =3D 5,\
+ attribute =3D 0x7, name =3D PchSetup, guid =3D PCH_SETUP_GUID;
+#define SI_SETUP_VARSTORE\
+ efivarstore SI_SETUP, varid =3D 6,\
+ attribute =3D 0x7, name =3D SiSetup, guid =3D SI_SETUP_GUID;
+#ifdef DEBUG_INTERFACE_FORM_ENABLE
+#define DEBUG_CONFIG_DATA_ID 0xF001
+#define DEBUG_CONFIG_DATA_VARSTORE\
+ efivarstore DEBUG_CONFIG_DATA, varid =3D DEBUG_CONFIG_DATA_ID,\
+ attribute =3D 0x7, name =3D DebugConfigData, guid =3D DEBUG_CONFIG=
_GUID;
+#endif // DEBUG_INTERFACE_FORM_ENABLE
+#define SYSTEM_ACCESS_VARSTORE\
+ varstore SYSTEM_ACCESS, varid =3D SYSTEM_ACCESS_KEY_ID,\
+ name =3D SystemAccess, guid =3D SYSTEM_ACCESS_GUID;
+#define SYSTEM_PASSWORD_VARSTORE\
+ varstore EFI_PASSWORD_STATUS,\
+ name =3D PasswordStatus, guid =3D SYSTEM_ACCESS_GUID;
+
+#define BOOT_FLOW_CONDITION_RECOVERY 2
+#define BOOT_FLOW_CONDITION_FIRST_BOOT 4
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h b/Platf=
orm/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h
new file mode 100644
index 0000000000..53822a83f6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h
@@ -0,0 +1,157 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SIO_REG_H_
+#define _SIO_REG_H_
+
+#define REG_LOGICAL_DEVICE 0x07
+#define ACTIVATE 0x30
+
+#define BASE_ADDRESS_HIGH0 0x60
+#define BASE_ADDRESS_LOW0 0x61
+#define BASE_ADDRESS_HIGH1 0x62
+#define BASE_ADDRESS_LOW1 0x63
+#define BASE_ADDRESS_HIGH2 0x64
+#define BASE_ADDRESS_LOW2 0x65
+#define BASE_ADDRESS_HIGH3 0x66
+#define BASE_ADDRESS_LOW3 0x67
+#define PRIMARY_INTERRUPT_SELECT 0x70
+#define WAKEUP_ON_IRQ_EN 0x70
+#define INTERRUPT_TYPE 0x71
+#define DMA_CHANNEL_SELECT0 0x74
+#define DMA_CHANNEL_SELECT1 0x75
+
+
+
+//
+//Port address for PILOT - III
+//
+#define PILOTIII_CHIP_ID 0x03
+#define PILOTIII_SIO_INDEX_PORT 0x04E
+#define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1)
+
+#define PILOTIII_UNLOCK 0x5A
+#define PILOTIII_LOCK 0xA5
+
+//
+// logical device in PILOT-III
+//
+#define PILOTIII_SIO_PSR 0x00
+#define PILOTIII_SIO_COM2 0x01
+#define PILOTIII_SIO_COM1 0x02
+#define PILOTIII_SIO_SWCP 0x03
+#define PILOTIII_SIO_GPIO 0x04
+#define PILOTIII_SIO_WDT 0x05
+#define PILOTIII_SIO_KCS3 0x08
+#define PILOTIII_SIO_KCS4 0x09
+#define PILOTIII_SIO_KCS5 0x0A
+#define PILOTIII_SIO_BT 0x0B
+#define PILOTIII_SIO_SMIC 0x0C
+#define PILOTIII_SIO_MAILBOX 0x0D
+#define PILOTIII_SIO_RTC 0x0E
+#define PILOTIII_SIO_SPI 0x0F
+#define PILOTIII_SIO_TAP 0x10
+//
+// Regisgers for Pilot-III
+//
+#define PILOTIII_CHIP_ID_REG 0x20
+#define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE
+#define PILOTIII_ACTIVATE ACTIVATE
+#define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
+#define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
+#define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1
+#define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1
+#define PILOTIII_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
+
+//
+// Port address for PC8374
+//
+#define PC8374_SIO_INDEX_PORT 0x02E
+#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1)
+
+//
+// Logical device in PC8374
+//
+#define PC8374_SIO_FLOPPY 0x00
+#define PC8374_SIO_PARA 0x01
+#define PC8374_SIO_COM2 0x02
+#define PC8374_SIO_COM1 0x03
+#define PC8374_SIO_MOUSE 0x05
+#define PC8374_SIO_KYBD 0x06
+#define PC8374_SIO_GPIO 0x07
+
+//
+// Registers specific for PC8374
+//
+#define PC8374_CLOCK_SELECT 0x2D
+#define PC8374_CLOCK_CONFIG 0x29
+
+//
+// Registers for PC8374
+//
+#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE
+#define PC8374_ACTIVATE ACTIVATE
+#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
+#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
+#define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
+#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0
+
+#define PC87427_SERVERIO_CNF2 0x22
+
+
+//
+// Pilot III Mailbox Data Register definitions
+//
+#define MBDAT00_OFFSET 0x00
+#define MBDAT01_OFFSET 0x01
+#define MBDAT02_OFFSET 0x02
+#define MBDAT03_OFFSET 0x03
+#define MBDAT04_OFFSET 0x04
+#define MBDAT05_OFFSET 0x05
+#define MBDAT06_OFFSET 0x06
+#define MBDAT07_OFFSET 0x07
+#define MBDAT08_OFFSET 0x08
+#define MBDAT09_OFFSET 0x09
+#define MBDAT10_OFFSET 0x0A
+#define MBDAT11_OFFSET 0x0B
+#define MBDAT12_OFFSET 0x0C
+#define MBDAT13_OFFSET 0x0D
+#define MBDAT14_OFFSET 0x0E
+#define MBDAT15_OFFSET 0x0F
+#define MBST0_OFFSET 0x10
+#define MBST1_OFFSET 0x11
+#define MBBINT_OFFSET 0x12
+
+//
+// Mailbox Bit definitions...
+//
+#define MBBINT_MBBIST_BIT 0x80
+// If both are there, use the default one
+//
+#define W83527_EXIST BIT2
+#define PC8374_EXIST BIT1
+#define PILOTIII_EXIST BIT0
+#define DEFAULT_SIO PILOTIII_EXIST
+#define DEFAULT_KDB PC8374_EXIST
+
+#define IPMI_DEFAULT_SMM_IO_BASE 0xca2
+//
+// For Pilot III
+//
+
+#define PILOTIII_SWC_BASE_ADDRESS 0xA00
+#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
+#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
+#define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86
+#define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4
+#define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5
+#define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2
+#define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3
+#define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600
+#define PILOTIII_MAILBOX_MASK 0xFFE0
+#define BMC_KCS_BASE_ADDRESS 0x0CA0
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec b/Platfo=
rm/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec
new file mode 100644
index 0000000000..1f8322eaeb
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec
@@ -0,0 +1,564 @@
+## @file
+# Module describe the entire platform configuration.
+#
+# The DEC files are used by the utilities that parse DSC and
+# INF files to generate AutoGen.c and AutoGen.h files
+# for the build infrastructure.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+
+[Defines]
+DEC_SPECIFICATION =3D 0x00010017
+PACKAGE_NAME =3D OpenBoardPkg
+PACKAGE_VERSION =3D 0.1
+PACKAGE_GUID =3D 7F1FFF90-0F5F-4980-88FE-A9E683CFBB32
+
+[Includes]
+Include
+Features/Tbt/Include
+CometlakeURvp/Include
+
+[Guids]
+
+gCometlakeOpenBoardPkgTokenSpaceGuid =3D {0xfe2ab368, 0x7cc1, 0x4de8, {0=
xb7, 0x19, 0xad, 0x56, 0xee, 0xb8, 0xcc, 0x84}}
+
+gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0=
x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+
+gTbtInfoHobGuid =3D {0x74a81eaa, 0x033c, 0x4783, {0=
xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}}
+
+gPlatformModuleTokenSpaceGuid =3D {0x69d13bf0, 0xaf91, 0x4d96, {0=
xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+
+gMeInfoSetupGuid =3D {0x78259433, 0x7b6d, 0x4db3, {0=
x9a, 0xe8, 0x36, 0xc4, 0xc2, 0xc3, 0xa1, 0x7d}}
+gRealModeFileGuid =3D {0xdf84ed23, 0x5d53, 0x423f, {0=
xaa, 0x81, 0x0f, 0x0e, 0x6f, 0x55, 0xc6, 0x9b}}
+gVirtualKeyboardDriverImageGuid =3D {0xe4735aac, 0x9c27, 0x493f, {0=
x86, 0xea, 0x9e, 0xff, 0x43, 0xd7, 0xad, 0xcd}}
+gPegConfigVariableGuid =3D {0xb414caf8, 0x8225, 0x4d6f, {0=
xb9, 0x18, 0xcd, 0xe5, 0xcb, 0x84, 0xcf, 0x0b}}
+gSaSetupVariableGuid =3D {0x72c5e28c, 0x7783, 0x43a1, {0=
x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4}}
+gMeSetupVariableGuid =3D {0x5432122d, 0xd034, 0x49d2, {0=
xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}}
+gCpuSetupVariableGuid =3D {0xb08f97ff, 0xe6e8, 0x4193, {0=
xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa, 0xdb, 0x32}}
+gCpuSmmGuid =3D {0x90d93e09, 0x4e91, 0x4b3d, {0=
x8c, 0x77, 0xc8, 0x2f, 0xf1, 0xe, 0x3c, 0x81}}
+gPchSetupVariableGuid =3D {0x4570b7f1, 0xade8, 0x4943, {0=
x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84}}
+gSiSetupVariableGuid =3D {0xAAF8E719, 0x48F8, 0x4099, {0=
xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D}}
+gDebugConfigVariableGuid =3D {0xDE0A5E74, 0x4E3E, 0x3D96, {0=
xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97}}
+gDebugConfigHobGuid =3D {0x2f6a6bb7, 0x9dc7, 0x4bf6, {0=
x94, 0x04, 0x22, 0x70, 0xc0, 0xe3, 0xbe, 0x2f}}
+gChassisIntrudeDetHobGuid =3D {0xdea43de2, 0x756b, 0x4b3b, {0=
x75, 0x1c, 0xad, 0xeb, 0x8d, 0xff, 0x56, 0xa3}}
+
+gGpioCheckConflictHobGuid =3D {0x5603f872, 0xefac, 0x40ae, {0=
xb9, 0x7e, 0x13, 0xb2, 0xf8, 0x07, 0x80, 0x21}}
+
+gAttemptUsbFirstHotkeyInfoHobGuid =3D {0x38b8e214, 0x1468, 0x4bb7, {0=
x95, 0xb1, 0x74, 0x59, 0x1e, 0x4c, 0x6e, 0x1d}}
+gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0=
x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+##
+## ChipsetInitBinary
+##
+gCnlPchLpChipsetInitTableDxGuid =3D {0xc9505bc0, 0xaa3d, 0x4056,=
{0x99, 0x95, 0x87, 0x0c, 0x8d, 0xe8, 0x59, 0x4e}}
+
+
+[Protocols]
+gTbtNvsAreaProtocolGuid =3D {0x4d6a54d1, 0xcd56, 0x47f3, {0=
x93, 0x6e, 0x7e, 0x51, 0xd9, 0x31, 0x15, 0x4f}}
+gDxeTbtPolicyProtocolGuid =3D {0x196bf9e3, 0x20d7, 0x4b7b, {0=
x89, 0xf9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}}
+
+[Ppis]
+gPeiTbtPolicyPpiGuid =3D {0xd7e7e1e6, 0xcbec, 0x4f5f, {0=
xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}}
+gPeiTbtPolicyBoardInitDonePpiGuid =3D {0x970f9c60, 0x8547, 0x49d7, { =
0xa4, 0xb, 0x1e, 0xc4, 0xbc, 0x4e, 0xe8, 0x9b}}
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+
+[PcdsFixedAtBuild]
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x1=
0001004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|=
0x10001005
+
+gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT64|0x900000=
03
+gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x90000004
+gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFED19000|UINT64|0x90000005
+gPlatformModuleTokenSpaceGuid.PcdEpMmioSize|0x1000|UINT32|0x90000006
+gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress|0xFED84000|UINT64|0x90000=
007
+gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize|0x1000|UINT32|0x90000008
+gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x9000=
0009
+gPlatformModuleTokenSpaceGuid.PcdEdramMmioSize|0x4000|UINT32|0x9000000A
+gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9000=
000B
+gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize|0x1000|UINT32|0x9000000C
+gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000000D
+gPlatformModuleTokenSpaceGuid.PcdApicIoMmioSize|0x1000|UINT32|0x9000000E
+gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xCF000000|UINT64|0x9000000F
+gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xD0000000|UINT64|0x90000010
+gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+gPlatformModuleTokenSpaceGuid.PcdPcieDockBridgeResourcePatchSmi|0x4D|UINT8=
|0x90000014
+gPlatformModuleTokenSpaceGuid.PcdCmosFastBootDefaultValue|0x01|UINT8|0x900=
00016
+gPlatformModuleTokenSpaceGuid.PcdCmosDebugPrintErrorLevelDefaultValue|0x80=
000046|UINT32|0x90000017
+gPlatformModuleTokenSpaceGuid.PcdOverClockingInterfaceSwSmi|0x72|UINT8|0x9=
0000019
+gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort|0x2F|UINT16|=
0x9000001A
+gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort|0x2E|UINT16=
|0x9000001B
+gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E
+gPlatformModuleTokenSpaceGuid.PcdRuntimeUpdateFvHeaderLength|0x48|UINT8|0x=
90000020
+gPlatformModuleTokenSpaceGuid.PcdEcExtraIoBase|0x6A0|UINT16|0x20000505
+gPlatformModuleTokenSpaceGuid.PcdFspTemporaryRamSize|0x1000|UINT32|0x10001=
003
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x=
90000015
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x9000=
0018
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UIN=
T16|0x9000001C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x900=
0001D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x90000=
01F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT=
16|0x90000021
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT1=
6|0x90000022
+
+[PcdsDynamic]
+# Board GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x0000=
0041
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x000=
00043
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x00=
0000113
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|=
0x000000114
+
+# Board Expander GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000=
044
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x0=
0000045
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x0000=
0046
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x=
00000047
+
+# TouchPanel & SDHC CD GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|=
0x00000048
+
+# PCH-LP HSIO PTSS Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x=
0000004A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x=
0000004B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT1=
6|0x0000004C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT1=
6|0x0000004D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|=
0x0000004E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|=
0x0000004F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UIN=
T16|0x00000050
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UIN=
T16|0x00000051
+
+# PCH-H HSIO PTSS Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x0=
0000052
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x0=
0000053
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16=
|0x00000054
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16=
|0x00000055
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0=
x00000056
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0=
x00000057
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT=
16|0x00000058
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT=
16|0x00000059
+
+# HDA Verb Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x000=
0005D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x000=
0005E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x000=
0005F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|=
0x00000060
+
+# SA Misc Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|=
0x00000067
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101
+
+# DRAM Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x000000=
68
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x000000=
6B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x00000=
06C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0=
000006D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|=
BOOLEAN|0x0000006E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN=
|0x0000006F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071
+
+# PEG RESET GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|=
0x00000072
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|=
0x00000073
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0=
000007A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000=
007B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0=
x0000007C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0=
x0000007D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x00=
00007E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN=
|0x0000007F
+
+# SPD Address Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x0000=
0099
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000=
009A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000=
009B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000=
009C
+
+# CA Vref Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D
+
+# USB 2.0 Port AFE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE
+
+# USB 2.0 Port Over Current Pin
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0=
x000000CF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0=
x000000D0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0=
x000000D1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0=
x000000D2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0=
x000000D3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0=
x000000D4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0=
x000000D5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0=
x000000D6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0=
x000000D7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0=
x000000D8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|=
0x000000D9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|=
0x000000DA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|=
0x000000DB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|=
0x000000DC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|=
0x000000DD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|=
0x000000DE
+
+# USB 3.0 Port Over Current Pin
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0=
x000000DF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0=
x000000E0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0=
x000000E1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0=
x000000E2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0=
x000000E3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0=
x000000E4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0=
x000000E5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0=
x000000E6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0=
x000000E7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0=
x000000E8
+
+# Misc
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x=
000000EC
+
+# TBT
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x=
000000F4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|=
0x000000F5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x00000=
0FA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x0=
0000107
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000=
108
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x=
00000109
+
+# UCMC GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x0000=
00111
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x=
000000112
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x=
4000000A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0=
x4000000B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|=
0x4000000C
+
+# 0: Type-C
+# 1: Stacked-Jack
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013
+
+# gIntelPeiGraphicsVbtGuid =3D {0x4ad46122, 0xffeb, 0x4a52, {0xbf, 0xb0, =
0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}}
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4,=
0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0x=
b0}|VOID*|0x40000014
+#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+#
+# The PCD which indicates the Memory Slot Population.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType|FALSE|=
BOOLEAN|0x00101027
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate|0|UIN=
T64|0x00000010
+
+# Board GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem|0|=
UINT32|0x001000115
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSiz=
e|0|UINT16|0x001000116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem|0=
|UINT32|0x001000117
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSi=
ze|0|UINT16|0x001000118
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio|0x0|UINT3=
2|0x0010020C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|UINT8|0x=
0010022E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32|0x0010022F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32|0x00100230
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BOOLEAN|0x001=
00231
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32|0x00100234
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWlanRootPortNumber|0x0|UINT8|0x001=
00235
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround|FALSE|BOOLEAN|=
0x00100236
+
+# UCMC GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00=
100033
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|=
0x00100034
+
+# PEG RESET GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT32|0x000000=
74
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|BOOLEAN|=
0x00000075
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT32|0x000001=
05
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|BOOLEAN|=
0x00000106
+
+# PCIE RTD3 GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x00000076
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0x00000077
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000104
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|0x00000078
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|0x00000080
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32|0x00000081
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|UINT8|0x0=
0000082
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT32|0x0000=
0083
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|BOOLEAN|0=
x00000084
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo|0|UINT8|0=
x00000085
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UINT32|0x00=
000086
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE|BOOLEAN=
|0x00000087
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|0x00000088
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32|0x00000089
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|UINT8|0x0=
000008A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT32|0x0000=
008B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|BOOLEAN|0=
x0000008C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo|0|UINT8|0=
x0000008D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UINT32|0x00=
00008E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE|BOOLEAN=
|0x0000008F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|0x00000130
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32|0x00000131
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|UINT8|0x0=
0000132
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT32|0x0000=
0133
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|BOOLEAN|0=
x00000134
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo|0|UINT8|0=
x00000135
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UINT32|0x00=
000136
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE|BOOLEAN=
|0x00000137
+
+# Root Port Clock Info
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD
+
+# GPIO Group Tier
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x00000=
0E9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x00000=
0EA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x00000=
0EB
+
+# Board related PCH PmConfig
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FALSE|BOOLEA=
N|0x000000F6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE|BOOLEAN|0=
x000000F7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE|BOOLEAN|0=
x000000F8
+
+# Misc
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|=
0x000000ED
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0=
x000000EE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BOOLEAN|0x0=
00000EF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT64|0x000000=
F0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent|FALSE|BOOLEAN|0x=
000000F1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BOOLEAN|0x00=
0000F2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|=
0x000000F9
+#gCometlakeOpenBoardPkgTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLEAN|0x00000=
0FC
+
+#PlatformInfoPcd
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLE=
AN|0x00101000
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLEAN|0x00101=
001
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BOOLEAN|0x0=
0101002
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0x00101003
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|0x00101005
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardName|L"0123456789ABCDEF012345=
6789ABCDEF"|VOID*|0x00101007
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8|0x001010=
08
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8|0x001010=
09
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBiosVersion|L"01234567890123456789=
01234567890123456789"|VOID*|0x0010100E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdReleaseDate|L"01234567890123456789=
"|VOID*|0x0010100F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdReleaseTime|L"01234567890123456789=
"|VOID*|0x00101010
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x001=
01011
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDockAttached|FALSE|BOOLEAN|0x00101=
013
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x00101016
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x00101017
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101018
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|0x0010101A
+
+# PCH Misc Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE|BOOLEAN|0=
x00000061
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x=
00000065
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosFabBoardName|0|UINT64|0x0000=
0102
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UINT64|0x000=
00103
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|=
0x00000110
+
+# Control PCD to dump default silicon policy
+gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy|FALSE|BOOLEAN|0x=
00010064
+
+# Pch SerialIo I2c Pads Termination
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1=
|UINT8|0x00000020
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1=
|UINT8|0x00000021
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1=
|UINT8|0x00000022
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1=
|UINT8|0x00000023
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1=
|UINT8|0x00000030
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1=
|UINT8|0x00000031
+#
+# The PCD which holds the pointer of Smbios Platform Info table
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT64|0x0010=
101B
+#
+# The PCD which used to enable / disable the code to use RVP Smbios Board =
Info
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FALSE|BOOLEA=
N|0x0010101C
+#
+# The PCD which holds the pointer of RVP Smbios Board Info
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|0x0010101D
+#
+# CoEngineering Custom Defaults PCD
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCoEngEnableCustomDefaults|0x0|UINT=
8|0x00100227
+#
+# The PCD which is defined to enable/disable the SMBus Alert function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0=
010101E
+#
+# The PCD which is defined to enable/disable the SATA LED function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010=
101F
+#
+# The PCD which is defined to enable/disable the VR Alert function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x0010=
1020
+#
+# The PCD which is defined to enable/disable the PCH thermal hot threshold=
function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable|FALSE|BOOLEAN|=
0x00101021
+#
+# The PCD which is defined to enable/disable the memory thermal sensor GPI=
O C/D function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnab=
le|TRUE|BOOLEAN|0x00101022
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnab=
le|TRUE|BOOLEAN|0x00101023
+#
+# The PCD defines the I2C bus number to which PSS chip connected.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101024
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UINT8|0x00101=
025
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00=
101026
+#
+# The PCD defines the USB port number to which BLE connected.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber =
|0x0|UINT8|0x00101028
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support =
|0x00|UINT8|0x00100113
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support =
|0x00|UINT8|0x00100114
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support =
|0x00|UINT8|0x00100115
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support =
|0x00|UINT8|0x00100116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support =
|0x00|UINT8|0x00100117
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support =
|0x00|UINT8|0x00100118
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport =
|FALSE|BOOLEAN|0x00100119
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport =
|FALSE|BOOLEAN|0x0010011A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport =
|FALSE|BOOLEAN|0x0010011B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSupport =
|FALSE|BOOLEAN|0x0010011C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport =
|FALSE|BOOLEAN|0x0010011D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport =
|FALSE|BOOLEAN|0x0010011F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin =
|0x00|UINT32|0x00100120
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport =
|FALSE|BOOLEAN|0x00100121
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport =
|FALSE|BOOLEAN|0x00100122
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature =
|FALSE|BOOLEAN|0x00100123
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent =
|0x0|UINT8|0x00100124
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BOOLEAN|0x00=
100212
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOOLEAN|0x001=
00213
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|=
0x00100204
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x001=
00205
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UINT32|0x=
00100209
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT32|0x00=
10020A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|0x0010020B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT32|0x00100=
20F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UINT32|0x001=
00210
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio =
|0x0|UINT32|0x00100126
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber =
|0x0|UINT8|0x00100127
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x00100200
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio =
|0x0|UINT32|0x00100125
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x00100201
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALSE|BOOLEAN|=
0x00100202
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0=
x00100203
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x00100215
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT64|0x0010=
0217
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8|0x00100039
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UINT8|0x0010=
003A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|UINT8|0x0=
010003B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8|0x0010003C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UINT8|0x0010=
003D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|UINT8|0x0=
010003E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8|0x0010003F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UINT8|0x0010=
0040
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|UINT8|0x0=
0100041
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8|0x00100042
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UINT8|0x0010=
0043
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|UINT8|0x0=
0100044
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8|0x00100045
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UINT8|0x0010=
0046
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|UINT8|0x0=
0100047
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8|0x00100048
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UINT8|0x0010=
0049
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|UINT8|0x0=
010004A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed =
|0x0|UINT8|0x00100128
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed =
|0x0|UINT8|0x00100129
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed =
|0x0|UINT8|0x0010012A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed =
|0x0|UINT8|0x0010012B
+
+# Super IO Pcd
+gPlatformModuleTokenSpaceGuid.PcdH8S2113Present|TRUE|BOOLEAN|0xF0000100
+gPlatformModuleTokenSpaceGuid.PcdNat87393Present|TRUE|BOOLEAN|0xF0000104
+gPlatformModuleTokenSpaceGuid.PcdNct677FPresent|TRUE|BOOLEAN|0xF0000105
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport =
|FALSE|BOOLEAN|0x00100112
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin =
|0x00|UINT32|0x00100111
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control =
|0x00|UINT8|0x00100103
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control =
|0x00|UINT8|0x00100104
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|=
0x00100221
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x0010020E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x0010020D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCmlURtd3TableEnable|FALSE|BOOLEAN|=
0x0010022C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported|0x00|UINT8|0x0=
010004B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor =
|FALSE|BOOLEAN|0x00100105
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO =
|FALSE|BOOLEAN|0x0010010A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM =
|FALSE|BOOLEAN|0x00100107
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO =
|FALSE|BOOLEAN|0x00100108
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON =
|FALSE|BOOLEAN|0x00100109
+
+[PcdsDynamicEx]
+
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|=
0xF0000062
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN|=
0xF0000000
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEAN=
|0x000000115
+
--=20
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From: "Kathappan Esakkithevar" <kathappan.esakkithevar@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
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Prince Agyeman <prince.agyeman@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 2/7]
CometlakeOpenBoardPkg/CometlakeURvp: Add headers
Date: Wed, 12 Feb 2020 00:42:36 +0530
Message-Id: <20200211191241.53188-3-kathappan.esakkithevar@intel.com>
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280
Header files for the CometlakeURvp board instance.
Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../CometlakeURvp/Include/Fdf/FlashMapInclude.fdf | 49 ++++++++
.../CometlakeURvp/Include/PeiPlatformHookLib.h | 131 +++++++++++++++++=
++++
.../CometlakeURvp/Include/PeiPlatformLib.h | 40 +++++++
.../CometlakeURvp/Include/PlatformBoardConfig.h | 105 +++++++++++++++++
.../CometlakeURvp/Include/PlatformInfo.h | 44 +++++++
5 files changed, 369 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl=
ude/Fdf/FlashMapInclude.fdf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl=
ude/PeiPlatformHookLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl=
ude/PeiPlatformLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl=
ude/PlatformBoardConfig.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl=
ude/PlatformInfo.h
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf=
/FlashMapInclude.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/I=
nclude/Fdf/FlashMapInclude.fdf
new file mode 100644
index 0000000000..d9959a79d0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashM=
apInclude.fdf
@@ -0,0 +1,49 @@
+## @file
+# FDF file for the CometlakeURvp board.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D#
+# 8 M BIOS - for FSP wrapper
+#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D#
+DEFINE FLASH_BASE =3D 0x=
FF800000 #
+DEFINE FLASH_SIZE =3D 0x=
00800000 #
+DEFINE FLASH_BLOCK_SIZE =3D 0x=
00010000 #
+DEFINE FLASH_NUM_BLOCKS =3D 0x=
00000080 #
+#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D#
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x=
00000000 # Flash addr (0xFF800000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D 0x=
00040000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x=
00000000 # Flash addr (0xFF800000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0x=
0001E000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D 0x=
0001E000 # Flash addr (0xFF81E000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D 0x=
00002000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x=
00020000 # Flash addr (0xFF820000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x=
00020000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x=
00040000 # Flash addr (0xFF840000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x=
00050000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x=
00090000 # Flash addr (0xFF890000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x=
00070000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x=
00100000 # Flash addr (0xFF900000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x=
00090000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x=
00190000 # Flash addr (0xFF990000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x=
00190000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x=
00320000 # Flash addr (0xFFB20000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x=
00170000 #
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x=
00490000 # Flash addr (0xFFC90000)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x=
000B0000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x=
00540000 # Flash addr (0xFFD40000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x=
00070000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x=
005B0000 # Flash addr (0xFFDB0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x=
000EC000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x=
0069C000 # Flash addr (0xFFE9C000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x=
00014000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =3D 0x=
006B0000 # Flash addr (0xFFEB0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize =3D 0x=
00010000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x=
006C0000 # Flash addr (0xFFEC0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x=
00140000 #
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pei=
PlatformHookLib.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl=
ude/PeiPlatformHookLib.h
new file mode 100644
index 0000000000..690054d2e9
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfor=
mHookLib.h
@@ -0,0 +1,131 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_HOOK_LIB_H_
+#define _PEI_PLATFORM_HOOK_LIB_H_
+
+#include <PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+
+
+//EC Command to provide one byte of debug indication
+#define BSSB_DEBUG_INDICATION 0xAE
+/**
+ Configure EC for specific devices
+
+ @param[in] PchLan - The PchLan of PCH_SETUP variable.
+ @param[in] BootMode - The current boot mode.
+**/
+VOID
+EcInit (
+ IN UINT8 PchLan,
+ IN EFI_BOOT_MODE BootMode
+ );
+
+/**
+ Checks if Premium PMIC present
+
+ @retval TRUE if present
+ @retval FALSE it discrete/other PMIC
+**/
+BOOLEAN
+IsPremiumPmicPresent (
+ VOID
+ );
+
+/**
+ Pmic Programming to supprort LPAL Feature
+
+ @retval NONE
+**/
+VOID
+PremiumPmicDisableSlpS0Voltage (
+ VOID
+ );
+
+/**
+Pmic Programming to supprort LPAL Feature
+ @retval NONE
+**/
+VOID
+PremiumPmicEnableSlpS0Voltage(
+ VOID
+ );
+
+/**
+ Do platform specific programming pre-memory. For example, EC init, Chips=
et programming
+
+ @retval Status
+**/
+EFI_STATUS
+PlatformSpecificInitPreMem (
+ VOID
+ );
+
+/**
+ Do platform specific programming post-memory.
+
+ @retval Status
+**/
+EFI_STATUS
+PlatformSpecificInit (
+ VOID
+ );
+
+/**
+ Configure GPIO and SIO Before Memory is ready.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+ VOID
+ );
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ VOID
+ );
+
+/**
+Voltage Margining Routine
+
+@retval EFI_SUCCESS Operation success
+**/
+EFI_STATUS
+VoltageMarginingRoutine(
+ VOID
+ );
+
+/**
+ Detect recovery mode
+
+ @retval EFI_SUCCESS System in Recovery Mode
+ @retval EFI_UNSUPPORTED System doesn't support Recovery Mode
+ @retval EFI_NOT_FOUND System is not in Recovery Mode
+**/
+EFI_STATUS
+IsRecoveryMode (
+ VOID
+ );
+
+/**
+ Early board Configuration before Memory is ready.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+ VOID
+ );
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pei=
PlatformLib.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/=
PeiPlatformLib.h
new file mode 100644
index 0000000000..3443479a52
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfor=
mLib.h
@@ -0,0 +1,40 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED 1
+
+typedef struct {
+ UINT8 Register;
+ UINT32 Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+ PCH_GPIO_DEV Use_Sel;
+ PCH_GPIO_DEV Use_Sel2;
+ PCH_GPIO_DEV Use_Sel3;
+ PCH_GPIO_DEV Io_Sel;
+ PCH_GPIO_DEV Io_Sel2;
+ PCH_GPIO_DEV Io_Sel3;
+ PCH_GPIO_DEV Lvl;
+ PCH_GPIO_DEV Lvl2;
+ PCH_GPIO_DEV Lvl3;
+ PCH_GPIO_DEV Inv;
+ PCH_GPIO_DEV Blink;
+ PCH_GPIO_DEV Rst_Sel;
+ PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pla=
tformBoardConfig.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Inc=
lude/PlatformBoardConfig.h
new file mode 100644
index 0000000000..4d286b897a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformBo=
ardConfig.h
@@ -0,0 +1,105 @@
+/** @file
+ Header file for Platform Boards Configurations.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include <ConfigBlock.h>
+#include <PchPolicyCommon.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <GpioConfig.h>
+#include <TbtBoardInfo.h>
+
+#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1)
+#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16)=
& 0xFFF0))
+
+#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001
+#define BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001
+#define BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001
+#define BOARD_NO_BATTERY_SUPPORT 0
+#define BOARD_REAL_BATTERY_SUPPORTED BIT0
+#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1
+
+#pragma pack(1)
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block=
Header
+} BOARD_CONFIG_BLOCK;
+
+typedef struct {
+ UINT8 GpioSupport;
+ UINT32 WakeGpioNo;
+ UINT8 HoldRstExpanderNo;
+ UINT32 HoldRstGpioNo;
+ BOOLEAN HoldRstActive;
+ UINT8 PwrEnableExpanderNo;
+ UINT32 PwrEnableGpioNo;
+ BOOLEAN PwrEnableActive;
+} SWITCH_GRAPHIC_GPIO;
+
+typedef struct {
+ UINT8 ClkReqNumber : 4;
+ UINT8 ClkReqSupported : 1;
+ UINT8 DeviceResetPadActiveHigh : 1;
+ UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+ UINT8 Section;
+ UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef enum {
+ BoardGpioTypePch,
+ BoardGpioTypeExpander,
+ BoardGpioTypeNotSupported =3D 0xFF
+} BOARD_GPIO_TYPE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
+ union {
+ UINT32 Pin;
+ EXPANDER_GPIO_CONFIG Expander;
+ } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAG=
E from PCH RC.
+#define NOT_USED 0xFF
+#define FREE_RUNNING 0x80
+#define LAN_CLOCK 0x70
+#define PCIE_PEG 0x40
+#define PCIE_PCH 0x00
+
+typedef struct {
+ UINT32 ClockUsage;
+ UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+ UINT64 Blob;
+ BOARD_GPIO_CONFIG BoardGpioConfig;
+ ROOT_PORT_CLK_INFO Info;
+ PCIE_CLOCK_CONFIG PcieClock;
+} PCD64_BLOB;
+
+typedef union {
+ UINT32 Blob;
+ USB20_AFE Info;
+} PCD32_BLOB;
+
+#ifndef IO_EXPANDER_DISABLED
+#define IO_EXPANDER_DISABLED 0xFF
+#endif
+
+#define SPD_DATA_SIZE 512
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pla=
tformInfo.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pl=
atformInfo.h
new file mode 100644
index 0000000000..f8854485b4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformIn=
fo.h
@@ -0,0 +1,44 @@
+/** @file
+ GUID used for Platform Info Data entries in the HOB list.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INFO_H_
+#define _PLATFORM_INFO_H_
+
+#pragma pack(1)
+
+///
+/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h
+///
+typedef UINT32 PCH_GPIO_PAD; //Copied from GpioConfig.h (need to change it=
based on include)
+
+typedef struct {
+UINT8 Expander;
+UINT8 Pin;
+UINT16 Reserved; // Reserved for future use
+} IO_EXPANDER_PAD;
+
+typedef union {
+PCH_GPIO_PAD PchGpio;
+IO_EXPANDER_PAD IoExpGpio;
+} GPIO_PAD_CONFIG;
+
+typedef struct {
+UINT8 GpioType; // 0: Disabled (no GPIO support), 1: PCH=
, 2: I/O Expander
+UINT8 Reserved[3]; // Reserved for future use
+GPIO_PAD_CONFIG GpioData;
+} PACKED_GPIO_CONFIG;
+
+typedef union {
+PACKED_GPIO_CONFIG PackedGpio;
+UINT64 Data64;
+} COMMON_GPIO_CONFIG;
+
+#pragma pack()
+
+#endif
+
--=20
2.16.2.windows.1
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From: "Kathappan Esakkithevar" <kathappan.esakkithevar@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
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Prince Agyeman <prince.agyeman@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 3/7] CometlakeOpenBoardPkg:
Add library instances
Date: Wed, 12 Feb 2020 00:42:37 +0530
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280
Common package library instances.
* BaseAcpiTimerLib - Support for ACPI timer services.
* BaseGpioExpanderLib - Support for the TCA6424 IO expander.
* DxePolicyUpdateLib - Policy update in DXE.
* DxeTbtPolicyLib - DXE Thunderbolt policy initialization.
* PeiDTbtInitLib - PEI discrete Thunderbolt initialization services.
* PeiFspPolicyInitLib - PEI Intel FSP policy initialization.
* PeiI2cAccessLib - Provides I2C read and write services.
* PeiPolicyInitLib - Policy initialization in PEI.
* PeiPolicyUpdateLib - Policy update in PEI.
* PeiSiliconPolicyUpdateLibFsp - PEI FSP silicon policy initialization.
* PeiTbtPolicyLib - PEI Thunderbolt policy initialization.
* SecFspWrapperPlatformSecLib - FSP wrapper PlatformSecLib instance.
* TbtCommonLib - Common Thunderbolt services.
* PeiHdaVerbTableLib - PEI Intel HD Audio Verb Table library.
* BaseGpioExpanderLib - Common Gpio Expander functions
Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
---
.../Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c | 148 ++
.../Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf | 45 +
.../Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h | 24 +
.../Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c | 316 +++
.../Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf | 60 +
.../Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c | 206 ++
.../Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf | 51 +
.../Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h | 19 +
.../Private/PeiDTbtInitLib/PeiDTbtInitLib.c | 567 ++++++
.../Private/PeiDTbtInitLib/PeiDTbtInitLib.inf | 45 +
.../PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c | 460 +++++
.../PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c | 121 ++
.../PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c | 77 +
.../PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c | 743 +++++++
.../PeiFspPolicyInitLib/PeiFspPolicyInitLib.c | 223 +++
.../PeiFspPolicyInitLib/PeiFspPolicyInitLib.h | 233 +++
.../PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 162 ++
.../PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c | 848 ++++++++
.../PeiFspSecurityPolicyInitLib.c | 70 +
.../PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c | 96 +
.../PeiFspMiscUpdUpdateLib.c | 100 +
.../PeiFspPolicyUpdateLib.c | 124 ++
.../PeiMiscPolicyUpdate.h | 25 +
.../PeiPchPolicyUpdate.c | 60 +
.../PeiPchPolicyUpdate.h | 27 +
.../PeiPchPolicyUpdatePreMem.c | 39 +
.../PeiSaPolicyUpdate.c | 85 +
.../PeiSaPolicyUpdate.h | 30 +
.../PeiSaPolicyUpdatePreMem.c | 87 +
.../PeiSiliconPolicyUpdateLibFsp.inf | 140 ++
.../Library/AcpiTimerLib/AcpiTimerLib.c | 394 ++++
.../Library/AcpiTimerLib/BaseAcpiTimerLib.c | 48 +
.../Library/AcpiTimerLib/BaseAcpiTimerLib.inf | 54 +
.../Library/AcpiTimerLib/BaseAcpiTimerLib.uni | 15 +
.../BaseGpioExpanderLib/BaseGpioExpanderLib.c | 308 +++
.../BaseGpioExpanderLib/BaseGpioExpanderLib.inf | 36 +
.../Library/PeiHdaVerbTableLib/PchHdaVerbTables.c | 2053 ++++++++++++++++=
++++
.../PeiHdaVerbTableLib/PeiHdaVerbTableLib.c | 137 ++
.../PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf | 69 +
.../Library/PeiI2cAccessLib/PeiI2cAccessLib.c | 115 ++
.../Library/PeiI2cAccessLib/PeiI2cAccessLib.inf | 39 +
.../DxePolicyUpdateLib/DxeCpuPolicyUpdate.c | 88 +
.../Library/DxePolicyUpdateLib/DxeMePolicyUpdate.c | 105 +
.../Library/DxePolicyUpdateLib/DxeMePolicyUpdate.h | 90 +
.../DxePolicyUpdateLib/DxePchPolicyUpdate.c | 40 +
.../DxePolicyUpdateLib/DxePolicyUpdateLib.inf | 59 +
.../Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.c | 58 +
.../Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.h | 25 +
.../Library/PeiPolicyInitLib/PeiCpuPolicyInit.h | 37 +
.../Library/PeiPolicyInitLib/PeiMePolicyInit.h | 23 +
.../Library/PeiPolicyInitLib/PeiPolicyInit.c | 65 +
.../Library/PeiPolicyInitLib/PeiPolicyInit.h | 23 +
.../Library/PeiPolicyInitLib/PeiPolicyInitLib.inf | 62 +
.../Library/PeiPolicyInitLib/PeiPolicyInitPreMem.c | 60 +
.../Library/PeiPolicyInitLib/PeiSaPolicyInit.c | 114 ++
.../Library/PeiPolicyInitLib/PeiSaPolicyInit.h | 58 +
.../Library/PeiPolicyInitLib/PeiSiPolicyInit.h | 22 +
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c | 80 +
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h | 32 +
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c | 108 +
.../Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c | 49 +
.../Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.h | 14 +
.../PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c | 32 +
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 518 +++++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.h | 24 +
.../PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c | 114 ++
.../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 273 +++
.../Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c | 243 +++
.../Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h | 53 +
.../PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c | 213 ++
.../Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c | 169 ++
.../Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h | 18 +
72 files changed, 11368 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/DxeTbtPolicyLib/DxeTbtPolicyLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/DxeTbtPolicyLib/DxeTbtPolicyLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/PeiDxeSmmTbtCommonLib/TbtCommonLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/PeiTbtPolicyLib/PeiTbtPolicyLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/Private/PeiDTbtInitLib/PeiDTbtInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Libra=
ry/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library=
/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerL=
ib/AcpiTimerLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerL=
ib/BaseAcpiTimerLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerL=
ib/BaseAcpiTimerLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerL=
ib/BaseAcpiTimerLib.uni
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioEx=
panderLib/BaseGpioExpanderLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioEx=
panderLib/BaseGpioExpanderLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerb=
TableLib/PchHdaVerbTables.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerb=
TableLib/PeiHdaVerbTableLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerb=
TableLib/PeiHdaVerbTableLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAcce=
ssLib/PeiI2cAccessLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAcce=
ssLib/PeiI2cAccessLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Dxe=
PolicyUpdateLib/DxeCpuPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Dxe=
PolicyUpdateLib/DxeMePolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Dxe=
PolicyUpdateLib/DxeMePolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Dxe=
PolicyUpdateLib/DxePchPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Dxe=
PolicyUpdateLib/DxePolicyUpdateLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Dxe=
PolicyUpdateLib/DxeSaPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Dxe=
PolicyUpdateLib/DxeSaPolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiCpuPolicyInit.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiMePolicyInit.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiPolicyInit.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiPolicyInit.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiPolicyInitLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiPolicyInitPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiSaPolicyInit.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiSaPolicyInit.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyInitLib/PeiSiPolicyInit.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiCpuPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiCpuPolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiMePolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiMePolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiMePolicyUpdatePreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiPchPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiPchPolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiPolicyUpdateLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiSaPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiSaPolicyUpdate.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiSiPolicyUpdate.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/Pei=
PolicyUpdateLib/PeiSiPolicyUpdate.h
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeT=
btPolicyLib/DxeTbtPolicyLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Featur=
es/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c
new file mode 100644
index 0000000000..3e3203b841
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolic=
yLib/DxeTbtPolicyLib.c
@@ -0,0 +1,148 @@
+/** @file
+ This file is DxeTbtPolicyLib library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <DxeTbtPolicyLibrary.h>
+#include <TbtBoardInfo.h>
+#include <Protocol/DxeTbtPolicy.h>
+#include <Guid/HobList.h>
+#include <Library/HobLib.h>
+
+
+/**
+ Update Tbt Policy Callback
+**/
+
+VOID
+EFIAPI
+UpdateTbtPolicyCallback (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig;
+
+ DxeTbtConfig =3D NULL;
+ Status =3D EFI_NOT_FOUND;
+ DEBUG ((DEBUG_INFO, "UpdateTbtPolicyCallback\n"));
+
+ Status =3D gBS->LocateProtocol (
+ &gDxeTbtPolicyProtocolGuid,
+ NULL,
+ (VOID **) &DxeTbtConfig
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n"));
+ } else {
+
+ }
+
+ return;
+}
+
+/**
+ Print DXE TBT Policy
+**/
+VOID
+TbtPrintDxePolicyConfig (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Index;
+ DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig;
+
+ DEBUG ((DEBUG_INFO, "TbtPrintDxePolicyConfig Start\n"));
+
+ DxeTbtConfig =3D NULL;
+ Status =3D EFI_NOT_FOUND;
+ Status =3D gBS->LocateProtocol (
+ &gDxeTbtPolicyProtocolGuid,
+ NULL,
+ (VOID **) &DxeTbtConfig
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n"));
+ }
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Print DTBT Policy
+ //
+ DEBUG ((DEBUG_ERROR, " =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D DXE TBT POLICY =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D \n"));
+ for (Index =3D 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) {
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieExtr=
aBusRsvd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcie=
ExtraBusRsvd));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemR=
svd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieMemRs=
vd));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemA=
ddrRngMax =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPci=
eMemAddrRngMax));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMem=
Rsvd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPciePMem=
Rsvd));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMem=
AddrRngMax =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPc=
iePMemAddrRngMax));
+ }
+
+ //
+ // Print TBT Common Policy
+ //
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAspm =3D %x\n", Dx=
eTbtConfig->TbtCommonConfig.TbtAspm));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtL1SubStates =3D %x=
\n", DxeTbtConfig->TbtCommonConfig.TbtL1SubStates));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotNotify =3D %x\n=
", DxeTbtConfig->TbtCommonConfig.TbtHotNotify));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotSMI =3D %x\n", =
DxeTbtConfig->TbtCommonConfig.TbtHotSMI));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtLtr =3D %x\n", Dxe=
TbtConfig->TbtCommonConfig.TbtLtr));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtPtm =3D %x\n", Dxe=
TbtConfig->TbtCommonConfig.TbtPtm));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtSetClkReq =3D %x\n=
", DxeTbtConfig->TbtCommonConfig.TbtSetClkReq));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport =3D =
%x\n", DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.SecurityMode =3D %x\n=
", DxeTbtConfig->TbtCommonConfig.SecurityMode));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Gpio5Filter =3D %x\n"=
, DxeTbtConfig->TbtCommonConfig.Gpio5Filter));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TrA0OsupWa =3D %x\n",=
DxeTbtConfig->TbtCommonConfig.TrA0OsupWa));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch =3D %x\=
n", DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3Tbt =3D %x\n", Dx=
eTbtConfig->TbtCommonConfig.Rtd3Tbt));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay =3D %=
x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq =3D %x\=
n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay =
=3D %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Win10Support =3D %x\n=
", DxeTbtConfig->TbtCommonConfig.Win10Support));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity =
=3D %x\n", DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity));
+ DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.ControlIommu =3D %x\n=
", DxeTbtConfig->TbtCommonConfig.ControlIommu));
+ return;
+}
+
+/**
+ Install Tbt Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b=
uffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallTbtPolicy (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ DXE_TBT_POLICY_PROTOCOL *DxeTbtPolicy;
+
+ DEBUG ((DEBUG_INFO, "Install DXE TBT Policy\n"));
+
+ DxeTbtPolicy =3D NULL;
+ //Alloc memory for DxeTbtPolicy
+ DxeTbtPolicy =3D (DXE_TBT_POLICY_PROTOCOL *) AllocateZeroPool (sizeof (D=
XE_TBT_POLICY_PROTOCOL));
+ if (DxeTbtPolicy =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status =3D gBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gDxeTbtPolicyProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ DxeTbtPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Install Tbt Secure Boot List protocol failed\n")=
);
+ }
+ return Status;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeT=
btPolicyLib/DxeTbtPolicyLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Feat=
ures/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf
new file mode 100644
index 0000000000..eafe2ae56a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolic=
yLib/DxeTbtPolicyLib.inf
@@ -0,0 +1,45 @@
+## @file
+# Component description file for Tbt functionality
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+INF_VERSION =3D 0x00010017
+BASE_NAME =3D DxeTbtPolicyLib
+FILE_GUID =3D 28ABF346-4E52-4BD3-b1FF-63BA7563C9D4
+VERSION_STRING =3D 1.0
+MODULE_TYPE =3D BASE
+LIBRARY_CLASS =3D DxeTbtPolicyLib
+
+
+[LibraryClasses]
+BaseMemoryLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+HobLib
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+CometlakeOpenBoardPkg/OpenBoardPkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+DxeTbtPolicyLib.c
+
+
+[Guids]
+gEfiEndOfDxeEventGroupGuid
+gTbtInfoHobGuid
+
+[Protocols]
+gDxeTbtPolicyProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeT=
btPolicyLib/DxeTbtPolicyLibrary.h b/Platform/Intel/CometlakeOpenBoardPkg/Fe=
atures/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h
new file mode 100644
index 0000000000..6603518f0a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolic=
yLib/DxeTbtPolicyLibrary.h
@@ -0,0 +1,24 @@
+/** @file
+ Header file for the DxeTBTPolicy library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_TBT_POLICY_LIBRARY_H_
+#define _DXE_TBT_POLICY_LIBRARY_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <ConfigBlock.h>
+//#include <SetupVariable.h>
+#include <Guid/EventGroup.h>
+
+#endif // _DXE_TBT_POLICY_LIBRARY_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiD=
xeSmmTbtCommonLib/TbtCommonLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Fea=
tures/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c
new file mode 100644
index 0000000000..c843175f82
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTb=
tCommonLib/TbtCommonLib.c
@@ -0,0 +1,316 @@
+/** @file
+ PeiTbtInit library implementition with empty functions.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DebugLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/TbtCommonLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/GpioLib.h>
+
+
+/**
+ Selects the proper TBT Root port to assign resources
+ based on the user input value
+
+ @param[in] SetupData Pointer to Setup data
+
+ @retval TbtSelectorChosen Rootport number.
+**/
+VOID
+GetRootporttoSetResourcesforTbt (
+ IN UINTN RpIndex,
+ OUT UINT8 *RsvdExtraBusNum,
+ OUT UINT16 *RsvdPcieMegaMem,
+ OUT UINT8 *PcieMemAddrRngMax,
+ OUT UINT16 *RsvdPciePMegaMem,
+ OUT UINT8 *PciePMemAddrRngMax,
+ OUT BOOLEAN *SetResourceforTbt
+ )
+{
+ UINTN TbtRpNumber;
+ TbtRpNumber =3D (UINTN) PcdGet8 (PcdDTbtPcieRpNumber);
+
+ if (RpIndex =3D=3D (TbtRpNumber - 1)) {
+ *RsvdExtraBusNum =3D PcdGet8 (PcdDTbtPcieExtraBusRsvd);
+ *RsvdPcieMegaMem =3D PcdGet16 (PcdDTbtPcieMemRsvd);
+ *PcieMemAddrRngMax =3D PcdGet8 (PcdDTbtPcieMemAddrRngMax);
+ *RsvdPciePMegaMem =3D PcdGet16 (PcdDTbtPciePMemRsvd);
+ *PciePMemAddrRngMax =3D PcdGet8 (PcdDTbtPciePMemAddrRngMax);
+ *SetResourceforTbt =3D TRUE;
+ }
+ else {
+ *SetResourceforTbt =3D FALSE;
+ }
+ }
+
+/**
+ Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
+ @param[in] CommandOffsetAddress Tbt2Pcie Register Address
+ @param[in] TimeOut Time out with 100 ms garnularity
+ @param[in] Tbt2PcieDone Wait condition (wait for Bit to Cl=
ear/Set)
+ @param[out] *Tbt2PcieValue Function Register value
+**/
+BOOLEAN
+InternalWaitforCommandCompletion(
+ IN UINT64 CommandOffsetAddress,
+ IN UINT32 TimeOut,
+ IN BOOLEAN Tbt2PcieDone,
+ OUT UINT32 *Tbt2PcieValue
+ )
+{
+ BOOLEAN ReturnFlag;
+ UINT32 Tbt2PcieCheck;
+
+ ReturnFlag =3D FALSE;
+ while (TimeOut-- > 0) {
+ *Tbt2PcieValue =3D PciSegmentRead32 (CommandOffsetAddress);
+
+ if (0xFFFFFFFF =3D=3D *Tbt2PcieValue ) {
+ //
+ // Device is not here return now
+ //
+ ReturnFlag =3D FALSE;
+ break;
+ }
+
+ if(Tbt2PcieDone) {
+ Tbt2PcieCheck =3D *Tbt2PcieValue & TBT2PCIE_DON_R;
+ } else {
+ Tbt2PcieCheck =3D !(*Tbt2PcieValue & TBT2PCIE_DON_R);
+ }
+
+ if (Tbt2PcieCheck) {
+ ReturnFlag =3D TRUE;
+ break;
+ }
+
+ MicroSecondDelay(TBT_MAIL_BOX_DELAY);
+ }
+ return ReturnFlag;
+}
+/**
+ Get Security Level.
+ @param[in] Bus Bus number Host Router (DTBT)
+ @param[in] Device Device number for Host Router (DTBT)
+ @param[in] Function Function number for Host Router (DTBT)
+ @param[in] Command Command for Host Router (DTBT)
+ @param[in] Timeout Time out with 100 ms garnularity
+**/
+UINT8
+GetSecLevel (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 Command,
+ IN UINT32 Timeout
+ )
+{
+ UINT64 Pcie2Tbt;
+ UINT64 Tbt2Pcie;
+ UINT32 RegisterValue;
+ UINT8 ReturnFlag;
+
+ ReturnFlag =3D 0xFF;
+
+ DEBUG ((DEBUG_INFO, "GetSecLevel() \n"));
+
+ GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+ GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
+
+ PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
+
+ if(InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterVa=
lue)) {
+ ReturnFlag =3D (UINT8) (0xFF & (RegisterValue >> 8));
+ }
+
+ PciSegmentWrite32 (Pcie2Tbt, 0);
+
+ InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValu=
e);
+ DEBUG ((DEBUG_INFO, "Security Level configured to %x \n", ReturnFlag));
+
+ return ReturnFlag;
+}
+
+/**
+ Set Security Level.
+ @param[in] Data Security State
+ @param[in] Bus Bus number for Host Router (DTBT)
+ @param[in] Device Device number for Host Router (DTBT)
+ @param[in] Function Function number for Host Router (DTBT)
+ @param[in] Command Command for Host Router (DTBT)
+ @param[in] Timeout Time out with 100 ms garnularity
+**/
+BOOLEAN
+SetSecLevel (
+ IN UINT8 Data,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 Command,
+ IN UINT32 Timeout
+ )
+{
+ UINT64 Pcie2Tbt;
+ UINT64 Tbt2Pcie;
+ UINT32 RegisterValue;
+ BOOLEAN ReturnFlag;
+
+ ReturnFlag =3D FALSE;
+
+ DEBUG ((DEBUG_INFO, "SetSecLevel() \n"));
+
+ GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+ GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
+
+ PciSegmentWrite32 (Pcie2Tbt, (Data << 8) | Command | PCIE2TBT_VLD_B);
+
+ ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,=
&RegisterValue);
+ DEBUG ((DEBUG_INFO, "RegisterValue %x \n", RegisterValue));
+ PciSegmentWrite32 (Pcie2Tbt, 0);
+
+ InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValu=
e);
+ DEBUG ((DEBUG_INFO, "Return value %x \n", ReturnFlag));
+ return ReturnFlag;
+}
+
+/**
+Based on the Security Mode Selection, BIOS drives FORCE_PWR.
+
+@param[in] GpioNumber
+@param[in] Value
+**/
+VOID
+ForceDtbtPower(
+ IN UINT8 GpioAccessType,
+ IN UINT8 Expander,
+ IN UINT32 GpioNumber,
+ IN BOOLEAN Value
+)
+{
+ if (GpioAccessType =3D=3D 0x01) {
+ // PCH
+ GpioSetOutputValue (GpioNumber, (UINT32)Value);
+ } else if (GpioAccessType =3D=3D 0x02) {
+ // IoExpander {TCA6424A}
+ GpioExpSetOutput (Expander, (UINT8)GpioNumber, (UINT8)Value);
+ }
+}
+
+/**
+Execute TBT Mail Box Command
+
+@param[in] Command TBT Command
+@param[in] Bus Bus number for Host Router (DTBT)
+@param[in] Device Device number for Host Router (DTBT)
+@param[in] Function Function number for Host Router (DTBT)
+@param[in] Timeout Time out with 100 ms garnularity
+@Retval true if command executes succesfully
+**/
+BOOLEAN
+TbtSetPcie2TbtCommand(
+ IN UINT8 Command,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT32 Timeout
+)
+{
+ UINT64 Pcie2Tbt;
+ UINT64 Tbt2Pcie;
+ UINT32 RegisterValue;
+ BOOLEAN ReturnFlag;
+
+ GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+ GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
+
+ PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
+
+ ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE=
, &RegisterValue);
+
+ PciSegmentWrite32(Pcie2Tbt, 0);
+
+ return ReturnFlag;
+}
+/**
+ Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Po=
rt physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device =
number.
+ @param[out] RpFun Return corresponding root port functio=
n number.
+
+ @retval EFI_SUCCESS Root port device and function is retri=
eved
+ @retval EFI_INVALID_PARAMETER If Invalid Root Port Number or TYPE is=
Passed
+**/
+EFI_STATUS
+EFIAPI
+GetDTbtRpDevFun (
+ IN BOOLEAN Type,
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFunc
+ )
+{
+ EFI_STATUS Status;
+ UINTN TbtRpDev;
+ UINTN TbtRpFunc;
+
+ Status =3D EFI_INVALID_PARAMETER; // Update the Status to EFI_SUCCESS if=
valid input found.
+ //
+ // PCH-H can support up to 24 root ports. PEG0,PEG1 and PEG2 will be
+ // with device number 0x1 and Function number 0,1 and 2 respectively.
+ //
+ if (Type =3D=3D DTBT_TYPE_PEG)
+ {
+ //
+ // PEG Rootport
+ //
+ if (RpNumber <=3D 2) {
+ *RpDev =3D 0x01;
+ *RpFunc =3D RpNumber;
+ Status =3D EFI_SUCCESS;
+ }
+ }
+ if (Type =3D=3D DTBT_TYPE_PCH)
+ {
+ //
+ // PCH Rootport
+ //
+ if (RpNumber <=3D 23) {
+ Status =3D GetPchPcieRpDevFun (RpNumber, &TbtRpDev, &TbtRpFunc);
+ *RpDev =3D TbtRpDev;
+ *RpFunc =3D TbtRpFunc;
+ }
+ }
+
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
+BOOLEAN
+IsTbtHostRouter (
+ IN UINT16 DeviceID
+ )
+{
+ switch (DeviceID) {
+ case AR_HR_2C:
+ case AR_HR_4C:
+ case AR_HR_LP:
+ case AR_HR_C0_2C:
+ case AR_HR_C0_4C:
+ case TR_HR_2C:
+ case TR_HR_4C:
+ return TRUE;
+ }
+
+ return FALSE;
+} // IsTbtHostRouter
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiD=
xeSmmTbtCommonLib/TbtCommonLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/F=
eatures/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
new file mode 100644
index 0000000000..7a9e2d28dd
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTb=
tCommonLib/TbtCommonLib.inf
@@ -0,0 +1,60 @@
+## @file
+# Component information file for Tbt common library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D TbtCommonLib
+ FILE_GUID =3D 5F03614E-CB56-40B1-9989-A09E25BBA294
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D BASE
+ LIBRARY_CLASS =3D TbtCommonLib
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32 X64 EBC
+#
+
+[LibraryClasses]
+ DebugLib
+ PchPcieRpLib
+ PciSegmentLib
+ TimerLib
+ BaseLib
+ GpioLib
+ GpioExpanderLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber
+
+[Sources]
+ TbtCommonLib.c
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiT=
btPolicyLib/PeiTbtPolicyLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Featur=
es/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c
new file mode 100644
index 0000000000..7c1614a69a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolic=
yLib/PeiTbtPolicyLib.c
@@ -0,0 +1,206 @@
+/** @file
+ This file is PeiTbtPolicyLib library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+#include <PiPei.h>
+#include <PeiTbtPolicyLibrary.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/PeiTbtPolicy.h>
+#include <Base.h>
+#include <GpioConfig.h>
+
+/**
+ Update PEI TBT Policy Callback
+**/
+VOID
+EFIAPI
+UpdatePeiTbtPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ PEI_TBT_POLICY *PeiTbtConfig;
+
+ PeiTbtConfig =3D NULL;
+ Status =3D EFI_NOT_FOUND;
+
+ DEBUG ((DEBUG_INFO, "UpdatePeiTbtPolicy \n"));
+
+ Status =3D PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &VariableServices
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D PeiServicesLocatePpi (
+ &gPeiTbtPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiTbtConfig
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update DTBT Policy
+ //
+ PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn =3D PcdGet8 (PcdDTb=
tControllerEn);
+ if (PcdGet8 (PcdDTbtControllerType) =3D=3D TYPE_PEG)
+ {
+ PeiTbtConfig-> DTbtControllerConfig.Type =3D (UINT8) TYPE_PEG;
+ PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D 1; // PEG RP 1 (F=
unction no. 0)
+ }
+ else {
+ PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D PcdGet8 (PcdDTbtP=
cieRpNumber);
+ PeiTbtConfig-> DTbtControllerConfig.Type =3D PcdGet8 (PcdDTbtControlle=
rType);
+ }
+ PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D (GPIO_PA=
D) PcdGet32 (PcdDTbtCioPlugEventGpioPad);
+ if (GpioCheckFor2Tier(PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpi=
o.GpioPad)) {
+ PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo=
rting =3D 0;
+ PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =
=3D SIGNATURE_32('X', 'T', 'B', 'T');
+ }
+ else {
+ PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo=
rting =3D 1;
+ //
+ // Update Signature based on platform GPIO.
+ //
+ PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =
=3D SIGNATURE_32('X', 'T', 'B', 'T');
+ }
+ PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D PcdGet8 (PcdDTbtBootOn);
+ PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D PcdGet8 (PcdDTbtUsbOn);
+ PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D PcdGet8 (PcdDTbtGpio3Fo=
rcePwr);
+ PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D PcdGet16 (PcdDTbtGpi=
o3ForcePwrDly);
+
+ return;
+}
+
+/**
+ Print PEI TBT Policy
+**/
+VOID
+EFIAPI
+TbtPrintPeiPolicyConfig (
+ VOID
+ )
+{
+ DEBUG_CODE_BEGIN ();
+ EFI_STATUS Status;
+ PEI_TBT_POLICY *PeiTbtConfig;
+
+ PeiTbtConfig =3D NULL;
+ Status =3D EFI_NOT_FOUND;
+ DEBUG ((DEBUG_INFO, "TbtPrintPolicyConfig Start\n"));
+
+ Status =3D PeiServicesLocatePpi (
+ &gPeiTbtPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiTbtConfig
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Print DTBT Policy
+ //
+ DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print B=
EGIN -----------------\n"));
+ DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", PEI_TBT_POLICY_REVISION));
+ DEBUG ((DEBUG_INFO, "------------------------ PEI_TBT_CONFIG ----------=
-------\n"));
+ DEBUG ((DEBUG_INFO, " Revision : %d\n", PEI_TBT_POLICY_REVISION));
+
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.DTbtControllerEn=
=3D %x\n", PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.Type =3D %x\n", =
PeiTbtConfig-> DTbtControllerConfig.Type));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRpNumber =3D=
%x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.Gpi=
oPad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.Gpi=
oLevel =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLeve=
l));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.Gpio=
Pad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioPad));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.Gpio=
Level =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel)=
);
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio=
.GpioPad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.Gp=
ioPad));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio=
.AcpiGpeSignature =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEve=
ntGpio.AcpiGpeSignature));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio=
.AcpiGpeSignaturePorting =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.Cio=
PlugEventGpio.AcpiGpeSignaturePorting));
+
+
+ //
+ // Print DTBT Common Policy
+ //
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D %x\n",=
PeiTbtConfig->DTbtCommonConfig.TbtBootOn));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D %x\n", =
PeiTbtConfig->DTbtCommonConfig.TbtUsbOn));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D %x=
\n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D=
%x\n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfig=
uration =3D %x\n", PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfigurati=
on));
+ DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.PcieRstSupport =3D %=
x\n", PeiTbtConfig->DTbtCommonConfig.PcieRstSupport));
+
+ DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print E=
ND -----------------\n"));
+ DEBUG_CODE_END ();
+
+ return;
+}
+
+/**
+ Install Tbt Policy
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b=
uffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallPeiTbtPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *PeiTbtPolicyPpiDesc;
+ PEI_TBT_POLICY *PeiTbtConfig;
+
+ DEBUG ((DEBUG_INFO, "Install PEI TBT Policy\n"));
+
+ PeiTbtConfig =3D NULL;
+
+ //
+ // Allocate memory for PeiTbtPolicyPpiDesc
+ //
+ PeiTbtPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (siz=
eof (EFI_PEI_PPI_DESCRIPTOR));
+ ASSERT (PeiTbtPolicyPpiDesc !=3D NULL);
+ if (PeiTbtPolicyPpiDesc =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Allocate memory and initialize all default to zero for PeiTbtPolicy
+ //
+ PeiTbtConfig =3D (PEI_TBT_POLICY *) AllocateZeroPool (sizeof (PEI_TBT_PO=
LICY));
+ ASSERT (PeiTbtConfig !=3D NULL);
+ if (PeiTbtConfig =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Initialize PPI
+ //
+ PeiTbtPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_=
DESCRIPTOR_TERMINATE_LIST;
+ PeiTbtPolicyPpiDesc->Guid =3D &gPeiTbtPolicyPpiGuid;
+ PeiTbtPolicyPpiDesc->Ppi =3D PeiTbtConfig;
+
+ Status =3D PeiServicesInstallPpi (PeiTbtPolicyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Install PEI TBT Policy failed\n"));
+ }
+ return Status;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiT=
btPolicyLib/PeiTbtPolicyLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Feat=
ures/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
new file mode 100644
index 0000000000..a892479210
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolic=
yLib/PeiTbtPolicyLib.inf
@@ -0,0 +1,51 @@
+## @file
+# Component description file for Tbt policy
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+INF_VERSION =3D 0x00010017
+BASE_NAME =3D PeiTbtPolicyLib
+FILE_GUID =3D 4A95FDBB-2535-49eb-9A79-D56D24257106
+VERSION_STRING =3D 1.0
+MODULE_TYPE =3D PEIM
+LIBRARY_CLASS =3D PeiTbtPolicyLib
+
+
+[LibraryClasses]
+BaseMemoryLib
+PeiServicesLib
+PeiServicesTablePointerLib
+MemoryAllocationLib
+DebugLib
+PostCodeLib
+HobLib
+GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CO=
NSUMES
+
+[Sources]
+PeiTbtPolicyLib.c
+
+[Guids]
+gTbtInfoHobGuid
+
+[Ppis]
+gEfiPeiReadOnlyVariable2PpiGuid
+gPeiTbtPolicyPpiGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiT=
btPolicyLib/PeiTbtPolicyLibrary.h b/Platform/Intel/CometlakeOpenBoardPkg/Fe=
atures/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h
new file mode 100644
index 0000000000..f4b337f397
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolic=
yLib/PeiTbtPolicyLibrary.h
@@ -0,0 +1,19 @@
+/** @file
+ Header file for the PeiTBTPolicy library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_TBT_POLICY_LIBRARY_H_
+#define _PEI_TBT_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#endif // _PEI_TBT_POLICY_LIBRARY_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/Priv=
ate/PeiDTbtInitLib/PeiDTbtInitLib.c b/Platform/Intel/CometlakeOpenBoardPkg/=
Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.c
new file mode 100644
index 0000000000..cdfba613f2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/Private/Pei=
DTbtInitLib/PeiDTbtInitLib.c
@@ -0,0 +1,567 @@
+/** @file
+ Thunderbolt(TM) Pei Library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/MmPciLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/GpioExpanderLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <Base.h>
+#include <Library/TbtCommonLib.h>
+#include <TbtBoardInfo.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Ppi/PeiTbtPolicy.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiTbtPolicyLib.h>
+#include <Library/PchPmcLib.h>
+#include <Private/Library/PeiDTbtInitLib.h>
+
+/**
+Is host router (For dTBT) or End Point (For iTBT) present before sleep
+
+@param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER
+@param[in] Controller - Controller begin offset of CMOS
+
+@Retval TRUE There is a TBT HostRouter presented before sleep
+@Retval FALSE There is no TBT HostRouter presented before sleep
+
+BOOLEAN
+IsHostRouterPresentBeforeSleep(
+IN UINT8 ControllerType,
+IN UINT8 Controller
+)
+{
+ UINT8 SavedState;
+
+ SavedState =3D (UINT8)GetTbtHostRouterStatus();
+ if (ControllerType =3D=3D DTBT_CONTROLLER){
+ return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) =3D=3D (=
DTBT_SAVE_STATE_OFFSET << Controller));
+ } else {
+ if (ControllerType =3D=3D ITBT_CONTROLLER) {
+ return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) =3D=3D=
(ITBT_SAVE_STATE_OFFSET << Controller));
+ }
+ }
+ return 0;
+}
+**/
+
+/**
+Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4 mode wi=
th PreBootAclEnable
+
+@param[in] Bus Bus number for Host Router (DTBT)
+@param[in] Device Device number for Host Router (DTBT)
+@param[in] Function Function number for Host Router (DTBT)
+@param[in] Timeout Time out with 100 ms garnularity
+@Retval true if command executes succesfully
+**/
+BOOLEAN
+TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT32 Timeout
+)
+{
+ UINT64 Pcie2Tbt;
+ UINT64 Tbt2Pcie;
+ UINT32 RegisterValue;
+ BOOLEAN ReturnFlag;
+ UINT32 Command;
+
+ GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+ GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
+
+// If PreBootAcl is Enable, we need to enable DATA bit while sending SX EX=
IT MAIL BOX Command
+ Command =3D (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED;
+ PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
+
+ ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,=
&RegisterValue);
+
+ PciSegmentWrite32(Pcie2Tbt, 0);
+
+ return ReturnFlag;
+}
+
+/**
+Set the Sleep Mode if the HR is up.
+@param[in] Bus Bus number for Host Router (DTBT)
+@param[in] Device Device number for Host Router (DTBT)
+@param[in] Function Function number for Host Router (DTBT)
+**/
+VOID
+TbtSetSxMode(
+IN UINT8 Bus,
+IN UINT8 Device,
+IN UINT8 Function,
+IN UINT8 TbtBootOn
+)
+{
+ UINT64 TbtUsDevId;
+ UINT64 Tbt2Pcie;
+ UINT32 RegVal;
+ UINT32 MaxLoopCount;
+ UINTN Delay;
+ UINT8 RetCode;
+ EFI_BOOT_MODE BootMode;
+ EFI_STATUS Status;
+
+ TbtUsDevId =3D PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0);
+ GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+
+ MaxLoopCount =3D TBT_5S_TIMEOUT; // Wait 5 sec
+ Delay =3D 100 * 1000;
+ RetCode =3D 0x62;
+
+ Status =3D PeiServicesGetBootMode(&BootMode);
+ ASSERT_EFI_ERROR(Status);
+
+ if ((BootMode =3D=3D BOOT_ON_S4_RESUME) && (TbtBootOn =3D=3D 2)) {
+ MaxLoopCount =3D TBT_3S_TIMEOUT;
+ if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device, Func=
tion, MaxLoopCount)) {
+ //
+ // Nothing to wait, HR is not responsive
+ //
+ return;
+ }
+ }
+ else {
+ if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus, Device=
, Function, MaxLoopCount)) {
+ //
+ // Nothing to wait, HR is not responsive
+ //
+ return;
+ }
+ }
+
+ DEBUG((DEBUG_INFO, "Wait for Dev ID !=3D 0xFF\n"));
+
+ while (MaxLoopCount-- > 0) {
+ //
+ // Check what HR still here
+ //
+ RegVal =3D PciSegmentRead32(Tbt2Pcie);
+ if (0xFFFFFFFF =3D=3D RegVal) {
+ RetCode =3D 0x6F;
+ break;
+ }
+ //
+ // Check completion of TBT link
+ //
+ RegVal =3D PciSegmentRead32(TbtUsDevId);
+ if (0xFFFFFFFF !=3D RegVal) {
+ RetCode =3D 0x61;
+ break;
+ }
+
+ MicroSecondDelay(Delay);
+ }
+
+ DEBUG((DEBUG_INFO, "Return code =3D 0x%x\n", RetCode));
+}
+/**
+ set tPCH25 Timing to 10 ms for DTBT.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSetTPch25Timing (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+)
+{
+ DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n"));
+ UINT32 PchPwrmBase;
+
+ //
+ //During boot, reboot and wake tPCH25 Timing should be set to 10 ms
+ //
+ MmioOr32 (
+ (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG),
+ (BIT0 | BIT1)
+ );
+
+ DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n"));
+ return EFI_SUCCESS;
+}
+
+/**
+ Do ForcePower for DTBT Controller
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtForcePower (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+)
+{
+
+ DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n"));
+
+ if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) {
+ DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad =3D %x \n", PeiTbtConfig-=
> DTbtControllerConfig.ForcePwrGpio.GpioPad));
+ ForceDtbtPower(PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Gp=
ioAccessType,PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Expander, Pei=
TbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig-> DTbtC=
ontrollerConfig.ForcePwrGpio.GpioLevel);
+ DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n"));
+ MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly *=
1000);
+ DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower =3D 0x%x ms \n", Pe=
iTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly));
+ }
+
+ DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n"));
+ return EFI_SUCCESS;
+}
+
+/**
+ Clear VGA Registers for DTBT.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtClearVgaRegisters (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+)
+{
+ UINTN RpDev;
+ UINTN RpFunc;
+ EFI_STATUS Status;
+ UINT64 BridngeBaseAddress;
+ UINT16 Data16;
+
+ DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n"));
+
+ Status =3D EFI_SUCCESS;
+
+ Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, Pei=
TbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
+ ASSERT_EFI_ERROR(Status);
+ //
+ // VGA Enable and VGA 16-bit decode registers of Bridge control register=
of Root port where
+ // Host router resides should be cleaned
+ //
+
+ BridngeBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev, (UIN=
T32)RpFunc, 0);
+ Data16 =3D PciSegmentRead16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGI=
STER_OFFSET);
+ Data16 &=3D (~(EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_1=
6));
+ PciSegmentWrite16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSE=
T, Data16);
+
+ DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n"));
+ return Status;
+}
+
+/**
+ Exectue Mail box command "Boot On".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtBootOn(
+ IN PEI_TBT_POLICY *PeiTbtConfig
+)
+{
+ EFI_STATUS Status;
+ UINT32 OrgBusNumberConfiguration;
+ UINTN RpDev;
+ UINTN RpFunc;
+
+ DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n"));
+
+ Status =3D EFI_SUCCESS;
+
+ Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,=
PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
+ ASSERT_EFI_ERROR(Status);
+ OrgBusNumberConfiguration =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDR=
ESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
+ //
+ // Set Sec/Sub buses to 0xF0
+ //
+ PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_=
BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
+ //
+ //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup we =
need to do the below:
+ //Bios should send "Boot On" message through PCIE2TBT register
+ //The Boot On command as described above would include the command a=
nd acknowledge from FW (with the default timeout in BIOS),
+ //once the Boot On command is completed it is guaranteed that the Al=
pineRidge(AR) device is there and the PCI tunneling was done by FW,
+ //next step from BIOS is enumeration using SMI
+ //
+
+ if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
+ //
+ // Exectue Mail box command "Boot On / Pre-Boot ACL"
+ //
+ //Command may be executed only during boot/reboot and not during S=
x exit flow
+ if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 1) {
+ if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0, TBT_5S_=
TIMEOUT)) {
+ //
+ // Nothing to wait, HR is not responsive
+ //
+ DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Boot On message sent=
failed \n"));
+ }
+ }
+ if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2) {
+ if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0, TBT_=
3S_TIMEOUT)) {
+ //
+ // Nothing to wait, HR is not responsive
+ //
+ DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Pre-Boot ACL message=
sent failed \n"));
+ }
+ }
+ }
+ //
+ // Reset Sec/Sub buses to original value
+ //
+ PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_=
BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
+
+ DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n"));
+ return Status;
+}
+
+/**
+ Exectue Mail box command "USB On".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtUsbOn(
+ IN PEI_TBT_POLICY *PeiTbtConfig
+)
+{
+ EFI_STATUS Status;
+ UINTN RpDev;
+ UINTN RpFunc;
+ UINT32 OrgBusNumberConfiguration;
+ UINT64 TbtBaseAddress;
+ UINT32 MaxWaitIter;
+ UINT32 RegVal;
+ EFI_BOOT_MODE BootMode;
+
+ DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n"));
+
+ Status =3D EFI_SUCCESS;
+
+ Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,=
PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
+ ASSERT_EFI_ERROR(Status);
+ OrgBusNumberConfiguration =3D PciSegmentRead32(PCI_SEGMENT_LIB_ADDRE=
SS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
+ //
+ // Set Sec/Sub buses to 0xF0
+ //
+ PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_=
BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
+
+ //
+ //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios setup =
we need to do the below:
+ //Bios should send "Usb On" message through PCIE2TBT register
+ //The Usb On command as described above would include the command an=
d acknowledge from FW (with the default timeout in BIOS),
+ //once the Usb On command is completed it is guaranteed that the Alp=
ineRidge(AR) device is there and the PCI tunneling was done by FW,
+ //next step from BIOS is enumeration using SMI
+ //
+ if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) {
+ if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
+ MaxWaitIter =3D 50; // Wait 5 sec
+ TbtBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0);
+ //
+ // Driver clears the PCIe2TBT Valid bit to support two consicuti=
ve mailbox commands
+ //
+ PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0);
+ DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R =3D 0x%lx \=
n", TbtBaseAddress + PCIE2TBT_DTBT_R));
+ while (MaxWaitIter-- > 0) {
+ RegVal =3D PciSegmentRead32(TbtBaseAddress + TBT2PCIE_DTBT_R);
+ if (0xFFFFFFFF =3D=3D RegVal) {
+ //
+ // Device is not here return now
+ //
+ DEBUG((DEBUG_INFO, "TBT device is not present \n"));
+ break;
+ }
+
+ if (!(RegVal & TBT2PCIE_DON_R)) {
+ break;
+ }
+ MicroSecondDelay(100 * 1000);
+ }
+ }
+
+ Status =3D PeiServicesGetBootMode(&BootMode);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Exectue Mail box command "Usb On"
+ //
+ //Command may be executed only during boot/reboot and not during S=
3 exit flow
+ //In case of S4 Exit send USB ON cmd only if Host Router was inact=
ive/not present during S4 entry
+ if ((BootMode =3D=3D BOOT_ON_S4_RESUME) ) {
+ // USB_ON cmd not required
+ } else {
+ if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0, TBT_5S_T=
IMEOUT)) {
+ //
+ // Nothing to wait, HR is not responsive
+ //
+ DEBUG((DEBUG_INFO, "<TbtPei> TbtBootSupport - Usb On message s=
ent failed \n"));
+ }
+ }
+ }
+ //
+ // Reset Sec/Sub buses to original value
+ //
+ PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_=
BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
+
+ DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n"));
+ return Status;
+}
+
+/**
+ Exectue Mail box command "Sx Exit".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSxExitFlow(
+ IN PEI_TBT_POLICY *PeiTbtConfig
+)
+{
+ EFI_STATUS Status;
+ UINT32 OrgBusNumberConfiguration;
+ UINTN RpDev;
+ UINTN RpFunc;
+ UINT32 Count;
+
+ DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n"));
+
+ Status =3D EFI_SUCCESS;
+ Count =3D 0;
+
+ Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,=
PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
+ ASSERT_EFI_ERROR(Status);
+ OrgBusNumberConfiguration =3D PciSegmentRead32(PCI_SEGMENT_LIB_ADDRE=
SS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
+ //
+ // Set Sec/Sub buses to 0xF0
+ //
+ PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_=
BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
+
+ if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2)) {
+ //
+ // WA: When system with TBT 3.1 device, resume SX system need to w=
ait device ready. In document that maximum time out should be 500ms.
+ //
+ while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0, 0x0,=
0x08)) =3D=3D 0xffffffff) { //End Device will be with Device Number 0x0, F=
unction Number 0x0.
+ MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); // 1000usec
+ Count++;
+ if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S bo=
ard.
+ break;
+ }
+ }
+
+ //
+ // Upon wake, if BIOS saved pre-Sx Host Router state as active (sy=
stem went to sleep with
+ // attached devices), BIOS should:
+ // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
+ // 2. If procedure above returns true, BIOS should perform "wait f=
or fast link bring-up" loop
+ // 3. Continue regular wake flow.
+ //
+ //
+ // Exectue Mail box command and perform "wait for fast link bring-=
up" loop
+ //
+ TbtSetSxMode(0xF0, 0, 0, PeiTbtConfig->DTbtCommonConfig.TbtBootOn);
+ }
+ //
+ // Reset Sec/Sub buses to original value
+ //
+ PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_=
BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
+
+ DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n"));
+ return Status;
+}
+
+
+/**
+ Initialize Thunderbolt(TM)
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+TbtInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ PEI_TBT_POLICY *PeiTbtConfig;
+
+ //
+ // Get the TBT Policy
+ //
+ Status =3D PeiServicesLocatePpi (
+ &gPeiTbtPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiTbtConfig
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+ }
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Exectue Mail box command "Boot On"
+ //
+ Status =3D DTbtBootOn (PeiTbtConfig);
+ //
+ // Exectue Mail box command "Usb On"
+ //
+ Status =3D DTbtUsbOn (PeiTbtConfig);
+ //
+ //During boot, reboot and wake (bits [1:0]) of PCH PM_CFG register shou=
ld be
+ //set to 11b - 10 ms (default value is 0b - 10 us)
+ //
+ Status =3D DTbtSetTPch25Timing (PeiTbtConfig);
+ //
+ // Configure Tbt Force Power
+ //
+ Status =3D DTbtForcePower (PeiTbtConfig);
+ //
+ // VGA Enable and VGA 16-bit decode registers of Bridge control register=
of Root port where
+ // Host router resides should be cleaned
+ //
+ Status =3D DTbtClearVgaRegisters (PeiTbtConfig);
+ //
+ // Upon wake, if BIOS saved pre-Sx Host Router state as active (system w=
ent to sleep with
+ // attached devices), BIOS should:
+ // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
+ // 2. If procedure above returns true, BIOS should perform "wait for fas=
t link bring-up" loop
+ // 3. Continue regular wake flow.
+ //
+ Status =3D DTbtSxExitFlow (PeiTbtConfig);
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/Priv=
ate/PeiDTbtInitLib/PeiDTbtInitLib.inf b/Platform/Intel/CometlakeOpenBoardPk=
g/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
new file mode 100644
index 0000000000..3f075e0ec2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/Private/Pei=
DTbtInitLib/PeiDTbtInitLib.inf
@@ -0,0 +1,45 @@
+## @file
+# Component description file for PEI DTBT Init library.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PeiDTbtInitLib
+ FILE_GUID =3D 06768A8D-8152-403f-83C1-59584FD2B438
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D PEIM
+ LIBRARY_CLASS =3D PeiDTbtInitLib
+
+[LibraryClasses]
+ PeiServicesLib
+ DebugLib
+ PcdLib
+ TbtCommonLib
+ PciSegmentLib
+ PeiTbtPolicyLib
+ PchPmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Ppis]
+ gPeiTbtPolicyPpiGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ #gClientCommonModuleTokenSpaceGuid.PcdTbtSupport ## PRODUCES
+
+[Sources]
+ PeiDTbtInitLib.c
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspCpuPolicyInitLib.c b/Platform/Intel/CometlakeOpenBoardP=
kg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
new file mode 100644
index 0000000000..9c29f93fc2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspCpuPolicyInitLib.c
@@ -0,0 +1,460 @@
+/** @file
+ Implementation of Fsp CPU Policy Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Ppi/SecPlatformInformation2.h>
+
+#include <CpuAccess.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PcdLib.h>
+#include <FspEas.h>
+
+/**
+ Performs FSP CPU PEI Policy initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig;
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n=
"));
+
+ //
+ // Locate SiPreMemPolicyPpi
+ //
+ SiPreMemPolicyPpi =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclocking=
PreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre=
MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ ///
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n")=
);
+
+ //
+ // Overclocking PreMem policies
+ //
+ FspmUpd->FspmConfig.OcSupport =3D (UINT8) CpuOverClockingP=
reMemConfig->OcSupport;
+ FspmUpd->FspmConfig.OcLock =3D (UINT8) CpuOverClockingP=
reMemConfig->OcLock;
+ FspmUpd->FspmConfig.CoreMaxOcRatio =3D (UINT8) CpuOverClockingP=
reMemConfig->CoreMaxOcRatio;
+ FspmUpd->FspmConfig.CoreVoltageMode =3D (UINT8) CpuOverClockingP=
reMemConfig->CoreVoltageMode;
+ FspmUpd->FspmConfig.CoreVoltageOverride =3D (UINT16) CpuOverClocking=
PreMemConfig->CoreVoltageOverride;
+ FspmUpd->FspmConfig.CoreVoltageAdaptive =3D (UINT16) CpuOverClocking=
PreMemConfig->CoreVoltageAdaptive;
+ FspmUpd->FspmConfig.CoreVoltageOffset =3D (UINT16) CpuOverClocking=
PreMemConfig->CoreVoltageOffset;
+ FspmUpd->FspmConfig.CorePllVoltageOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->CorePllVoltageOffset;
+ FspmUpd->FspmConfig.RingMaxOcRatio =3D (UINT8) CpuOverClockingP=
reMemConfig->RingMaxOcRatio;
+ FspmUpd->FspmConfig.RingVoltageOverride =3D (UINT16) CpuOverClocking=
PreMemConfig->RingVoltageOverride;
+ FspmUpd->FspmConfig.RingVoltageAdaptive =3D (UINT16) CpuOverClocking=
PreMemConfig->RingVoltageAdaptive;
+ FspmUpd->FspmConfig.RingVoltageOffset =3D (UINT16) CpuOverClocking=
PreMemConfig->RingVoltageOffset;
+ FspmUpd->FspmConfig.RingPllVoltageOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->RingPllVoltageOffset;
+ FspmUpd->FspmConfig.GtPllVoltageOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->GtPllVoltageOffset;
+ FspmUpd->FspmConfig.RingPllVoltageOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->RingPllVoltageOffset;
+ FspmUpd->FspmConfig.SaPllVoltageOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->SaPllVoltageOffset;
+ FspmUpd->FspmConfig.McPllVoltageOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->McPllVoltageOffset;
+ FspmUpd->FspmConfig.RingDownBin =3D (UINT8) CpuOverClockingP=
reMemConfig->RingDownBin;
+ FspmUpd->FspmConfig.RingVoltageMode =3D (UINT8) CpuOverClockingP=
reMemConfig->RingVoltageMode;
+ FspmUpd->FspmConfig.Avx2RatioOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->Avx2RatioOffset;
+ FspmUpd->FspmConfig.Avx3RatioOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->Avx3RatioOffset;
+ FspmUpd->FspmConfig.BclkAdaptiveVoltage =3D (UINT8) CpuOverClockingP=
reMemConfig->BclkAdaptiveVoltage;
+ FspmUpd->FspmConfig.TjMaxOffset =3D (UINT8) CpuOverClockingP=
reMemConfig->TjMaxOffset;
+ FspmUpd->FspmConfig.TvbRatioClipping =3D (UINT8) CpuOverClockingP=
reMemConfig->TvbRatioClipping;
+ FspmUpd->FspmConfig.TvbVoltageOptimization =3D (UINT8) CpuOverClockingP=
reMemConfig->TvbVoltageOptimization;
+
+ //
+ // Cpu Config Lib policies
+ //
+ FspmUpd->FspmConfig.HyperThreading =3D (UINT8) CpuConfigLibPr=
eMemConfig->HyperThreading;
+ FspmUpd->FspmConfig.BootFrequency =3D (UINT8) CpuConfigLibPr=
eMemConfig->BootFrequency;
+ FspmUpd->FspmConfig.ActiveCoreCount =3D (UINT8) CpuConfigLibPr=
eMemConfig->ActiveCoreCount;
+ FspmUpd->FspmConfig.JtagC10PowerGateDisable =3D (UINT8) CpuConfigLibPr=
eMemConfig->JtagC10PowerGateDisable;
+ FspmUpd->FspmConfig.FClkFrequency =3D (UINT8) CpuConfigLibPr=
eMemConfig->FClkFrequency;
+ FspmUpd->FspmConfig.BistOnReset =3D (UINT8) CpuConfigLibPr=
eMemConfig->BistOnReset;
+ FspmUpd->FspmConfig.VmxEnable =3D (UINT8) CpuConfigLibPr=
eMemConfig->VmxEnable;
+ FspmUpd->FspmConfig.CpuRatio =3D (UINT8) CpuConfigLibPr=
eMemConfig->CpuRatio;
+ FspmUpd->FspmConfig.PeciSxReset =3D (UINT8) CpuConfigLibPr=
eMemConfig->PeciSxReset;
+ FspmUpd->FspmConfig.PeciC10Reset =3D (UINT8) CpuConfigLibPr=
eMemConfig->PeciC10Reset;
+ FspmUpd->FspmConfig.SkipMpInit =3D (UINT8) CpuConfigLibPr=
eMemConfig->SkipMpInit;
+
+ //
+ // DisableMtrrProgram <1> Disable Mtrrs program. <0> Program Mtrrs in FSP
+ //
+ FspmUpd->FspmConfig.DisableMtrrProgram =3D (UINT8) 0;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine is used to get Sec Platform Information Record2 Pointer.
+
+ @param[in] PeiServices Pointer to the PEI services table
+
+ @retval GetSecPlatformInformation2 - The pointer of Sec Platform Informat=
ion Record2 Pointer.
+ **/
+
+EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformation2(
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_SEC_PLATFORM_INFORMATION2_PPI *SecPlatformInformation2Ppi;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2 =3D NULL;
+ UINT64 InformationSize;
+ EFI_STATUS Status;
+
+ //
+ // Get BIST information from Sec Platform Information2 Ppi firstly
+ //
+ Status =3D PeiServicesLocatePpi (
+ &gEfiSecPlatformInformation2PpiGuid, // GUID
+ 0, // Instance
+ NULL, // EFI_PEI_PPI_DESCRIP=
TOR
+ (VOID ** ) &SecPlatformInformation2Ppi // PPI
+ );
+
+ DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi2 Status - %x\n",=
Status));
+ if (EFI_ERROR(Status)) {
+ return NULL;
+ }
+
+ InformationSize =3D 0;
+
+ Status =3D SecPlatformInformation2Ppi->PlatformInformation2 (
+ (CONST EFI_PEI_SERVICES **) PeiS=
ervices,
+ &InformationSize,
+ SecPlatformInformation2
+ );
+
+ ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL);
+ if (Status !=3D EFI_BUFFER_TOO_SMALL) {
+ return NULL;
+ }
+
+ SecPlatformInformation2 =3D AllocatePool((UINTN)InformationSize);
+ ASSERT (SecPlatformInformation2 !=3D NULL);
+ if (SecPlatformInformation2 =3D=3D NULL) {
+ return NULL;
+ }
+
+ //
+ // Retrieve BIST data from SecPlatform2
+ //
+ Status =3D SecPlatformInformation2Ppi->PlatformInformation2 (
+ (CONST EFI_PEI_SERVICES **) PeiS=
ervices,
+ &InformationSize,
+ SecPlatformInformation2
+ );
+ DEBUG((DEBUG_INFO, "SecPlatformInformation2Ppi->PlatformInformation2 Sta=
tus - %x\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ return SecPlatformInformation2;
+}
+
+/**
+ This routine is used to get Sec Platform Information Record Pointer.
+
+ @param[in] PeiServices Pointer to the PEI services table
+
+ @retval GetSecPlatformInformation2 - The pointer of Sec Platform Informat=
ion Record Pointer.
+ **/
+EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformationInfoInForm=
at2(
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformInformationPpi;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD *SecPlatformInformation =3D NULL;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2;
+ UINT64 InformationSize;
+ EFI_STATUS Status;
+
+ //
+ // Get BIST information from Sec Platform Information
+ //
+ Status =3D PeiServicesLocatePpi (
+ &gEfiSecPlatformInformationPpiGuid, // GUID
+ 0, // Instance
+ NULL, // EFI_PEI_PPI_DESCRIP=
TOR
+ (VOID ** ) &SecPlatformInformationPpi // PPI
+ );
+
+ DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi Status - %x\n", =
Status));
+ if (EFI_ERROR(Status)) {
+ return NULL;
+ }
+
+ InformationSize =3D 0;
+ Status =3D SecPlatformInformationPpi->PlatformInformation (
+ (CONST EFI_PEI_SERVICES **) PeiSe=
rvices,
+ &InformationSize,
+ SecPlatformInformation
+ );
+
+ ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL);
+ if (Status !=3D EFI_BUFFER_TOO_SMALL) {
+ return NULL;
+ }
+
+ SecPlatformInformation =3D AllocatePool((UINTN)InformationSize);
+ ASSERT (SecPlatformInformation !=3D NULL);
+ if (SecPlatformInformation =3D=3D NULL) {
+ return NULL;
+ }
+
+ //
+ // Retrieve BIST data from SecPlatform
+ //
+ Status =3D SecPlatformInformationPpi->PlatformInformation (
+ (CONST EFI_PEI_SERVICES **) PeiSe=
rvices,
+ &InformationSize,
+ SecPlatformInformation
+ );
+ DEBUG((DEBUG_INFO, "FSP SecPlatformInformation2Ppi->PlatformInformation=
Status - %x\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ SecPlatformInformation2 =3D AllocatePool(sizeof (EFI_SEC_PLATFORM_INFORM=
ATION_RECORD2));
+ ASSERT (SecPlatformInformation2 !=3D NULL);
+ if (SecPlatformInformation2 =3D=3D NULL) {
+ return NULL;
+ }
+
+ SecPlatformInformation2->NumberOfCpus =3D 1;
+ SecPlatformInformation2->CpuInstance[0].CpuLocation =3D 0;
+ SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32=
=3D SecPlatformInformation->x64HealthFlags.Uint32;
+
+ FreePool(SecPlatformInformation);
+
+ return SecPlatformInformation2;
+}
+
+
+/**
+ Performs FSP CPU PEI Policy post memory initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_CONFIG *CpuConfig;
+ CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;
+ CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig;
+ CPU_TEST_CONFIG *CpuTestConfig;
+ CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig;
+ UINTN Index;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2;
+ EFI_PEI_SERVICES **PeiServices;
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy\n"));
+ PeiServices =3D (EFI_PEI_SERVICES **)GetPeiServicesTablePointer ();
+ //
+ // Locate gSiPolicyPpiGuid
+ //
+ SiPolicyPpi =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID =
*) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConf=
igGuid, (VOID *) &CpuPowerMgmtBasicConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomCon=
figGuid, (VOID *) &CpuPowerMgmtCustomConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (V=
OID *) &CpuTestConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfi=
gGuid, (VOID *) &CpuPowerMgmtTestConfig);
+ ASSERT_EFI_ERROR (Status);
+ ///
+ ///Production RC Policies
+ ///
+
+ FspsUpd->FspsConfig.AesEnable =3D (UINT8) CpuConfig->Aes=
Enable;
+ FspsUpd->FspsConfig.DebugInterfaceEnable =3D (UINT8) CpuConfig->Deb=
ugInterfaceEnable;
+
+ FspsUpd->FspsConfig.TurboMode =3D (UINT8) CpuPowerMgmtBa=
sicConfig->TurboMode;
+
+ ///
+ /// Test RC Policies
+ ///
+ FspsUpd->FspsTestConfig.MlcStreamerPrefetcher =3D (UINT8) CpuTestCo=
nfig->MlcStreamerPrefetcher;
+ FspsUpd->FspsTestConfig.MlcSpatialPrefetcher =3D (UINT8) CpuTestCo=
nfig->MlcSpatialPrefetcher;
+ FspsUpd->FspsTestConfig.MonitorMwaitEnable =3D (UINT8) CpuTestCo=
nfig->MonitorMwaitEnable;
+ FspsUpd->FspsTestConfig.DebugInterfaceLockEnable =3D (UINT8) CpuTestCo=
nfig->DebugInterfaceLockEnable;
+ FspsUpd->FspsTestConfig.ApIdleManner =3D PcdGet8 (PcdCpuAp=
LoopMode);
+ FspsUpd->FspsTestConfig.ProcessorTraceOutputScheme =3D (UINT8) CpuTestCo=
nfig->ProcessorTraceOutputScheme;
+ FspsUpd->FspsTestConfig.ProcessorTraceEnable =3D (UINT8) CpuTestCo=
nfig->ProcessorTraceEnable;
+ FspsUpd->FspsTestConfig.ProcessorTraceMemBase =3D CpuTestConfig->Pr=
ocessorTraceMemBase;
+ FspsUpd->FspsTestConfig.ProcessorTraceMemLength =3D (UINT32) CpuTestC=
onfig->ProcessorTraceMemLength;
+ FspsUpd->FspsTestConfig.VoltageOptimization =3D (UINT8) CpuTestCo=
nfig->VoltageOptimization;
+ FspsUpd->FspsTestConfig.ThreeStrikeCounterDisable =3D (UINT8) CpuTestCo=
nfig->ThreeStrikeCounterDisable;
+ FspsUpd->FspsTestConfig.MachineCheckEnable =3D (UINT8) CpuTestCo=
nfig->MachineCheckEnable;
+ FspsUpd->FspsTestConfig.CpuWakeUpTimer =3D (UINT8) CpuTestCo=
nfig->CpuWakeUpTimer;
+
+ FspsUpd->FspsTestConfig.OneCoreRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->OneCoreRatioLimit;
+ FspsUpd->FspsTestConfig.TwoCoreRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->TwoCoreRatioLimit;
+ FspsUpd->FspsTestConfig.ThreeCoreRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->ThreeCoreRatioLimit;
+ FspsUpd->FspsTestConfig.FourCoreRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->FourCoreRatioLimit;
+ FspsUpd->FspsTestConfig.FiveCoreRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->FiveCoreRatioLimit;
+ FspsUpd->FspsTestConfig.SixCoreRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->SixCoreRatioLimit;
+ FspsUpd->FspsTestConfig.SevenCoreRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->SevenCoreRatioLimit;
+ FspsUpd->FspsTestConfig.EightCoreRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->EightCoreRatioLimit;
+ FspsUpd->FspsTestConfig.Hwp =3D (UINT8) CpuPowerM=
gmtBasicConfig->Hwp;
+ FspsUpd->FspsTestConfig.HdcControl =3D (UINT8) CpuPowerM=
gmtBasicConfig->HdcControl;
+ FspsUpd->FspsTestConfig.PowerLimit1Time =3D (UINT8) CpuPowerM=
gmtBasicConfig->PowerLimit1Time;
+ FspsUpd->FspsTestConfig.PowerLimit2 =3D (UINT8) CpuPowerM=
gmtBasicConfig->PowerLimit2;
+ FspsUpd->FspsTestConfig.TurboPowerLimitLock =3D (UINT8) CpuPowerM=
gmtBasicConfig->TurboPowerLimitLock;
+ FspsUpd->FspsTestConfig.PowerLimit3Time =3D (UINT8) CpuPowerM=
gmtBasicConfig->PowerLimit3Time;
+ FspsUpd->FspsTestConfig.PowerLimit3DutyCycle =3D (UINT8) CpuPowerM=
gmtBasicConfig->PowerLimit3DutyCycle;
+ FspsUpd->FspsTestConfig.PowerLimit3Lock =3D (UINT8) CpuPowerM=
gmtBasicConfig->PowerLimit3Lock;
+ FspsUpd->FspsTestConfig.PowerLimit4Lock =3D (UINT8) CpuPowerM=
gmtBasicConfig->PowerLimit4Lock;
+ FspsUpd->FspsTestConfig.TccActivationOffset =3D (UINT8) CpuPowerM=
gmtBasicConfig->TccActivationOffset;
+ FspsUpd->FspsTestConfig.TccOffsetClamp =3D (UINT8) CpuPowerM=
gmtBasicConfig->TccOffsetClamp;
+ FspsUpd->FspsTestConfig.TccOffsetLock =3D (UINT8) CpuPowerM=
gmtBasicConfig->TccOffsetLock;
+ FspsUpd->FspsTestConfig.PowerLimit1 =3D (UINT32) (CpuPowe=
rMgmtBasicConfig->PowerLimit1 * 125);
+ FspsUpd->FspsTestConfig.PowerLimit2Power =3D (UINT32) (CpuPowe=
rMgmtBasicConfig->PowerLimit2Power * 125);
+ FspsUpd->FspsTestConfig.PowerLimit3 =3D (UINT32) (CpuPowe=
rMgmtBasicConfig->PowerLimit3 * 125);
+ FspsUpd->FspsTestConfig.PowerLimit4 =3D (UINT32) (CpuPowe=
rMgmtBasicConfig->PowerLimit4 * 125);
+ FspsUpd->FspsTestConfig.TccOffsetTimeWindowForRatl =3D (UINT32) CpuPower=
MgmtBasicConfig->TccOffsetTimeWindowForRatl;
+ FspsUpd->FspsTestConfig.HwpInterruptControl =3D (UINT8) CpuPowerM=
gmtBasicConfig->HwpInterruptControl;
+ FspsUpd->FspsTestConfig.EnableItbm =3D (UINT8) CpuPowerM=
gmtBasicConfig->EnableItbm;
+ FspsUpd->FspsTestConfig.EnableItbmDriver =3D (UINT8) CpuPowerM=
gmtBasicConfig->EnableItbmDriver;
+ FspsUpd->FspsTestConfig.MinRingRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->MinRingRatioLimit;
+ FspsUpd->FspsTestConfig.MaxRingRatioLimit =3D (UINT8) CpuPowerM=
gmtBasicConfig->MaxRingRatioLimit;
+ FspsUpd->FspsTestConfig.NumberOfEntries =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomRatioTable.NumberOfEntries;
+ FspsUpd->FspsTestConfig.Custom1PowerLimit1Time =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1Time;
+ FspsUpd->FspsTestConfig.Custom2PowerLimit1Time =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1Time;
+ FspsUpd->FspsTestConfig.Custom3PowerLimit1Time =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1Time;
+ FspsUpd->FspsTestConfig.Custom1TurboActivationRatio =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomConfigTdpTable[0].CustomTurboActivationRatio;
+ FspsUpd->FspsTestConfig.Custom2TurboActivationRatio =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomConfigTdpTable[1].CustomTurboActivationRatio;
+ FspsUpd->FspsTestConfig.Custom3TurboActivationRatio =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomConfigTdpTable[2].CustomTurboActivationRatio;
+ FspsUpd->FspsTestConfig.ConfigTdpLock =3D (UINT8) CpuPower=
MgmtCustomConfig->ConfigTdpLock;
+ FspsUpd->FspsTestConfig.ConfigTdpBios =3D (UINT8) CpuPower=
MgmtCustomConfig->ConfigTdpBios;
+ FspsUpd->FspsTestConfig.MaxRatio =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomRatioTable.MaxRatio;
+ for (Index =3D 0; Index < CpuPowerMgmtCustomConfig->CustomRatioTable.Num=
berOfEntries; Index++) {
+ FspsUpd->FspsTestConfig.StateRatio[Index] =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomRatioTable.StateRatio[Index];
+ }
+ for (Index =3D 0; Index < MAX_16_CUSTOM_RATIO_TABLE_ENTRIES; Index++) {
+ FspsUpd->FspsTestConfig.StateRatioMax16[Index] =3D (UINT8) CpuPower=
MgmtCustomConfig->CustomRatioTable.StateRatioMax16[Index];
+ }
+ FspsUpd->FspsTestConfig.Custom1PowerLimit1 =3D (UINT32) (CpuPow=
erMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1 * 125);
+ FspsUpd->FspsTestConfig.Custom1PowerLimit2 =3D (UINT32) (CpuPow=
erMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit2 * 125);
+ FspsUpd->FspsTestConfig.Custom2PowerLimit1 =3D (UINT32) (CpuPow=
erMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1 * 125);
+ FspsUpd->FspsTestConfig.Custom2PowerLimit2 =3D (UINT32) (CpuPow=
erMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit2 * 125);
+ FspsUpd->FspsTestConfig.Custom3PowerLimit1 =3D (UINT32) (CpuPow=
erMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1 * 125);
+ FspsUpd->FspsTestConfig.Custom3PowerLimit2 =3D (UINT32) (CpuPow=
erMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit2 * 125);
+
+ FspsUpd->FspsTestConfig.Eist =3D (UINT8) CpuPow=
erMgmtTestConfig->Eist;
+ FspsUpd->FspsTestConfig.EnergyEfficientPState =3D (UINT8) CpuPow=
erMgmtTestConfig->EnergyEfficientPState;
+ FspsUpd->FspsTestConfig.EnergyEfficientTurbo =3D (UINT8) CpuPow=
erMgmtTestConfig->EnergyEfficientTurbo;
+ FspsUpd->FspsTestConfig.TStates =3D (UINT8) CpuPow=
erMgmtTestConfig->TStates;
+ FspsUpd->FspsTestConfig.BiProcHot =3D (UINT8) CpuPow=
erMgmtTestConfig->BiProcHot;
+ FspsUpd->FspsTestConfig.DisableProcHotOut =3D (UINT8) CpuPow=
erMgmtTestConfig->DisableProcHotOut;
+ FspsUpd->FspsTestConfig.ProcHotResponse =3D (UINT8) CpuPow=
erMgmtTestConfig->ProcHotResponse;
+ FspsUpd->FspsTestConfig.DisableVrThermalAlert =3D (UINT8) CpuPow=
erMgmtTestConfig->DisableVrThermalAlert;
+ FspsUpd->FspsTestConfig.AutoThermalReporting =3D (UINT8) CpuPow=
erMgmtTestConfig->AutoThermalReporting;
+ FspsUpd->FspsTestConfig.ThermalMonitor =3D (UINT8) CpuPow=
erMgmtTestConfig->ThermalMonitor;
+ FspsUpd->FspsTestConfig.Cx =3D (UINT8) CpuPow=
erMgmtTestConfig->Cx;
+ FspsUpd->FspsTestConfig.PmgCstCfgCtrlLock =3D (UINT8) CpuPow=
erMgmtTestConfig->PmgCstCfgCtrlLock;
+ FspsUpd->FspsTestConfig.C1e =3D (UINT8) CpuPow=
erMgmtTestConfig->C1e;
+ FspsUpd->FspsTestConfig.C1StateAutoDemotion =3D (UINT8) CpuPow=
erMgmtTestConfig->C1AutoDemotion;
+ FspsUpd->FspsTestConfig.C1StateUnDemotion =3D (UINT8) CpuPow=
erMgmtTestConfig->C1UnDemotion;
+ FspsUpd->FspsTestConfig.C3StateAutoDemotion =3D (UINT8) CpuPow=
erMgmtTestConfig->C3AutoDemotion;
+ FspsUpd->FspsTestConfig.C3StateUnDemotion =3D (UINT8) CpuPow=
erMgmtTestConfig->C3UnDemotion;
+ FspsUpd->FspsTestConfig.CstateLatencyControl0TimeUnit =3D (UINT8) CpuPow=
erMgmtTestConfig->CstateLatencyControl0TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl =3D (UINT16) CpuPo=
werMgmtTestConfig->CstateLatencyControl0Irtl;
+ FspsUpd->FspsTestConfig.PkgCStateDemotion =3D (UINT8) CpuPow=
erMgmtTestConfig->PkgCStateDemotion;
+ FspsUpd->FspsTestConfig.PkgCStateUnDemotion =3D (UINT8) CpuPow=
erMgmtTestConfig->PkgCStateUnDemotion;
+ FspsUpd->FspsTestConfig.CStatePreWake =3D (UINT8) CpuPow=
erMgmtTestConfig->CStatePreWake;
+ FspsUpd->FspsTestConfig.TimedMwait =3D (UINT8) CpuPow=
erMgmtTestConfig->TimedMwait;
+ FspsUpd->FspsTestConfig.CstCfgCtrIoMwaitRedirection =3D (UINT8) CpuPow=
erMgmtTestConfig->CstCfgCtrIoMwaitRedirection;
+ FspsUpd->FspsTestConfig.PkgCStateLimit =3D (UINT8) CpuPow=
erMgmtTestConfig->PkgCStateLimit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl1TimeUnit =3D (UINT8) CpuPow=
erMgmtTestConfig->CstateLatencyControl1TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl2TimeUnit =3D (UINT8) CpuPow=
erMgmtTestConfig->CstateLatencyControl2TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl3TimeUnit =3D (UINT8) CpuPow=
erMgmtTestConfig->CstateLatencyControl3TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl4TimeUnit =3D (UINT8) CpuPow=
erMgmtTestConfig->CstateLatencyControl4TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl5TimeUnit =3D (UINT8) CpuPow=
erMgmtTestConfig->CstateLatencyControl5TimeUnit;
+ FspsUpd->FspsTestConfig.PpmIrmSetting =3D (UINT8) CpuPow=
erMgmtTestConfig->PpmIrmSetting;
+ FspsUpd->FspsTestConfig.ProcHotLock =3D (UINT8) CpuPow=
erMgmtTestConfig->ProcHotLock;
+ FspsUpd->FspsTestConfig.RaceToHalt =3D (UINT8) CpuPow=
erMgmtTestConfig->RaceToHalt;
+ FspsUpd->FspsTestConfig.ConfigTdpLevel =3D (UINT8) CpuPow=
erMgmtTestConfig->ConfigTdpLevel;
+ FspsUpd->FspsTestConfig.CstateLatencyControl1Irtl =3D (UINT16) CpuPo=
werMgmtTestConfig->CstateLatencyControl1Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl2Irtl =3D (UINT16) CpuPo=
werMgmtTestConfig->CstateLatencyControl2Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl3Irtl =3D (UINT16) CpuPo=
werMgmtTestConfig->CstateLatencyControl3Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl4Irtl =3D (UINT16) CpuPo=
werMgmtTestConfig->CstateLatencyControl4Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl5Irtl =3D (UINT16) CpuPo=
werMgmtTestConfig->CstateLatencyControl5Irtl;
+
+ //
+ // Get BIST information from Sec Platform Information
+ //
+ SecPlatformInformation2 =3D GetSecPlatformInformation2 (PeiServices);
+ if (SecPlatformInformation2 =3D=3D NULL) {
+ SecPlatformInformation2 =3D GetSecPlatformInformationInfoInFormat2 (Pe=
iServices);
+ }
+
+ ASSERT (SecPlatformInformation2 !=3D NULL);
+
+ if (SecPlatformInformation2 !=3D NULL) {
+ FspsUpd->FspsConfig.CpuBistData =3D (UINT32)SecPlatformInformation2;
+ DEBUG((DEBUG_INFO, "SecPlatformInformation NumberOfCpus - %x\n", SecPl=
atformInformation2->NumberOfCpus));
+ DEBUG ((DEBUG_INFO, "SecPlatformInformation BIST - %x\n", SecPlatformI=
nformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32));
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspMePolicyInitLib.c b/Platform/Intel/CometlakeOpenBoardPk=
g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c
new file mode 100644
index 0000000000..66e7710595
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspMePolicyInitLib.c
@@ -0,0 +1,121 @@
+/** @file
+ Implementation of Fsp Me Policy Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <ConfigBlock/MePeiConfig.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ Performs FSP ME PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+ ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig;
+
+ DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n"));
+
+ //
+ // Locate gSiPreMemPolicyPpi
+ //
+ SiPreMemPolicy =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gMePeiPreMemConfigG=
uid, (VOID *) &MePeiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ FspmUpd->FspmConfig.HeciTimeouts =3D (UINT8) MePei=
PreMemConfig->HeciTimeouts;
+ //
+ // Test policies
+ //
+ FspmUpd->FspmTestConfig.DidInitStat =3D (UINT8) MePeiP=
reMemConfig->DidInitStat;
+ FspmUpd->FspmTestConfig.DisableCpuReplacedPolling =3D (UINT8) MePeiP=
reMemConfig->DisableCpuReplacedPolling;
+ FspmUpd->FspmTestConfig.SendDidMsg =3D (UINT8) MePeiP=
reMemConfig->SendDidMsg;
+ FspmUpd->FspmTestConfig.DisableMessageCheck =3D (UINT8) MePeiP=
reMemConfig->DisableMessageCheck;
+ FspmUpd->FspmTestConfig.SkipMbpHob =3D (UINT8) MePeiP=
reMemConfig->SkipMbpHob;
+
+ FspmUpd->FspmTestConfig.HeciCommunication2 =3D (UINT8) MePeiP=
reMemConfig->HeciCommunication2;
+ FspmUpd->FspmTestConfig.KtDeviceEnable =3D (UINT8) MePeiP=
reMemConfig->KtDeviceEnable;
+
+ FspmUpd->FspmConfig.Heci1BarAddress =3D MePeiPreMemCon=
fig->Heci1BarAddress;
+ FspmUpd->FspmConfig.Heci2BarAddress =3D MePeiPreMemCon=
fig->Heci2BarAddress;
+ FspmUpd->FspmConfig.Heci3BarAddress =3D MePeiPreMemCon=
fig->Heci3BarAddress;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs FSP ME PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ ME_PEI_CONFIG *MePeiConfig;
+
+ DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n"));
+ //
+ // Locate gSiPolicyPpiGuid
+ //
+ SiPolicyPpi =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI=
D *) &MePeiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ FspsUpd->FspsConfig.Heci3Enabled =3D (UINT8) MePeiConfi=
g->Heci3Enabled;
+ FspsUpd->FspsConfig.MeUnconfigOnRtcClear =3D (UINT8) MePeiConfi=
g->MeUnconfigOnRtcClear;
+
+ //
+ // Test policies
+ //
+ FspsUpd->FspsTestConfig.MctpBroadcastCycle =3D (UINT8) MePeiConfi=
g->MctpBroadcastCycle;
+ FspsUpd->FspsTestConfig.EndOfPostMessage =3D (UINT8) MePeiConfi=
g->EndOfPostMessage;
+ FspsUpd->FspsTestConfig.DisableD0I3SettingForHeci =3D (UINT8) MePeiConfi=
g->DisableD0I3SettingForHeci;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspMiscUpdInitLib.c b/Platform/Intel/CometlakeOpenBoardPkg=
/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c
new file mode 100644
index 0000000000..ee2558e9d3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspMiscUpdInitLib.c
@@ -0,0 +1,77 @@
+/** @file
+ Implementation of Fsp Misc UPD Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+
+#define STATUS_CODE_USE_RAM BIT0
+#define STATUS_CODE_USE_ISA_SERIAL BIT1
+#define STATUS_CODE_USE_USB BIT2
+#define STATUS_CODE_USE_USB3 BIT3
+#define STATUS_CODE_USE_SERIALIO BIT4
+#define STATUS_CODE_USE_TRACEHUB BIT5
+#define STATUS_CODE_CMOS_INVALID BIT6
+#define STATUS_CODE_CMOS_VALID BIT7
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ DEBUG_CONFIG_DATA_HOB *DebugConfigData;
+ UINT8 DebugInterfaces;
+
+ FspmUpd->FspmArchUpd.StackBase =3D (VOID *)(UINTN)(PcdGet32(PcdTemporary=
RamBase) + PcdGet32(PcdTemporaryRamSize) - (PcdGet32(PcdFspTemporaryRamSize=
) + PcdGet32(PcdFspReservedBufferSize)));
+ FspmUpd->FspmArchUpd.StackSize =3D PcdGet32(PcdFspTemporaryRamSize);
+
+ Status =3D PeiServicesGetBootMode (&(FspmUpd->FspmArchUpd.BootMode));
+ if (EFI_ERROR (Status)) {
+ FspmUpd->FspmArchUpd.BootMode =3D BOOT_WITH_FULL_CONFIGURATION;
+ }
+
+ FspmUpd->FspmArchUpd.BootLoaderTolumSize =3D 0x0;
+
+ //
+ // Initialize DebugConfigData
+ //
+ DebugInterfaces =3D 0x00;
+ Hob.Guid =3D GetFirstGuidHob (&gDebugConfigHobGuid);
+ if (Hob.Guid !=3D NULL) {
+ DebugConfigData =3D (DEBUG_CONFIG_DATA_HOB *) GET_GUID_HOB_DATA (Hob.G=
uid);
+ if (DebugConfigData !=3D NULL) {
+ // Debug Interfaces
+ if (DebugConfigData->RamDebugInterface) { DebugInterfaces |=3D =
STATUS_CODE_USE_RAM; }
+ if (DebugConfigData->UartDebugInterface) { DebugInterfaces |=3D =
STATUS_CODE_USE_ISA_SERIAL; }
+ if (DebugConfigData->Usb3DebugInterface) { DebugInterfaces |=3D =
STATUS_CODE_USE_USB3; }
+ if (DebugConfigData->SerialIoDebugInterface) { DebugInterfaces |=3D =
STATUS_CODE_USE_SERIALIO; }
+ if (DebugConfigData->TraceHubDebugInterface) { DebugInterfaces |=3D =
STATUS_CODE_USE_TRACEHUB; }
+ FspmUpd->FspmConfig.PcdDebugInterfaceFlags =3D DebugInterfaces;
+ // Serial debug message baud rate
+ FspmUpd->FspmConfig.PcdSerialDebugBaudRate =3D DebugConfigData->Ser=
ialDebugBaudRate;
+ //Serial debug message level
+ FspmUpd->FspmConfig.PcdSerialDebugLevel =3D DebugConfigData->Ser=
ialDebug;
+ }
+ }
+ DEBUG ((DEBUG_INFO, "FspmConfig.PcdDebugInterfaceFlags is 0x%X\n", FspmU=
pd->FspmConfig.PcdDebugInterfaceFlags));
+ DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugBaudRate is 0x%X\=
n", FspmUpd->FspmConfig.PcdSerialDebugBaudRate));
+ DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugLevel is 0x%X\n",=
FspmUpd->FspmConfig.PcdSerialDebugLevel));
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspPchPolicyInitLib.c b/Platform/Intel/CometlakeOpenBoardP=
kg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c
new file mode 100644
index 0000000000..65ec61f5ac
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspPchPolicyInitLib.c
@@ -0,0 +1,743 @@
+/** @file
+ Implementation of Fsp PCH Policy Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ Performs FSP PCH PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN MaxPcieRootPorts;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+ PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig;
+ PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig;
+ PCH_DCI_PREMEM_CONFIG *DciPreMemConfig;
+ PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
+ PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
+ PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig;
+ PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
+ PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig;
+ PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig;
+ PCH_ISH_PREMEM_CONFIG *IshPreMemConfig;
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicyPreMem\n"));
+ DEBUG((DEBUG_INFO | DEBUG_INIT, "FspmUpd =3D 0x%x\n", FspmUpd));
+ //
+ // Locate PchPreMemPolicyPpi
+ //
+ SiPreMemPolicy =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemC=
onfigGuid, (VOID *) &PchTraceHubPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigG=
uid, (VOID *) &SmbusPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGui=
d, (VOID *) &DciPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPciePreMemConf=
igGuid, (VOID *) &HsioPciePreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConf=
igGuid, (VOID *) &HsioSataPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGui=
d, (VOID *) &LpcPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemCo=
nfigGuid, (VOID *) &PchGeneralPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConf=
igGuid, (VOID *) &WdtPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfig=
Guid, (VOID *) &PcieRpPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfi=
gGuid, (VOID *) &HdaPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGui=
d, (VOID *) &IshPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ UpdatePeiPchPolicyPreMem\n"));
+ //
+ // Update PCIE RP policies
+ //
+// MaxPcieRootPorts =3D 16;
+
+ MaxPcieRootPorts =3D GetPchMaxPciePortNum ();
+// MaxPcieRootPorts =3D 16;
+ FspmUpd->FspmConfig.PcieRpEnableMask =3D PcieRpPreMemConfig->RpEnabledMa=
sk & ((1 << MaxPcieRootPorts) - 1);
+ FspmUpd->FspmConfig.PcieImrEnabled =3D PcieRpPreMemConfig->PcieImrEnable=
d;
+ FspmUpd->FspmConfig.PcieImrSize =3D PcieRpPreMemConfig->PcieImrSize;
+ FspmUpd->FspmConfig.ImrRpSelection =3D PcieRpPreMemConfig->ImrRpSelectio=
n;
+ //
+ // Update TraceHub policies
+ //
+ FspmUpd->FspmConfig.PchTraceHubMode =3D (UINT8) PchTraceHubPreMemConfig-=
>EnableMode;
+ FspmUpd->FspmConfig.PchTraceHubMemReg0Size =3D (UINT8) PchTraceHubPreMem=
Config->MemReg0Size;
+ FspmUpd->FspmConfig.PchTraceHubMemReg1Size =3D (UINT8) PchTraceHubPreMem=
Config->MemReg1Size;
+
+ //
+ // Update Smbus policies
+ //
+ FspmUpd->FspmConfig.SmbusEnable =3D (UINT8)SmbusPreMemConfig->Enable;
+ FspmUpd->FspmConfig.SmbusArpEnable =3D (UINT8)SmbusPreMemConfig->ArpEnab=
le;
+ FspmUpd->FspmTestConfig.SmbusDynamicPowerGating =3D (UINT8)SmbusPreMemCo=
nfig->DynamicPowerGating;
+ FspmUpd->FspmTestConfig.SmbusSpdWriteDisable =3D (UINT8)SmbusPreMemConfi=
g->SpdWriteDisable;
+ FspmUpd->FspmConfig.PchSmbAlertEnable =3D (UINT8)SmbusPreMemConfig->SmbA=
lertEnable;
+ FspmUpd->FspmConfig.PchSmbusIoBase =3D (UINT16)SmbusPreMemConfig->SmbusI=
oBase;
+ FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses =3D (UINT8)SmbusPreMemConfi=
g->NumRsvdSmbusAddresses;
+ FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr =3D (UINT32)SmbusPreMemConf=
ig->RsvdSmbusAddressTable;
+
+ DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ1 UpdatePeiPchPolicyPreMem\n"));
+ //
+ // Update Dci policies
+ //
+ FspmUpd->FspmConfig.PlatformDebugConsent =3D (UINT8)DciPreMemConfig->Pla=
tformDebugConsent;
+ DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ11 UpdatePeiPchPolicyPreMem\n"));
+ FspmUpd->FspmConfig.DciUsb3TypecUfpDbg =3D (UINT8)DciPreMemConfig->DciUs=
b3TypecUfpDbg;
+ //
+ // Update HSIO PCIE policies
+ //
+ for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) {
+ FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable;
+ FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index] =3D (U=
INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0;
+ }
+
+ //
+ // Update HSIO SATA policies
+ //
+ for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index ++) {
+ FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable;
+ FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag;
+ FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable;
+ FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag;
+ FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable;
+ FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp;
+ FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph;
+ FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index] =3D (U=
INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph;
+ }
+ DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ2 UpdatePeiPchPolicyPreMem\n"));
+ // Update LPC policies
+ //
+ FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding =3D (UINT8)LpcPreMemCon=
fig->EnhancePort8xhDecoding;
+
+ //
+ // Update Pch General Premem policies
+ //
+ FspmUpd->FspmConfig.PchPort80Route =3D (UINT8)PchGeneralPreMemConfig->Po=
rt80Route;
+
+ //
+ // Update Wdt policies
+ //
+ FspmUpd->FspmTestConfig.WdtDisableAndLock =3D (UINT8)WdtPreMemConfig->Di=
sableAndLock;
+
+ //
+ // HdAudioConfig
+ //
+ FspmUpd->FspmConfig.PchHdaEnable =3D (UINT8)HdaPreMemConfig->Enable;
+
+ //
+ // IshConfig
+ //
+ FspmUpd->FspmConfig.PchIshEnable =3D (UINT8)IshPreMemConfig->Enable;
+
+ DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ3 UpdatePeiPchPolicyPreMem\n"));
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN MaxPcieRootPorts;
+ UINT8 Data8;
+ SI_POLICY_PPI *SiPolicy;
+ PCH_LAN_CONFIG *LanConfig;
+ PCH_HDAUDIO_CONFIG *HdAudioConfig;
+ PCH_SCS_CONFIG *ScsConfig;
+ PCH_ISH_CONFIG *IshConfig;
+ PCH_SATA_CONFIG *SataConfig;
+ USB_CONFIG *UsbConfig;
+ PCH_SERIAL_IO_CONFIG *SerialIoConfig;
+ PCH_INTERRUPT_CONFIG *InterruptConfig;
+ PCH_LOCK_DOWN_CONFIG *LockDownConfig;
+ PCH_CNVI_CONFIG *CnviConfig;
+ PCH_HSIO_CONFIG *HsioConfig;
+ PCH_ESPI_CONFIG *EspiConfig;
+ PCH_PCIE_CONFIG *PcieRpConfig;
+ PCH_DMI_CONFIG *DmiConfig;
+ PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
+ PCH_IOAPIC_CONFIG *IoApicConfig;
+ PCH_P2SB_CONFIG *P2sbConfig;
+ PCH_GENERAL_CONFIG *PchGeneralConfig;
+ PCH_PM_CONFIG *PmConfig;
+ PCH_LPC_SIRQ_CONFIG *PchSerialIrqConfig;
+ PCH_THERMAL_CONFIG *PchThermalConfig;
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n"));
+ //
+ // Locate SiPolicyPpi
+ //
+ SiPolicy =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) =
&LanConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID=
*) &HdAudioConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) =
&ScsConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) =
&IshConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *)=
&SataConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) =
&UsbConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOI=
D *) &SerialIoConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VO=
ID *) &InterruptConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOI=
D *) &LockDownConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID =
*) &PcieRpConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) =
&DmiConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGui=
d, (VOID *) &FlashProtectionConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID =
*) &IoApicConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *)=
&P2sbConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (V=
OID *) &PchGeneralConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &=
PmConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VO=
ID *) &PchSerialIrqConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID=
*) &PchThermalConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *)=
&CnviConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHsioConfigGuid, (VOID *)=
&HsioConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *)=
&EspiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update LAN policies
+ //
+ FspsUpd->FspsConfig.PchLanEnable =3D (UINT8)LanConfig->Enable;
+ FspsUpd->FspsConfig.PchLanLtrEnable =3D (UINT8)LanConfig->LtrEnabl=
e;
+
+ //
+ // Update HDA policies
+ //
+ FspsUpd->FspsConfig.PchHdaDspEnable =3D (UINT8)HdAudioConfig=
->DspEnable;
+ FspsUpd->FspsConfig.PchHdaPme =3D (UINT8)HdAudioConfig=
->Pme;
+ FspsUpd->FspsConfig.PchHdaVcType =3D (UINT8)HdAudioConfig=
->VcType;
+ FspsUpd->FspsConfig.PchHdaLinkFrequency =3D (UINT8)HdAudioConfig=
->HdAudioLinkFrequency;
+ FspsUpd->FspsConfig.PchHdaIDispLinkFrequency =3D (UINT8)HdAudioConfig=
->IDispLinkFrequency;
+ FspsUpd->FspsConfig.PchHdaIDispLinkTmode =3D (UINT8)HdAudioConfig=
->IDispLinkTmode;
+ FspsUpd->FspsConfig.PchHdaDspUaaCompliance =3D (UINT8)HdAudioConfig=
->DspUaaCompliance;
+ FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect =3D (UINT8)HdAudioConfig=
->IDispCodecDisconnect;
+ FspsUpd->FspsConfig.PchHdaCodecSxWakeCapability =3D (UINT8)HdAudioConfig=
->CodecSxWakeCapability;
+ FspsUpd->FspsTestConfig.PchHdaResetWaitTimer =3D (UINT16)HdAudioConfi=
g->ResetWaitTimer;
+ FspsUpd->FspsConfig.PchHdaVerbTableEntryNum =3D HdAudioConfig->VerbT=
ableEntryNum;
+ FspsUpd->FspsConfig.PchHdaVerbTablePtr =3D HdAudioConfig->VerbT=
ablePtr;
+ FspsUpd->FspsConfig.PchHdaAudioLinkHda =3D (UINT8)HdAudioConfig=
->AudioLinkHda;
+ FspsUpd->FspsConfig.PchHdaAudioLinkDmic0 =3D (UINT8)HdAudioConfig=
->AudioLinkDmic0;
+ FspsUpd->FspsConfig.PchHdaAudioLinkDmic1 =3D (UINT8)HdAudioConfig=
->AudioLinkDmic1;
+ FspsUpd->FspsConfig.PchHdaAudioLinkSsp0 =3D (UINT8)HdAudioConfig=
->AudioLinkSsp0;
+ FspsUpd->FspsConfig.PchHdaAudioLinkSsp1 =3D (UINT8)HdAudioConfig=
->AudioLinkSsp1;
+ FspsUpd->FspsConfig.PchHdaAudioLinkSsp2 =3D (UINT8)HdAudioConfig=
->AudioLinkSsp2;
+ FspsUpd->FspsConfig.PchHdaAudioLinkSndw1 =3D (UINT8)HdAudioConfig=
->AudioLinkSndw1;
+ FspsUpd->FspsConfig.PchHdaAudioLinkSndw2 =3D (UINT8)HdAudioConfig=
->AudioLinkSndw2;
+ FspsUpd->FspsConfig.PchHdaAudioLinkSndw3 =3D (UINT8)HdAudioConfig=
->AudioLinkSndw3;
+ FspsUpd->FspsConfig.PchHdaAudioLinkSndw4 =3D (UINT8)HdAudioConfig=
->AudioLinkSndw4;
+ FspsUpd->FspsConfig.PchHdaSndwBufferRcomp =3D (UINT8)HdAudioConfig=
->SndwBufferRcomp;
+
+ //
+ // Update SCS policies
+ //
+ FspsUpd->FspsConfig.ScsEmmcEnabled =3D (UINT8)ScsConfig->ScsEmmcEnabled;
+ FspsUpd->FspsConfig.ScsEmmcHs400Enabled =3D (UINT8)ScsConfig->ScsEmmcHs4=
00Enabled;
+ FspsUpd->FspsConfig.ScsSdCardEnabled =3D (UINT8)ScsConfig->ScsSdcardEnab=
led;
+ FspsUpd->FspsConfig.SdCardPowerEnableActiveHigh =3D (UINT8)ScsConfig->Sd=
CardPowerEnableActiveHigh;
+#ifdef CFL_SIMICS
+ FspsUpd->FspsConfig.ScsUfsEnabled =3D 0;
+#else
+ FspsUpd->FspsConfig.ScsUfsEnabled =3D (UINT8)ScsConfig->ScsUfsEnabled;
+#endif
+ FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired =3D (UINT8)ScsConfig->=
ScsEmmcHs400TuningRequired;
+ FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid =3D (UINT8)ScsConfig->=
ScsEmmcHs400DllDataValid;
+ FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1 =3D (UINT8)ScsConfig->=
ScsEmmcHs400RxStrobeDll1;
+ FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll =3D (UINT8)ScsConfig->=
ScsEmmcHs400TxDataDll;
+ FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength =3D (UINT8)ScsConfig->=
ScsEmmcHs400DriverStrength;
+
+ //
+ // Update ISH policies
+ //
+ FspsUpd->FspsConfig.PchIshSpiGpioAssign =3D (UINT8)IshConfig->SpiGpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshUart0GpioAssign =3D (UINT8)IshConfig->Uart0Gpi=
oAssign;
+ FspsUpd->FspsConfig.PchIshUart1GpioAssign =3D (UINT8)IshConfig->Uart1Gpi=
oAssign;
+ FspsUpd->FspsConfig.PchIshI2c0GpioAssign =3D (UINT8)IshConfig->I2c0Gpio=
Assign;
+ FspsUpd->FspsConfig.PchIshI2c1GpioAssign =3D (UINT8)IshConfig->I2c1Gpio=
Assign;
+ FspsUpd->FspsConfig.PchIshI2c2GpioAssign =3D (UINT8)IshConfig->I2c2Gpio=
Assign;
+ FspsUpd->FspsConfig.PchIshGp0GpioAssign =3D (UINT8)IshConfig->Gp0GpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshGp1GpioAssign =3D (UINT8)IshConfig->Gp1GpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshGp2GpioAssign =3D (UINT8)IshConfig->Gp2GpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshGp3GpioAssign =3D (UINT8)IshConfig->Gp3GpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshGp4GpioAssign =3D (UINT8)IshConfig->Gp4GpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshGp5GpioAssign =3D (UINT8)IshConfig->Gp5GpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshGp6GpioAssign =3D (UINT8)IshConfig->Gp6GpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshGp7GpioAssign =3D (UINT8)IshConfig->Gp7GpioA=
ssign;
+ FspsUpd->FspsConfig.PchIshPdtUnlock =3D (UINT8)IshConfig->PdtUnloc=
k;
+
+ //
+ // Update PCIE RP RootPort policies
+ //
+ MaxPcieRootPorts =3D GetPchMaxPciePortNum ();
+ FspsUpd->FspsConfig.PcieRpDpcMask =3D 0;
+ FspsUpd->FspsConfig.PcieRpDpcExtensionsMask =3D 0;
+ FspsUpd->FspsConfig.PcieRpPtmMask =3D 0;
+ for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) {
+ FspsUpd->FspsConfig.PcieRpHotPlug[Index] =3D (UINT8)PcieRpConfig->Root=
Port[Index].HotPlug;
+ FspsUpd->FspsConfig.PcieRpSlotImplemented[Index] =3D (UINT8)PcieRpConf=
ig->RootPort[Index].SlotImplemented;
+ FspsUpd->FspsConfig.PcieRpPmSci[Index] =3D (UINT8)PcieRpConfig->RootPo=
rt[Index].PmSci;
+ FspsUpd->FspsConfig.PcieRpExtSync[Index] =3D (UINT8)PcieRpConfig->Root=
Port[Index].ExtSync;
+ FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] =3D (UINT8)PcieR=
pConfig->RootPort[Index].TransmitterHalfSwing;
+ FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] =3D (UINT8)PcieRpConfig-=
>RootPort[Index].ClkReqDetect;
+ FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] =3D (UINT8)Pci=
eRpConfig->RootPort[Index].AdvancedErrorReporting;
+ FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] =3D (UINT8)P=
cieRpConfig->RootPort[Index].UnsupportedRequestReport;
+ FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] =3D (UINT8)PcieRpCon=
fig->RootPort[Index].FatalErrorReport;
+ FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] =3D (UINT8)PcieRpC=
onfig->RootPort[Index].NoFatalErrorReport;
+ FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] =3D (UINT8)Pci=
eRpConfig->RootPort[Index].CorrectableErrorReport;
+ FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] =3D (UINT8)Pc=
ieRpConfig->RootPort[Index].SystemErrorOnFatalError;
+ FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] =3D (UINT8=
)PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError;
+ FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] =3D (UI=
NT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError;
+ FspsUpd->FspsConfig.PcieRpMaxPayload[Index] =3D (UINT8)PcieRpConfig->R=
ootPort[Index].MaxPayload;
+ if (PcieRpConfig->RootPort[Index].DpcEnabled) {
+ FspsUpd->FspsConfig.PcieRpDpcMask |=3D (BIT0<<Index);
+ }
+ if (PcieRpConfig->RootPort[Index].RpDpcExtensionsEnabled) {
+ FspsUpd->FspsConfig.PcieRpDpcExtensionsMask |=3D (BIT0<<Index);
+ }
+ if (PcieRpConfig->RootPort[Index].PtmEnabled) {
+ FspsUpd->FspsConfig.PcieRpPtmMask |=3D (BIT0<<Index);
+ }
+ FspsUpd->FspsConfig.PcieRpPcieSpeed[Index] =3D (UINT8)PcieRpConfig->Ro=
otPort[Index].PcieSpeed;
+ FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] =3D (UINT8)PcieRpConf=
ig->RootPort[Index].Gen3EqPh3Method;
+ FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] =3D (UINT8)PcieRpC=
onfig->RootPort[Index].PhysicalSlotNumber;
+ FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] =3D (UINT8)PcieRpCo=
nfig->RootPort[Index].CompletionTimeout;
+ FspsUpd->FspsConfig.PcieRpAspm[Index] =3D (UINT8)PcieRpConfig->RootPor=
t[Index].Aspm;
+ FspsUpd->FspsConfig.PcieRpL1Substates[Index] =3D (UINT8)PcieRpConfig->=
RootPort[Index].L1Substates;
+ FspsUpd->FspsConfig.PcieRpLtrEnable[Index] =3D (UINT8)PcieRpConfig->Ro=
otPort[Index].LtrEnable;
+ FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] =3D (UINT8)PcieRpConfig=
->RootPort[Index].LtrConfigLock;
+ FspsUpd->FspsConfig.PcieRpAcsEnabled[Index] =3D (UINT8)PcieRpConfig->R=
ootPort[Index].AcsEnabled;
+ FspsUpd->FspsConfig.PcieRpDetectTimeoutMs[Index] =3D (UINT16)PcieRpCon=
fig->RootPort[Index].DetectTimeoutMs;
+ FspsUpd->FspsConfig.PcieRootPortGen2PllL1CgDisable[Index] =3D (UINT8)P=
cieRpConfig->RootPort[Index].PcieRootPortGen2PllL1CgDisable;
+
+ FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] =3D (UINT16)Pc=
ieRpConfig->RootPort[Index].LtrMaxSnoopLatency;
+ FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] =3D (UINT16)=
PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency;
+
+ FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] =3D (UIN=
T8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode;
+ FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] =
=3D (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier;
+ FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] =3D (UI=
NT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue;
+
+ FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] =3D (=
UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode;
+ FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index]=
=3D (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier;
+ FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] =3D =
(UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue;
+
+ FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] =3D (UINT8)Pc=
ieRpConfig->RootPort[Index].SlotPowerLimitScale;
+ FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] =3D (UINT16)P=
cieRpConfig->RootPort[Index].SlotPowerLimitValue;
+ FspsUpd->FspsTestConfig.PcieRpUptp[Index] =3D (UINT8)PcieRpConfig->Roo=
tPort[Index].Uptp;
+ FspsUpd->FspsTestConfig.PcieRpDptp[Index] =3D (UINT8)PcieRpConfig->Roo=
tPort[Index].Dptp;
+
+ }
+ for (Index =3D 0; Index < GetPchMaxPcieClockNum (); Index ++) {
+ FspsUpd->FspsConfig.PcieClkSrcUsage[Index] =3D PcieRpConfig->PcieClock=
[Index].Usage;
+ FspsUpd->FspsConfig.PcieClkSrcClkReq[Index] =3D PcieRpConfig->PcieCloc=
k[Index].ClkReq;
+ }
+
+ //
+ // Update PCIE RP EqPh3LaneParam policies
+ //
+ for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) {
+ FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] =3D (UINT8)PcieRpConfi=
g->EqPh3LaneParam[Index].Cm;
+ FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] =3D (UINT8)PcieRpConfi=
g->EqPh3LaneParam[Index].Cp;
+ }
+
+ //
+ // Update PCIE RP SwEqCoeffList policies
+ //
+ for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) {
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] =3D (UINT8)PcieRpConfig=
->SwEqCoeffList[Index].Cm;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] =3D (UINT8)PcieRpConfig=
->SwEqCoeffList[Index].Cp;
+ }
+
+ //
+ // Update PCIE RP policies
+ //
+ FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode =3D (UINT8)PcieRp=
Config->EnablePort8xhDecode;
+ FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex =3D (UINT8)PcieRp=
Config->PchPciePort8xhDecodePortIndex;
+ FspsUpd->FspsConfig.PcieDisableRootPortClockGating =3D (UINT8)PcieRpConf=
ig->DisableRootPortClockGating;
+ FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite =3D (UINT8)PcieRpConf=
ig->EnablePeerMemoryWrite;
+ FspsUpd->FspsConfig.PcieComplianceTestMode =3D (UINT8)PcieRpConf=
ig->ComplianceTestMode;
+ FspsUpd->FspsConfig.PcieRpFunctionSwap =3D (UINT8)PcieRpConf=
ig->RpFunctionSwap;
+ FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D PcieRpConfig->Pci=
eDeviceOverrideTablePtr;
+
+ //
+ // Update Sata Policies
+ //
+ FspsUpd->FspsConfig.SataEnable =3D (UINT8)SataConfig=
->Enable;
+ FspsUpd->FspsTestConfig.SataTestMode =3D (UINT8)SataConfig=
->TestMode;
+ FspsUpd->FspsConfig.SataSalpSupport =3D (UINT8)SataConfig=
->SalpSupport;
+ FspsUpd->FspsConfig.SataPwrOptEnable =3D (UINT8)SataConfig->PwrOptEnable;
+ FspsUpd->FspsConfig.EsataSpeedLimit =3D (UINT8)SataConfig->EsataSpeedLi=
mit;
+ FspsUpd->FspsConfig.SataLedEnable =3D (UINT8)SataConfig->LedEnable;
+ FspsUpd->FspsConfig.SataMode =3D (UINT8)SataConfig->SataMode;
+ FspsUpd->FspsConfig.SataSpeedLimit =3D (UINT8)SataConfig->SpeedLimit;
+
+ for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index++) {
+ FspsUpd->FspsConfig.SataPortsEnable[Index] =3D (UINT8)SataConfig->Port=
Settings[Index].Enable;
+ FspsUpd->FspsConfig.SataPortsHotPlug[Index] =3D (UINT8)SataConfig-=
>PortSettings[Index].HotPlug;
+ FspsUpd->FspsConfig.SataPortsInterlockSw[Index] =3D (UINT8)SataConfig-=
>PortSettings[Index].InterlockSw;
+ FspsUpd->FspsConfig.SataPortsExternal[Index] =3D (UINT8)SataConfig-=
>PortSettings[Index].External;
+ FspsUpd->FspsConfig.SataPortsSpinUp[Index] =3D (UINT8)SataConfig-=
>PortSettings[Index].SpinUp;
+ FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index] =3D (UINT8)SataCo=
nfig->PortSettings[Index].SolidStateDrive;
+ FspsUpd->FspsConfig.SataPortsDevSlp[Index] =3D (UINT8)SataConfig->Port=
Settings[Index].DevSlp;
+ FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] =3D (UINT8)SataCo=
nfig->PortSettings[Index].EnableDitoConfig;
+ FspsUpd->FspsConfig.SataPortsDmVal[Index] =3D (UINT8)SataConfig-=
>PortSettings[Index].DmVal;
+ FspsUpd->FspsConfig.SataPortsDitoVal[Index] =3D (UINT16)SataConfig=
->PortSettings[Index].DitoVal;
+ FspsUpd->FspsConfig.SataPortsZpOdd[Index] =3D (UINT8)SataConfig-=
>PortSettings[Index].ZpOdd;
+ }
+
+ FspsUpd->FspsConfig.SataRstRaidDeviceId =3D (UINT8)SataConfig=
->Rst.RaidDeviceId;
+ FspsUpd->FspsConfig.SataRstInterrupt =3D (UINT8)SataConfig=
->Rst.SataRstInterrupt;
+ FspsUpd->FspsConfig.SataRstRaid0 =3D (UINT8)SataConfig=
->Rst.Raid0;
+ FspsUpd->FspsConfig.SataRstRaid1 =3D (UINT8)SataConfig=
->Rst.Raid1;
+ FspsUpd->FspsConfig.SataRstRaid10 =3D (UINT8)SataConfig=
->Rst.Raid10;
+ FspsUpd->FspsConfig.SataRstRaid5 =3D (UINT8)SataConfig=
->Rst.Raid5;
+ FspsUpd->FspsConfig.SataRstIrrt =3D (UINT8)SataConfig=
->Rst.Irrt;
+ FspsUpd->FspsConfig.SataRstOromUiBanner =3D (UINT8)SataConfig=
->Rst.OromUiBanner;
+ FspsUpd->FspsConfig.SataRstOromUiDelay =3D (UINT8)SataConfig=
->Rst.OromUiDelay;
+ FspsUpd->FspsConfig.SataRstHddUnlock =3D (UINT8)SataConfig=
->Rst.HddUnlock;
+ FspsUpd->FspsConfig.SataRstLedLocate =3D (UINT8)SataConfig=
->Rst.LedLocate;
+ FspsUpd->FspsConfig.SataRstIrrtOnly =3D (UINT8)SataConfig=
->Rst.IrrtOnly;
+ FspsUpd->FspsConfig.SataRstSmartStorage =3D (UINT8)SataConfig=
->Rst.SmartStorage;
+ FspsUpd->FspsConfig.SataRstOptaneMemory =3D (UINT8)SataConfig=
->Rst.OptaneMemory;
+ FspsUpd->FspsConfig.SataRstLegacyOrom =3D (UINT8)SataConfig=
->Rst.LegacyOrom;
+ FspsUpd->FspsConfig.SataRstCpuAttachedStorage =3D (UINT8)SataConfig=
->Rst.CpuAttachedStorage;
+
+ for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
+ FspsUpd->FspsConfig.SataRstPcieEnable[Index] =3D (UINT8)Sata=
Config->RstPcieStorageRemap[Index].Enable;
+ FspsUpd->FspsConfig.SataRstPcieStoragePort[Index] =3D (UINT8)Sata=
Config->RstPcieStorageRemap[Index].RstPcieStoragePort;
+ FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] =3D (UINT8)Sata=
Config->RstPcieStorageRemap[Index].DeviceResetDelay;
+ }
+
+ FspsUpd->FspsConfig.SataP0T1M =3D (UINT8)SataConfig->ThermalT=
hrottling.P0T1M;
+ FspsUpd->FspsConfig.SataP0T2M =3D (UINT8)SataConfig->ThermalT=
hrottling.P0T2M;
+ FspsUpd->FspsConfig.SataP0T3M =3D (UINT8)SataConfig->ThermalT=
hrottling.P0T3M;
+ FspsUpd->FspsConfig.SataP0TDisp =3D (UINT8)SataConfig->ThermalT=
hrottling.P0TDisp;
+ FspsUpd->FspsConfig.SataP1T1M =3D (UINT8)SataConfig->ThermalT=
hrottling.P1T1M;
+ FspsUpd->FspsConfig.SataP1T2M =3D (UINT8)SataConfig->ThermalT=
hrottling.P1T2M;
+ FspsUpd->FspsConfig.SataP1T3M =3D (UINT8)SataConfig->ThermalT=
hrottling.P1T3M;
+ FspsUpd->FspsConfig.SataP1TDisp =3D (UINT8)SataConfig->ThermalT=
hrottling.P1TDisp;
+ FspsUpd->FspsConfig.SataP0Tinact =3D (UINT8)SataConfig->ThermalT=
hrottling.P0Tinact;
+ FspsUpd->FspsConfig.SataP0TDispFinit =3D (UINT8)SataConfig->ThermalT=
hrottling.P0TDispFinit;
+ FspsUpd->FspsConfig.SataP1Tinact =3D (UINT8)SataConfig->ThermalT=
hrottling.P1Tinact;
+ FspsUpd->FspsConfig.SataP1TDispFinit =3D (UINT8)SataConfig->ThermalT=
hrottling.P1TDispFinit;
+ FspsUpd->FspsConfig.SataThermalSuggestedSetting =3D (UINT8)SataConfig->T=
hermalThrottling.SuggestedSetting;
+
+ //
+ // Update USB policies
+ //
+ FspsUpd->FspsConfig.PchEnableComplianceMode =3D (UINT8)UsbConf=
ig->EnableComplianceMode;
+ FspsUpd->FspsConfig.UsbPdoProgramming =3D (UINT8)UsbConf=
ig->PdoProgramming;
+ FspsUpd->FspsConfig.PchUsbOverCurrentEnable =3D (UINT8)UsbConf=
ig->OverCurrentEnable;
+ FspsUpd->FspsConfig.PchUsb2PhySusPgEnable =3D (UINT8)UsbConf=
ig->Usb2PhySusPgEnable;
+ FspsUpd->FspsTestConfig.PchXhciOcLock =3D (UINT8)UsbConf=
ig->XhciOcLock;
+ for (Index =3D 0; Index < PCH_MAX_USB2_PORTS; Index++) {
+ FspsUpd->FspsConfig.PortUsb20Enable[Index] =3D (UINT8)UsbConfig->Port=
Usb20[Index].Enable;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] =3D (UINT8)UsbConfig->Po=
rtUsb20[Index].OverCurrentPin;
+ FspsUpd->FspsConfig.Usb2AfePetxiset[Index] =3D (UINT8)UsbConfig->Port=
Usb20[Index].Afe.Petxiset;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[Index] =3D (UINT8)UsbConfig->Port=
Usb20[Index].Afe.Txiset;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[Index] =3D (UINT8)UsbConfig->Port=
Usb20[Index].Afe.Predeemp;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] =3D (UINT8)UsbConfig->Port=
Usb20[Index].Afe.Pehalfbit;
+ }
+ for (Index =3D 0; Index < PCH_MAX_USB3_PORTS; Index++) {
+ FspsUpd->FspsConfig.PortUsb30Enable[Index] =3D (UINT8)Usb=
Config->PortUsb30[Index].Enable;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] =3D (UINT8)Usb=
Config->PortUsb30[Index].OverCurrentPin;
+ FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] =3D (UINT8)Usb=
Config->PortUsb30[Index].HsioTxDeEmphEnable;
+ FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] =3D (UINT8)Usb=
Config->PortUsb30[Index].HsioTxDeEmph;
+ FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] =3D (UINT8)Usb=
Config->PortUsb30[Index].HsioTxDownscaleAmpEnable;
+ FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] =3D (UINT8)Usb=
Config->PortUsb30[Index].HsioTxDownscaleAmp;
+
+ Data8 =3D 0;
+ Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfgEna=
ble ? B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN : 0;
+ Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelNEnable ? B_=
XHCI_HSIO_FILTER_SELECT_N_EN : 0;
+ Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelPEnable ? B_=
XHCI_HSIO_FILTER_SELECT_P_EN : 0;
+ Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnResE=
nable ? B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN : 0;
+ FspsUpd->FspsConfig.PchUsbHsioRxTuningEnable[Index] =3D Data8;
+
+ Data8 =3D ((UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfg &=
0x1F) << N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG) |
+ ((UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnRes &=
0x7) << N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES);
+ FspsUpd->FspsConfig.PchUsbHsioRxTuningParameters[Index] =3D Data8;
+
+ Data8 =3D ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelN & 0x7) <<=
N_XHCI_UPD_HSIO_FILTER_SELECT_N) |
+ ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelP & 0x7) << N=
_XHCI_UPD_HSIO_FILTER_SELECT_P);
+ FspsUpd->FspsConfig.PchUsbHsioFilterSel[Index] =3D Data8;
+ }
+
+ FspsUpd->FspsConfig.XdciEnable =3D (UINT8)UsbConfig->XdciConfig.Enab=
le;
+
+ //
+ // Update SerialIo policies
+ //
+ for (Index =3D 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index++=
) {
+ FspsUpd->FspsConfig.SerialIoSpiMode[Index] =3D SerialIoConfig->DevMode=
[Index];
+ }
+
+ //
+ // SPI CS Polarity
+ //
+ FspsUpd->FspsConfig.SerialIoSpi0CsPolarity[0] =3D 1;
+ FspsUpd->FspsConfig.SerialIoSpi0CsPolarity[1] =3D 0;
+ FspsUpd->FspsConfig.SerialIoSpi1CsPolarity[0] =3D 0;
+ FspsUpd->FspsConfig.SerialIoSpi1CsPolarity[1] =3D 0;
+ FspsUpd->FspsConfig.SerialIoSpi2CsPolarity[0] =3D 1;
+ FspsUpd->FspsConfig.SerialIoSpi2CsPolarity[1] =3D 0;
+ for (Index =3D 0; Index < GetPchMaxSerialIoUartControllersNum (); Index+=
+) {
+ FspsUpd->FspsConfig.SerialIoUartAutoFlow[Index] =3D SerialIoConfig->Ua=
rtHwFlowCtrl[Index];
+ }
+ for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++=
) {
+ FspsUpd->FspsConfig.SerialIoI2cMode[Index] =3D SerialIoC=
onfig->DevMode[Index];
+ FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index] =3D SerialIoC=
onfig->I2cPadsTermination[Index];
+ }
+
+ FspsUpd->FspsConfig.SerialIoDebugUartNumber =3D (UINT8)SerialIo=
Config->DebugUartNumber;
+ FspsUpd->FspsConfig.SerialIoUartPinMux[0] =3D (UINT8)SerialIo=
Config->Uart0PinMuxing;
+
+ //
+ // Update Interrupt policies
+ //
+ FspsUpd->FspsConfig.DevIntConfigPtr =3D (UINT32)InterruptConfig->DevIntC=
onfig;
+ FspsUpd->FspsConfig.NumOfDevIntConfig =3D InterruptConfig->NumOfDevIntCo=
nfig;
+ for (Index =3D 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) {
+ FspsUpd->FspsConfig.PxRcConfig[Index] =3D (UINT8)InterruptConfig->PxRc=
Config[Index];
+ }
+ FspsUpd->FspsConfig.GpioIrqRoute =3D (UINT8)InterruptConfig->GpioIrqRout=
e;
+ FspsUpd->FspsConfig.SciIrqSelect =3D (UINT8)InterruptConfig->SciIrqSelec=
t;
+ FspsUpd->FspsConfig.TcoIrqSelect =3D (UINT8)InterruptConfig->TcoIrqSelec=
t;
+ FspsUpd->FspsConfig.TcoIrqEnable =3D (UINT8)InterruptConfig->TcoIrqEnabl=
e;
+
+ //
+ // Update LockDown policies
+ //
+ FspsUpd->FspsTestConfig.PchLockDownGlobalSmi =3D (UINT8)LockDownConf=
ig->GlobalSmi;
+ FspsUpd->FspsTestConfig.PchLockDownBiosInterface =3D (UINT8)LockDownConf=
ig->BiosInterface;
+ FspsUpd->FspsConfig.PchLockDownBiosLock =3D (UINT8)LockDownConf=
ig->BiosLock;
+ FspsUpd->FspsConfig.PchLockDownRtcMemoryLock =3D (UINT8)LockDownConf=
ig->RtcMemoryLock;
+ FspsUpd->FspsTestConfig.PchUnlockGpioPads =3D (UINT8)LockDownConf=
ig->UnlockGpioPads;
+
+ //
+ // Update Dmi policies
+ //
+ FspsUpd->FspsConfig.PchPwrOptEnable =3D (UINT8)DmiConfig->PwrOptEnable;
+ FspsUpd->FspsConfig.PchDmiAspmCtrl =3D (UINT8)DmiConfig->DmiAspmCtrl;
+
+ //
+ // Update Flash Protection policies
+ //
+ for (Index =3D 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) {
+ FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] =3D (UINT8)FlashPr=
otectionConfig->ProtectRange[Index].WriteProtectionEnable;
+ FspsUpd->FspsConfig.PchReadProtectionEnable[Index] =3D (UINT8)FlashPr=
otectionConfig->ProtectRange[Index].ReadProtectionEnable;
+ FspsUpd->FspsConfig.PchProtectedRangeLimit[Index] =3D (UINT16)FlashPr=
otectionConfig->ProtectRange[Index].ProtectedRangeLimit;
+ FspsUpd->FspsConfig.PchProtectedRangeBase[Index] =3D (UINT16)FlashPr=
otectionConfig->ProtectRange[Index].ProtectedRangeBase;
+ }
+
+ //
+ // Update IO Apic policies
+ //
+ FspsUpd->FspsConfig.PchIoApicEntry24_119 =3D (UINT8)IoApicConfig->=
IoApicEntry24_119;
+ FspsUpd->FspsConfig.Enable8254ClockGating =3D (UINT8)IoApicConfig->=
Enable8254ClockGating;
+ FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 =3D (UINT8)IoApicConfig->=
Enable8254ClockGatingOnS3;
+ FspsUpd->FspsConfig.PchIoApicId =3D (UINT8)IoApicConfig->=
IoApicId;
+
+ //
+ // Update P2sb policies
+ //
+ FspsUpd->FspsTestConfig.PchSbAccessUnlock =3D (UINT8)P2sbConfig->SbAcce=
ssUnlock;
+
+ //
+ // Update Pch General policies
+ //
+ FspsUpd->FspsConfig.PchCrid =3D (UINT8)PchGeneralConfig->C=
rid;
+ FspsUpd->FspsConfig.PchLegacyIoLowLatency =3D (UINT8)PchGeneralConfig->L=
egacyIoLowLatency;
+
+ //
+ // Update Pm policies
+ //
+ FspsUpd->FspsConfig.PchPmPmeB0S5Dis =3D (UINT8)PmConfig->WakeCon=
fig.PmeB0S5Dis;
+ FspsUpd->FspsConfig.PchPmWolEnableOverride =3D (UINT8)PmConfig->WakeCon=
fig.WolEnableOverride;
+ FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx =3D (UINT8)PmConfig->WakeCon=
fig.PcieWakeFromDeepSx;
+ FspsUpd->FspsConfig.PchPmWoWlanEnable =3D (UINT8)PmConfig->WakeCon=
fig.WoWlanEnable;
+ FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable =3D (UINT8)PmConfig->WakeCon=
fig.WoWlanDeepSxEnable;
+ FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx =3D (UINT8)PmConfig->WakeCon=
fig.LanWakeFromDeepSx;
+
+ FspsUpd->FspsConfig.PchPmDeepSxPol =3D (UINT8)PmConfig->PchDeep=
SxPol;
+ FspsUpd->FspsConfig.PchPmSlpS3MinAssert =3D (UINT8)PmConfig->PchSlpS=
3MinAssert;
+ FspsUpd->FspsConfig.PchPmSlpS4MinAssert =3D (UINT8)PmConfig->PchSlpS=
4MinAssert;
+ FspsUpd->FspsConfig.PchPmSlpSusMinAssert =3D (UINT8)PmConfig->PchSlpS=
usMinAssert;
+ FspsUpd->FspsConfig.PchPmSlpAMinAssert =3D (UINT8)PmConfig->PchSlpA=
MinAssert;
+ FspsUpd->FspsConfig.PchPmLpcClockRun =3D (UINT8)PmConfig->LpcCloc=
kRun;
+ FspsUpd->FspsConfig.PchPmSlpStrchSusUp =3D (UINT8)PmConfig->SlpStrc=
hSusUp;
+ FspsUpd->FspsConfig.PchPmSlpLanLowDc =3D (UINT8)PmConfig->SlpLanL=
owDc;
+ FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod =3D (UINT8)PmConfig->PwrBt=
nOverridePeriod;
+ FspsUpd->FspsTestConfig.PchPmDisableEnergyReport =3D (UINT8)PmConfig->D=
isableEnergyReport;
+ FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown =3D (UINT8)PmConfig=
->DisableDsxAcPresentPulldown;
+ FspsUpd->FspsConfig.PchPmDisableNativePowerButton =3D (UINT8)PmConfig=
->DisableNativePowerButton;
+ FspsUpd->FspsConfig.PmcPowerButtonDebounce =3D PmConfig->PowerButtonDeb=
ounce;
+ FspsUpd->FspsConfig.PchPmSlpS0Enable =3D (UINT8)PmConfig->SlpS0En=
able;
+ FspsUpd->FspsConfig.PchPmMeWakeSts =3D (UINT8)PmConfig->MeWakeS=
ts;
+ FspsUpd->FspsConfig.PchPmWolOvrWkSts =3D (UINT8)PmConfig->WolOvrW=
kSts;
+ FspsUpd->FspsConfig.EnableTcoTimer =3D (UINT8)PmConfig->EnableT=
coTimer;
+ FspsUpd->FspsConfig.PchPmVrAlert =3D (UINT8)PmConfig->VrAlert;
+ FspsUpd->FspsConfig.PchPmPwrCycDur =3D (UINT8)PmConfig->PchPwrC=
ycDur;
+ FspsUpd->FspsConfig.PchPmPciePllSsc =3D (UINT8)PmConfig->PciePll=
Ssc;
+ FspsUpd->FspsConfig.PchPmSlpS0VmRuntimeControl =3D (UINT8)PmConfig->SlpS=
0VmRuntimeControl;
+ FspsUpd->FspsConfig.PchPmSlpS0Vm070VSupport =3D (UINT8)PmConfig->SlpS0=
Vm070VSupport;
+ FspsUpd->FspsConfig.PchPmSlpS0Vm075VSupport =3D (UINT8)PmConfig->SlpS0=
Vm075VSupport;
+ FspsUpd->FspsConfig.SlpS0Override =3D (UINT8)PmConfig->SlpS0=
Override;
+ FspsUpd->FspsConfig.SlpS0DisQForDebug =3D (UINT8)PmConfig->SlpS0=
DisQForDebug;
+ FspsUpd->FspsConfig.PmcDbgMsgEn =3D (UINT8)PmConfig->PmcDb=
gMsgEn;
+ FspsUpd->FspsConfig.PsOnEnable =3D (UINT8)PmConfig->PsOnE=
nable;
+ FspsUpd->FspsConfig.PmcCpuC10GatePinEnable =3D (UINT8)PmConfig->CpuC1=
0GatePinEnable;
+ FspsUpd->FspsConfig.PmcModPhySusPgEnable =3D (UINT8)PmConfig->ModPh=
ySusPgEnable;
+ FspsUpd->FspsConfig.SlpS0WithGbeSupport =3D (UINT8)PmConfig->SlpS0=
WithGbeSupport;
+ //
+ // Update Pch Serial IRQ policies
+ //
+ FspsUpd->FspsConfig.PchSirqEnable =3D (UINT8)PchSerialIrqConfig->S=
irqEnable;
+ FspsUpd->FspsConfig.PchSirqMode =3D (UINT8)PchSerialIrqConfig->S=
irqMode;
+ FspsUpd->FspsConfig.PchStartFramePulse =3D (UINT8)PchSerialIrqConfig->S=
tartFramePulse;
+ //
+ // Update Pch Thermal policies
+ //
+ FspsUpd->FspsConfig.PchTsmicLock =3D (UINT8)PchThermalConfig->Tsm=
icLock;
+ FspsUpd->FspsConfig.PchHotEnable =3D (UINT8)PchThermalConfig->Pch=
HotEnable;
+
+ FspsUpd->FspsConfig.PchT0Level =3D (UINT16)PchThermalConfig->TT=
Levels.T0Level;
+ FspsUpd->FspsConfig.PchT1Level =3D (UINT16)PchThermalConfig->TT=
Levels.T1Level;
+ FspsUpd->FspsConfig.PchT2Level =3D (UINT16)PchThermalConfig->TT=
Levels.T2Level;
+ FspsUpd->FspsConfig.PchTTEnable =3D (UINT8)PchThermalConfig->TTL=
evels.TTEnable;
+ FspsUpd->FspsConfig.PchTTState13Enable =3D (UINT8)PchThermalConfig->TTL=
evels.TTState13Enable;
+ FspsUpd->FspsConfig.PchTTLock =3D (UINT8)PchThermalConfig->TTL=
evels.TTLock;
+ FspsUpd->FspsConfig.TTSuggestedSetting =3D (UINT8)PchThermalConfig->TTL=
evels.SuggestedSetting;
+ FspsUpd->FspsConfig.TTCrossThrottling =3D (UINT8)PchThermalConfig->TTL=
evels.PchCrossThrottling;
+
+ FspsUpd->FspsConfig.PchDmiTsawEn =3D (UINT8)PchThermalConfig->Dmi=
HaAWC.DmiTsawEn;
+ FspsUpd->FspsConfig.DmiSuggestedSetting =3D (UINT8)PchThermalConfig->Dmi=
HaAWC.SuggestedSetting;
+ FspsUpd->FspsConfig.DmiTS0TW =3D (UINT8)PchThermalConfig->Dmi=
HaAWC.TS0TW;
+ FspsUpd->FspsConfig.DmiTS1TW =3D (UINT8)PchThermalConfig->Dmi=
HaAWC.TS1TW;
+ FspsUpd->FspsConfig.DmiTS2TW =3D (UINT8)PchThermalConfig->Dmi=
HaAWC.TS2TW;
+ FspsUpd->FspsConfig.DmiTS3TW =3D (UINT8)PchThermalConfig->Dmi=
HaAWC.TS3TW;
+
+ FspsUpd->FspsConfig.PchMemoryThrottlingEnable =3D (UINT8)PchThermalCo=
nfig->MemoryThrottling.Enable;
+ FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0] =3D (UINT8)PchThermalCo=
nfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEnable;
+ FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1] =3D (UINT8)PchThermalCo=
nfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEnable;
+ FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] =3D (UINT8)PchThermalCo=
nfig->MemoryThrottling.TsGpioPinSetting[0].C0TransmitEnable;
+ FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] =3D (UINT8)PchThermalCo=
nfig->MemoryThrottling.TsGpioPinSetting[1].C0TransmitEnable;
+ FspsUpd->FspsConfig.PchMemoryPinSelection[0] =3D (UINT8)PchThermalCo=
nfig->MemoryThrottling.TsGpioPinSetting[0].PinSelection;
+ FspsUpd->FspsConfig.PchMemoryPinSelection[1] =3D (UINT8)PchThermalCo=
nfig->MemoryThrottling.TsGpioPinSetting[1].PinSelection;
+
+ FspsUpd->FspsConfig.PchTemperatureHotLevel =3D (UINT16)PchThermalConfig-=
>PchHotLevel;
+
+ //
+ // Update Pch CNVi policies
+ //
+ FspsUpd->FspsConfig.CnviMode =3D (UINT8)CnviConfig->Mode;
+
+ //
+ // Update Pch HSIO policies
+ //
+ FspsUpd->FspsConfig.ChipsetInitBinPtr =3D HsioConfig->ChipsetInitBinPtr;
+ FspsUpd->FspsConfig.ChipsetInitBinLen =3D HsioConfig->ChipsetInitBinLen;
+
+ //
+ // Update Pch Espi policies
+ //
+ FspsUpd->FspsConfig.PchEspiLgmrEnable =3D (UINT8)EspiConfig->LgmrEnable;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspPolicyInitLib.c b/Platform/Intel/CometlakeOpenBoardPkg/=
FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c
new file mode 100644
index 0000000000..50cfe7b27b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspPolicyInitLib.c
@@ -0,0 +1,223 @@
+/** @file
+ Instance of Fsp Policy Initialization Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <Library/SpiLib.h>
+
+VOID
+EFIAPI
+FspPolicyInitPreMem(
+ IN FSPM_UPD *FspmUpdDataPtr
+);
+
+VOID *
+EFIAPI
+SiliconPolicyInitPreMem(
+ IN OUT VOID *FspmUpd
+)
+{
+ FspPolicyInitPreMem((FSPM_UPD *)FspmUpd);
+ return FspmUpd;
+}
+
+RETURN_STATUS
+EFIAPI
+SiliconPolicyDonePreMem(
+ IN VOID *FspmUpd
+)
+{
+ EFI_STATUS Status;
+
+ Status =3D SpiServiceInit();
+ ASSERT_EFI_ERROR(Status);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Performs FSP PEI Policy Pre-memory initialization.
+
+ @param[in] FspmUpdDataPtr Pointer to FSPM UPD data.
+**/
+VOID
+EFIAPI
+FspPolicyInitPreMem (
+ IN FSPM_UPD *FspmUpdDataPtr
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // SI Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspSiPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy in Pre-Memory Initiali=
zation fail, Status =3D %r\n", Status));
+ }
+
+ //
+ // PCH Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspPchPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initial=
ization fail, Status =3D %r\n", Status));
+ }
+
+ //
+ // Cpu Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initial=
ization fail, Status =3D %r\n", Status));
+ }
+
+ //
+ // Security Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspSecurityPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy in Pre-Memory In=
itialization fail, Status =3D %r\n", Status));
+ }
+
+ //
+ // ME Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspMePolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy in Pre-Memory Initiali=
zation fail, Status =3D %r\n", Status));
+ }
+
+ //
+ // SystemAgent Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspSaPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory=
Initialization fail, Status =3D %r\n", Status));
+ }
+
+ //
+ // Other Upd Initialization
+ //
+ Status =3D PeiFspMiscUpdInitPreMem (FspmUpdDataPtr);
+
+}
+
+/**
+ Performs FSP PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer UPD data region
+
+**/
+VOID
+EFIAPI
+FspPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // SI Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspSiPolicyInit (FspsUpd);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy iInitialization fail, =
Status =3D %r\n", Status));
+ }
+
+ //
+ // PCH Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspPchPolicyInit (FspsUpd);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy iInitialization fail,=
Status =3D %r\n", Status));
+ }
+
+ //
+ // ME Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspMePolicyInit (FspsUpd);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy Initialization fail, S=
tatus =3D %r\n", Status));
+ }
+
+ //
+ // SystemAgent Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspSaPolicyInit (FspsUpd);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy Initializatio=
n fail, Status =3D %r\n", Status));
+ }
+
+ //
+ // Cpu Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspCpuPolicyInit (FspsUpd);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy Initialization fail, =
Status =3D %r\n", Status));
+ }
+
+ //
+ // Security Pei Fsp Policy Initialization
+ //
+ Status =3D PeiFspSecurityPolicyInit(FspsUpd);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy Initialization fa=
il, Status =3D %r\n", Status));
+ }
+
+}
+
+/**
+Performs silicon post-mem policy initialization.
+
+The meaning of Policy is defined by silicon code.
+It could be the raw data, a handle, a PPI, etc.
+
+The returned data must be used as input data for SiliconPolicyDonePostMem(=
),
+and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem().
+
+1) In FSP path, the input Policy should be FspsUpd.
+Value of FspsUpd has been initialized by FSP binary default value.
+Only a subset of FspsUpd needs to be updated for different silicon sku.
+The return data is same FspsUpd.
+
+2) In non-FSP path, the input policy could be NULL.
+The return data is the initialized policy.
+
+@param[in, out] Policy Pointer to policy.
+
+@return the initialized policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyInitPostMem(
+ IN OUT VOID *FspsUpd
+)
+{
+ FspPolicyInit((FSPS_UPD *)FspsUpd);
+ return FspsUpd;
+}
+
+/*
+The silicon post-mem policy is finalized.
+Silicon code can do initialization based upon the policy data.
+
+The input Policy must be returned by SiliconPolicyInitPostMem().
+
+@param[in] Policy Pointer to policy.
+
+@retval EFI_SUCCESS The policy is handled consumed by silicon code.
+*/
+EFI_STATUS
+EFIAPI
+SiliconPolicyDonePostMem(
+ IN OUT VOID *FspsUpd
+)
+{
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspPolicyInitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/=
FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h
new file mode 100644
index 0000000000..6b25f0763b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspPolicyInitLib.h
@@ -0,0 +1,233 @@
+/** @file
+ Internal header file for Fsp Policy Initialization Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_FSP_POLICY_INIT_LIB_H_
+#define _PEI_FSP_POLICY_INIT_LIB_H_
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#include <Setup.h>
+
+/**
+ Performs FSP SI PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP SI PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+ Performs FSP PCH PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+ Performs FSP CPU PEI Policy initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+Performs FSP Security PEI Policy initialization.
+
+@param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+@retval EFI_SUCCESS FSP UPD Data is updated.
+@retval EFI_NOT_FOUND Fail to locate required PPI.
+@retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSecurityPolicyInitPreMem(
+IN OUT FSPM_UPD *FspmUpd
+);
+
+/**
+ Performs FSP ME PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP ME PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP SA PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+ Performs FSP CPU PEI Policy post memory initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+Performs FSP Security PEI Policy post memory initialization.
+
+@param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+@retval EFI_SUCCESS FSP UPD Data is updated.
+@retval EFI_NOT_FOUND Fail to locate required PPI.
+@retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSecurityPolicyInit(
+IN OUT FSPS_UPD *FspsUpd
+);
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section fr=
om FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ );
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+#endif // _PEI_FSP_POLICY_INIT_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/CometlakeOpenBoardPk=
g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
new file mode 100644
index 0000000000..b92653b975
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspPolicyInitLib.inf
@@ -0,0 +1,162 @@
+## @file
+# Library functions for Fsp Policy Initialization Library.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+##########################################################################=
######
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+##########################################################################=
######
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D PeiFspPolicyInitLib
+ FILE_GUID =3D 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D SiliconPolicyInitLib
+
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32
+#
+
+##########################################################################=
######
+#
+# Sources Section - list of files that are required for the build to succe=
ed.
+#
+##########################################################################=
######
+
+[Sources]
+ PeiFspPolicyInitLib.c
+ PeiFspSiPolicyInitLib.c
+ PeiFspPchPolicyInitLib.c
+ PeiFspCpuPolicyInitLib.c
+ PeiFspMePolicyInitLib.c
+ PeiFspSaPolicyInitLib.c
+ PeiFspSecurityPolicyInitLib.c
+ PeiFspMiscUpdInitLib.c
+
+##########################################################################=
######
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+##########################################################################=
######
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ IoLib
+ PeiServicesLib
+ SmbusLib
+ ConfigBlockLib
+ PcdLib
+ MemoryAllocationLib
+ PchInfoLib
+ SpiLib
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdTsegSize
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CON=
SUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CON=
SUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CON=
SUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize ## CON=
SUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CON=
SUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CON=
SUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CON=
SUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CON=
SUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CON=
SUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CON=
SUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CON=
SUMES
+
+[Ppis]
+ gSiPolicyPpiGuid ## CONSUMES
+ gSiPreMemPolicyPpiGuid ## CONSUMES
+ gEfiSecPlatformInformation2PpiGuid ## CONSUMES
+ gEfiSecPlatformInformationPpiGuid ## CONSUMES
+
+[Guids]
+ gPchTraceHubPreMemConfigGuid ## CONSUMES
+ gSmbusPreMemConfigGuid ## CONSUMES
+ gDciPreMemConfigGuid ## CONSUMES
+ gPcieRpPreMemConfigGuid ## CONSUMES
+ gHdAudioPreMemConfigGuid ## CONSUMES
+ gIshPreMemConfigGuid ## CONSUMES
+ gHsioPciePreMemConfigGuid ## CONSUMES
+ gHsioSataPreMemConfigGuid ## CONSUMES
+ gLpcPreMemConfigGuid ## CONSUMES
+ gPchGeneralPreMemConfigGuid ## CONSUMES
+ gWatchDogPreMemConfigGuid ## CONSUMES
+ gLanConfigGuid ## CONSUMES
+ gPcieRpConfigGuid ## CONSUMES
+ gSataConfigGuid ## CONSUMES
+ gHdAudioConfigGuid ## CONSUMES
+ gScsConfigGuid ## CONSUMES
+ gIshConfigGuid ## CONSUMES
+ gSataConfigGuid ## CONSUMES
+ gUsbConfigGuid ## CONSUMES
+ gSerialIoConfigGuid ## CONSUMES
+ gInterruptConfigGuid ## CONSUMES
+ gLockDownConfigGuid ## CONSUMES
+ gSaMiscPeiPreMemConfigGuid ## PRODUCES
+ gSaMiscPeiConfigGuid ## PRODUCES
+ gMemoryConfigGuid ## CONSUMES
+ gMemoryConfigNoCrcGuid ## CONSUMES
+ gSwitchableGraphicsConfigGuid ## CONSUMES
+ gGraphicsPeiPreMemConfigGuid ## CONSUMES
+ gSaPciePeiPreMemConfigGuid ## CONSUMES
+ gSaMiscPeiConfigGuid ## CONSUMES
+ gSaPciePeiConfigGuid ## CONSUMES
+ gGraphicsPeiConfigGuid ## CONSUMES
+ gCpuTraceHubConfigGuid ## CONSUMES
+ gIpuPreMemConfigGuid ## CONSUMES
+ gCnviConfigGuid ## CONSUMES
+ gHsioConfigGuid ## CONSUMES
+ gEspiConfigGuid ## CONSUMES
+ gGnaConfigGuid ## CONSUMES
+ gVtdConfigGuid ## CONSUMES
+ gSaOverclockingPreMemConfigGuid ## CONSUMES
+ gMePeiPreMemConfigGuid ## CONSUMES
+ gMePeiConfigGuid ## CONSUMES
+ gDmiConfigGuid ## CONSUMES
+ gFlashProtectionConfigGuid ## CONSUMES
+ gIoApicConfigGuid ## CONSUMES
+ gPmConfigGuid ## CONSUMES
+ gP2sbConfigGuid ## CONSUMES
+ gPchGeneralConfigGuid ## CONSUMES
+ gSerialIrqConfigGuid ## CONSUMES
+ gThermalConfigGuid ## CONSUMES
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gCpuConfigGuid ## CONSUMES
+ gCpuOverclockingPreMemConfigGuid ## CONSUMES
+ gCpuConfigLibPreMemConfigGuid ## CONSUMES
+ gCpuPowerMgmtBasicConfigGuid ## CONSUMES
+ gCpuPowerMgmtCustomConfigGuid ## CONSUMES
+ gCpuTestConfigGuid ## CONSUMES
+ gCpuPidTestConfigGuid ## CONSUMES
+ gCpuPowerMgmtTestConfigGuid ## CONSUMES
+ gFspNonVolatileStorageHobGuid ## CONSUMES
+ gSmramCpuDataHeaderGuid ## CONSUMES
+ gFspReservedMemoryResourceHobTsegGuid ## CONSUMES
+ gSiConfigGuid ## CONSUMES
+ gDebugConfigHobGuid ## CONSUMES
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspSaPolicyInitLib.c b/Platform/Intel/CometlakeOpenBoardPk=
g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c
new file mode 100644
index 0000000000..45d76ad5e4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspSaPolicyInitLib.c
@@ -0,0 +1,848 @@
+/** @file
+ Implementation of Fsp SA Policy Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmbusLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PcdLib.h>
+
+#include <IndustryStandard/Pci.h>
+#include <PchAccess.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/ConfigBlockLib.h>
+
+#define MAX_SPD_PAGE_COUNT (2)
+#define MAX_SPD_PAGE_SIZE (256)
+#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COU=
NT)
+#define SPD_PAGE_ADDRESS_0 (0x6C)
+#define SPD_PAGE_ADDRESS_1 (0x6E)
+#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02)
+#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B)
+#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C)
+#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1)
+#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F)
+#define XMP_ID_STRING (0x4A0C)
+#define SPD3_MANUF_START (117)
+#define SPD3_MANUF_END (127)
+#define SPD4_MANUF_START (320)
+#define SPD4_MANUF_END (328)
+#define SPDLP_MANUF_START (320)
+#define SPDLP_MANUF_END (328)
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] =3D {
+ { 0, 1, (1 << SpdCold),},
+ { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
+ { 3, 41, (1 << SpdCold),},
+ { 60, 63, (1 << SpdCold),},
+ { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+ { 128, 145, (1 << SpdCold),},
+ { 39, 59, (1 << SpdCold),},
+ { 64, 125, (1 << SpdCold),},
+ { 176, 179, (1 << SpdCold),},
+ { 180, 184, (1 << SpdCold),},
+ { 185, 215, (1 << SpdCold),},
+ { 220, 250, (1 << SpdCold),},
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] =3D {
+ { 0, 1, (1 << SpdCold),},
+ { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
+ { 3, 40, (1 << SpdCold),},
+ { 117, 131, (1 << SpdCold),},
+ { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+ { 329, 348, (1 << SpdCold),},
+ { 32, 119, (1 << SpdCold),},
+ { 126, 255, (1 << SpdCold),},
+ { 349, 383, (1 << SpdCold),},
+ { 384, 387, (1 << SpdCold),},
+ { 388, 389, (1 << SpdCold),},
+ { 393, 431, (1 << SpdCold),},
+ { 440, 478, (1 << SpdCold),},
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] =3D {
+ { 0, 1, (1 << SpdCold),},
+ { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
+ { 3, 32, (1 << SpdCold),},
+ { 120, 130, (1 << SpdCold),},
+ { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+ { 329, 348, (1 << SpdCold),},
+ { 31, 121, (1 << SpdCold),},
+ { 126, 255, (1 << SpdCold),},
+ { 349, 383, (1 << SpdCold),},
+ { 384, 387, (1 << SpdCold),},
+ { 388, 389, (1 << SpdCold),},
+ { 393, 431, (1 << SpdCold),},
+ { 440, 478, (1 << SpdCold),},
+};
+
+
+/**
+ Update Spd Data
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+ @param[in] MemConfigNoCrc Pointer to Mem Config No Crc.
+ @param[in] MiscPeiPreMemConfig Pointer to Misc Config.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval Other The function fail
+**/
+VOID
+EFIAPI
+InternalUpdateSpdInfo (
+ IN OUT FSPM_UPD *FspmUpd,
+ IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc,
+ IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig
+ )
+{
+
+ DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n"));
+ if ((FspmUpd =3D=3D NULL) || (MemConfigNoCrc =3D=3D NULL) || (MiscPeiPre=
MemConfig =3D=3D NULL)) {
+ DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n"));
+ DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n"));
+ return;
+ }
+
+ //
+ // Update MemorySpdPtrXX if SpdAddressTable is zero
+ //
+ if (MiscPeiPreMemConfig->SpdAddressTable[0] =3D=3D 0x0) {
+ FspmUpd->FspmConfig.MemorySpdPtr00 =3D (UINT32)MemConfigNoCrc->SpdData=
->SpdData;
+ } else {
+ FspmUpd->FspmConfig.SpdAddressTable[0] =3D MiscPeiPreMemConfig->SpdAdd=
ressTable[0];
+ }
+
+ if (MiscPeiPreMemConfig->SpdAddressTable[1] =3D=3D 0x0) {
+ FspmUpd->FspmConfig.MemorySpdPtr01 =3D (UINT32)MemConfigNoCrc->SpdData=
->SpdData + (1 * SA_MC_MAX_SPD_SIZE);
+ } else {
+ FspmUpd->FspmConfig.SpdAddressTable[1] =3D MiscPeiPreMemConfig->SpdAdd=
ressTable[1];
+ }
+
+ if (MiscPeiPreMemConfig->SpdAddressTable[2] =3D=3D 0x0) {
+ FspmUpd->FspmConfig.MemorySpdPtr10 =3D (UINT32)MemConfigNoCrc->SpdData=
->SpdData + (2 * SA_MC_MAX_SPD_SIZE);
+ } else {
+ FspmUpd->FspmConfig.SpdAddressTable[2] =3D MiscPeiPreMemConfig->SpdAdd=
ressTable[2];
+ }
+
+ if (MiscPeiPreMemConfig->SpdAddressTable[3] =3D=3D 0x0) {
+ FspmUpd->FspmConfig.MemorySpdPtr11 =3D (UINT32)MemConfigNoCrc->SpdData=
->SpdData + (3 * SA_MC_MAX_SPD_SIZE);
+ } else {
+ FspmUpd->FspmConfig.SpdAddressTable[3] =3D MiscPeiPreMemConfig->SpdAdd=
ressTable[3];
+ }
+
+ DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n"));
+}
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section fr=
om FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
+ EFI_FV_FILE_INFO FvFileInfo;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ EFI_PEI_FILE_HANDLE VbtFileHandle;
+ EFI_GUID *VbtGuid;
+ EFI_COMMON_SECTION_HEADER *Section;
+ CONST EFI_PEI_SERVICES **PeiServices;
+
+ PeiServices =3D GetPeiServicesTablePointer ();
+
+ PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+
+ Status =3D PeiServicesLocatePpi (
+ &gEfiFirmwareFileSystem2Guid,
+ 0,
+ NULL,
+ (VOID **) &FvPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ CurrentFv =3D PrivateData->CurrentPeimFvCount;
+ CoreFvHandle =3D &(PrivateData->Fv[CurrentFv]);
+
+ Status =3D FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHan=
dle, &VbtFileHandle);
+ if (!EFI_ERROR(Status) && VbtFileHandle !=3D NULL) {
+
+ DEBUG ((DEBUG_INFO, "Find SectionByType \n"));
+
+ Status =3D FvPpi->FindSectionByType (FvPpi, EFI_SECTION_RAW, VbtFileHa=
ndle, (VOID **) &VbtGuid);
+ if (!EFI_ERROR (Status)) {
+
+ DEBUG ((DEBUG_INFO, "GetFileInfo \n"));
+
+ Status =3D FvPpi->GetFileInfo (FvPpi, VbtFileHandle, &FvFileInfo);
+ Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+ if (IS_SECTION2 (Section)) {
+ ASSERT (SECTION2_SIZE (Section) > 0x00FFFFFF);
+ *Size =3D SECTION2_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEA=
DER2);
+ *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER=
2));
+ } else {
+ *Size =3D SECTION_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEAD=
ER);
+ *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER=
));
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ MEMORY_CONFIGURATION *MemConfig;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig;
+ SWITCHABLE_GRAPHICS_CONFIG *SgGpioData;
+ GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig;
+ OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig;
+ VTD_CONFIG *Vtd;
+ IPU_PREMEM_CONFIG *IpuPreMemPolicy;
+ UINT8 Index;
+ VOID *Buffer;
+
+ SiPreMemPolicyPpi =3D NULL;
+ MiscPeiPreMemConfig =3D NULL;
+ MemConfig =3D NULL;
+ MemConfigNoCrc =3D NULL;
+ PciePeiPreMemConfig =3D NULL;
+ SgGpioData =3D NULL;
+ GtPreMemConfig =3D NULL;
+ OcPreMemConfig =3D NULL;
+ Vtd =3D NULL;
+ IpuPreMemPolicy =3D NULL;
+
+
+
+ //
+ // Locate SiPreMemPolicyPpi
+ //
+ Status =3D PeiServicesLocatePpi(
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ if ((Status =3D=3D EFI_SUCCESS) && (SiPreMemPolicyPpi !=3D NULL)) {
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreM=
emConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigN=
oCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigG=
uid, (VOID *) &MemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPr=
eMemConfigGuid, (VOID *) &GtPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreM=
emConfigGuid, (VOID *) &PciePeiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSwitchableGra=
phicsConfigGuid, (VOID *) &SgGpioData);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid=
, (VOID *) &Vtd);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConf=
igGuid, (VOID *) &IpuPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaOverclockin=
gPreMemConfigGuid, (VOID *) &OcPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ }
+
+ DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings=
...\n"));
+ Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 1=
2, 12);
+ }
+ Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffe=
r + 8, 8);
+ }
+
+ DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp =
Target Settings...\n"));
+ Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
+ }
+ Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
+ }
+
+ //
+ // Update UPD:MemorySpdPtrXX and SpdAddressTable
+ //
+ InternalUpdateSpdInfo (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig);
+
+ //
+ // Update UPD:MemorySpdDataLen
+ //
+ FspmUpd->FspmConfig.MemorySpdDataLen =3D SA_MC_MAX_SPD_SIZE;
+
+ if (MemConfigNoCrc !=3D NULL) {
+ //
+ // Update UPD:PlatformMemorySize
+ //
+ //
+ // @todo: This value is used since #183932. Revisit.
+ //
+ FspmUpd->FspmConfig.PlatformMemorySize =3D MemConfigNoCrc->PlatformMe=
morySize;
+ FspmUpd->FspmConfig.CleanMemory =3D (UINT8) MemConfigNoCrc->Cl=
eanMemory;
+ FspmUpd->FspmConfig.MemTestOnWarmBoot =3D (UINT8) MemConfigNoCrc->Me=
mTestOnWarmBoot;
+ }
+
+ if (MemConfig !=3D NULL) {
+ //
+ // Update UPD:DqPinsInterleaved
+ //
+ FspmUpd->FspmConfig.DqPinsInterleaved =3D (UINT8) MemConfig->DqPin=
sInterleaved;
+
+ FspmUpd->FspmConfig.ProbelessTrace =3D MemConfig->ProbelessTrac=
e;
+ FspmUpd->FspmConfig.GdxcIotSize =3D MemConfig->GdxcIotSize;
+ FspmUpd->FspmConfig.GdxcMotSize =3D MemConfig->GdxcMotSize;
+ FspmUpd->FspmConfig.DualDimmPerChannelBoardType =3D(UINT8) MemConfig->=
DualDimmPerChannelBoardType;
+ FspmUpd->FspmConfig.Ddr4MixedUDimm2DpcLimit =3D(UINT8) MemConfig->=
Ddr4MixedUDimm2DpcLimit;
+ //
+ // Update UPD:CaVrefConfig
+ //
+ FspmUpd->FspmConfig.CaVrefConfig =3D MemConfig->CaVrefConfig;
+ FspmUpd->FspmConfig.SaGv =3D MemConfig->SaGv;
+ FspmUpd->FspmConfig.FreqSaGvLow =3D MemConfig->FreqSaGvLow;
+ FspmUpd->FspmConfig.RMT =3D (UINT8) MemConfig->RMT;
+ FspmUpd->FspmConfig.DdrFreqLimit =3D MemConfig->DdrFreqLimit;
+
+ FspmUpd->FspmConfig.SpdProfileSelected =3D MemConfig->SpdProfileSel=
ected;
+ FspmUpd->FspmConfig.VddVoltage =3D MemConfig->VddVoltage;
+ FspmUpd->FspmConfig.RefClk =3D MemConfig->RefClk;
+ FspmUpd->FspmConfig.Ratio =3D MemConfig->Ratio;
+ FspmUpd->FspmConfig.OddRatioMode =3D (UINT8) MemConfig->OddRa=
tioMode;
+ FspmUpd->FspmConfig.tCL =3D (UINT8) MemConfig->tCL;
+ FspmUpd->FspmConfig.tCWL =3D (UINT8) MemConfig->tCWL;
+ FspmUpd->FspmConfig.tFAW =3D MemConfig->tFAW;
+ FspmUpd->FspmConfig.tRAS =3D MemConfig->tRAS;
+ FspmUpd->FspmConfig.tRCDtRP =3D (UINT8) MemConfig->tRCDt=
RP;
+ FspmUpd->FspmConfig.tREFI =3D MemConfig->tREFI;
+ FspmUpd->FspmConfig.tRFC =3D MemConfig->tRFC;
+ FspmUpd->FspmConfig.tRRD =3D (UINT8) MemConfig->tRRD;
+ FspmUpd->FspmConfig.tRTP =3D (UINT8) MemConfig->tRTP;
+ FspmUpd->FspmConfig.tWR =3D (UINT8) MemConfig->tWR;
+ FspmUpd->FspmConfig.tWTR =3D (UINT8) MemConfig->tWTR;
+ FspmUpd->FspmConfig.NModeSupport =3D MemConfig->NModeSupport;
+ FspmUpd->FspmConfig.DllBwEn0 =3D MemConfig->DllBwEn0;
+ FspmUpd->FspmConfig.DllBwEn1 =3D MemConfig->DllBwEn1;
+ FspmUpd->FspmConfig.DllBwEn2 =3D MemConfig->DllBwEn2;
+ FspmUpd->FspmConfig.DllBwEn3 =3D MemConfig->DllBwEn3;
+ FspmUpd->FspmConfig.MrcSafeConfig =3D (UINT8) MemConfig->MrcSa=
feConfig; // Typecasting as MrcSafeConfig is of UINT32 in MEMORY_CONFIGURAT=
ION
+ FspmUpd->FspmConfig.LpDdrDqDqsReTraining =3D (UINT8) MemConfig->Lp4Dq=
sOscEn;
+ FspmUpd->FspmConfig.RmtPerTask =3D (UINT8) MemConfig->RmtPe=
rTask;
+ FspmUpd->FspmConfig.TrainTrace =3D (UINT8) MemConfig->Train=
Trace;
+ FspmUpd->FspmConfig.ScramblerSupport =3D (UINT8) MemConfig->Scram=
blerSupport;
+ FspmUpd->FspmConfig.SafeMode =3D (UINT8) MemConfig->SafeM=
ode;
+
+ //
+ // Update UPD:SmramMask and DisableDimmChannel
+ //
+ FspmUpd->FspmConfig.SmramMask =3D MemConfig->SmramMask;
+ FspmUpd->FspmConfig.DisableDimmChannel0 =3D MemConfig->DisableDimm=
Channel[0];
+ FspmUpd->FspmConfig.DisableDimmChannel1 =3D MemConfig->DisableDimm=
Channel[1];
+ FspmUpd->FspmConfig.HobBufferSize =3D MemConfig->HobBufferSi=
ze;
+
+ FspmUpd->FspmConfig.ECT =3D (UINT8) MemConfig->ECT;
+ FspmUpd->FspmConfig.SOT =3D (UINT8) MemConfig->SOT;
+ FspmUpd->FspmConfig.ERDMPRTC2D =3D (UINT8) MemConfig->ERD=
MPRTC2D;
+ FspmUpd->FspmConfig.RDMPRT =3D (UINT8) MemConfig->RDM=
PRT;
+ FspmUpd->FspmConfig.RCVET =3D (UINT8) MemConfig->RCV=
ET;
+ FspmUpd->FspmConfig.JWRL =3D (UINT8) MemConfig->JWR=
L;
+ FspmUpd->FspmConfig.EWRTC2D =3D (UINT8) MemConfig->EWR=
TC2D;
+ FspmUpd->FspmConfig.ERDTC2D =3D (UINT8) MemConfig->ERD=
TC2D;
+ FspmUpd->FspmConfig.WRTC1D =3D (UINT8) MemConfig->WRT=
C1D;
+ FspmUpd->FspmConfig.WRVC1D =3D (UINT8) MemConfig->WRV=
C1D;
+ FspmUpd->FspmConfig.RDTC1D =3D (UINT8) MemConfig->RDT=
C1D;
+ FspmUpd->FspmConfig.DIMMODTT =3D (UINT8) MemConfig->DIM=
MODTT;
+ FspmUpd->FspmConfig.DIMMRONT =3D (UINT8) MemConfig->DIM=
MRONT;
+ FspmUpd->FspmConfig.WRSRT =3D (UINT8) MemConfig->WRS=
RT;
+ FspmUpd->FspmConfig.RDODTT =3D (UINT8) MemConfig->RDO=
DTT;
+ FspmUpd->FspmConfig.RDEQT =3D (UINT8) MemConfig->RDE=
QT;
+ FspmUpd->FspmConfig.RDAPT =3D (UINT8) MemConfig->RDA=
PT;
+ FspmUpd->FspmConfig.WRTC2D =3D (UINT8) MemConfig->WRT=
C2D;
+ FspmUpd->FspmConfig.RDTC2D =3D (UINT8) MemConfig->RDT=
C2D;
+ FspmUpd->FspmConfig.WRVC2D =3D (UINT8) MemConfig->WRV=
C2D;
+ FspmUpd->FspmConfig.RDVC2D =3D (UINT8) MemConfig->RDV=
C2D;
+ FspmUpd->FspmConfig.CMDVC =3D (UINT8) MemConfig->CMD=
VC;
+ FspmUpd->FspmConfig.LCT =3D (UINT8) MemConfig->LCT;
+ FspmUpd->FspmConfig.RTL =3D (UINT8) MemConfig->RTL;
+ FspmUpd->FspmConfig.TAT =3D (UINT8) MemConfig->TAT;
+ FspmUpd->FspmConfig.RCVENC1D =3D (UINT8) MemConfig->RCV=
ENC1D;
+ FspmUpd->FspmConfig.RMT =3D (UINT8) MemConfig->RMT;
+ FspmUpd->FspmConfig.MEMTST =3D (UINT8) MemConfig->MEM=
TST;
+ FspmUpd->FspmConfig.ALIASCHK =3D (UINT8) MemConfig->ALI=
ASCHK;
+ FspmUpd->FspmConfig.RMC =3D (UINT8) MemConfig->RMC;
+ FspmUpd->FspmConfig.WRDSUDT =3D (UINT8) MemConfig->WRD=
SUDT;
+ FspmUpd->FspmConfig.EnBER =3D (UINT8) MemConfig->EnB=
ER;
+ FspmUpd->FspmConfig.EccSupport =3D (UINT8) MemConfig->Ecc=
Support;
+ FspmUpd->FspmConfig.RemapEnable =3D (UINT8) MemConfig->Rem=
apEnable;
+ FspmUpd->FspmConfig.ScramblerSupport =3D (UINT8) MemConfig->Scr=
amblerSupport;
+ FspmUpd->FspmConfig.MrcFastBoot =3D (UINT8) MemConfig->Mrc=
FastBoot;
+ FspmUpd->FspmConfig.RankInterleave =3D (UINT8) MemConfig->Ran=
kInterleave;
+ FspmUpd->FspmConfig.EnhancedInterleave =3D (UINT8) MemConfig->Enh=
ancedInterleave;
+ FspmUpd->FspmConfig.MemoryTrace =3D (UINT8) MemConfig->Mem=
oryTrace;
+ FspmUpd->FspmConfig.ChHashEnable =3D (UINT8) MemConfig->ChH=
ashEnable;
+ FspmUpd->FspmConfig.EnableExtts =3D (UINT8) MemConfig->Ena=
bleExtts;
+ FspmUpd->FspmConfig.EnableCltm =3D (UINT8) MemConfig->Ena=
bleCltm;
+ FspmUpd->FspmConfig.EnableOltm =3D (UINT8) MemConfig->Ena=
bleOltm;
+ FspmUpd->FspmConfig.EnablePwrDn =3D (UINT8) MemConfig->Ena=
blePwrDn;
+ FspmUpd->FspmConfig.EnablePwrDnLpddr =3D (UINT8) MemConfig->Ena=
blePwrDnLpddr;
+ FspmUpd->FspmConfig.UserPowerWeightsEn =3D (UINT8) MemConfig->Use=
rPowerWeightsEn;
+ FspmUpd->FspmConfig.RaplLim2Lock =3D (UINT8) MemConfig->Rap=
lLim2Lock;
+ FspmUpd->FspmConfig.RaplLim2Ena =3D (UINT8) MemConfig->Rap=
lLim2Ena;
+ FspmUpd->FspmConfig.RaplLim1Ena =3D (UINT8) MemConfig->Rap=
lLim1Ena;
+ FspmUpd->FspmConfig.SrefCfgEna =3D (UINT8) MemConfig->Sre=
fCfgEna;
+ FspmUpd->FspmConfig.ThrtCkeMinDefeatLpddr =3D (UINT8) MemConfig->Thr=
tCkeMinDefeatLpddr;
+ FspmUpd->FspmConfig.ThrtCkeMinDefeat =3D (UINT8) MemConfig->Thr=
tCkeMinDefeat;
+ FspmUpd->FspmConfig.RhPrevention =3D (UINT8) MemConfig->RhP=
revention;
+ FspmUpd->FspmConfig.ExitOnFailure =3D (UINT8) MemConfig->Exi=
tOnFailure;
+ FspmUpd->FspmConfig.DdrThermalSensor =3D (UINT8) MemConfig->Ddr=
ThermalSensor;
+ FspmUpd->FspmConfig.Ddr4DdpSharedClock =3D (UINT8) MemConfig->Ddr=
4DdpSharedClock;
+ FspmUpd->FspmConfig.Ddr4DdpSharedZq =3D (UINT8) MemConfig->Sha=
redZqPin;
+ FspmUpd->FspmConfig.BClkFrequency =3D MemConfig->BClkFrequen=
cy;
+ FspmUpd->FspmConfig.ChHashInterleaveBit =3D MemConfig->ChHashInter=
leaveBit;
+ FspmUpd->FspmConfig.ChHashMask =3D MemConfig->ChHashMask;
+ FspmUpd->FspmConfig.EnergyScaleFact =3D MemConfig->EnergyScale=
Fact;
+ FspmUpd->FspmConfig.Idd3n =3D MemConfig->Idd3n;
+ FspmUpd->FspmConfig.Idd3p =3D MemConfig->Idd3p;
+ FspmUpd->FspmConfig.CMDSR =3D (UINT8) MemConfig->CMD=
SR;
+ FspmUpd->FspmConfig.CMDDSEQ =3D (UINT8) MemConfig->CMD=
DSEQ;
+ FspmUpd->FspmConfig.CMDNORM =3D (UINT8) MemConfig->CMD=
NORM;
+ FspmUpd->FspmConfig.EWRDSEQ =3D (UINT8) MemConfig->EWR=
DSEQ;
+ FspmUpd->FspmConfig.FreqSaGvLow =3D MemConfig->FreqSaGvLow;
+ FspmUpd->FspmConfig.RhActProbability =3D MemConfig->RhActProbab=
ility;
+ FspmUpd->FspmConfig.RaplLim2WindX =3D MemConfig->RaplLim2Win=
dX;
+ FspmUpd->FspmConfig.RaplLim2WindY =3D MemConfig->RaplLim2Win=
dY;
+ FspmUpd->FspmConfig.RaplLim1WindX =3D MemConfig->RaplLim1Win=
dX;
+ FspmUpd->FspmConfig.RaplLim1WindY =3D MemConfig->RaplLim1Win=
dY;
+ FspmUpd->FspmConfig.RaplLim2Pwr =3D MemConfig->RaplLim2Pwr;
+ FspmUpd->FspmConfig.RaplLim1Pwr =3D MemConfig->RaplLim1Pwr;
+ FspmUpd->FspmConfig.WarmThresholdCh0Dimm0 =3D MemConfig->WarmThresho=
ldCh0Dimm0;
+ FspmUpd->FspmConfig.WarmThresholdCh0Dimm1 =3D MemConfig->WarmThresho=
ldCh0Dimm1;
+ FspmUpd->FspmConfig.WarmThresholdCh1Dimm0 =3D MemConfig->WarmThresho=
ldCh1Dimm0;
+ FspmUpd->FspmConfig.WarmThresholdCh1Dimm1 =3D MemConfig->WarmThresho=
ldCh1Dimm1;
+ FspmUpd->FspmConfig.HotThresholdCh0Dimm0 =3D MemConfig->HotThreshol=
dCh0Dimm0;
+ FspmUpd->FspmConfig.HotThresholdCh0Dimm1 =3D MemConfig->HotThreshol=
dCh0Dimm1;
+ FspmUpd->FspmConfig.HotThresholdCh1Dimm0 =3D MemConfig->HotThreshol=
dCh1Dimm0;
+ FspmUpd->FspmConfig.HotThresholdCh1Dimm1 =3D MemConfig->HotThreshol=
dCh1Dimm1;
+ FspmUpd->FspmConfig.WarmBudgetCh0Dimm0 =3D MemConfig->WarmBudgetC=
h0Dimm0;
+ FspmUpd->FspmConfig.WarmBudgetCh0Dimm1 =3D MemConfig->WarmBudgetC=
h0Dimm1;
+ FspmUpd->FspmConfig.WarmBudgetCh1Dimm0 =3D MemConfig->WarmBudgetC=
h1Dimm0;
+ FspmUpd->FspmConfig.WarmBudgetCh1Dimm1 =3D MemConfig->WarmBudgetC=
h1Dimm1;
+ FspmUpd->FspmConfig.HotBudgetCh0Dimm0 =3D MemConfig->HotBudgetCh=
0Dimm0;
+ FspmUpd->FspmConfig.HotBudgetCh0Dimm1 =3D MemConfig->HotBudgetCh=
0Dimm1;
+ FspmUpd->FspmConfig.HotBudgetCh1Dimm0 =3D MemConfig->HotBudgetCh=
1Dimm0;
+ FspmUpd->FspmConfig.HotBudgetCh1Dimm1 =3D MemConfig->HotBudgetCh=
1Dimm1;
+ FspmUpd->FspmConfig.IdleEnergyCh0Dimm0 =3D MemConfig->IdleEnergyC=
h0Dimm0;
+ FspmUpd->FspmConfig.IdleEnergyCh0Dimm1 =3D MemConfig->IdleEnergyC=
h0Dimm1;
+ FspmUpd->FspmConfig.IdleEnergyCh1Dimm0 =3D MemConfig->IdleEnergyC=
h1Dimm0;
+ FspmUpd->FspmConfig.IdleEnergyCh1Dimm1 =3D MemConfig->IdleEnergyC=
h1Dimm1;
+ FspmUpd->FspmConfig.PdEnergyCh0Dimm0 =3D MemConfig->PdEnergyCh0=
Dimm0;
+ FspmUpd->FspmConfig.PdEnergyCh0Dimm1 =3D MemConfig->PdEnergyCh0=
Dimm1;
+ FspmUpd->FspmConfig.PdEnergyCh1Dimm0 =3D MemConfig->PdEnergyCh1=
Dimm0;
+ FspmUpd->FspmConfig.PdEnergyCh1Dimm1 =3D MemConfig->PdEnergyCh1=
Dimm1;
+ FspmUpd->FspmConfig.ActEnergyCh0Dimm0 =3D MemConfig->ActEnergyCh=
0Dimm0;
+ FspmUpd->FspmConfig.ActEnergyCh0Dimm1 =3D MemConfig->ActEnergyCh=
0Dimm1;
+ FspmUpd->FspmConfig.ActEnergyCh1Dimm0 =3D MemConfig->ActEnergyCh=
1Dimm0;
+ FspmUpd->FspmConfig.ActEnergyCh1Dimm1 =3D MemConfig->ActEnergyCh=
1Dimm1;
+ FspmUpd->FspmConfig.RdEnergyCh0Dimm0 =3D MemConfig->RdEnergyCh0=
Dimm0;
+ FspmUpd->FspmConfig.RdEnergyCh0Dimm1 =3D MemConfig->RdEnergyCh0=
Dimm1;
+ FspmUpd->FspmConfig.RdEnergyCh1Dimm0 =3D MemConfig->RdEnergyCh1=
Dimm0;
+ FspmUpd->FspmConfig.RdEnergyCh1Dimm1 =3D MemConfig->RdEnergyCh1=
Dimm1;
+ FspmUpd->FspmConfig.WrEnergyCh0Dimm0 =3D MemConfig->WrEnergyCh0=
Dimm0;
+ FspmUpd->FspmConfig.WrEnergyCh0Dimm1 =3D MemConfig->WrEnergyCh0=
Dimm1;
+ FspmUpd->FspmConfig.WrEnergyCh1Dimm0 =3D MemConfig->WrEnergyCh1=
Dimm0;
+ FspmUpd->FspmConfig.WrEnergyCh1Dimm1 =3D MemConfig->WrEnergyCh1=
Dimm1;
+ FspmUpd->FspmConfig.ThrtCkeMinTmr =3D MemConfig->ThrtCkeMinT=
mr;
+ FspmUpd->FspmConfig.CkeRankMapping =3D MemConfig->CkeRankMapp=
ing;
+ FspmUpd->FspmConfig.CaVrefConfig =3D MemConfig->CaVrefConfi=
g;
+ FspmUpd->FspmConfig.RaplPwrFlCh1 =3D MemConfig->RaplPwrFlCh=
1;
+ FspmUpd->FspmConfig.RaplPwrFlCh0 =3D MemConfig->RaplPwrFlCh=
0;
+ FspmUpd->FspmConfig.EnCmdRate =3D MemConfig->EnCmdRate;
+ FspmUpd->FspmConfig.Refresh2X =3D MemConfig->Refresh2X;
+ FspmUpd->FspmConfig.EpgEnable =3D MemConfig->EpgEnable;
+ FspmUpd->FspmConfig.RhSolution =3D MemConfig->RhSolution;
+ FspmUpd->FspmConfig.UserThresholdEnable =3D MemConfig->UserThresho=
ldEnable;
+ FspmUpd->FspmConfig.UserBudgetEnable =3D MemConfig->UserBudgetE=
nable;
+ FspmUpd->FspmConfig.TsodTcritMax =3D MemConfig->TsodTcritMa=
x;
+ FspmUpd->FspmConfig.TsodEventMode =3D MemConfig->TsodEventMo=
de;
+ FspmUpd->FspmConfig.TsodEventPolarity =3D MemConfig->TsodEventPo=
larity;
+ FspmUpd->FspmConfig.TsodCriticalEventOnly =3D MemConfig->TsodCritica=
lEventOnly;
+ FspmUpd->FspmConfig.TsodEventOutputControl =3D MemConfig->TsodEventOu=
tputControl;
+ FspmUpd->FspmConfig.TsodAlarmwindowLockBit =3D MemConfig->TsodAlarmwi=
ndowLockBit;
+ FspmUpd->FspmConfig.TsodCriticaltripLockBit =3D MemConfig->TsodCritica=
ltripLockBit;
+ FspmUpd->FspmConfig.TsodShutdownMode =3D MemConfig->TsodShutdow=
nMode;
+ FspmUpd->FspmConfig.TsodThigMax =3D MemConfig->TsodThigMax;
+ FspmUpd->FspmConfig.TsodManualEnable =3D MemConfig->TsodManualE=
nable;
+ FspmUpd->FspmConfig.IsvtIoPort =3D MemConfig->IsvtIoPort;
+ FspmUpd->FspmConfig.ForceOltmOrRefresh2x =3D MemConfig->ForceOltmOr=
Refresh2x;
+ FspmUpd->FspmConfig.PwdwnIdleCounter =3D MemConfig->PwdwnIdleCo=
unter;
+ FspmUpd->FspmConfig.CmdRanksTerminated =3D MemConfig->CmdRanksTer=
minated;
+ FspmUpd->FspmConfig.GdxcEnable =3D MemConfig->GdxcEnable;
+ FspmUpd->FspmConfig.RMTLoopCount =3D MemConfig->RMTLoopCoun=
t;
+
+ // DDR4 Memory Timings
+ FspmUpd->FspmTestConfig.tRRD_L =3D (UINT8) MemConfig->tRRD_L;
+ FspmUpd->FspmTestConfig.tRRD_S =3D (UINT8) MemConfig->tRRD_S;
+ FspmUpd->FspmTestConfig.tWTR_L =3D (UINT8) MemConfig->tWTR_L;
+ FspmUpd->FspmTestConfig.tWTR_S =3D (UINT8) MemConfig->tWTR_S;
+
+ // TurnAround Timing
+ // Read-to-Read
+ FspmUpd->FspmTestConfig.tRd2RdSG =3D MemConfig->tRd2RdSG;
+ FspmUpd->FspmTestConfig.tRd2RdDG =3D MemConfig->tRd2RdDG;
+ FspmUpd->FspmTestConfig.tRd2RdDR =3D MemConfig->tRd2RdDR;
+ FspmUpd->FspmTestConfig.tRd2RdDD =3D MemConfig->tRd2RdDD;
+ // Write-to-Read
+ FspmUpd->FspmTestConfig.tWr2RdSG =3D MemConfig->tWr2RdSG;
+ FspmUpd->FspmTestConfig.tWr2RdDG =3D MemConfig->tWr2RdDG;
+ FspmUpd->FspmTestConfig.tWr2RdDR =3D MemConfig->tWr2RdDR;
+ FspmUpd->FspmTestConfig.tWr2RdDD =3D MemConfig->tWr2RdDD;
+ // Write-to-Write
+ FspmUpd->FspmTestConfig.tWr2WrSG =3D MemConfig->tWr2WrSG;
+ FspmUpd->FspmTestConfig.tWr2WrDG =3D MemConfig->tWr2WrDG;
+ FspmUpd->FspmTestConfig.tWr2WrDR =3D MemConfig->tWr2WrDR;
+ FspmUpd->FspmTestConfig.tWr2WrDD =3D MemConfig->tWr2WrDD;
+ // Read-to-Write
+ FspmUpd->FspmTestConfig.tRd2WrSG =3D MemConfig->tRd2WrSG;
+ FspmUpd->FspmTestConfig.tRd2WrDG =3D MemConfig->tRd2WrDG;
+ FspmUpd->FspmTestConfig.tRd2WrDR =3D MemConfig->tRd2WrDR;
+ FspmUpd->FspmTestConfig.tRd2WrDD =3D MemConfig->tRd2WrDD;
+ }
+
+ if (MiscPeiPreMemConfig !=3D NULL) {
+ FspmUpd->FspmConfig.IedSize =3D MiscPeiPreMemConfig->Ied=
Size;
+ FspmUpd->FspmConfig.UserBd =3D MiscPeiPreMemConfig->Use=
rBd;
+ FspmUpd->FspmConfig.SgDelayAfterPwrEn =3D MiscPeiPreMemConfig->SgD=
elayAfterPwrEn;
+ FspmUpd->FspmConfig.SgDelayAfterHoldReset =3D MiscPeiPreMemConfig->SgD=
elayAfterHoldReset;
+ FspmUpd->FspmConfig.MmioSize =3D MiscPeiPreMemConfig->Mmi=
oSize;
+ FspmUpd->FspmConfig.MmioSizeAdjustment =3D MiscPeiPreMemConfig->Mmi=
oSizeAdjustment;
+ FspmUpd->FspmConfig.TsegSize =3D MiscPeiPreMemConfig->Tse=
gSize;
+
+ FspmUpd->FspmTestConfig.SkipExtGfxScan =3D (UINT8) MiscPeiPr=
eMemConfig->SkipExtGfxScan;
+ FspmUpd->FspmTestConfig.BdatEnable =3D (UINT8) MiscPeiPr=
eMemConfig->BdatEnable;
+ FspmUpd->FspmTestConfig.BdatTestType =3D (UINT8) MiscPeiPr=
eMemConfig->BdatTestType;
+ FspmUpd->FspmTestConfig.ScanExtGfxForLegacyOpRom =3D (UINT8) MiscPeiPr=
eMemConfig->ScanExtGfxForLegacyOpRom;
+ FspmUpd->FspmTestConfig.LockPTMregs =3D (UINT8) MiscPeiPr=
eMemConfig->LockPTMregs;
+ }
+
+ if (Vtd !=3D NULL) {
+ FspmUpd->FspmConfig.X2ApicOptOut =3D (UINT8) Vtd->X2ApicOptOut;
+ FspmUpd->FspmConfig.VtdBaseAddress[0] =3D Vtd->BaseAddress[0];
+ FspmUpd->FspmConfig.VtdBaseAddress[1] =3D Vtd->BaseAddress[1];
+ FspmUpd->FspmConfig.VtdBaseAddress[2] =3D Vtd->BaseAddress[2];
+ FspmUpd->FspmTestConfig.VtdDisable =3D (UINT8) Vtd->VtdDisable;
+ }
+
+ if (PciePeiPreMemConfig !=3D NULL) {
+ FspmUpd->FspmConfig.DmiGen3ProgramStaticEq =3D (UINT8) PciePeiPreMemCo=
nfig->DmiGen3ProgramStaticEq;
+ FspmUpd->FspmConfig.Peg0Enable =3D (UINT8) PciePeiPreMemConfig->Peg0En=
able;
+ FspmUpd->FspmConfig.Peg1Enable =3D (UINT8) PciePeiPreMemConfig->Peg1En=
able;
+ FspmUpd->FspmConfig.Peg2Enable =3D (UINT8) PciePeiPreMemConfig->Peg2En=
able;
+ FspmUpd->FspmConfig.Peg3Enable =3D (UINT8) PciePeiPreMemConfig->Peg3En=
able;
+ FspmUpd->FspmConfig.Peg0MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->=
Peg0MaxLinkSpeed;
+ FspmUpd->FspmConfig.Peg1MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->=
Peg1MaxLinkSpeed;
+ FspmUpd->FspmConfig.Peg2MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->=
Peg2MaxLinkSpeed;
+ FspmUpd->FspmConfig.Peg3MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->=
Peg3MaxLinkSpeed;
+ FspmUpd->FspmConfig.Peg0MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->=
Peg0MaxLinkWidth;
+ FspmUpd->FspmConfig.Peg1MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->=
Peg1MaxLinkWidth;
+ FspmUpd->FspmConfig.Peg2MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->=
Peg2MaxLinkWidth;
+ FspmUpd->FspmConfig.Peg3MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->=
Peg3MaxLinkWidth;
+ FspmUpd->FspmConfig.Peg0PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem=
Config->Peg0PowerDownUnusedLanes;
+ FspmUpd->FspmConfig.Peg1PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem=
Config->Peg1PowerDownUnusedLanes;
+ FspmUpd->FspmConfig.Peg2PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem=
Config->Peg2PowerDownUnusedLanes;
+ FspmUpd->FspmConfig.Peg3PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem=
Config->Peg3PowerDownUnusedLanes;
+ FspmUpd->FspmConfig.InitPcieAspmAfterOprom =3D (UINT8) PciePeiPreMemCo=
nfig->InitPcieAspmAfterOprom;
+ FspmUpd->FspmConfig.PegDisableSpreadSpectrumClocking =3D (UINT8) PcieP=
eiPreMemConfig->PegDisableSpreadSpectrumClocking;
+ for (Index =3D 0; Index < SA_DMI_MAX_LANE; Index++) {
+ FspmUpd->FspmConfig.DmiGen3RootPortPreset[Index] =3D PciePeiPreMemCo=
nfig->DmiGen3RootPortPreset[Index];
+ FspmUpd->FspmConfig.DmiGen3EndPointPreset[Index] =3D PciePeiPreMemCo=
nfig->DmiGen3EndPointPreset[Index];
+ FspmUpd->FspmConfig.DmiGen3EndPointHint[Index] =3D PciePeiPreMemConf=
ig->DmiGen3EndPointHint[Index];
+ }
+ for (Index =3D 0; Index < SA_DMI_MAX_BUNDLE; Index++) {
+ FspmUpd->FspmConfig.DmiGen3RxCtlePeaking[Index] =3D PciePeiPreMemCon=
fig->DmiGen3RxCtlePeaking[Index];
+ }
+ for (Index =3D 0; Index < SA_PEG_MAX_BUNDLE ; Index++) {
+ FspmUpd->FspmConfig.PegGen3RxCtlePeaking[Index] =3D PciePeiPreMemCon=
fig->PegGen3RxCtlePeaking[Index];
+ }
+ FspmUpd->FspmConfig.PegDataPtr =3D (UINT32) PciePeiPreMemConfig->PegDa=
taPtr;
+ CopyMem((VOID *)FspmUpd->FspmConfig.PegGpioData, &PciePeiPreMemConfig-=
>PegGpioData, sizeof (PEG_GPIO_DATA));
+ FspmUpd->FspmConfig.DmiDeEmphasis =3D PciePeiPreMemConfig->DmiDeEmphas=
is;
+
+ for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) {
+ FspmUpd->FspmConfig.PegRootPortHPE[Index] =3D PciePeiPreMemConfig->P=
egRootPortHPE[Index];
+ }
+ FspmUpd->FspmTestConfig.DmiMaxLinkSpeed =3D (UINT8) PciePeiPreMemC=
onfig->DmiMaxLinkSpeed;
+ FspmUpd->FspmTestConfig.DmiGen3EqPh2Enable =3D (UINT8) PciePeiPreMemC=
onfig->DmiGen3EqPh2Enable;
+ FspmUpd->FspmTestConfig.DmiGen3EqPh3Method =3D (UINT8) PciePeiPreMemC=
onfig->DmiGen3EqPh3Method;
+ FspmUpd->FspmTestConfig.Peg0Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC=
onfig->Peg0Gen3EqPh2Enable;
+ FspmUpd->FspmTestConfig.Peg1Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC=
onfig->Peg1Gen3EqPh2Enable;
+ FspmUpd->FspmTestConfig.Peg2Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC=
onfig->Peg2Gen3EqPh2Enable;
+ FspmUpd->FspmTestConfig.Peg3Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC=
onfig->Peg3Gen3EqPh2Enable;
+ FspmUpd->FspmTestConfig.Peg0Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC=
onfig->Peg0Gen3EqPh3Method;
+ FspmUpd->FspmTestConfig.Peg1Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC=
onfig->Peg1Gen3EqPh3Method;
+ FspmUpd->FspmTestConfig.Peg2Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC=
onfig->Peg2Gen3EqPh3Method;
+ FspmUpd->FspmTestConfig.Peg3Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC=
onfig->Peg3Gen3EqPh3Method;
+ FspmUpd->FspmTestConfig.PegGen3ProgramStaticEq =3D (UINT8) PciePeiPreM=
emConfig->PegGen3ProgramStaticEq;
+ FspmUpd->FspmTestConfig.Gen3SwEqAlwaysAttempt =3D (UINT8) PciePeiPreMe=
mConfig->Gen3SwEqAlwaysAttempt;
+ FspmUpd->FspmTestConfig.Gen3SwEqNumberOfPresets =3D (UINT8) PciePeiPre=
MemConfig->Gen3SwEqNumberOfPresets;
+ FspmUpd->FspmTestConfig.Gen3SwEqEnableVocTest =3D (UINT8) PciePeiPreMe=
mConfig->Gen3SwEqEnableVocTest;
+ FspmUpd->FspmTestConfig.PegRxCemTestingMode =3D (UINT8) PciePeiPreMemC=
onfig->PegRxCemTestingMode;
+ FspmUpd->FspmTestConfig.PegRxCemLoopbackLane =3D (UINT8) PciePeiPreMem=
Config->PegRxCemLoopbackLane;
+ FspmUpd->FspmTestConfig.PegGenerateBdatMarginTable =3D (UINT8) PciePei=
PreMemConfig->PegGenerateBdatMarginTable;
+ FspmUpd->FspmTestConfig.PegRxCemNonProtocolAwareness =3D (UINT8) PcieP=
eiPreMemConfig->PegRxCemNonProtocolAwareness;
+ FspmUpd->FspmTestConfig.PegGen3RxCtleOverride =3D (UINT8) PciePeiPreMe=
mConfig->PegGen3RxCtleOverride;
+ for (Index =3D 0; Index < SA_PEG_MAX_LANE; Index++) {
+ FspmUpd->FspmTestConfig.PegGen3RootPortPreset[Index] =3D PciePeiPreM=
emConfig->PegGen3RootPortPreset[Index];
+ FspmUpd->FspmTestConfig.PegGen3EndPointPreset[Index] =3D PciePeiPreM=
emConfig->PegGen3EndPointPreset[Index];
+ FspmUpd->FspmTestConfig.PegGen3EndPointHint[Index] =3D PciePeiPreMem=
Config->PegGen3EndPointHint[Index];
+ }
+ FspmUpd->FspmTestConfig.Gen3SwEqJitterDwellTime =3D PciePeiPreMemConfi=
g->Gen3SwEqJitterDwellTime;
+ FspmUpd->FspmTestConfig.Gen3SwEqJitterErrorTarget =3D PciePeiPreMemCon=
fig->Gen3SwEqJitterErrorTarget;
+ FspmUpd->FspmTestConfig.Gen3SwEqVocDwellTime =3D PciePeiPreMemConfig->=
Gen3SwEqVocDwellTime;
+ FspmUpd->FspmTestConfig.Gen3SwEqVocErrorTarget =3D PciePeiPreMemConfig=
->Gen3SwEqVocErrorTarget;
+ }
+
+ if (GtPreMemConfig !=3D NULL) {
+ FspmUpd->FspmConfig.PrimaryDisplay =3D (UINT8) GtPreMemConfig->Primary=
Display;
+ FspmUpd->FspmConfig.InternalGfx =3D (UINT8) GtPreMemConfig->InternalGr=
aphics;
+ FspmUpd->FspmConfig.IgdDvmt50PreAlloc =3D (UINT8) GtPreMemConfig->IgdD=
vmt50PreAlloc;
+ FspmUpd->FspmConfig.ApertureSize =3D (UINT8) GtPreMemConfig->ApertureS=
ize;
+ FspmUpd->FspmConfig.GttMmAdr =3D GtPreMemConfig->GttMmAdr;
+ FspmUpd->FspmConfig.GmAdr =3D GtPreMemConfig->GmAdr;
+ FspmUpd->FspmConfig.GttSize =3D GtPreMemConfig->GttSize;
+ FspmUpd->FspmConfig.PsmiRegionSize =3D (UINT8) GtPreMemConfig->PsmiReg=
ionSize;
+ FspmUpd->FspmConfig.GtPsmiSupport =3D (UINT8)GtPreMemConfig->GtPsmiSup=
port;
+ FspmUpd->FspmTestConfig.PanelPowerEnable =3D (UINT8) GtPreMemConfig->P=
anelPowerEnable;
+ FspmUpd->FspmTestConfig.DeltaT12PowerCycleDelayPreMem =3D (UINT16) GtP=
reMemConfig->DeltaT12PowerCycleDelayPreMem;
+ }
+
+ if (SgGpioData !=3D NULL) {
+ CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie0Gpio, &SgGpioData->SaR=
td3Pcie0Gpio, sizeof (SA_PCIE_RTD3_GPIO));
+ CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie1Gpio, &SgGpioData->SaR=
td3Pcie1Gpio, sizeof (SA_PCIE_RTD3_GPIO));
+ CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie2Gpio, &SgGpioData->SaR=
td3Pcie2Gpio, sizeof (SA_PCIE_RTD3_GPIO));
+ FspmUpd->FspmConfig.RootPortIndex =3D SgGpioData->RootPortIndex;
+ }
+
+ if (IpuPreMemPolicy !=3D NULL) {
+ FspmUpd->FspmConfig.SaIpuEnable =3D (UINT8) IpuPreMemPolicy->SaIpuEnab=
le;
+ FspmUpd->FspmConfig.SaIpuImrConfiguration =3D (UINT8) IpuPreMemPolicy-=
>SaIpuImrConfiguration;
+ }
+
+ if (OcPreMemConfig !=3D NULL) {
+ FspmUpd->FspmConfig.SaOcSupport =3D (UINT8) OcPreMemConfig->OcSupport;
+ FspmUpd->FspmConfig.RealtimeMemoryTiming =3D (UINT8) OcPreMemConfig->R=
ealtimeMemoryTiming;
+ FspmUpd->FspmConfig.GtVoltageMode =3D (UINT8) OcPreMemConfig->GtVoltag=
eMode;
+ FspmUpd->FspmConfig.GtMaxOcRatio =3D OcPreMemConfig->GtMaxOcRatio;
+ FspmUpd->FspmConfig.GtVoltageOffset =3D OcPreMemConfig->GtVoltageOffse=
t;
+ FspmUpd->FspmConfig.GtVoltageOverride =3D OcPreMemConfig->GtVoltageOve=
rride;
+ FspmUpd->FspmConfig.GtExtraTurboVoltage =3D OcPreMemConfig->GtExtraTur=
boVoltage;
+ FspmUpd->FspmConfig.SaVoltageOffset =3D OcPreMemConfig->SaVoltageOffse=
t;
+ FspmUpd->FspmConfig.GtusMaxOcRatio =3D OcPreMemConfig->GtusMaxOcRatio;
+ FspmUpd->FspmConfig.GtusVoltageMode =3D (UINT8) OcPreMemConfig->GtusVo=
ltageMode;
+ FspmUpd->FspmConfig.GtusVoltageOffset =3D OcPreMemConfig->GtusVoltageO=
ffset;
+ FspmUpd->FspmConfig.GtusVoltageOverride =3D OcPreMemConfig->GtusVoltag=
eOverride;
+ FspmUpd->FspmConfig.GtusExtraTurboVoltage =3D OcPreMemConfig->GtusExtr=
aTurboVoltage;
+ }
+
+
+
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Performs FSP SA PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ SA_MISC_PEI_CONFIG *MiscPeiConfig;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ PCIE_PEI_CONFIG *PciePeiConfig;
+ GNA_CONFIG *GnaConfig;
+ UINT8 Index;
+ EFI_BOOT_MODE BootMode;
+
+ MiscPeiConfig =3D NULL;
+ GtConfig =3D NULL;
+ PciePeiConfig =3D NULL;
+ GnaConfig =3D NULL;
+
+ //
+ // @todo This could be cleared up after FSP provides ExitBootServices No=
tifyPhase.
+ //
+ Status =3D PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate SiPolicyPpi
+ //
+ SiPolicyPpi =3D NULL;
+ Status =3D PeiServicesLocatePpi(
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SiPolicyPpi
+ );
+ if ((Status =3D=3D EFI_SUCCESS) && (SiPolicyPpi !=3D NULL)) {
+ MiscPeiConfig =3D NULL;
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid=
, (VOID *) &MiscPeiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ GtConfig =3D NULL;
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGu=
id, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ GnaConfig =3D NULL;
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOI=
D *) &GnaConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ PciePeiConfig =3D NULL;
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid=
, (VOID *) &PciePeiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ }
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n"));
+
+
+ if (MiscPeiConfig !=3D NULL) {
+ FspsUpd->FspsConfig.Device4Enable =3D (UINT8) MiscPeiConfig->Device4En=
able;
+ FspsUpd->FspsConfig.CridEnable =3D (UINT8) MiscPeiConfig->CridEnable;
+ FspsUpd->FspsTestConfig.ChapDeviceEnable =3D (UINT8) MiscPeiConfig->Ch=
apDeviceEnable;
+ FspsUpd->FspsTestConfig.SkipPamLock =3D (UINT8) MiscPeiConfig->SkipPam=
Lock;
+ FspsUpd->FspsTestConfig.EdramTestMode =3D (UINT8) MiscPeiConfig->Edram=
TestMode;
+ }
+
+ if (PciePeiConfig !=3D NULL) {
+ FspsUpd->FspsConfig.DmiAspm =3D (UINT8) PciePeiConfig->DmiAspm;
+ FspsUpd->FspsTestConfig.DmiExtSync =3D (UINT8) PciePeiConfig->DmiExtSy=
nc;
+ FspsUpd->FspsTestConfig.DmiIot =3D (UINT8) PciePeiConfig->DmiIot;
+ for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) {
+ FspsUpd->FspsConfig.PegDeEmphasis[Index] =3D PciePeiConfig->PegDeEmp=
hasis[Index];
+ FspsUpd->FspsConfig.PegSlotPowerLimitValue[Index] =3D PciePeiConfig-=
>PegSlotPowerLimitValue[Index];
+ FspsUpd->FspsConfig.PegSlotPowerLimitScale[Index] =3D PciePeiConfig-=
>PegSlotPowerLimitScale[Index];
+ FspsUpd->FspsConfig.PegPhysicalSlotNumber[Index] =3D PciePeiConfig->=
PegPhysicalSlotNumber[Index];
+ FspsUpd->FspsTestConfig.PegMaxPayload[Index] =3D PciePeiConfig->PegM=
axPayload[Index];
+ }
+ }
+
+ if (GtConfig !=3D NULL) {
+ FspsUpd->FspsConfig.PavpEnable =3D (UINT8) GtConfig->PavpEnable;
+ FspsUpd->FspsConfig.CdClock =3D (UINT8) GtConfig->CdClock;
+ FspsUpd->FspsTestConfig.RenderStandby =3D (UINT8) GtConfig->RenderStan=
dby;
+ FspsUpd->FspsTestConfig.PmSupport =3D (UINT8) GtConfig->PmSupport;
+ FspsUpd->FspsTestConfig.CdynmaxClampEnable =3D (UINT8) GtConfig->Cdynm=
axClampEnable;
+ FspsUpd->FspsTestConfig.GtFreqMax =3D (UINT8) GtConfig->GtFreqMax;
+ FspsUpd->FspsTestConfig.DisableTurboGt =3D (UINT8) GtConfig->DisableTu=
rboGt;
+ FspsUpd->FspsConfig.SkipS3CdClockInit =3D (UINT8)GtConfig->SkipS3CdClo=
ckInit;
+
+ //
+ // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled =
as default.
+ //
+ FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D (UINT8) GtConfig->PeiGraph=
icsPeimInit; // SA: InternalOnly: For Internal validation we still need to =
enable both Enable/Disable Cases
+
+ //
+ // Update UPD: VBT & LogoPtr
+ //
+ if (BootMode =3D=3D BOOT_ON_S3_RESUME) {
+ FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32) NULL;
+ } else {
+ FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32) GtConfig->Graphic=
sConfigPtr;
+ }
+ DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd=
->FspsConfig.GraphicsConfigPtr));
+
+ FspsUpd->FspsConfig.LogoPtr =3D (UINT32) GtConfig->LogoPtr;
+ FspsUpd->FspsConfig.LogoSize =3D GtConfig->LogoSize;
+ DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig=
is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
+ DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfi=
g is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
+
+ FspsUpd->FspsConfig.BltBufferAddress =3D (UINT32) GtConfig->BltBuffer=
Address;
+ FspsUpd->FspsConfig.BltBufferSize =3D (UINT32) GtConfig->BltBuffer=
Size;
+
+ //
+ // Update DDI/DDC configuration
+ //
+ FspsUpd->FspsConfig.DdiPortEdp =3D GtConfig->DdiConfiguration.DdiPortE=
dp;
+ FspsUpd->FspsConfig.DdiPortBHpd =3D GtConfig->DdiConfiguration.DdiPort=
BHpd;
+ FspsUpd->FspsConfig.DdiPortCHpd =3D GtConfig->DdiConfiguration.DdiPort=
CHpd;
+ FspsUpd->FspsConfig.DdiPortDHpd =3D GtConfig->DdiConfiguration.DdiPort=
DHpd;
+ FspsUpd->FspsConfig.DdiPortFHpd =3D GtConfig->DdiConfiguration.DdiPort=
FHpd;
+ FspsUpd->FspsConfig.DdiPortBDdc =3D GtConfig->DdiConfiguration.DdiPort=
BDdc;
+ FspsUpd->FspsConfig.DdiPortCDdc =3D GtConfig->DdiConfiguration.DdiPort=
CDdc;
+ FspsUpd->FspsConfig.DdiPortDDdc =3D GtConfig->DdiConfiguration.DdiPort=
DDdc;
+ FspsUpd->FspsConfig.DdiPortFDdc =3D GtConfig->DdiConfiguration.DdiPort=
FDdc;
+
+ }
+
+ if (GnaConfig !=3D NULL) {
+ FspsUpd->FspsConfig.GnaEnable =3D (UINT8) GnaConfig->GnaEnable;
+#ifdef TESTMENU_FLAG
+#endif // TESTMENU_FLAG
+ }
+
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspSecurityPolicyInitLib.c b/Platform/Intel/CometlakeOpenB=
oardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c
new file mode 100644
index 0000000000..47d0a85e77
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspSecurityPolicyInitLib.c
@@ -0,0 +1,70 @@
+/** @file
+ Implementation of Fsp Security Policy Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+
+/**
+ Performs FSP Security PEI Policy initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSecurityPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem Star=
t\n"));
+
+ //
+ // Locate SiPreMemPolicyPpi
+ //
+ SiPreMemPolicyPpi =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem End\=
n"));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs FSP Security PEI Policy post memory initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSecurityPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspSiPolicyInitLib.c b/Platform/Intel/CometlakeOpenBoardPk=
g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c
new file mode 100644
index 0000000000..1a82436f23
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspSiPolicyInitLib.c
@@ -0,0 +1,96 @@
+/** @file
+ Implementation of Fsp SI Policy Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ Performs FSP SI PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+
+ //
+ // Locate SiPreMemPolicyPpi
+ //
+ SiPreMemPolicyPpi =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs FSP SI PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicy;
+ SI_CONFIG *SiConfig;
+
+ //
+ // Locate SiPolicyPpi
+ //
+ SiPolicy =3D NULL;
+ Status =3D PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &=
SiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update SiConfig policies
+ //
+ FspsUpd->FspsConfig.SiCsmFlag =3D (UINT8)SiConfig->CsmFla=
g;
+ FspsUpd->FspsConfig.SiSsidTablePtr =3D (UINT32)(UINTN)SiConfig=
->SsidTablePtr;
+ FspsUpd->FspsConfig.SiNumberOfSsidTableEntry =3D (UINT16)SiConfig->Numbe=
rOfSsidTableEntry;
+ FspsUpd->FspsConfig.TraceHubMemBase =3D SiConfig->TraceHubMemB=
ase;
+
+ return EFI_SUCCESS;
+}
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/CometlakeO=
penBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUp=
dateLib.c
new file mode 100644
index 0000000000..7dbdfa7c16
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -0,0 +1,100 @@
+/** @file
+ Implementation of Fsp Misc UPD Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PeiLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PeiServicesLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PciLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <PchAccess.h>
+
+#include "PeiMiscPolicyUpdate.h"
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in,out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND An instance of gEfiPeiReadOnly=
Variable2PpiGuid
+ could not be located.
+ @retval EFI_OUT_OF_RESOURCES Insufficent resources to alloc=
ate a memory buffer.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ UINTN VariableSize;
+ VOID *MemorySavedData;
+
+ Status =3D PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &VariableServices
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ VariableSize =3D 0;
+ MemorySavedData =3D NULL;
+ Status =3D VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gFspNonVolatileStorageHobGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {
+ MemorySavedData =3D AllocatePool (VariableSize);
+ if (MemorySavedData =3D=3D NULL) {
+ ASSERT (MemorySavedData !=3D NULL);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize));
+ Status =3D VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gFspNonVolatileStorageHobGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (Status =3D=3D EFI_SUCCESS) {
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;
+ } else {
+ DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" gMe=
moryConfigVariableGuid, Status =3D %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/CometlakeOp=
enBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpda=
teLib.c
new file mode 100644
index 0000000000..820696584d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiFspPolicyUpdateLib.c
@@ -0,0 +1,124 @@
+/** @file
+ Provide FSP wrapper platform related function.
+
+` Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/FspWrapperApiLib.h>
+#include <Library/SiliconPolicyUpdateLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#include "PeiMiscPolicyUpdate.h"
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+VOID
+InternalPrintVariableData (
+ IN UINT8 *Data8,
+ IN UINTN DataSize
+ )
+{
+ UINTN Index;
+
+ for (Index =3D 0; Index < DataSize; Index++) {
+ if (Index % 0x10 =3D=3D 0) {
+ DEBUG ((DEBUG_INFO, "\n%08X:", Index));
+ }
+ DEBUG ((DEBUG_INFO, " %02X", *Data8++));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+}
+
+/**
+ Performs silicon pre-mem policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a PPI, etc.
+
+ The input Policy must be returned by SiliconPolicyDonePreMem().
+
+ 1) In FSP path, the input Policy should be FspmUpd.
+ A platform may use this API to update the FSPM UPD policy initialized
+ by the silicon module or the default UPD data.
+ The output of FSPM UPD data from this API is the final UPD data.
+
+ 2) In non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+ IN OUT VOID *FspmUpd
+ )
+{
+ FSPM_UPD *FspmUpdDataPtr;
+
+ FspmUpdDataPtr =3D FspmUpd;
+
+ PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
+ InternalPrintVariableData ((VOID *) FspmUpdDataPtr, sizeof (FSPM_UPD));
+
+ return FspmUpd;
+}
+
+/**
+ Performs silicon post-mem policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a PPI, etc.
+
+ The input Policy must be returned by SiliconPolicyDonePostMem().
+
+ 1) In FSP path, the input Policy should be FspsUpd.
+ A platform may use this API to update the FSPS UPD policy initialized
+ by the silicon module or the default UPD data.
+ The output of FSPS UPD data from this API is the final UPD data.
+
+ 2) In non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+ IN OUT VOID *FspsUpd
+ )
+{
+ FSPS_UPD *FspsUpdDataPtr;
+
+ FspsUpdDataPtr =3D FspsUpd;
+
+ PeiFspPchPolicyUpdate (FspsUpd);
+ InternalPrintVariableData ((VOID * )FspsUpdDataPtr, sizeof (FSPS_UPD));
+
+ return FspsUpd;
+}
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h b/Platform/Intel/CometlakeOpen=
BoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdat=
e.h
new file mode 100644
index 0000000000..1f2e82cf43
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiMiscPolicyUpdate.h
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_MISC_POLICY_UPDATE_H_
+#define _PEI_MISC_POLICY_UPDATE_H_
+
+#include <FspmUpd.h>
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+#endif
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/CometlakeOpenB=
oardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..445a0de371
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiPchPolicyUpdate.c
@@ -0,0 +1,60 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initiali=
zation.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <GpioConfig.h>
+#include <GpioPinsSklH.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+#include <PcieDeviceOverrideTable.h>
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D (UINT32) mPcieDevi=
ceTable;
+
+ AddPlatformVerbTables (
+ PchHdaCodecPlatformOnboard,
+ &(FspsUpd->FspsConfig.PchHdaVerbTableEntryNum),
+ &(FspsUpd->FspsConfig.PchHdaVerbTablePtr)
+ );
+
+DEBUG_CODE_BEGIN();
+if ((PcdGet8 (PcdSerialIoUartDebugEnable) =3D=3D 1) &&
+ FspsUpd->FspsConfig.SerialIoUartMode[PchSerialIoIndexUart0 + PcdGet8 (=
PcdSerialIoUartNumber)] =3D=3D PchSerialIoDisabled ) {
+ FspsUpd->FspsConfig.SerialIoUartMode[PchSerialIoIndexUart0 + PcdGet8 (=
PcdSerialIoUartNumber)] =3D PchSerialIoHidden;
+ }
+DEBUG_CODE_END();
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/CometlakeOpenB=
oardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
new file mode 100644
index 0000000000..5684567c7b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiPchPolicyUpdate.h
@@ -0,0 +1,27 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real E=
DKII
+// environment
+//
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/MmPciLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/Cometlak=
eOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyU=
pdatePreMem.c
new file mode 100644
index 0000000000..cbe9bf8fbb
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,39 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initiali=
zation.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <PchHsioPtssTables.h>
+#include <Library/DebugLib.h>
+
+/**
+ Performs FSP PCH PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/CometlakeOpenBo=
ardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..b8905788df
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -0,0 +1,85 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/PeiLib.h>
+
+/**
+ Performs FSP SA PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ VOID *Buffer;
+ VOID *MemBuffer;
+ UINT32 Size;
+
+ DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+
+ FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1;
+
+ Size =3D 0;
+ Buffer =3D NULL;
+ PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA=
W, 0, &Buffer, &Size);
+ if (Buffer =3D=3D NULL) {
+ DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
+ } else {
+ MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)=
);
+ if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {
+ CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+ FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32)(UINTN)MemBuffer;
+ } else {
+ DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
+ FspsUpd->FspsConfig.GraphicsConfigPtr =3D 0;
+ }
+ }
+ DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", F=
spsUpd->FspsConfig.GraphicsConfigPtr));
+ DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size=
));
+
+ Size =3D 0;
+ Buffer =3D NULL;
+ PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, =
&Size);
+ if (Buffer =3D=3D NULL) {
+ DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
+ } else {
+ MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)=
);
+ if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {
+ CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+ FspsUpd->FspsConfig.LogoPtr =3D (UINT32)(UINTN)MemBuffer;
+ FspsUpd->FspsConfig.LogoSize =3D Size;
+ } else {
+ DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
+ FspsUpd->FspsConfig.LogoPtr =3D 0;
+ FspsUpd->FspsConfig.LogoSize =3D 0;
+ }
+ }
+ DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsU=
pd->FspsConfig.LogoPtr));
+ DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", Fsps=
Upd->FspsConfig.LogoSize));
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/CometlakeOpenBo=
ardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
new file mode 100644
index 0000000000..07013eddb9
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiSaPolicyUpdate.h
@@ -0,0 +1,30 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real E=
DKII
+// environment
+//
+#include <SaPolicyCommon.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <CpuAccess.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+extern EFI_GUID gTianoLogoGuid;
+
+#endif
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/Cometlake=
OpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpd=
atePreMem.c
new file mode 100644
index 0000000000..fffd4156f4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,87 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ VOID *Buffer;
+
+ //
+ // If SpdAddressTable are not all 0, it means DIMM slots implemented and
+ // MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPoli=
cyInitPreMem.
+ //
+ // If SpdAddressTable all 0, this is memory down design and hardcoded Sp=
dData
+ // should be applied to MemorySpdPtr*.
+ //
+ if ((PcdGet8 (PcdMrcSpdAddressTable0) =3D=3D 0) && (PcdGet8 (PcdMrcSpdAd=
dressTable1) =3D=3D 0)
+ && (PcdGet8 (PcdMrcSpdAddressTable2) =3D=3D 0) && (PcdGet8 (PcdMrcSp=
dAddressTable3) =3D=3D 0)) {
+ DEBUG ((DEBUG_INFO, "Overriding SPD data for down memory.\n"));
+ CopyMem (
+ (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00,
+ (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
+ PcdGet16 (PcdMrcSpdDataSize)
+ );
+ CopyMem (
+ (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10,
+ (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
+ PcdGet16 (PcdMrcSpdDataSize)
+ );
+ }
+
+ DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings=
...\n"));
+ Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 1=
2, 12);
+ }
+ Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
+ CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffe=
r + 8, 8);
+ }
+
+ DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp =
Target Settings...\n"));
+ Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
+ }
+ Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
+ if (Buffer) {
+ CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
+ }
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/Co=
metlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSili=
conPolicyUpdateLibFsp.inf
new file mode 100644
index 0000000000..c842b7eef6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -0,0 +1,140 @@
+## @file
+# Provide FSP wrapper platform related function.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+##########################################################################=
######
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+##########################################################################=
######
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D SiliconPolicyUpdateLibFsp
+ FILE_GUID =3D 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2
+ MODULE_TYPE =3D PEIM
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32 X64
+#
+
+##########################################################################=
######
+#
+# Sources Section - list of files that are required for the build to succe=
ed.
+#
+##########################################################################=
######
+
+[Sources]
+ PeiFspPolicyUpdateLib.c
+ PeiPchPolicyUpdatePreMem.c
+ PeiPchPolicyUpdate.c
+ PeiSaPolicyUpdatePreMem.c
+ PeiSaPolicyUpdate.c
+ PeiFspMiscUpdUpdateLib.c
+
+##########################################################################=
######
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+##########################################################################=
######
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses.IA32]
+ FspWrapperApiLib
+ OcWdtLib
+ PchResetLib
+ FspWrapperPlatformLib
+ BaseMemoryLib
+ CpuPlatformLib
+ DebugLib
+ HdaVerbTableLib
+ HobLib
+ IoLib
+ PcdLib
+ PostCodeLib
+ SmbusLib
+ ConfigBlockLib
+ PeiSaPolicyLib
+ PchGbeLib
+ PchInfoLib
+ PchHsioLib
+ PchPcieRpLib
+ MemoryAllocationLib
+ DebugPrintErrorLevelLib
+ SiPolicyLib
+ PchGbeLib
+ TimerLib
+ GpioLib
+ PeiLib
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUM=
ES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUM=
ES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUM=
ES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUM=
ES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
+
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid
+
+ # SPD Address Table
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+[Guids]
+ gFspNonVolatileStorageHobGuid ## CONSUMES
+ gTianoLogoGuid ## CONSUMES
+ gEfiMemoryOverwriteControlDataGuid
+
+[Depex]
+ gEdkiiVTdInfoPpiGuid
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/Acpi=
TimerLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/Acpi=
TimerLib.c
new file mode 100644
index 0000000000..446fb267fd
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/AcpiTimerLi=
b.c
@@ -0,0 +1,394 @@
+/** @file
+ ACPI Timer implements one instance of Timer Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <IndustryStandard/Acpi.h>
+//
+// OVERRIDE: OverrideBegin
+//
+#include <Register/Cpuid.h>
+//
+// OVERRIDE: OverrideEnd
+//
+
+
+/**
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+InternalGetPerformanceCounterFrequency (
+ VOID
+ );
+
+/**
+ The constructor function enables ACPI IO space.
+
+ If ACPI I/O space not enabled, this function will enable it.
+ It will always return RETURN_SUCCESS.
+
+ @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
+
+**/
+RETURN_STATUS
+EFIAPI
+AcpiTimerLibConstructor (
+ VOID
+ )
+{
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+ UINTN EnableRegister;
+ UINT8 EnableMask;
+
+ //
+ // ASSERT for the invalid PCD values. They must be configured to the rea=
l value.
+ //
+ ASSERT (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) !=3D 0xFFFF);
+ ASSERT (PcdGet16 (PcdAcpiIoPortBaseAddress) !=3D 0xFFFF);
+
+ //
+ // If the register offset to the BAR for the ACPI I/O Port Base Address =
is 0x0000, then
+ // no PCI register programming is required to enable access to the the A=
CPI registers
+ // specified by PcdAcpiIoPortBaseAddress
+ //
+ if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) =3D=3D 0x0000) {
+ return RETURN_SUCCESS;
+ }
+
+ //
+ // ASSERT for the invalid PCD values. They must be configured to the rea=
l value.
+ //
+ ASSERT (PcdGet8 (PcdAcpiIoPciDeviceNumber) !=3D 0xFF);
+ ASSERT (PcdGet8 (PcdAcpiIoPciFunctionNumber) !=3D 0xFF);
+ ASSERT (PcdGet16 (PcdAcpiIoPciEnableRegisterOffset) !=3D 0xFFFF);
+
+ //
+ // Retrieve the PCD values for the PCI configuration space required to p=
rogram the ACPI I/O Port Base Address
+ //
+ Bus =3D PcdGet8 (PcdAcpiIoPciBusNumber);
+ Device =3D PcdGet8 (PcdAcpiIoPciDeviceNumber);
+ Function =3D PcdGet8 (PcdAcpiIoPciFunctionNumber);
+ EnableRegister =3D PcdGet16 (PcdAcpiIoPciEnableRegisterOffset);
+ EnableMask =3D PcdGet8 (PcdAcpiIoBarEnableMask);
+
+ //
+ // If ACPI I/O space is not enabled yet, program ACPI I/O base address a=
nd enable it.
+ //
+ if ((PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, EnableRegister)) =
& EnableMask) !=3D EnableMask) {
+ PciWrite16 (
+ PCI_LIB_ADDRESS (Bus, Device, Function, PcdGet16 (PcdAcpiIoPciBarReg=
isterOffset)),
+ PcdGet16 (PcdAcpiIoPortBaseAddress)
+ );
+ PciOr8 (
+ PCI_LIB_ADDRESS (Bus, Device, Function, EnableRegister),
+ EnableMask
+ );
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Internal function to retrieve the ACPI I/O Port Base Address.
+
+ Internal function to retrieve the ACPI I/O Port Base Address.
+
+ @return The 16-bit ACPI I/O Port Base Address.
+
+**/
+UINT16
+InternalAcpiGetAcpiTimerIoPort (
+ VOID
+ )
+{
+ UINT16 Port;
+
+ Port =3D PcdGet16 (PcdAcpiIoPortBaseAddress);
+
+ //
+ // If the register offset to the BAR for the ACPI I/O Port Base Address =
is not 0x0000, then
+ // read the PCI register for the ACPI BAR value in case the BAR has been=
programmed to a
+ // value other than PcdAcpiIoPortBaseAddress
+ //
+ if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) !=3D 0x0000) {
+ Port =3D PciRead16 (PCI_LIB_ADDRESS (
+ PcdGet8 (PcdAcpiIoPciBusNumber),
+ PcdGet8 (PcdAcpiIoPciDeviceNumber),
+ PcdGet8 (PcdAcpiIoPciFunctionNumber),
+ PcdGet16 (PcdAcpiIoPciBarRegisterOffset)
+ ));
+ }
+
+ return (Port & PcdGet16 (PcdAcpiIoPortBaseAddressMask)) + PcdGet16 (PcdA=
cpiPm1TmrOffset);
+}
+
+/**
+ Stalls the CPU for at least the given number of ticks.
+
+ Stalls the CPU for at least the given number of ticks. It's invoked by
+ MicroSecondDelay() and NanoSecondDelay().
+
+ @param Delay A period of time to delay in ticks.
+
+**/
+VOID
+InternalAcpiDelay (
+ IN UINT32 Delay
+ )
+{
+ UINT16 Port;
+ UINT32 Ticks;
+ UINT32 Times;
+
+ Port =3D InternalAcpiGetAcpiTimerIoPort ();
+ Times =3D Delay >> 22;
+ Delay &=3D BIT22 - 1;
+ do {
+ //
+ // The target timer count is calculated here
+ //
+ Ticks =3D IoBitFieldRead32 (Port, 0, 23) + Delay;
+ Delay =3D BIT22;
+ //
+ // Wait until time out
+ // Delay >=3D 2^23 could not be handled by this function
+ // Timer wrap-arounds are handled correctly by this function
+ //
+ while (((Ticks - IoBitFieldRead32 (Port, 0, 23)) & BIT23) =3D=3D 0) {
+ CpuPause ();
+ }
+ } while (Times-- > 0);
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ InternalAcpiDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ MicroSeconds,
+ ACPI_TIMER_FREQUENCY
+ ),
+ 1000000u
+ )
+ );
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ InternalAcpiDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ NanoSeconds,
+ ACPI_TIMER_FREQUENCY
+ ),
+ 1000000000u
+ )
+ );
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ Retrieves the current value of a 64-bit free running performance counter=
. The
+ counter can either count up by 1 or count down by 1. If the physical
+ performance counter counts by a larger increment, then the counter values
+ must be translated. The properties of the counter can be retrieved from
+ GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ return AsmReadTsc ();
+}
+
+/**
+ Retrieves the 64-bit frequency in Hz and the range of performance counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance counter s=
tarts
+ with immediately after is it rolls over is returned in StartValue. If
+ EndValue is not NULL, then the value that the performance counter end wi=
th
+ immediately before it rolls over is returned in EndValue. The 64-bit
+ frequency of the performance counter in Hz is always returned. If StartV=
alue
+ is less than EndValue, then the performance counter counts up. If StartV=
alue
+ is greater than EndValue, then the performance counter counts down. For
+ example, a 64-bit free running counter that counts up would have a Start=
Value
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of =
0.
+
+ @param StartValue The value the performance counter starts with when it
+ rolls over.
+ @param EndValue The value that the performance counter ends with bef=
ore
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue !=3D NULL) {
+ *StartValue =3D 0;
+ }
+
+ if (EndValue !=3D NULL) {
+ *EndValue =3D 0xffffffffffffffffULL;
+ }
+ return InternalGetPerformanceCounterFrequency ();
+}
+
+/**
+ Converts elapsed ticks of performance counter to time in nanoseconds.
+
+ This function converts the elapsed ticks of running performance counter =
to
+ time value in unit of nanoseconds.
+
+ @param Ticks The number of elapsed ticks of running performance cou=
nter.
+
+ @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+ IN UINT64 Ticks
+ )
+{
+ UINT64 Frequency;
+ UINT64 NanoSeconds;
+ UINT64 Remainder;
+ INTN Shift;
+ Frequency =3D GetPerformanceCounterProperties (NULL, NULL);
+
+ //
+ // Ticks
+ // Time =3D --------- x 1,000,000,000
+ // Frequency
+ //
+ NanoSeconds =3D MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remai=
nder), 1000000000u);
+
+ //
+ // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
+ // Since 2^29 < 1,000,000,000 =3D 0x3B9ACA00 < 2^30, Remainder should < =
2^(64-30) =3D 2^34,
+ // i.e. highest bit set in Remainder should <=3D 33.
+ //
+ Shift =3D MAX (0, HighBitSet64 (Remainder) - 33);
+ Remainder =3D RShiftU64 (Remainder, (UINTN) Shift);
+ Frequency =3D RShiftU64 (Frequency, (UINTN) Shift);
+ NanoSeconds +=3D DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u)=
, Frequency, NULL);
+
+ return NanoSeconds;
+}
+
+//
+// OVERRIDE: OverrideBegin
+//
+/**
+ Calculate TSC frequency.
+
+ The TSC counting frequency is determined by using CPUID leaf 0x15 that i=
s the preferred
+ method for Skylake and beyond. Frequency in MHz =3D Core XTAL frequency=
* EBX/EAX.
+ In newer flavors of the CPU, core xtal frequency is returned in ECX (or =
0 if not
+ supported). If ECX is 0, 24MHz is assumed.
+ @return The number of TSC counts per second.
+
+**/
+UINT64
+InternalCalculateTscFrequency (
+ VOID
+ )
+{
+ UINT64 TscFrequency;
+ UINT64 CoreXtalFrequency;
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+
+ //
+ // Use CPUID leaf 0x15.
+ // TSC frequency =3D (Core Xtal Frequency) * EBX/EAX. EBX returns 0 if =
not
+ // supported. ECX, if non zero, provides Core Xtal Frequency in hertz
+ // (SDM Dec 2016).
+ //
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &RegEax, &RegEbx, &RegEcx, NULL);
+ ASSERT (RegEbx !=3D 0);
+
+ //
+ // If core xtal frequency (ECX) returns 0, it is safe to use 24MHz for p=
ost
+ // Skylake client CPU's.
+ //
+ if (RegEcx =3D=3D 0) {
+ CoreXtalFrequency =3D 24000000ul;
+ } else {
+ CoreXtalFrequency =3D (UINT64)RegEcx;
+ }
+
+ //
+ // Calculate frequency. For integer division, round up/down result
+ // correctly by adding denominator/2 to the numerator prior to division.
+ //
+ TscFrequency =3D DivU64x32 (MultU64x32 (CoreXtalFrequency, RegEbx) + (UI=
NT64)(RegEax >> 1), RegEax);
+
+ return TscFrequency;
+}
+//
+// OVERRIDE: OverrideEnd
+//
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/Base=
AcpiTimerLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/=
BaseAcpiTimerLib.c
new file mode 100644
index 0000000000..523e88447a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTim=
erLib.c
@@ -0,0 +1,48 @@
+/** @file
+ ACPI Timer implements one instance of Timer Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+
+/**
+ Calculate TSC frequency.
+
+ The TSC counting frequency is determined by comparing how far it counts
+ during a 101.4 us period as determined by the ACPI timer.
+ The ACPI timer is used because it counts at a known frequency.
+ The TSC is sampled, followed by waiting 363 counts of the ACPI timer,
+ or 101.4 us. The TSC is then sampled again. The difference multiplied by
+ 9861 is the TSC frequency. There will be a small error because of the
+ overhead of reading the ACPI timer. An attempt is made to determine and
+ compensate for this error.
+
+ @return The number of TSC counts per second.
+
+**/
+UINT64
+InternalCalculateTscFrequency (
+ VOID
+ );
+
+/**
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+InternalGetPerformanceCounterFrequency (
+ VOID
+ )
+{
+ return InternalCalculateTscFrequency ();
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/Base=
AcpiTimerLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLi=
b/BaseAcpiTimerLib.inf
new file mode 100644
index 0000000000..918dd7bf92
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTim=
erLib.inf
@@ -0,0 +1,54 @@
+## @file
+# Base ACPI Timer Library
+#
+# Provides basic timer support using the ACPI timer hardware. The perfor=
mance
+# counter features are provided by the processors time stamp counter.
+#
+# Note: The implementation uses the lower 24-bits of the ACPI timer and
+# is compatible with both 24-bit and 32-bit ACPI timers.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D BaseAcpiTimerLib
+ FILE_GUID =3D 564DE85F-049E-4481-BF7A-CA04D2788CF9
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D TimerLib|SEC PEI_CORE PEIM
+ CONSTRUCTOR =3D AcpiTimerLibConstructor
+ MODULE_UNI_FILE =3D BaseAcpiTimerLib.uni
+
+[Sources]
+ AcpiTimerLib.c
+ BaseAcpiTimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PcAtChipsetPkg/PcAtChipsetPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec ## OVERRIDE
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ PciLib
+ IoLib
+ DebugLib
+
+[Pcd]
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber ## CONSU=
MES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber ## CONSU=
MES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber ## CONSU=
MES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset ## CONSU=
MES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask ## CONSU=
MES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset ## CONSU=
MES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress ## CONSU=
MES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset ## CONSU=
MES
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask ## CONSU=
MES
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/Base=
AcpiTimerLib.uni b/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLi=
b/BaseAcpiTimerLib.uni
new file mode 100644
index 0000000000..5cf4d16d5c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTim=
erLib.uni
@@ -0,0 +1,15 @@
+/** @file
+ Base ACPI Timer Library
+ Provides basic timer support using the ACPI timer hardware. The perform=
ance
+ counter features are provided by the processors time stamp counter.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#string STR_MODULE_ABSTRACT #language en-US "ACPI Timer Librar=
y"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti=
mer support using the ACPI timer hardware."
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioExpanderL=
ib/BaseGpioExpanderLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Library/Bas=
eGpioExpanderLib/BaseGpioExpanderLib.c
new file mode 100644
index 0000000000..01a338c50f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioExpanderLib/Base=
GpioExpanderLib.c
@@ -0,0 +1,308 @@
+/** @file
+ Support for IO expander TCA6424.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioExpanderLib.h>
+#include <Library/I2cAccessLib.h>
+
+//
+// Addresses of registers inside expander
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mInputRegister[3] =3D {0x0,0x1,0x2=
};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mOutputRegister[3] =3D {0x4,0x5,0x6=
};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mConfigRegister[3] =3D {0xC,0xD,0xE=
};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPolarityRegister[3] =3D {0x8,0x9,0xA=
};
+
+#define PCH_SERIAL_IO_I2C4 4
+#define TCA6424_I2C_ADDRESS 0x22
+#define PINS_PER_REGISTER 8
+#define GPIO_EXP_PIN_DIRECTION_OUT 1
+#define GPIO_EXP_PIN_DIRECTION_IN 0
+#define GPIO_EXP_PIN_POLARITY_NORMAL 0
+#define GPIO_EXP_PIN_POLARITY_INVERTED 1
+#define GPIO_EXP_SET_OUTPUT 0
+#define GPIO_EXP_SET_DIR 1
+#define GPIO_EXP_GET_INPUT 2
+#define GPIO_EXP_SET_POLARITY 3
+#define AUTO_INCREMENT 0x80
+
+/**
+ Returns the Controller on which GPIO expander is present.
+
+ This function returns the Controller value
+
+ @param[out] Controller Pointer to a Controller value on
+ which I2C expander is configured.
+
+ @retval EFI_SUCCESS non.
+**/
+EFI_STATUS
+GpioExpGetController (
+ OUT UINT8 *Controller
+ )
+{
+ *Controller =3D PCH_SERIAL_IO_I2C4;
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the data from register value giving in the input.
+
+ This function is to get the data from the Expander
+ Registers by following the I2C Protocol communication
+
+
+ @param[in] Bar0 Bar address of the SerialIo Controller
+ @param[in] Address Expander Value with in the Contoller
+ @param[in] Register Address of Input/Output/Configure/Polarity
+ registers with in the Expander
+
+ @retval UINT8 Value returned from the register
+**/
+UINT8
+GpioExpGetRegister (
+ IN UINTN Bar0,
+ IN UINT8 Address,
+ IN UINT8 Register
+ )
+{
+ UINT8 WriBuf[1];
+ UINT8 ReBuf[1] =3D {0};
+
+ WriBuf[0] =3D Register;
+ I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 1, WriBuf, 1, ReBuf, =
WAIT_1_SECOND);
+
+ return ReBuf[0];
+}
+/**
+ Set the input register to a give value mentioned in the function.
+
+ This function is to Programm the data value to the Expander
+ Register by following the I2C Protocol communication.
+
+ @param[in] Bar0 Bar address of the SerialIo Controller
+ @param[in] Address Expander Value with in the Contoller
+ @param[in] Register Address of Input/Output/Configure/Polarity
+ registers with in the Expander
+ @param[in] Value Value to set in the mentioned the register
+**/
+VOID
+GpioExpSetRegister (
+ IN UINTN Bar0,
+ IN UINT8 Address,
+ IN UINT8 Register,
+ IN UINT8 Value
+ )
+{
+ UINT8 WriBuf[2];
+
+ WriBuf[0] =3D Register;
+ WriBuf[1] =3D Value;
+
+ I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 2, WriBuf, 0, NULL, W=
AIT_1_SECOND);
+}
+/**
+ Set the input register to a give value mentioned in the function.
+
+ This function is to update the status of the Gpio Expander
+ pin based on the input Operation value of the caller.This
+ function calculates the exact address of the register with
+ the help of the Register Bank
+
+ @param[in] Controller SerialIo Controller value
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+ @param[in] Operation Type of operation (Setoutput/Setdirection
+ /Getinput/Setpolarity)
+ @retval UINT8 Final Value returned from the register
+**/
+UINT8
+GpioExpDecodeRegAccess (
+ IN UINT8 Controller,
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Value,
+ IN UINT8 Operation
+ )
+{
+ UINT8* RegisterBank;
+ UINT8 OldValue;
+ UINT8 NewValue;
+ UINT8 RegisterAddress;
+ UINT8 PinNumber;
+ UINT8 ReturnValue =3D 0;
+
+ DEBUG ((DEBUG_INFO, "GpioExpDecodeRegAccess() %x:%x:%x:%x:%x\n", Control=
ler, Expander, Pin, Value, Operation));
+ ASSERT(Controller<6);
+ ASSERT(Expander<2);
+ ASSERT(Pin<24);
+ ASSERT(Value<2);
+ ASSERT(Operation<4);
+ //
+ // Find the register Address value based on the OPeration
+ //
+ switch(Operation) {
+ case GPIO_EXP_SET_OUTPUT:
+ RegisterBank =3D mOutputRegister;
+ break;
+ case GPIO_EXP_SET_DIR:
+ RegisterBank =3D mConfigRegister;
+ break;
+ case GPIO_EXP_GET_INPUT:
+ RegisterBank =3D mInputRegister;
+ break;
+ case GPIO_EXP_SET_POLARITY:
+ RegisterBank =3D mPolarityRegister;
+ break;
+ default:
+ ASSERT(FALSE);
+ return 0;
+ }
+ //
+ // Each bit of register represents each Pin
+ // calaulate the register address and Pinnumber(offset with in register)
+ //
+ if (Pin >=3D 24) {
+ //
+ // Avoid out-of-bound usage of RegisterBank
+ //
+ return 0;
+ }
+
+ RegisterAddress =3D RegisterBank[(Pin/PINS_PER_REGISTER)];
+ PinNumber =3D Pin%PINS_PER_REGISTER;
+
+ OldValue =3D GpioExpGetRegister(FindSerialIoBar(Controller, 0), Expander=
, RegisterAddress);
+ //
+ // If it to get the data ,just returned otherwise mark the input value a=
nd write the register
+ //
+ if (Operation =3D=3D GPIO_EXP_GET_INPUT) {
+ ReturnValue =3D 0x1 & (OldValue>>PinNumber);
+ } else {
+ NewValue =3D OldValue;
+ NewValue &=3D ~(BIT0<<PinNumber);
+ NewValue |=3D (Value<<PinNumber);
+ if(NewValue!=3DOldValue) {
+ GpioExpSetRegister(FindSerialIoBar(Controller, 0), Expander, Registe=
rAddress, NewValue);
+ }
+ }
+ return ReturnValue;
+}
+/**
+ Set the Output value for the given Expander Gpio pin.
+
+ This function is to Set the Output value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+
+**/
+VOID
+GpioExpSetOutput (
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Value
+ )
+{
+ UINT8 Controller;
+ if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+ GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_OUTP=
UT);
+ }
+}
+/**
+ Set the Direction value for the given Expander Gpio pin.
+
+ This function is to Set the direction value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+**/
+VOID
+GpioExpSetDirection (
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Value
+ )
+{
+
+ UINT8 Controller;
+ if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+ GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_DIR);
+ }
+}
+
+
+/**
+ Get the input value for the given Expander Gpio pin.
+
+ This function is to get the input value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+
+ @retval UINT8 Final Value returned from the register
+**/
+UINT8
+GpioExpGetInput (
+ IN UINT8 Expander,
+ IN UINT8 Pin
+ )
+{
+ UINT8 Controller;
+ if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+ return GpioExpDecodeRegAccess(Controller,Expander,Pin,0,GPIO_EXP_GET_I=
NPUT);
+ }
+ return 0;
+}
+
+/**
+ Configures all registers of a single IO Expander in one go.
+
+ @param[in] Expander Expander number (0/1)
+ @param[in] Direction Bit-encoded direction values. BIT0 is for pin0, =
etc. 0=3Doutput, 1=3Dinput
+ @param[in] Polarity Bit-encoded input inversion values. BIT0 is for =
pin0, etc. 0=3Dnormal, 1=3Dinversion
+ @param[in] Output Bit-encoded output state, ignores polarity, only=
applicable if direction=3DINPUT. BIT0 is for pin0, etc. 0=3Dlow, 1=3Dhigh
+
+**/
+VOID
+GpioExpBulkConfig (
+ IN UINT8 Expander,
+ IN UINT32 Direction,
+ IN UINT32 Polarity,
+ IN UINT32 Output
+ )
+{
+ UINT8 WriteBuf[4];
+ UINT8 Controller;
+
+ GpioExpGetController(&Controller);
+
+ WriteBuf[0] =3D mOutputRegister[0] + AUTO_INCREMENT;
+ WriteBuf[1] =3D Output & 0xFF;
+ WriteBuf[2] =3D (Output>>8) & 0xFF;
+ WriteBuf[3] =3D (Output>>16) & 0xFF;
+ I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande=
r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+ WriteBuf[0] =3D mPolarityRegister[0] + AUTO_INCREMENT;
+ WriteBuf[1] =3D Polarity & 0xFF;
+ WriteBuf[2] =3D (Polarity>>8) & 0xFF;
+ WriteBuf[3] =3D (Polarity>>16) & 0xFF;
+ I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande=
r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+ WriteBuf[0] =3D mConfigRegister[0] + AUTO_INCREMENT;
+ WriteBuf[1] =3D Direction & 0xFF;
+ WriteBuf[2] =3D (Direction>>8) & 0xFF;
+ WriteBuf[3] =3D (Direction>>16) & 0xFF;
+ I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande=
r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioExpanderL=
ib/BaseGpioExpanderLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Library/B=
aseGpioExpanderLib/BaseGpioExpanderLib.inf
new file mode 100644
index 0000000000..fe9238a553
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioExpanderLib/Base=
GpioExpanderLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Library producing Gpio Expander functionality.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D BaseGpioExpanderLib
+ FILE_GUID =3D D10AE2A4-782E-427E-92FB-BB74505ED329
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D BASE
+ LIBRARY_CLASS =3D GpioExpanderLib
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ TimerLib
+ PchSerialIoLib
+ I2cAccessLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ BaseGpioExpanderLib.c
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLi=
b/PchHdaVerbTables.c b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaV=
erbTableLib/PchHdaVerbTables.c
new file mode 100644
index 0000000000..0f5571724d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHd=
aVerbTables.c
@@ -0,0 +1,2053 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <ConfigBlock/HdAudioConfig.h>
+#include <Ppi/SiPolicy.h>
+
+HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: CFL Display Audio Codec
+ // Revision ID =3D 0xFF
+ // Codec Vendor: 0x8086280B
+ //
+ 0x8086, 0x280B,
+ 0xFF, 0xFF,
+ //
+ // Display Audio Verb Table
+ //
+ // For GEN9, the Vendor Node ID is 08h
+ // Port to be exposed to the inbox driver in the vanilla mode: PORT C - =
BIT[7:6] =3D 01b
+ 0x00878140,
+ // Pin Widget 5 - PORT B - Configuration Default: 0x18560010
+ 0x00571C10,
+ 0x00571D00,
+ 0x00571E56,
+ 0x00571F18,
+ // Pin Widget 6 - PORT C - Configuration Default: 0x18560020
+ 0x00671C20,
+ 0x00671D00,
+ 0x00671E56,
+ 0x00671F18,
+ // Pin Widget 7 - PORT D - Configuration Default: 0x18560030
+ 0x00771C30,
+ 0x00771D00,
+ 0x00771E56,
+ 0x00771F18,
+ // Disable the third converter and third Pin (NID 08h)
+ 0x00878140
+);
+
+//
+//codecs verb tables
+//
+HDAUDIO_VERB_TABLE HdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC700)
+ // Revision ID =3D 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0700
+ //
+ 0x10EC, 0x0700,
+ 0xFF, 0xFF,
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC700
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11030
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40622005
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211020
+ // NID 0x29 : 0x411111F0
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //HDA Codec Subsystem ID : 0x10EC10F2
+ 0x001720F2,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C30,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C05,
+ 0x01D71D20,
+ 0x01D71E62,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205004A,
+ 0x0204201B,
+ //Widget node 0x20 - 1 :
+ 0x05850000,
+ 0x05843888,
+ 0x0205006F,
+ 0x02042C0B,
+
+
+ //Widget node 0X20 for ALC1305 20160603 update
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040600,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FFD0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02040DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x0204005D,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040442,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040005,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040006,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040008,
+ 0x02050028,
+ 0x0204B000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204002E,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C3,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204D4A0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204400A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040320,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040039,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003B,
+ 0x02050028,
+ 0x0204FFFF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02041DFE,
+ 0x02050029,
+ 0x0204B024,
+ //
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C0,
+ 0x02050028,
+ 0x020401FA,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C1,
+ 0x02050028,
+ 0x0204DE23,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C2,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C3,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C4,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C5,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C6,
+ 0x02050028,
+ 0x020403F5,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C7,
+ 0x02050028,
+ 0x0204AF1B,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C8,
+ 0x02050028,
+ 0x02041E0A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C9,
+ 0x02050028,
+ 0x0204368E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CA,
+ 0x02050028,
+ 0x020401FA,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CB,
+ 0x02050028,
+ 0x0204DE23,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CC,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CD,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CE,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CF,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D0,
+ 0x02050028,
+ 0x020403F5,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D1,
+ 0x02050028,
+ 0x0204AF1B,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D2,
+ 0x02050028,
+ 0x02041E0A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D3,
+ 0x02050028,
+ 0x0204368E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040040,
+ 0x02050028,
+ 0x0204800F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040062,
+ 0x02050028,
+ 0x02048000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040063,
+ 0x02050028,
+ 0x02044848,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040064,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040065,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040066,
+ 0x02050028,
+ 0x02044004,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040067,
+ 0x02050028,
+ 0x02040802,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040068,
+ 0x02050028,
+ 0x0204890F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040069,
+ 0x02050028,
+ 0x0204E021,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040070,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040071,
+ 0x02050000,
+ 0x02043330,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040072,
+ 0x02050000,
+ 0x02043333,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040073,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040074,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040075,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040076,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040050,
+ 0x02050028,
+ 0x020402EC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040051,
+ 0x02050028,
+ 0x02044909,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040052,
+ 0x02050028,
+ 0x020440B0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040046,
+ 0x02050028,
+ 0x0204C22E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040047,
+ 0x02050028,
+ 0x02040C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040048,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040049,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004A,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004B,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204721F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204009E,
+ 0x02050028,
+ 0x02040001,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040500,
+ 0x02050029,
+ 0x0204B024
+); // HdaVerbTableAlc700
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc701 =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC701)
+ // Revision ID =3D 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0701
+ //
+ 0x10EC, 0x0701,
+ 0xFF, 0xFF,
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC701
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11030
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40610041
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211020
+ // NID 0x29 : 0x411111F0
+
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //HDA Codec Subsystem ID : 0x10EC1124
+ 0x00172024,
+ 0x00172111,
+ 0x001722EC,
+ 0x00172310,
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C30,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C41,
+ 0x01D71D00,
+ 0x01D71E61,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205004A,
+ 0x0204201B,
+ //Widget node 0x20 - 1 :
+ 0x05850000,
+ 0x05843888,
+ 0x0205006F,
+ 0x02042C0B
+); // HdaVerbTableAlc701
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc274 =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC274)
+ // Revision ID =3D 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0274
+ //
+ 0x10EC, 0x0274,
+ 0xFF, 0xFF,
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC274
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6
+ //The number of verb command block : 16
+
+ // NID 0x12 : 0x40000000
+ // NID 0x13 : 0x411111F0
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x411111F0
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11020
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40451B05
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211010
+
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //,DA Codec Subsystem ID : 0x10EC10F6
+ 0x001720F6,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371CF0,
+ 0x01371D11,
+ 0x01371E11,
+ 0x01371F41,
+ //Pin widget 0x14 - NPC
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S_OUT2
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S_OUT1
+ 0x01771CF0,
+ 0x01771D11,
+ 0x01771E11,
+ 0x01771F41,
+ //Pin widget 0x18 - I2S_IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C20,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C05,
+ 0x01D71D1B,
+ 0x01D71E45,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C10,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205006F,
+ 0x02042C0B,
+ //Widget node 0x20 - 1 :
+ 0x02050035,
+ 0x02048968,
+ 0x05B50001,
+ 0x05B48540,
+ //Widget node 0x20 - 2 :
+ 0x05850000,
+ 0x05843888,
+ 0x05850000,
+ 0x05843888,
+ //Widget node 0x20 - 3 :
+ 0x0205004A,
+ 0x0204201B,
+ 0x0205004A,
+ 0x0204201B
+); //HdaVerbTableAlc274
+
+//
+// WHL codecs verb tables
+//
+HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC700) WHL RVP
+ // Revision ID =3D 0xff
+ // Codec Verb Table for WHL PCH boards
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0700
+ //
+ 0x10EC, 0x0700,
+ 0xFF, 0xFF,
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.1
+ //Realtek HD Audio Codec : ALC700
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x02A19040
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40638029
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x02211020
+ // NID 0x29 : 0x411111F0
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //HDA Codec Subsystem ID : 0x10EC10F2
+ 0x001720F2,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271CF0,
+ 0x01271D11,
+ 0x01271E11,
+ 0x01271F41,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C40,
+ 0x01971D90,
+ 0x01971EA1,
+ 0x01971F02,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C29,
+ 0x01D71D80,
+ 0x01D71E63,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F02,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 - 0 FAKE JD unplug
+ 0x02050008,
+ 0x0204A80F,
+ 0x02050008,
+ 0x0204A80F,
+
+ //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 byp=
ass DAC02 DRE(NID5B bit14)
+ 0x05B50010,
+ 0x05B45C1D,
+ 0x0205006F,
+ 0x02040F8B, //Zeek, 0F8Bh
+
+ //Widget node 0x20 -2:
+ 0x02050045,
+ 0x02045089,
+ 0x0205004A,
+ 0x0204201B,
+
+ //Widget node 0x20 - 3 From JD detect
+ 0x02050008,
+ 0x0204A807,
+ 0x02050008,
+ 0x0204A807,
+
+ //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and en=
able I2S BCLK first
+ 0x02050090,
+ 0x02040424,
+ 0x00171620,
+ 0x00171720,
+
+ 0x00171520,
+ 0x01770740,
+ 0x01770740,
+ 0x01770740,
+
+ //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove ALC=
1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02045548,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02041000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040600,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FFD0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02040DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x0204005D,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040442,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040005,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040006,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040008,
+ 0x02050028,
+ 0x0204B000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204002E,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C3,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204D4A0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204400A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040320,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040039,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003B,
+ 0x02050028,
+ 0x0204FFFF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x020400C0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCF0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C0,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C1,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C2,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C3,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C4,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C5,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C6,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C7,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C8,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C9,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CA,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CB,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CC,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CD,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CE,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CF,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D0,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D1,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D2,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D3,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040062,
+ 0x02050028,
+ 0x02048000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040063,
+ 0x02050028,
+ 0x02045F5F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040064,
+ 0x02050028,
+ 0x02042000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040065,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040066,
+ 0x02050028,
+ 0x02044004,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040067,
+ 0x02050028,
+ 0x02040802,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040068,
+ 0x02050028,
+ 0x0204890F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040069,
+ 0x02050028,
+ 0x0204E021,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040070,
+ 0x02050028,
+ 0x02048012,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040071,
+ 0x02050028,
+ 0x02043450,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040072,
+ 0x02050028,
+ 0x02040123,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040073,
+ 0x02050028,
+ 0x02044543,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040074,
+ 0x02050028,
+ 0x02042100,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040075,
+ 0x02050028,
+ 0x02044321,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040076,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040050,
+ 0x02050028,
+ 0x02048200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040051,
+ 0x02050028,
+ 0x02040707,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040052,
+ 0x02050028,
+ 0x02044090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204721F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040012,
+ 0x02050028,
+ 0x0204DFDF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204009E,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040500,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040060,
+ 0x02050028,
+ 0x0204E213,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02041DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02043000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040040,
+ 0x02050028,
+ 0x0204000C,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040046,
+ 0x02050028,
+ 0x0204422E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004B,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024
+); // WhlHdaVerbTableAlc700
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLi=
b/PeiHdaVerbTableLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHd=
aVerbTableLib/PeiHdaVerbTableLib.c
new file mode 100644
index 0000000000..c0af462193
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHd=
aVerbTableLib.c
@@ -0,0 +1,137 @@
+/** @file
+ This file is SampleCode of the library for Intel HD Audio Verb Table con=
figuration.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <ConfigBlock.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+extern HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc274;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc700;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc701;
+extern HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700;
+
+/**
+ Add verb table helper function.
+ This function calculates verbtable number and shows verb table informati=
on.
+
+ @param[in,out] VerbTableEntryNum Input current VerbTable number and=
output the number after adding new table
+ @param[in,out] VerbTableArray Pointer to array of VerbTable
+ @param[in] VerbTable VerbTable which is going to add in=
to array
+**/
+STATIC
+VOID
+InternalAddVerbTable (
+ IN OUT UINT8 *VerbTableEntryNum,
+ IN OUT UINT32 *VerbTableArray,
+ IN HDAUDIO_VERB_TABLE *VerbTable
+ )
+{
+ if (VerbTable =3D=3D NULL) {
+ DEBUG ((DEBUG_INFO, "InternalAddVerbTable wrong input: VerbTable =3D=
=3D NULL\n"));
+ return;
+ }
+
+ VerbTableArray[*VerbTableEntryNum] =3D (UINT32) VerbTable;
+ *VerbTableEntryNum +=3D 1;
+
+ DEBUG ((DEBUG_INFO,
+ "HDA: Add verb table for vendor =3D 0x%04X devId =3D 0x%04X (size =3D =
%d DWords)\n",
+ VerbTable->Header.VendorId,
+ VerbTable->Header.DeviceId,
+ VerbTable->Header.DataDwords)
+ );
+}
+
+/**
+ Add verb table function.
+ This function update the verb table number and verb table ptr of policy.
+
+ @param[in] HdAudioConfig HD Audio config block
+ @param[out] VerbTableEntryNum Number of verb table entries
+ @param[out] HdaVerbTablePtr Pointer to the verb table
+**/
+VOID
+AddPlatformVerbTables (
+ IN UINT8 CodecType,
+ OUT UINT8 *VerbTableEntryNum,
+ OUT UINT32 *HdaVerbTablePtr
+ )
+{
+ UINT8 VerbTableEntries;
+ UINT32 VerbTableArray[6];
+ UINT32 *VerbTablePtr;
+
+ VerbTableEntries =3D 0;
+
+ InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN=
) PcdGet32 (PcdDisplayAudioHdaVerbTable));
+
+ if (CodecType =3D=3D PchHdaCodecPlatformOnboard) {
+ DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n"));
+ InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN=
TN) PcdGet32 (PcdHdaVerbTable));
+ InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN=
TN) PcdGet32 (PcdHdaVerbTable2));
+ } else {
+ DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));
+ InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN=
TN) PcdGet32 (PcdCommonHdaVerbTable1));
+ InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN=
TN) PcdGet32 (PcdCommonHdaVerbTable2));
+ InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN=
TN) PcdGet32 (PcdCommonHdaVerbTable3));
+ }
+
+ *VerbTableEntryNum =3D VerbTableEntries;
+
+ VerbTablePtr =3D (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTabl=
eEntries);
+ CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntrie=
s);
+ *HdaVerbTablePtr =3D (UINT32) VerbTablePtr;
+}
+
+/**
+ HDA VerbTable init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+HdaVerbTableInit (
+ IN UINT16 BoardId
+ )
+{
+ HDAUDIO_VERB_TABLE *VerbTable;
+ HDAUDIO_VERB_TABLE *VerbTable2;
+
+ VerbTable =3D NULL;
+ VerbTable2 =3D NULL;
+
+ switch (BoardId) {
+
+ case BoardIdCometLakeULpddr3Rvp:
+ VerbTable =3D &WhlHdaVerbTableAlc700;
+ break;
+
+ default:
+ DEBUG ((DEBUG_INFO, "HDA: Init default verb tables (Realtek ALC700 a=
nd ALC701)\n"));
+ VerbTable =3D &HdaVerbTableAlc700;
+ VerbTable2 =3D &HdaVerbTableAlc701;
+ break;
+ }
+
+ PcdSet32S (PcdHdaVerbTable, (UINT32) VerbTable);
+ PcdSet32S (PcdHdaVerbTable2, (UINT32) VerbTable2);
+ PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINT32) &HdaVerbTableDisplayAud=
io);
+
+ // Codecs - Realtek ALC700, ALC701, ALC274 (external - connected via HDA=
header)
+ PcdSet32S (PcdCommonHdaVerbTable1, (UINT32) &HdaVerbTableAlc700);
+ PcdSet32S (PcdCommonHdaVerbTable2, (UINT32) &HdaVerbTableAlc701);
+ PcdSet32S (PcdCommonHdaVerbTable3, (UINT32) &HdaVerbTableAlc274);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLi=
b/PeiHdaVerbTableLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Library/Pei=
HdaVerbTableLib/PeiHdaVerbTableLib.inf
new file mode 100644
index 0000000000..3a4c38f0db
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHd=
aVerbTableLib.inf
@@ -0,0 +1,69 @@
+## @file
+# PEI Intel HD Audio Verb Table library.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+##########################################################################=
######
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+##########################################################################=
######
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D PeiHdaVerbTableLib
+ FILE_GUID =3D 821486A2-CF3B-4D24-BC45-AFE40D9737EB
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D HdaVerbTableLib
+
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32 X64
+#
+
+##########################################################################=
######
+#
+# Sources Section - list of files that are required for the build to succe=
ed.
+#
+##########################################################################=
######
+
+[Sources]
+ PeiHdaVerbTableLib.c
+ PchHdaVerbTables.c
+
+##########################################################################=
######
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+##########################################################################=
######
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ MemoryAllocationLib
+ PcdLib
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable ## C=
ONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2 ## C=
ONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable ## C=
ONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1 ## C=
ONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2 ## C=
ONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3 ## C=
ONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable ## C=
ONSUMES
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAccessLib/P=
eiI2cAccessLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAcces=
sLib/PeiI2cAccessLib.c
new file mode 100644
index 0000000000..ddb0ec4640
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAc=
cessLib.c
@@ -0,0 +1,115 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/I2cAccessLib.h>
+
+EFI_STATUS
+I2cWriteRead (
+ IN UINTN MmioBase,
+ IN UINT8 SlaveAddress,
+ IN UINT8 WriteLength,
+ IN UINT8 *WriteBuffer,
+ IN UINT8 ReadLength,
+ IN UINT8 *ReadBuffer,
+ IN UINT64 TimeBudget
+ //TODO: add Speed parameter
+ )
+{
+ UINT8 ReadsNeeded =3D ReadLength;
+ UINT64 CutOffTime;
+
+ if ((WriteLength =3D=3D 0 && ReadLength =3D=3D 0) ||
+ (WriteLength !=3D 0 && WriteBuffer =3D=3D NULL) ||
+ (ReadLength !=3D 0 && ReadBuffer =3D=3D NULL) ) {
+ DEBUG ((DEBUG_ERROR, "I2cWR Invalid Parameters\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Sanity checks to verify the I2C controller is alive
+ // Conveniently, ICON register's values of 0 or FFFFFFFF indicate
+ // I2c controller is out-of-order: either disabled, in D3 or in reset.
+ //
+ if (MmioRead32(MmioBase+R_IC_CON) =3D=3D 0xFFFFFFFF || MmioRead32(MmioBa=
se+R_IC_CON) =3D=3D 0x0) {
+ DEBUG ((DEBUG_ERROR, "I2cWR Device Error\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ MmioWrite32(MmioBase+R_IC_ENABLE, 0x0);
+ MmioRead32(MmioBase+0x40);
+ MmioRead32(MmioBase+R_IC_CLR_TX_ABRT);
+ MmioWrite32(MmioBase+R_IC_SDA_HOLD, 0x001C001C);
+ //
+ // Set I2C Bus Speed at 400 kHz for GPIO Expander
+ //
+ MmioWrite32(MmioBase + R_IC_FS_SCL_HCNT, 128);
+ MmioWrite32(MmioBase + R_IC_FS_SCL_LCNT, 160);
+ MmioWrite32(MmioBase + R_IC_TAR, SlaveAddress);
+ MmioWrite32(MmioBase + R_IC_CON, B_IC_MASTER_MODE | V_IC_SPEED_FAST | B_=
IC_RESTART_EN | B_IC_SLAVE_DISABLE );
+ MmioWrite32(MmioBase+R_IC_ENABLE, 0x1);
+ CutOffTime =3D AsmReadTsc() + TimeBudget;
+
+ while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D0 ) {
+ if (AsmReadTsc() > CutOffTime) {
+ DEBUG ((DEBUG_ERROR, "I2cWR timeout\n"));
+ return EFI_TIMEOUT;
+ }
+ }
+
+ while(1) {
+ if(MmioRead32(MmioBase+R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT) {
+ DEBUG ((DEBUG_ERROR, "I2cWR Transfer aborted, reason =3D 0x%08x\n",M=
mioRead32(MmioBase+R_IC_TX_ABRT_SOURCE)));
+ MmioRead32(MmioBase+R_IC_CLR_TX_ABRT);
+ MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+ while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {}
+ return EFI_DEVICE_ERROR;
+ }
+ if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_TFNF) {
+ if (WriteLength > 1) {
+ MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer);
+ WriteBuffer++;
+ WriteLength--;
+ } else if (WriteLength=3D=3D1 && ReadLength !=3D 0) {
+ MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer);
+ WriteBuffer++;
+ WriteLength--;
+ } else if (WriteLength=3D=3D1 && ReadLength =3D=3D 0) {
+ MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer | B_IC_CMD_STOP);
+ WriteBuffer++;
+ WriteLength--;
+ } else if (ReadLength > 1) {
+ MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ);
+ ReadLength--;
+ } else if (ReadLength =3D=3D 1) {
+ MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ|B_IC_CMD_STOP);
+ ReadLength--;
+ }
+ }
+
+ if (ReadsNeeded) {
+ if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_RFNE) {
+ *ReadBuffer =3D (UINT8)MmioRead32(MmioBase+R_IC_DATA_CMD);
+ ReadBuffer++;
+ ReadsNeeded--;
+ }
+ }
+ if (WriteLength=3D=3D0 && ReadsNeeded=3D=3D0 && !(MmioRead32(MmioBase+=
R_IC_STATUS)&B_IC_STATUS_ACTIVITY)) {
+ MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+ while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {}
+ DEBUG ((DEBUG_INFO, "I2cWR success\n"));
+ return EFI_SUCCESS;
+ }
+ if (AsmReadTsc() > CutOffTime) {
+ MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+ while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {}
+ DEBUG ((DEBUG_ERROR, "I2cWR wrong ENST value\n"));
+ return EFI_TIMEOUT;
+ }
+
+ }
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAccessLib/P=
eiI2cAccessLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAcc=
essLib/PeiI2cAccessLib.inf
new file mode 100644
index 0000000000..faff1ce378
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAc=
cessLib.inf
@@ -0,0 +1,39 @@
+## @file
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PeiI2cAccessLib
+ FILE_GUID =3D 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D BASE
+ LIBRARY_CLASS =3D PeiI2cAccessLib
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiI2cAccessLib.c
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyU=
pdateLib/DxeCpuPolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy=
/Library/DxePolicyUpdateLib/DxeCpuPolicyUpdate.c
new file mode 100644
index 0000000000..5a6c4d322f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi=
b/DxeCpuPolicyUpdate.c
@@ -0,0 +1,88 @@
+/** @file
+ This file is the library for CPU DXE Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DxeCpuPolicyUpdateLib.h>
+
+/**
+ This function prints the CPU DXE phase policy.
+
+ @param[in] DxeCpuPolicy - CPU DXE Policy protocol
+**/
+VOID
+CpuDxePrintPolicyProtocol (
+ IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ )
+{
+ DEBUG_CODE_BEGIN ();
+ DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print B=
EGIN -----------------\n"));
+ DEBUG ((DEBUG_INFO, "Revision : %x\n", DxeCpuPolicy->Revision));
+ ASSERT (DxeCpuPolicy->Revision =3D=3D DXE_CPU_POLICY_PROTOCOL_REVISION);
+ DEBUG ((DEBUG_INFO, "\n------------------------ CPU_DXE_CONFIG ---------=
--------\n"));
+ DEBUG ((DEBUG_INFO, "EnableDts : %x\n", DxeCpuPolicy->EnableDts));
+ DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print E=
ND -----------------\n"));
+ DEBUG_CODE_END ();
+}
+
+/**
+ Get data for CPU policy from setup options.
+
+ @param[in] DxeCpuPolicy The pointer to get CPU Policy proto=
col instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSiCpuPolicy (
+ IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ CpuInstallPolicyProtocol installs CPU Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please=
update and override
+ any setting before calling this function.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol=
instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b=
uffer
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Print CPU DXE Policy
+ ///
+ CpuDxePrintPolicyProtocol(DxeCpuPolicy);
+
+ ///
+ /// Install the DXE_CPU_POLICY_PROTOCOL interface
+ ///
+ Status =3D gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gDxeCpuPolicyProtocolGuid,
+ DxeCpuPolicy,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyU=
pdateLib/DxeMePolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/DxePolicyUpdateLib/DxeMePolicyUpdate.c
new file mode 100644
index 0000000000..aa5f7eef32
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi=
b/DxeMePolicyUpdate.c
@@ -0,0 +1,105 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "DxeMePolicyUpdate.h"
+
+//
+// Record version
+//
+#define RECORD_REVISION_1 0x01
+#define MAX_FW_UPDATE_BIOS_SELECTIONS 2
+
+//
+// Function implementations executed during policy initialization phase
+//
+
+/**
+ Update the ME Policy Library
+
+ @param[in, out] DxeMePolicy The pointer to get ME Policy proto=
col instance
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this=
driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to in=
itialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnorma=
lly.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeMePolicy (
+ IN OUT ME_POLICY_PROTOCOL *DxeMePolicy
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT EndOfDxeEvent;
+
+ DEBUG ((DEBUG_INFO, "UpdateDxeMePolicy\n"));
+ UpdateMePolicyFromSetup (DxeMePolicy);
+ UpdateMePolicyFromMeSetup (DxeMePolicy);
+
+ //
+ // Register End of DXE event
+ //
+ Status =3D gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ UpdateMeSetupCallback,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &EndOfDxeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
+/**
+ Update ME Policy while MePlatformProtocol is installed.
+
+ @param[in] MePolicyInstance Instance of ME Policy Protocol
+
+**/
+VOID
+UpdateMePolicyFromMeSetup (
+ IN ME_POLICY_PROTOCOL *MePolicyInstance
+ )
+{
+
+}
+
+/**
+ Update ME Policy if Setup variable exists.
+
+ @param[in, out] MePolicyInstance Instance of ME Policy Protocol
+
+**/
+VOID
+UpdateMePolicyFromSetup (
+ IN OUT ME_POLICY_PROTOCOL *MePolicyInstance
+ )
+{
+
+}
+
+/**
+ Functions performs HECI exchange with FW to update MePolicy settings.
+
+ @param[in] Event A pointer to the Event that triggered the callb=
ack.
+ @param[in] Context A pointer to private data registered with the c=
allback function.
+
+**/
+VOID
+EFIAPI
+UpdateMeSetupCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ gBS->CloseEvent (Event);
+
+ return;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyU=
pdateLib/DxeMePolicyUpdate.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/DxePolicyUpdateLib/DxeMePolicyUpdate.h
new file mode 100644
index 0000000000..8637c9b43e
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi=
b/DxeMePolicyUpdate.h
@@ -0,0 +1,90 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_ME_POLICY_UPDATE_H_
+#define _DXE_ME_POLICY_UPDATE_H_
+
+#include <PiDxe.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Guid/EventGroup.h>
+#include <IndustryStandard/Acpi10.h>
+#include <Library/BaseMemoryLib.h>
+#include <Protocol/MePolicy.h>
+#include <Library/HobLib.h>
+#include <ConfigBlock/MePeiConfig.h>
+
+#define PLATFORM_BOOT_TABLE_PTR_TYPE 0x1001
+#define PLATFORM_BOOT_RECORD_TYPE 0x1022
+//
+// Timeout values based on HPET
+//
+#define HECI_MSG_DELAY 2000000 ///< show warning msg and =
stay for 2 seconds.
+#define CONVERSION_MULTIPLIER 1000000 ///< msec to nanosec multi=
plier
+#define PLATFORM_BOOT_TABLE_SIGNATURE SIGNATURE_32 ('P', 'B', 'P', 'T')
+
+//
+// Platform Boot Performance Table Record
+//
+
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT64 TimestampDelta1;
+ UINT64 TimestampDelta2;
+ UINT64 TimestampDelta3;
+} PLATFORM_BOOT_TABLE_RECORD;
+
+//
+// Platform boot Performance Table
+//
+
+typedef struct {
+ EFI_ACPI_COMMON_HEADER Header;
+ PLATFORM_BOOT_TABLE_RECORD PlatformBoot;
+} PLATFORM_BOOT_PERFORMANCE_TABLE;
+
+/**
+ Update ME Policy while MePlatformProtocol is installed.
+
+ @param[in] MePolicyInstance Instance of ME Policy Protocol
+
+**/
+VOID
+UpdateMePolicyFromMeSetup (
+ IN ME_POLICY_PROTOCOL *MePolicyInstance
+ );
+
+/**
+ Update ME Policy if Setup variable exists.
+
+ @param[in, out] MePolicyInstance Instance of ME Policy Protocol
+
+**/
+VOID
+UpdateMePolicyFromSetup (
+ IN OUT ME_POLICY_PROTOCOL *MePolicyInstance
+ );
+
+/**
+ Functions performs HECI exchange with FW to update MePolicy settings.
+
+ @param[in] Event A pointer to the Event that triggered the callb=
ack.
+ @param[in] Context A pointer to private data registered with the c=
allback function.
+
+**/
+VOID
+EFIAPI
+UpdateMeSetupCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyU=
pdateLib/DxePchPolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy=
/Library/DxePolicyUpdateLib/DxePchPolicyUpdate.c
new file mode 100644
index 0000000000..ca45c54162
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi=
b/DxePchPolicyUpdate.c
@@ -0,0 +1,40 @@
+/** @file
+ This file is the library for PCH DXE Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiDxe.h>
+#include <PchAccess.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/PchPolicy.h>
+#include <ConfigBlock/HdAudioConfig.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ Get data for PCH policy from setup options.
+
+ @param[in] PchPolicy The pointer to get PCH Policy proto=
col instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxePchPolicy (
+ IN OUT PCH_POLICY_PROTOCOL *PchPolicy
+ )
+{
+ EFI_STATUS Status;
+ PCH_HDAUDIO_DXE_CONFIG *HdAudioDxeConfig;
+
+ Status =3D GetConfigBlock ((VOID *)PchPolicy, &gHdAudioDxeConfigGuid, (V=
OID *)&HdAudioDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyU=
pdateLib/DxePolicyUpdateLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Poli=
cy/Library/DxePolicyUpdateLib/DxePolicyUpdateLib.inf
new file mode 100644
index 0000000000..71d1aa2dd2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi=
b/DxePolicyUpdateLib.inf
@@ -0,0 +1,59 @@
+## @file
+# Component description file for DXE DxePolicyUpdateLib Library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D DxePolicyUpdateLib
+ FILE_GUID =3D 690B3786-D215-4ABB-9EF2-7A80128560E0
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D DxePolicyUpdateLib|DXE_DRIVER
+
+#
+# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC
+#
+
+[Sources]
+ DxeMePolicyUpdate.c
+ DxeSaPolicyUpdate.c
+ DxePchPolicyUpdate.c
+ DxeCpuPolicyUpdate.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseLib
+ BaseMemoryLib
+ PcdLib
+ DebugLib
+ IoLib
+ CpuPlatformLib
+ HobLib
+ ConfigBlockLib
+ PciSegmentLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+[Guids]
+ gEfiGlobalVariableGuid ## CONSUMES
+ gEfiEndOfDxeEventGroupGuid ## CONSUMES
+ gMeInfoSetupGuid ## PRODUCES
+ gMePolicyHobGuid ## CONSUMES
+ gCpuSetupVariableGuid ## CONSUMES
+ gPchSetupVariableGuid ## CONSUMES
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyU=
pdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.c
new file mode 100644
index 0000000000..caac2c8bde
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi=
b/DxeSaPolicyUpdate.c
@@ -0,0 +1,58 @@
+/** @file
+ This file is the library for SA DXE Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <DxeSaPolicyUpdate.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ Get data for platform policy from setup options.
+
+ @param[in] SaPolicy The pointer to get SA Policy protoc=
ol instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicy (
+ IN OUT SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+ PCIE_DXE_CONFIG *PcieDxeConfig;
+ MISC_DXE_CONFIG *MiscDxeConfig;
+ MEMORY_DXE_CONFIG *MemoryDxeConfig;
+
+ GraphicsDxeConfig =3D NULL;
+ PcieDxeConfig =3D NULL;
+ MiscDxeConfig =3D NULL;
+ MemoryDxeConfig =3D NULL;
+ //
+ // Get requisite IP Config Blocks which needs to be used here
+ //
+ Status =3D GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, (V=
OID *)&GraphicsDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID =
*)&MiscDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOID =
*)&PcieDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMemoryDxeConfigGuid, (VOI=
D *)&MemoryDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ PcieDxeConfig->PegAspmL0s[0] =3D 3;
+ PcieDxeConfig->PegAspmL0s[1] =3D 3;
+ PcieDxeConfig->PegAspmL0s[2] =3D 3;
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyU=
pdateLib/DxeSaPolicyUpdate.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.h
new file mode 100644
index 0000000000..0f38899284
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi=
b/DxeSaPolicyUpdate.h
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_SA_POLICY_UPDATE_H_
+#define _DXE_SA_POLICY_UPDATE_H_
+
+#include <PiDxe.h>
+#include <CpuRegs.h>
+#include <PchAccess.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/SaPolicy.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiCpuPolicyInit.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Lib=
rary/PeiPolicyInitLib/PeiCpuPolicyInit.h
new file mode 100644
index 0000000000..bf5d9108a3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiCpuPolicyInit.h
@@ -0,0 +1,37 @@
+/** @file
+ Header file for the PeiCpuPolicyInit.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_CPU_POLICY_INIT_H_
+#define _PEI_CPU_POLICY_INIT_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/CpuPolicyLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <FirwmareConfigurations.h>
+
+/**
+ This function performs CPU PEI Policy initialization in PreMem.
+
+ @param[in, out] SiPreMemPolicyPpi The Si Pre-Mem Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali=
ze the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiMePolicyInit.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Libr=
ary/PeiPolicyInitLib/PeiMePolicyInit.h
new file mode 100644
index 0000000000..00d2b02462
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiMePolicyInit.h
@@ -0,0 +1,23 @@
+/** @file
+ Header file for the PeiMePolicyInit
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_ME_POLICY_INIT_H_
+#define _PEI_ME_POLICY_INIT_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiMePolicyLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <FirwmareConfigurations.h>
+
+#endif // _PEI_ME_POLICY_INIT_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiPolicyInit.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Librar=
y/PeiPolicyInitLib/PeiPolicyInit.c
new file mode 100644
index 0000000000..4810a1a113
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiPolicyInit.c
@@ -0,0 +1,65 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyInit.h"
+
+/**
+ Initialize Intel PEI Platform Policy
+
+ @param[in] PeiServices General purpose services available to =
every PEIM.
+ @param[in] FirmwareConfiguration It uses to skip specific policy init t=
hat depends
+ on the 'FirmwareConfiguration' varaibl=
e.
+**/
+VOID
+EFIAPI
+PeiPolicyInit (
+ IN UINT8 FirmwareConfiguration
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+
+ //
+ // Call SiCreateConfigBlocks to initialize Silicon Policy structure
+ // and get all Intel default policy settings.
+ //
+ Status =3D SiCreateConfigBlocks (&SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR(Status)) {
+ return;
+ }
+
+ if (PcdGetBool (PcdDumpDefaultSiliconPolicy)) {
+ DEBUG ((DEBUG_INFO, "Dump Default Silicon Policy...\n"));
+ DumpSiPolicy (SiPolicyPpi);
+ }
+
+ //
+ // Update policy by board configuration
+ //
+ UpdatePeiSiPolicyBoardConfig (SiPolicyPpi);
+ UpdatePeiPchPolicyBoardConfig (SiPolicyPpi);
+ UpdatePeiSaPolicyBoardConfig (SiPolicyPpi);
+ UpdatePeiCpuPolicyBoardConfig (SiPolicyPpi);
+ UpdatePeiMePolicyBoardConfig (SiPolicyPpi);
+
+ UpdatePeiSiPolicy(SiPolicyPpi);
+ UpdatePeiPchPolicy(SiPolicyPpi);
+ UpdatePeiSaPolicy(SiPolicyPpi);
+ UpdatePeiCpuPolicy(SiPolicyPpi);
+ UpdatePeiMePolicy(SiPolicyPpi);
+
+ //
+ // Install SiPolicyPpi.
+ // While installed, RC assumes the Policy is ready and finalized. So ple=
ase
+ // update and override any setting before calling this function.
+ //
+ Status =3D SiInstallPolicyPpi (SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiPolicyInit.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Librar=
y/PeiPolicyInitLib/PeiPolicyInit.h
new file mode 100644
index 0000000000..586f51ca33
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiPolicyInit.h
@@ -0,0 +1,23 @@
+/** @file
+ Header file for the PolicyInitPei PEIM.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_POLICY_INIT_H_
+#define _PEI_POLICY_INIT_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include "PeiCpuPolicyInit.h"
+#include "PeiMePolicyInit.h"
+#include "PeiSaPolicyInit.h"
+#include "PeiSiPolicyInit.h"
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiPolicyInitLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Policy/L=
ibrary/PeiPolicyInitLib/PeiPolicyInitLib.inf
new file mode 100644
index 0000000000..a9f9e19610
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiPolicyInitLib.inf
@@ -0,0 +1,62 @@
+## @file
+# Component description file for PeiPolicyInit library.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PeiPolicyInitLib
+ FILE_GUID =3D B494DF39-A5F8-48A1-B2D0-EF523AD91C55
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D PEIM
+ LIBRARY_CLASS =3D PeiPolicyInitLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ BaseLib
+ CpuPlatformLib
+ DebugLib
+ DebugPrintErrorLevelLib
+ HobLib
+ IoLib
+ MemoryAllocationLib
+ PeiServicesLib
+ PeiPolicyBoardConfigLib
+ PeiPolicyUpdateLib
+ PostCodeLib
+ SmbusLib
+ ConfigBlockLib
+ SiPolicyLib
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy ## CONSUMES
+
+
+[Sources]
+ PeiPolicyInitPreMem.c
+ PeiPolicyInit.c
+ PeiPolicyInit.h
+ PeiCpuPolicyInit.h
+ PeiMePolicyInit.h
+ PeiSaPolicyInit.c
+ PeiSaPolicyInit.h
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gSiPolicyPpiGuid ## CONSUMES
+ gSiPreMemPolicyPpiGuid ## CONSUMES
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiPolicyInitPreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/PeiPolicyInitLib/PeiPolicyInitPreMem.c
new file mode 100644
index 0000000000..3f81d7efc8
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiPolicyInitPreMem.c
@@ -0,0 +1,60 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyInit.h"
+
+/**
+ Initialize Intel PEI Platform Policy
+
+ @param[in] FirmwareConfiguration It uses to skip specific policy init =
that depends
+ on the 'FirmwareConfiguration' varaib=
le.
+**/
+VOID
+EFIAPI
+PeiPolicyInitPreMem (
+ IN UINT8 FirmwareConfiguration
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+
+ DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memo=
ry...\n"));
+ //
+ // Call SiCreatePreMemConfigBlocks to initialize platform policy structu=
re
+ // and get all intel default policy settings.
+ //
+ Status =3D SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update policy by board configuration
+ //
+ UpdatePeiPchPolicyBoardConfigPreMem (SiPreMemPolicyPpi);
+ UpdatePeiMePolicyBoardConfigPreMem (SiPreMemPolicyPpi);
+ UpdatePeiSaPolicyBoardConfigPreMem (SiPreMemPolicyPpi);
+ UpdatePeiCpuPolicyBoardConfigPreMem (SiPreMemPolicyPpi);
+
+ //
+ // Update and override all platform related and customized settings belo=
w.
+ //
+ UpdatePeiPchPolicyPreMem (SiPreMemPolicyPpi);
+ UpdatePeiMePolicyPreMem (SiPreMemPolicyPpi);
+ UpdatePeiSaPolicyPreMem (SiPreMemPolicyPpi);
+ UpdatePeiCpuPolicyPreMem (SiPreMemPolicyPpi);
+
+ //
+ // Install SiPreMemPolicyPpi.
+ // While installed, RC assumes the Policy is ready and finalized. So ple=
ase
+ // update and override any setting before calling this function.
+ //
+ Status =3D SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memor=
y\n"));
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiSaPolicyInit.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Libr=
ary/PeiPolicyInitLib/PeiSaPolicyInit.c
new file mode 100644
index 0000000000..1c7d14b61b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiSaPolicyInit.c
@@ -0,0 +1,114 @@
+/** @file
+ This file is SampleCode for Intel SA PEI Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyInit.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ PcieCardResetWorkAround performs PCIe Card reset on root port
+
+ @param[in out] SiPreMemPolicyPpi SI_PREMEM_POLICY_PPI
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+ PcieCardResetWorkAround (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ SWITCHABLE_GRAPHICS_CONFIG *SgGpioData;
+
+ Status =3D GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSaMiscPeiPreMemCo=
nfigGuid, (VOID *)&MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSwitchableGraphic=
sConfigGuid, (VOID *)&SgGpioData);
+ ASSERT_EFI_ERROR(Status);
+
+ if (SgGpioData->SaRtd3Pcie0Gpio.GpioSupport !=3D NotSupported) {
+ ///
+ /// dGPU is present.
+ /// If PCIe Mode or SG Muxless
+ /// Power on MXM
+ /// Configure GPIOs to drive MXM in PCIe mode or SG Muxle=
ss
+ /// else
+ /// Do Nothing
+ ///
+ if ((MiscPeiPreMemConfig->SgMode =3D=3D SgModeMuxless) ||
+ (MiscPeiPreMemConfig->SgMode =3D=3D SgModeDgpu)) {
+ DEBUG((DEBUG_INFO, "Configure GPIOs for driving the dGPU.\n"));
+ ///
+ /// Drive DGPU HOLD RST Enable to make sure we hold reset
+ ///
+ PcieGpioWrite (
+ SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo,
+ SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active,
+ GP_ENABLE
+ );
+ ///
+ /// wait 100ms
+ ///
+ MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STAL=
L_ONE_MILLI_SECOND);
+
+ ///
+ /// Drive DGPU PWR EN to Power On MXM
+ ///
+ PcieGpioWrite (
+ SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.GpioNo,
+ SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.Active,
+ GP_ENABLE
+ );
+ ///
+ /// wait 300ms
+ ///
+ MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterPwrEn) * STALL_ON=
E_MILLI_SECOND);
+
+ ///
+ /// Drive DGPU HOLD RST Disabled to remove reset
+ ///
+ PcieGpioWrite (
+ SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo,
+ SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active,
+ GP_DISABLE
+ );
+ ///
+ /// wait 100ms
+ ///
+ MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STAL=
L_ONE_MILLI_SECOND);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ PCIe GPIO Write
+
+ @param[in] Gpio - GPIO Number
+ @param[in] Active - GPIO Active Information; High/Low
+ @param[in] Level - Write GPIO value (0/1)
+
+**/
+VOID
+PcieGpioWrite (
+ IN UINT32 Gpio,
+ IN BOOLEAN Active,
+ IN BOOLEAN Level
+ )
+{
+ EFI_STATUS Status;
+
+ if (Active =3D=3D 0) {
+ Level =3D (~Level) & 0x1;
+ }
+ Status =3D GpioSetOutputValue(Gpio, (UINT32)Level);
+ if (Status !=3D EFI_SUCCESS) {
+ return;
+ }
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiSaPolicyInit.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Libr=
ary/PeiPolicyInitLib/PeiSaPolicyInit.h
new file mode 100644
index 0000000000..6d58c3d51f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiSaPolicyInit.h
@@ -0,0 +1,58 @@
+/** @file
+ Header file for the SaPolicyInitPei PEIM.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SA_POLICY_INIT_PEI_H_
+#define _SA_POLICY_INIT_PEI_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Ppi/SiPolicy.h>
+#include <SaPolicyCommon.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <FirwmareConfigurations.h>
+#include <Library/TimerLib.h>
+#include <Library/GpioLib.h>
+
+//
+// Functions
+//
+/**
+PCIe GPIO Write
+
+@param[in] Gpio - GPIO Number
+@param[in] Active - GPIO Active Information; High/Low
+@param[in] Level - Write GPIO value (0/1)
+
+**/
+VOID
+PcieGpioWrite(
+IN UINT32 Gpio,
+IN BOOLEAN Active,
+IN BOOLEAN Level
+);
+
+/**
+PcieCardResetWorkAround performs PCIe Card reset on root port
+
+@param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY_PPI
+
+@retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+PcieCardResetWorkAround(
+IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+);
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyI=
nitLib/PeiSiPolicyInit.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Libr=
ary/PeiPolicyInitLib/PeiSiPolicyInit.h
new file mode 100644
index 0000000000..f485f54b70
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/=
PeiSiPolicyInit.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for the PeiSiPolicyInit
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SI_POLICY_INIT_PEI_H_
+#define _SI_POLICY_INIT_PEI_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <FirwmareConfigurations.h>
+
+#endif // _SI_POLICY_INIT_PEI_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy=
/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
new file mode 100644
index 0000000000..b4f8bbb7d0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiCpuPolicyUpdate.c
@@ -0,0 +1,80 @@
+/** @file
+ CPU PEI Policy Update & initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/CpuPlatformLib.h>
+
+/**
+ This function performs CPU PEI Policy initialization.
+
+ @param[in] SiPolicyPpi The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initial=
ize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ CPU_CONFIG *CpuConfig;
+ CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig;
+ CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig;
+ CPU_TEST_CONFIG *CpuTestConfig;
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID =
*) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConf=
igGuid, (VOID *) &CpuPowerMgmtBasicConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuPowerMgmtCustomConfi=
gGuid, (VOID *)&CpuPowerMgmtCustomConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuTestConfigGuid, (VOI=
D *)&CpuTestConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuPowerMgmtTestConfigG=
uid, (VOID *)&CpuPowerMgmtTestConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Init Power Management Policy Variables
+ //
+ CpuPowerMgmtBasicConfig->HwpInterruptControl =3D 1;
+ CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio =3D 0x4;
+ CpuPowerMgmtBasicConfig->OneCoreRatioLimit =3D 0x22;
+ CpuPowerMgmtBasicConfig->TwoCoreRatioLimit =3D 0x22;
+ CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit =3D 0x22;
+ CpuPowerMgmtBasicConfig->FourCoreRatioLimit =3D 0x22;
+ CpuPowerMgmtBasicConfig->FiveCoreRatioLimit =3D 0;
+ CpuPowerMgmtBasicConfig->SixCoreRatioLimit =3D 0;
+ CpuPowerMgmtBasicConfig->SevenCoreRatioLimit =3D 0;
+ CpuPowerMgmtBasicConfig->EightCoreRatioLimit =3D 0;
+ CpuPowerMgmtBasicConfig->Hwp =3D 0x1;
+ CpuTestConfig->CpuWakeUpTimer =3D 1;
+ CpuPowerMgmtTestConfig->AutoThermalReporting =3D 0;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy=
/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
new file mode 100644
index 0000000000..4e2cd014de
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiCpuPolicyUpdate.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for PEI CpuPolicyUpdate.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_CPU_POLICY_UPDATE_H_
+#define _PEI_CPU_POLICY_UPDATE_H_
+
+#include <PiPei.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/Wdt.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiPlatformLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <PlatformBoardId.h>
+#include <PchAccess.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuAccess.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/PeiServicesLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/CpuPlatformLib.h>
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/=
Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..050df4fcd9
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiCpuPolicyUpdatePreMem.c
@@ -0,0 +1,108 @@
+/** @file
+ This file is SampleCode of the library for Intel CPU PEI Policy initiali=
zation.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/SpiLib.h>
+
+/**
+ Check on the processor if SGX is supported.
+
+ @retval True if SGX supported or FALSE if not
+**/
+BOOLEAN
+IsSgxCapSupported (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER CpuidRegs;
+
+ ///
+ /// Processor support SGX feature by reading CPUID.(EAX=3D7,ECX=3D0):EBX=
[2]
+ ///
+ AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, &CpuidRegs.RegEa=
x,&CpuidRegs.RegEbx,&CpuidRegs.RegEcx,&CpuidRegs.RegEdx);
+
+ ///
+ /// SGX feature is supported only on WHL and later,
+ /// with CPUID.(EAX=3D7,ECX=3D0):EBX[2]=3D1
+ /// PRMRR configuration enabled, MSR IA32_MTRRCAP (FEh) [12] =3D=3D 1
+ ///
+ if ((CpuidRegs.RegEbx & BIT2) && (AsmReadMsr64 (MSR_IA32_MTRRCAP) & BIT1=
2)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ This function performs CPU PEI Policy initialization in Pre-memory.
+
+ @param[in] SiPreMemPolicyPpi The SI Pre-Mem Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initial=
ize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+ CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig;
+ UINT32 PchSpiBar0;
+ UINT32 MaxLogicProcessors;
+
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre=
MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclocking=
PreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "UpdatePeiCpuPolicyPreMem Start\n"));
+
+ //
+ // Get current boot mode
+ //
+ Status =3D PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ SpiServiceInit ();
+
+ PchSpiBar0 =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SPI,
+ PCI_FUNCTION_NUMBER_PCH_SPI,
+ R_SPI_CFG_BAR0
+ ));
+ PchSpiBar0 &=3D ~(B_SPI_CFG_BAR0_MASK);
+
+ if (PchSpiBar0 =3D=3D 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n"));
+ ASSERT (FALSE);
+ }
+
+ CpuConfigLibPreMemConfig->PeciC10Reset =3D 0;
+ CpuConfigLibPreMemConfig->CpuRatio =3D 0;
+ ///
+ /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical process=
ors enabled
+ /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads
+ ///
+ MaxLogicProcessors =3D (UINT32) (AsmReadMsr64 (MSR_CORE_THREAD_COUNT) & =
B_THREAD_COUNT_MASK);
+ DEBUG ((DEBUG_INFO, "MaxLogicProcessors =3D %d\n", MaxLogicProcessors));
+ PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiMePolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c
new file mode 100644
index 0000000000..e5e628ed02
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiMePolicyUpdate.c
@@ -0,0 +1,49 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiMePolicyUpdate.h"
+#include <ConfigBlock/MePeiConfig.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PmcLib.h>
+
+/**
+ Update the ME Policy Library
+
+ @param[in, out] SiPolicyPpi The pointer to SiPolicyPpi
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+UpdatePeiMePolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ ME_PEI_CONFIG *MePeiConfig;
+
+ DEBUG ((DEBUG_INFO, "UpdatePeiMePolicy\n"));
+
+ Status =3D EFI_SUCCESS;
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI=
D *) &MePeiConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (!PmcIsRtcBatteryGood ()) {
+ //
+ // For non coin battery design, this can be skipped.
+ //
+ MePeiConfig->MeUnconfigOnRtcClear =3D 2;
+ }
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiMePolicyUpdate.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.h
new file mode 100644
index 0000000000..db91ab0b5a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiMePolicyUpdate.h
@@ -0,0 +1,14 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_ME_POLICY_UPDATE_H_
+#define _PEI_ME_POLICY_UPDATE_H_
+
+#include <Library/DebugLib.h>
+#include <Ppi/SiPolicy.h>
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiMePolicyUpdatePreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/P=
olicy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c
new file mode 100644
index 0000000000..81c1bda17f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiMePolicyUpdatePreMem.c
@@ -0,0 +1,32 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiMePolicyUpdate.h"
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ Update the ME Policy Library
+
+ @param[in] SiPreMemPolicyPpi The pointer to SiPreMemPolicyPpi
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+UpdatePeiMePolicyPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "UpdatePeiMePolicyPreMem\n"));
+
+ Status =3D EFI_SUCCESS;
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy=
/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..4a8ffa7226
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiPchPolicyUpdate.c
@@ -0,0 +1,518 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initiali=
zation.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/SataLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Ppi/Spi.h>
+#include <GpioConfig.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+#include <PlatformBoardConfig.h>
+#include <Library/CnviLib.h>
+#include <Register/PchRegsLpcCnl.h>
+#include <PcieDeviceOverrideTable.h>
+#include <Library/ConfigBlockLib.h>
+
+VOID
+UpdatePcieClockInfo (
+ PCH_PCIE_CONFIG *PcieRpConfig,
+ UINTN Index,
+ UINT64 Data
+ )
+{
+ PCD64_BLOB Pcd64;
+
+ Pcd64.Blob =3D Data;
+ DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Suppor=
ted %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupport=
ed));
+
+ PcieRpConfig->PcieClock[Index].Usage =3D (UINT8)Pcd64.PcieClock.ClockUsa=
ge;
+ if (Pcd64.PcieClock.ClkReqSupported) {
+ PcieRpConfig->PcieClock[Index].ClkReq =3D (UINT8)Index;
+ } else {
+ PcieRpConfig->PcieClock[Index].ClkReq =3D 0xFF;
+ }
+}
+
+/**
+ This is helper function for getting I2C Pads Internal Termination settin=
gs from Pcd
+
+ @param[in] Index I2C Controller Index
+**/
+UINT8
+GetSerialIoI2cPadsTerminationFromPcd (
+ IN UINT8 Index
+)
+{
+ switch (Index) {
+ case 0:
+ return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
+ case 1:
+ return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
+ case 2:
+ return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
+ case 3:
+ return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
+ case 4:
+ return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
+ case 5:
+ return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
+ default:
+ ASSERT (FALSE); // Invalid I2C Controller Index
+ }
+ return 0;
+}
+/**
+ This is a helper function for updating USB Policy according to Blob data
+
+ @param[in] UsbConfig Pointer to USB_CONFIG data buffer
+ @param[in] PortIndex USB Port index
+ @param[in] Data32 Blob containing USB2 Afe (PCD32_BLOB) data
+**/
+VOID
+UpdateUsb20AfePolicy (
+ IN USB_CONFIG *UsbConfig,
+ IN UINT8 PortIndex,
+ UINT32 Data32
+)
+{
+ PCD32_BLOB Pcd32;
+ Pcd32.Blob =3D Data32;
+
+ if (PortIndex < MAX_USB2_PORTS && Pcd32.Info.Petxiset !=3D 0) {
+ UsbConfig->PortUsb20[PortIndex].Afe.Petxiset =3D Pcd32.Info.Petxis=
et;
+ UsbConfig->PortUsb20[PortIndex].Afe.Txiset =3D Pcd32.Info.Txiset;
+ UsbConfig->PortUsb20[PortIndex].Afe.Predeemp =3D Pcd32.Info.Predee=
mp;
+ UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit =3D Pcd32.Info.Pehalf=
bit;
+ }
+}
+
+/**
+ This function updates USB Policy per port OC Pin number
+
+ @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
+ @param[in] PortIndex USB Port index
+ @param[in] Pin OverCurrent pin number
+**/
+VOID
+UpdateUsb20OverCurrentPolicy (
+ IN USB_CONFIG *UsbConfig,
+ IN UINT8 PortIndex,
+ UINT8 Pin
+)
+{
+ if (PortIndex < MAX_USB2_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin =
=3D=3D UsbOverCurrentPinSkip))) {
+ UsbConfig->PortUsb20[PortIndex].OverCurrentPin =3D Pin;
+ } else {
+ if (PortIndex >=3D MAX_USB2_PORTS) {
+ DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number=
%d is not a valid USB2 port number\n", PortIndex));
+ } else {
+ DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurr=
ent pin specified USB2 port %d\n", PortIndex));
+ }
+ }
+}
+
+/**
+ This function updates USB Policy per port OC Pin number
+
+ @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
+ @param[in] PortIndex USB Port index
+ @param[in] Pin OverCurrent pin number
+**/
+VOID
+UpdateUsb30OverCurrentPolicy (
+ IN USB_CONFIG *UsbConfig,
+ IN UINT8 PortIndex,
+ UINT8 Pin
+)
+{
+ if (PortIndex < MAX_USB3_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin =
=3D=3D UsbOverCurrentPinSkip))) {
+ UsbConfig->PortUsb30[PortIndex].OverCurrentPin =3D Pin;
+ } else {
+ if (PortIndex >=3D MAX_USB2_PORTS) {
+ DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number=
%d is not a valid USB3 port number\n", PortIndex));
+ } else {
+ DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurr=
ent pin specified USB3 port %d\n", PortIndex));
+ }
+ }
+}
+
+/**
+ This function performs PCH USB Platform Policy initialization
+
+ @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
+ @param[in] PchSetup Pointer to PCH_SETUP data buffer
+**/
+VOID
+UpdatePchUsbConfig (
+ IN USB_CONFIG *UsbConfig
+ )
+{
+ UINTN PortIndex;
+
+ UsbConfig->OverCurrentEnable =3D TRUE;
+
+ for (PortIndex =3D 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortI=
ndex++) {
+ UsbConfig->PortUsb20[PortIndex].Enable =3D TRUE;
+ }
+ for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex=
++) {
+ UsbConfig->PortUsb30[PortIndex].Enable =3D TRUE;
+ }
+
+ UsbConfig->XdciConfig.Enable =3D FALSE;
+
+
+ //
+ // USB2 AFE settings.
+ //
+ UpdateUsb20AfePolicy (UsbConfig, 0, PcdGet32 (PcdUsb20Port0Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 1, PcdGet32 (PcdUsb20Port1Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 2, PcdGet32 (PcdUsb20Port2Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 3, PcdGet32 (PcdUsb20Port3Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 4, PcdGet32 (PcdUsb20Port4Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 5, PcdGet32 (PcdUsb20Port5Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 6, PcdGet32 (PcdUsb20Port6Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 7, PcdGet32 (PcdUsb20Port7Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 8, PcdGet32 (PcdUsb20Port8Afe));
+ UpdateUsb20AfePolicy (UsbConfig, 9, PcdGet32 (PcdUsb20Port9Afe));
+ UpdateUsb20AfePolicy (UsbConfig,10, PcdGet32 (PcdUsb20Port10Afe));
+ UpdateUsb20AfePolicy (UsbConfig,11, PcdGet32 (PcdUsb20Port11Afe));
+ UpdateUsb20AfePolicy (UsbConfig,12, PcdGet32 (PcdUsb20Port12Afe));
+ UpdateUsb20AfePolicy (UsbConfig,13, PcdGet32 (PcdUsb20Port13Afe));
+ UpdateUsb20AfePolicy (UsbConfig,14, PcdGet32 (PcdUsb20Port14Afe));
+ UpdateUsb20AfePolicy (UsbConfig,15, PcdGet32 (PcdUsb20Port15Afe));
+
+ //
+ // Platform Board programming per the layout of each port.
+ //
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrent=
PinPort0));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrent=
PinPort1));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrent=
PinPort2));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrent=
PinPort3));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrent=
PinPort4));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrent=
PinPort5));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrent=
PinPort6));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrent=
PinPort7));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrent=
PinPort8));
+ UpdateUsb20OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrent=
PinPort9));
+ UpdateUsb20OverCurrentPolicy (UsbConfig,10, PcdGet8 (PcdUsb20OverCurrent=
PinPort10));
+ UpdateUsb20OverCurrentPolicy (UsbConfig,11, PcdGet8 (PcdUsb20OverCurrent=
PinPort11));
+ UpdateUsb20OverCurrentPolicy (UsbConfig,12, PcdGet8 (PcdUsb20OverCurrent=
PinPort12));
+ UpdateUsb20OverCurrentPolicy (UsbConfig,13, PcdGet8 (PcdUsb20OverCurrent=
PinPort13));
+ UpdateUsb20OverCurrentPolicy (UsbConfig,14, PcdGet8 (PcdUsb20OverCurrent=
PinPort14));
+ UpdateUsb20OverCurrentPolicy (UsbConfig,15, PcdGet8 (PcdUsb20OverCurrent=
PinPort15));
+
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrent=
PinPort0));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrent=
PinPort1));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrent=
PinPort2));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrent=
PinPort3));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrent=
PinPort4));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrent=
PinPort5));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrent=
PinPort6));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrent=
PinPort7));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrent=
PinPort8));
+ UpdateUsb30OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrent=
PinPort9));
+
+}
+
+/**
+ Return if input ImageGuid belongs to system FMP GUID list.
+
+ @param[in] ImageGuid A pointer to GUID
+
+ @retval TRUE ImageGuid is in the list of PcdSystemFmpCapsuleImageTypeId=
Guid
+ @retval FALSE ImageGuid is not in the list of PcdSystemFmpCapsuleImageTy=
peIdGuid
+**/
+BOOLEAN
+IsSystemFmpGuid (
+ IN GUID *ImageGuid
+ )
+{
+ GUID *Guid;
+ UINTN Count;
+ UINTN Index;
+
+ Guid =3D PcdGetPtr (PcdSystemFmpCapsuleImageTypeIdGuid);
+ Count =3D PcdGetSize (PcdSystemFmpCapsuleImageTypeIdGuid) / sizeof (GUID=
);
+
+ for (Index =3D 0; Index < Count; Index++, Guid++) {
+ if (CompareGuid (ImageGuid, Guid)) {
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali=
ze the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicy
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Index;
+ DMI_HW_WIDTH_CONTROL *DmiHaAWC;
+ PCH_GENERAL_CONFIG *PchGeneralConfig;
+ PCH_PCIE_CONFIG *PcieRpConfig;
+ PCH_SATA_CONFIG *SataConfig;
+ PCH_IOAPIC_CONFIG *IoApicConfig;
+ PCH_DMI_CONFIG *DmiConfig;
+ PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
+ PCH_HDAUDIO_CONFIG *HdAudioConfig;
+ PCH_INTERRUPT_CONFIG *InterruptConfig;
+ PCH_ISH_CONFIG *IshConfig;
+ PCH_LAN_CONFIG *LanConfig;
+ PCH_LOCK_DOWN_CONFIG *LockDownConfig;
+ PCH_PM_CONFIG *PmConfig;
+ PCH_SCS_CONFIG *ScsConfig;
+ PCH_SERIAL_IO_CONFIG *SerialIoConfig;
+ PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
+ PCH_THERMAL_CONFIG *ThermalConfig;
+ USB_CONFIG *UsbConfig;
+ PCH_ESPI_CONFIG *EspiConfig;
+ PCH_CNVI_CONFIG *CnviConfig;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (V=
OID *) &PchGeneralConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID =
*) &PcieRpConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *)=
&SataConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID =
*) &IoApicConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) =
&DmiConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGui=
d, (VOID *) &FlashProtectionConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID=
*) &HdAudioConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VO=
ID *) &InterruptConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) =
&IshConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) =
&LanConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOI=
D *) &LockDownConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &=
PmConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) =
&ScsConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOI=
D *) &SerialIoConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VO=
ID *) &SerialIrqConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID=
*) &ThermalConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) =
&UsbConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *)=
&EspiConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *)=
&CnviConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DmiConfig->PwrOptEnable =3D TRUE;
+ PmConfig->PchSlpS3MinAssert =3D 0;
+ PmConfig->PchSlpS4MinAssert =3D 0;
+ PmConfig->PchSlpSusMinAssert =3D 0;
+ PmConfig->PchSlpAMinAssert =3D 0;
+
+ SataConfig->ThermalThrottling.P1T3M =3D 3;
+ SataConfig->ThermalThrottling.P1T2M =3D 2;
+ SataConfig->ThermalThrottling.P1T1M =3D 1;
+ SataConfig->ThermalThrottling.P0T3M =3D 3;
+ SataConfig->ThermalThrottling.P0T2M =3D 2;
+ SataConfig->ThermalThrottling.P0T1M =3D 1;
+
+ UpdatePcieClockInfo (PcieRpConfig, 0, PcdGet64 (PcdPcieClock0));
+ UpdatePcieClockInfo (PcieRpConfig, 1, PcdGet64 (PcdPcieClock1));
+ UpdatePcieClockInfo (PcieRpConfig, 2, PcdGet64 (PcdPcieClock2));
+ UpdatePcieClockInfo (PcieRpConfig, 3, PcdGet64 (PcdPcieClock3));
+ UpdatePcieClockInfo (PcieRpConfig, 4, PcdGet64 (PcdPcieClock4));
+ UpdatePcieClockInfo (PcieRpConfig, 5, PcdGet64 (PcdPcieClock5));
+ UpdatePcieClockInfo (PcieRpConfig, 6, PcdGet64 (PcdPcieClock6));
+ UpdatePcieClockInfo (PcieRpConfig, 7, PcdGet64 (PcdPcieClock7));
+ UpdatePcieClockInfo (PcieRpConfig, 8, PcdGet64 (PcdPcieClock8));
+ UpdatePcieClockInfo (PcieRpConfig, 9, PcdGet64 (PcdPcieClock9));
+ UpdatePcieClockInfo (PcieRpConfig, 10, PcdGet64 (PcdPcieClock10));
+ UpdatePcieClockInfo (PcieRpConfig, 11, PcdGet64 (PcdPcieClock11));
+ UpdatePcieClockInfo (PcieRpConfig, 12, PcdGet64 (PcdPcieClock12));
+ UpdatePcieClockInfo (PcieRpConfig, 13, PcdGet64 (PcdPcieClock13));
+ UpdatePcieClockInfo (PcieRpConfig, 14, PcdGet64 (PcdPcieClock14));
+ UpdatePcieClockInfo (PcieRpConfig, 15, PcdGet64 (PcdPcieClock15));
+
+ PcieRpConfig->PcieDeviceOverrideTablePtr =3D (UINT32) mPcieDeviceTable;
+ PcieRpConfig->RootPort[0].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[1].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[2].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[3].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[4].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[5].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[6].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[7].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[8].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[9].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[10].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[11].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[12].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[13].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[14].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[15].ClkReqDetect =3D TRUE;
+ PcieRpConfig->RootPort[0].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[1].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[2].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[3].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[4].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[5].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[6].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[7].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[8].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[9].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[10].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[11].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[12].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[13].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[14].AdvancedErrorReporting =3D TRUE;
+ PcieRpConfig->RootPort[15].AdvancedErrorReporting =3D TRUE;
+
+ //
+ // Install HDA Link/iDisplay Codec Verb Table
+ //
+ AddPlatformVerbTables (
+ PchHdaCodecPlatformOnboard,
+ &(HdAudioConfig->VerbTableEntryNum),
+ &(HdAudioConfig->VerbTablePtr)
+ );
+
+ LockDownConfig->BiosLock =3D FALSE;
+ LockDownConfig->BiosInterface =3D FALSE;
+
+ //
+ // IOAPIC Config
+ //
+// IoApicConfig->IoApicEntry24_119 =3D PchSetup.PchIoApic24119Entries;
+ //
+ // To support SLP_S0, it's required to disable 8254 timer.
+ // Note that CSM may require this option to be disabled for correct oper=
ation.
+ // Once 8254 timer disabled, some legacy OPROM and legacy OS will fail w=
hile using 8254 timer.
+ // For some OS environment that it needs to set 8254CGE in late state it=
should
+ // set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in S=
MM later.
+ // This is also required during S3 resume.
+ //
+ // The Enable8254ClockGatingOnS3 is only applicable when Enable8254Clock=
Gating is disabled.
+ // If Enable8254ClockGating is enabled, RC will do 8254 CGE programming =
on S3 as well.
+ // else, RC will do the programming on S3 when Enable8254ClockGatingOnS3=
is enabled.
+ // This avoids the SMI requirement for the programming.
+ //
+ // If S0ix is not enabled, then disable 8254CGE for leagcy boot case.
+ //
+ IoApicConfig->Enable8254ClockGating =3D FALSE;
+ IoApicConfig->Enable8254ClockGatingOnS3 =3D FALSE;
+
+ //
+ // SerialIo Config
+ //
+ SerialIoConfig->DevMode[0] =3D 1;
+ SerialIoConfig->DevMode[1] =3D 1;
+ SerialIoConfig->DevMode[2] =3D 0;
+ SerialIoConfig->DevMode[3] =3D 0;
+ SerialIoConfig->DevMode[4] =3D 1;
+ SerialIoConfig->DevMode[5] =3D 0;
+ SerialIoConfig->DevMode[6] =3D 0;
+ SerialIoConfig->DevMode[7] =3D 0;
+ SerialIoConfig->DevMode[8] =3D 0;
+ SerialIoConfig->DevMode[9] =3D 0;
+ SerialIoConfig->DevMode[10] =3D 0;
+ SerialIoConfig->DevMode[11] =3D 3;
+
+ SerialIoConfig->Uart0PinMuxing =3D 1;
+ SerialIoConfig->SpiCsPolarity[0] =3D 1;
+ SerialIoConfig->SpiCsPolarity[1] =3D 0;
+ SerialIoConfig->SpiCsPolarity[2] =3D 0;
+
+ SerialIoConfig->UartHwFlowCtrl[0] =3D 1;
+ SerialIoConfig->UartHwFlowCtrl[1] =3D 1;
+ SerialIoConfig->UartHwFlowCtrl[2] =3D 1;
+ //
+ // I2C4 and I2C5 don't exist in SPT-H chipset
+ //
+ if (IsPchH ()) {
+ SerialIoConfig->DevMode[PchSerialIoIndexI2C4] =3D PchSerialIoDisabled;
+ SerialIoConfig->DevMode[PchSerialIoIndexI2C5] =3D PchSerialIoDisabled;
+ }
+
+ for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++=
) {
+ SerialIoConfig->I2cPadsTermination[Index] =3D GetSerialIoI2cPadsTermin=
ationFromPcd (Index);
+ }
+
+ PmConfig->SlpS0Override =3D 2; //PchSetup.SlpS0O=
verride;
+ PmConfig->SlpS0DisQForDebug =3D 3; //PchSetup.SlpS0=
DisQForDebug;
+ PmConfig->SlpS0Vm075VSupport =3D 1; // PcdGetBool(Pcd=
SlpS0Vm075VSupport);
+ PmConfig->CpuC10GatePinEnable =3D 1;
+
+ //
+ // Thermal Config
+ //
+ ThermalConfig->TsmicLock =3D TRUE;
+ ThermalConfig->PchHotEnable =3D PcdGetBool (PcdPchThermalHotEnabl=
e);
+
+ DmiHaAWC =3D &ThermalConfig->DmiHaAWC;
+ DmiHaAWC->TS3TW =3D 0;
+ DmiHaAWC->TS2TW =3D 1;
+ DmiHaAWC->TS1TW =3D 2;
+ DmiHaAWC->TS0TW =3D 3;
+ //
+ // Update Pch Usb Config
+ //
+ UpdatePchUsbConfig (
+ UsbConfig
+ );
+
+ ScsConfig->ScsUfsEnabled =3D 0;
+ ScsConfig->ScsEmmcHs400Enabled =3D 1;
+ ScsConfig->ScsEmmcHs400TuningRequired =3D TRUE;
+
+ IshConfig->I2c0GpioAssign =3D 1;
+ IshConfig->I2c1GpioAssign =3D 1;
+ IshConfig->Gp0GpioAssign =3D 1;
+ IshConfig->Gp1GpioAssign =3D 1;
+ IshConfig->Gp2GpioAssign =3D 1;
+ IshConfig->Gp3GpioAssign =3D 1;
+ IshConfig->Gp4GpioAssign =3D 1;
+ IshConfig->Gp5GpioAssign =3D 1;
+ IshConfig->Gp6GpioAssign =3D 1;
+
+ return Status;
+}
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy=
/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
new file mode 100644
index 0000000000..5492cfc7d6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiPchPolicyUpdate.h
@@ -0,0 +1,24 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real E=
DKII
+// environment
+//
+#include <PiPei.h>
+#include <PlatformBoardId.h>
+#include <Library/PeiPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PlatformBoardConfig.h>
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/=
Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..ac6da0293c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,114 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initiali=
zation.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/SataLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchPolicyLib.h>
+#include <Library/ConfigBlockLib.h>
+
+//
+// Sawtooth Peak
+// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
+//
+#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
+#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D {
+ DIMM_SMB_SPD_P0C0D0_STP,
+ DIMM_SMB_SPD_P0C0D1_STP,
+ DIMM_SMB_SPD_P0C1D0_STP,
+ DIMM_SMB_SPD_P0C1D1_STP
+};
+
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @param[in, out] SiPreMemPolicy The SI PREMEM Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali=
ze the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
+ )
+{
+ EFI_STATUS Status;
+ UINT8 *SmBusReservedTable;
+ UINT8 SmBusReservedNum;
+
+ PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
+ PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig;
+ PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig;
+ PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig;
+ PCH_WDT_PREMEM_CONFIG *WatchDogPreMemConfig;
+ PCH_DCI_PREMEM_CONFIG *DciPreMemConfig;
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
+ PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig;
+ PCH_ISH_PREMEM_CONFIG *IshPreMemConfig;
+
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemCo=
nfigGuid, (VOID *) &PchGeneralPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemC=
onfigGuid, (VOID *) &PchTraceHubPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigG=
uid, (VOID *) &SmbusPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGui=
d, (VOID *) &LpcPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConf=
igGuid, (VOID *) &WatchDogPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGui=
d, (VOID *) &DciPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfig=
Guid, (VOID *) &PcieRpPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfi=
gGuid, (VOID *) &HdaPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGui=
d, (VOID *) &IshPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ DciPreMemConfig->DciUsb3TypecUfpDbg =3D 2;
+ PchTraceHubPreMemConfig->MemReg0Size =3D 3;
+ PchTraceHubPreMemConfig->MemReg1Size =3D 3;
+ //
+ // SMBUS
+ //
+ SmbusPreMemConfig->Enable =3D TRUE;
+ SmbusPreMemConfig->SmbAlertEnable =3D PcdGetBool (PcdSmbusAlertEnable);
+ //
+ // SMBUS reserved addresses
+ //
+ SmBusReservedTable =3D NULL;
+ SmBusReservedNum =3D 0;
+ SmbusPreMemConfig->SmbusIoBase =3D PcdGet16 (PcdSmbusBaseAddress);
+ SmBusReservedTable =3D mSmbusSTPRsvdAddresses;
+ SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses);
+
+ if (SmBusReservedTable !=3D NULL) {
+ SmbusPreMemConfig->NumRsvdSmbusAddresses =3D SmBusReservedNum;
+ CopyMem (
+ SmbusPreMemConfig->RsvdSmbusAddressTable,
+ SmBusReservedTable,
+ SmBusReservedNum
+ );
+ }
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/Poli=
cy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
new file mode 100644
index 0000000000..014967c7f6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiPolicyUpdateLib.inf
@@ -0,0 +1,273 @@
+## @file
+# Module Information file for PEI PolicyUpdateLib Library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PeiPolicyUpdateLib
+ FILE_GUID =3D 6EA9585C-3C15-47DA-9FFC-25E9E4EA4D0C
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D PEIM
+ LIBRARY_CLASS =3D PeiPolicyUpdateLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+ HobLib
+ BaseCryptLib
+ CpuPlatformLib
+ IoLib
+ PeiSaPolicyLib
+ ConfigBlockLib
+ PchGbeLib
+ PchInfoLib
+ PchPcieRpLib
+ HdaVerbTableLib
+ MemoryAllocationLib
+ PeiServicesTablePointerLib
+ PcdLib
+ Tpm2CommandLib
+ Tpm12CommandLib
+ Tpm2DeviceLib
+ Tpm12DeviceLib
+ PmcLib
+ SataLib
+ PchInfoLib
+ PciSegmentLib
+ SiPolicyLib
+ PeiServicesLib
+ SpiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize ## CONSUMES
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES
+
+ # SA Misc Config
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize #=
# CONSUMES
+
+ # Display DDI
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize #=
# CONSUMES
+
+ # PEG Reset By GPIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive #=
# CONSUMES
+
+ # PCIE RTD3 GPIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex #=
# CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive #=
# CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive #=
# CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive #=
# CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive #=
# CONSUMES
+
+ # SPD Address Table
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 #=
# CONSUMES
+
+ # CA Vref Configuration
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent #=
# CONSUMES
+
+ # PCIe Clock Info
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15 #=
# CONSUMES
+
+ # USB 2.0 Port AFE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe #=
# CONSUMES
+
+ # USB 2.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 #=
# CONSUMES
+
+ # USB 3.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 #=
# CONSUMES
+
+ # Pch SerialIo I2c Pads Termination
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm #=
# CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid =
## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEn=
able ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEn=
able ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid ## C=
ONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## C=
ONSUMES
+
+[FixedPcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CO=
NSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CO=
NSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CO=
NSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CO=
NSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CO=
NSUMES
+
+[Sources]
+ PeiPchPolicyUpdatePreMem.c
+ PeiPchPolicyUpdate.c
+ PeiCpuPolicyUpdatePreMem.c
+ PeiCpuPolicyUpdate.c
+ PeiMePolicyUpdatePreMem.c
+ PeiMePolicyUpdate.c
+ PeiSaPolicyUpdate.c
+ PeiSaPolicyUpdatePreMem.c
+ PeiSiPolicyUpdate.c
+
+[Ppis]
+ gWdtPpiGuid ## CONSUMES
+ gPchSpiPpiGuid ## CONSUMES
+ gSiPolicyPpiGuid ## CONSUMES
+ gSiPreMemPolicyPpiGuid ## CONSUMES
+ gPeiTbtPolicyPpiGuid ## CONSUMES
+
+[Guids]
+ gTianoLogoGuid ## CONSUMES
+ gSiConfigGuid ## CONSUMES
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..fc9debbe38
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiSaPolicyUpdate.c
@@ -0,0 +1,243 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Protocol/GraphicsOutput.h>
+#include <IndustryStandard/Bmp.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/HobLib.h>
+#include <Platform.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ UpdatePeiSaPolicy performs SA PEI Policy initialization
+
+ @param[in out] SiPolicyPpi - SI_POLICY PPI
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+UpdatePeiSaPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ EFI_GUID FileGuid;
+ VOID *Buffer;
+ UINT8 SaDisplayConfigTable[9] =3D {0};
+ VOID *MemBuffer;
+ BMP_IMAGE_HEADER *BmpHeader;
+ UINT64 BltBufferSize;
+ UINT32 Size;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ GNA_CONFIG *GnaConfig;
+ WDT_PPI *gWdtPei;
+ PCIE_PEI_CONFIG *PciePeiConfig;
+ SA_MISC_PEI_CONFIG *MiscPeiConfig;
+ EFI_BOOT_MODE BootMode;
+
+ DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+
+ Size =3D 0;
+ MemBuffer =3D NULL;
+ BmpHeader =3D NULL;
+ BltBufferSize =3D 0;
+ GtConfig =3D NULL;
+ GnaConfig =3D NULL;
+
+ Status =3D GetConfigBlock((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid,=
(VOID *)&GtConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOID *=
)&GnaConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid, =
(VOID *)&PciePeiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid, =
(VOID *)&MiscPeiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+
+ //
+ // Locate WDT_PPI (ICC WDT PPI)
+ //
+ gWdtPei =3D NULL;
+ Status =3D PeiServicesLocatePpi(
+ &gWdtPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &gWdtPei
+ );
+
+ Status =3D PeiServicesGetBootMode(&BootMode);
+ ASSERT_EFI_ERROR(Status);
+
+ if (!EFI_ERROR (Status)) {
+ Buffer =3D NULL;
+
+ CopyMem(&FileGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(File=
Guid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer =3D=3D NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ }
+
+ MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+ if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {
+ CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+ GtConfig->GraphicsConfigPtr =3D MemBuffer;
+ } else {
+ DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
+ GtConfig->GraphicsConfigPtr =3D NULL;
+ }
+
+ GtConfig->PeiGraphicsPeimInit =3D 1;
+
+ DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", G=
tConfig->GraphicsConfigPtr));
+ DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size=
));
+
+ PeiGetSectionFromFv (gTianoLogoGuid, &Buffer, &Size);
+ if (Buffer =3D=3D NULL) {
+ DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
+ }
+
+ MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+ if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {
+ CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+ GtConfig->LogoPtr =3D MemBuffer;
+ GtConfig->LogoSize =3D Size;
+
+ //
+ // Calculate the BltBuffer needed size.
+ //
+ BmpHeader =3D (BMP_IMAGE_HEADER *) GtConfig->LogoPtr;
+
+ if (BmpHeader->CharB =3D=3D 'B' && BmpHeader->CharM =3D=3D 'M') {
+ BltBufferSize =3D MultU64x32 ((UINT64) BmpHeader->PixelWidth, BmpH=
eader->PixelHeight);
+ if (BltBufferSize < DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OU=
TPUT_BLT_PIXEL))) {
+ BltBufferSize =3D MultU64x32 (BltBufferSize, sizeof (EFI_GRAPHIC=
S_OUTPUT_BLT_PIXEL));
+ GtConfig->BltBufferSize =3D (UINT32) BltBufferSize;
+ GtConfig->BltBufferAddress =3D (VOID *) AllocatePages (EFI_SIZE_=
TO_PAGES ((UINTN)GtConfig->BltBufferSize));
+ } else {
+ DEBUG ((DEBUG_ERROR, "Blt Buffer Size overflow.\n"));
+ ASSERT (FALSE);
+ }
+ } else {
+ DEBUG ((DEBUG_ERROR, "Wrong Bmp Image Header.\n"));
+ ASSERT (FALSE);
+ }
+
+ } else {
+ DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
+ GtConfig->LogoPtr =3D NULL;
+ GtConfig->LogoSize =3D 0;
+ }
+
+ DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtCon=
fig->LogoPtr));
+ DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtCo=
nfig->LogoSize));
+
+ //
+ // Display DDI Initialization ( default Native GPIO as per board durin=
g AUTO case)
+ //
+ if (PcdGet32 (PcdSaDisplayConfigTable) !=3D 0) {
+ CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDispl=
ayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize));
+ GtConfig->DdiConfiguration.DdiPortEdp =3D SaDisplayConfigTable[0=
];
+ GtConfig->DdiConfiguration.DdiPortBHpd =3D SaDisplayConfigTable[1=
];
+ GtConfig->DdiConfiguration.DdiPortCHpd =3D SaDisplayConfigTable[2=
];
+ GtConfig->DdiConfiguration.DdiPortDHpd =3D SaDisplayConfigTable[3=
];
+ GtConfig->DdiConfiguration.DdiPortFHpd =3D SaDisplayConfigTable[4=
];
+ GtConfig->DdiConfiguration.DdiPortBDdc =3D SaDisplayConfigTable[5=
];
+ GtConfig->DdiConfiguration.DdiPortCDdc =3D SaDisplayConfigTable[6=
];
+ GtConfig->DdiConfiguration.DdiPortDDdc =3D SaDisplayConfigTable[7=
];
+ GtConfig->DdiConfiguration.DdiPortFDdc =3D SaDisplayConfigTable[8=
];
+ }
+ }
+
+ PciePeiConfig->DmiAspm =3D 0x3;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section fr=
om FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
+ EFI_FV_FILE_INFO FvFileInfo;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ EFI_PEI_FILE_HANDLE VbtFileHandle;
+ EFI_GUID *VbtGuid;
+ EFI_COMMON_SECTION_HEADER *Section;
+ CONST EFI_PEI_SERVICES **PeiServices;
+
+ PeiServices =3D GetPeiServicesTablePointer();
+
+ PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+
+ Status =3D PeiServicesLocatePpi(
+ &gEfiFirmwareFileSystem2Guid,
+ 0,
+ NULL,
+ (VOID **)&FvPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ CurrentFv =3D PrivateData->CurrentPeimFvCount;
+ CoreFvHandle =3D &(PrivateData->Fv[CurrentFv]);
+
+ Status =3D FvPpi->FindFileByName(FvPpi, &NameGuid, &CoreFvHandle->FvHand=
le, &VbtFileHandle);
+ if (!EFI_ERROR(Status) && VbtFileHandle !=3D NULL) {
+
+ DEBUG((DEBUG_INFO, "Find SectionByType \n"));
+
+ Status =3D FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, VbtFileHan=
dle, (VOID **)&VbtGuid);
+ if (!EFI_ERROR(Status)) {
+
+ DEBUG((DEBUG_INFO, "GetFileInfo \n"));
+
+ Status =3D FvPpi->GetFileInfo(FvPpi, VbtFileHandle, &FvFileInfo);
+ Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+ if (IS_SECTION2(Section)) {
+ ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF);
+ *Size =3D SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEAD=
ER2);
+ *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER=
2));
+ } else {
+ *Size =3D SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADE=
R);
+ *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER=
));
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
new file mode 100644
index 0000000000..ab5fbad638
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiSaPolicyUpdate.h
@@ -0,0 +1,53 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real E=
DKII
+// environment
+//
+#include <PlatformBoardId.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Ppi/Wdt.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <CpuAccess.h>
+
+#define WDT_TIMEOUT 60
+
+// BClk Frequency Limitations (in Hz)
+#define BCLK_MAX 538000000
+#define BCLK_100 100000000
+#define BCLK_GRANULARITY 1000000
+#define BCLK_100_KHZ 100000
+
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section fr=
om FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ );
+
+#endif
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/P=
olicy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..1f38e4e475
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,213 @@
+/** @file
+ Platform Stage System Agent initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <CpuRegs.h>
+#include <Register/Cpuid.h>
+#include <Library/CpuPlatformLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Library/HobLib.h>
+#include <Platform.h>
+#include <PlatformBoardConfig.h>
+#include <Library/SiPolicyLib.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/GpioLib.h>
+#include <Library/ConfigBlockLib.h>
+
+///
+/// Memory Reserved should be between 125% to 150% of the Current required=
memory
+/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resum=
e issues.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED STATIC EFI_MEMORY_TYPE_INFORMATION mDefaultM=
emoryTypeInformation[] =3D {
+ { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory=
Size) }, // ASL
+ { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize=
) }, // ACPI NVS (including S3 related)
+ { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz=
e) }, // BIOS Reserved (including S3 related)
+ { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize)=
}, // Runtime Service Data
+ { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize)=
}, // Runtime Service Code
+ { EfiMaxMemoryType, 0 }
+};
+
+/**
+ UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
+
+ @param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY PPI
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+UpdatePeiSaPolicyPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig =3D NULL;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc =3D NULL;
+ SA_MEMORY_RCOMP *RcompData;
+ WDT_PPI *gWdtPei;
+ UINT8 Index;
+ UINTN DataSize;
+ EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
+ EFI_BOOT_MODE BootMode;
+ UINT32 TraceHubTotalMemSize;
+ GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig =3D NULL;
+ MEMORY_CONFIGURATION *MemConfig =3D NULL;
+ PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig =3D NULL;
+ SWITCHABLE_GRAPHICS_CONFIG *SgGpioData =3D NULL;
+ IPU_PREMEM_CONFIG *IpuPreMemPolicy =3D NULL;
+ OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig =3D NULL;
+ VTD_CONFIG *Vtd =3D NULL;
+ UINT32 ProcessorTraceTotalMemSize;
+
+ TraceHubTotalMemSize =3D 0;
+ ProcessorTraceTotalMemSize =3D 0;
+
+ DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdateP=
eiSaPolicyPreMem\n"));
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC=
onfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMe=
mConfigGuid, (VOID *) &GtPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid=
, (VOID *) &MemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreMemC=
onfigGuid, (VOID *) &PciePeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSwitchableGraphi=
csConfigGuid, (VOID *) &SgGpioData);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConfigG=
uid, (VOID *) &IpuPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCr=
cGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaOverclockingPr=
eMemConfigGuid, (VOID *) &OcPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (=
VOID *)&Vtd);
+ ASSERT_EFI_ERROR(Status);
+
+ RcompData =3D MemConfigNoCrc->RcompData;
+
+ //
+ // Locate WDT_PPI (ICC WDT PPI)
+ //
+ gWdtPei =3D NULL;
+ Status =3D PeiServicesLocatePpi(
+ &gWdtPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &gWdtPei
+ );
+
+ Status =3D PeiServicesGetBootMode(&BootMode);
+ ASSERT_EFI_ERROR(Status);
+
+ MiscPeiPreMemConfig->S3DataPtr =3D NULL;
+ MiscPeiPreMemConfig->UserBd =3D 0; // It's a CRB mobile board by default=
(btCRBMB)
+
+ PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform)=
);
+ MiscPeiPreMemConfig->SpdAddressTable[0] =3D PcdGet8 (PcdMrcSpdAddressTab=
le0);
+ MiscPeiPreMemConfig->SpdAddressTable[1] =3D PcdGet8 (PcdMrcSpdAddressTab=
le1);
+ MiscPeiPreMemConfig->SpdAddressTable[2] =3D PcdGet8 (PcdMrcSpdAddressTab=
le2);
+ MiscPeiPreMemConfig->SpdAddressTable[3] =3D PcdGet8 (PcdMrcSpdAddressTab=
le3);
+ MemConfig->CaVrefConfig =3D PcdGet8 (PcdMrcCaVrefConfig);
+ MemConfig->DualDimmPerChannelBoardType =3D PcdGetBool (PcdDualDimmPerCh=
annelBoardType);
+ if (PcdGet32 (PcdMrcRcompResistor)) {
+ CopyMem((VOID *)RcompData->RcompResistor, (VOID *) (UINTN) PcdGet32 (P=
cdMrcRcompResistor), sizeof (RcompData->RcompResistor));
+ }
+ if (PcdGet32 (PcdMrcRcompTarget)) {
+ CopyMem((VOID *)RcompData->RcompTarget, (VOID *) (UINTN) PcdGet32 (Pcd=
MrcRcompTarget), sizeof (RcompData->RcompTarget));
+ }
+ if (PcdGet32 (PcdMrcDqByteMap)) {
+ CopyMem((VOID *)MemConfigNoCrc->DqByteMap, (VOID *) (UINTN) PcdGet32 (=
PcdMrcDqByteMap), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MRC_ITERATION_MAX=
* 2);
+ }
+ if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
+ CopyMem((VOID *)MemConfigNoCrc->DqsMap, (VOID *) (UINTN) PcdGet32 (Pcd=
MrcDqsMapCpu2Dram), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO=
_ECC);
+ }
+ if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
+ MemConfig->DqPinsInterleaved =3D PcdGetBool (PcdMrcDqPinsInterleaved);
+ }
+ if (PcdGet32 (PcdMrcSpdData)) {
+ CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *) (UINT=
N) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *) (UINT=
N) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ }
+
+ MiscPeiPreMemConfig->MchBar =3D (UINTN) PcdGet64 (PcdMchBaseAddress);
+ MiscPeiPreMemConfig->DmiBar =3D (UINTN) PcdGet64 (PcdDmiBaseAddress);
+ MiscPeiPreMemConfig->EpBar =3D (UINTN) PcdGet64 (PcdEpBaseAddress);
+ MiscPeiPreMemConfig->EdramBar =3D (UINTN) PcdGet64 (PcdEdramBaseAddress);
+ MiscPeiPreMemConfig->SmbusBar =3D PcdGet16(PcdSmbusBaseAddress);
+ MiscPeiPreMemConfig->TsegSize =3D PcdGet32(PcdTsegSize);
+ MiscPeiPreMemConfig->UserBd =3D PcdGet8 (PcdSaMiscUserBd);
+ MiscPeiPreMemConfig->MmioSizeAdjustment =3D PcdGet16 (PcdSaMiscMmioSizeA=
djustment);
+ if (PcdGetBool (PcdPegGpioResetControl)) {
+ PciePeiPreMemConfig->PegGpioData.GpioSupport =3D PcdGetBool (PcdPegGpi=
oResetSupoort);
+ } else {
+
+ }
+ PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.GpioPad =3D PcdGet32 (P=
cdPeg0ResetGpioPad);
+ PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active =3D PcdGetBool =
(PcdPeg0ResetGpioActive);
+
+ PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.GpioPad =3D PcdGet32 (P=
cdPeg3ResetGpioPad);
+ PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active =3D PcdGetBool =
(PcdPeg3ResetGpioActive);
+
+ MemConfig->CkeRankMapping =3D 0xAA;
+ ///
+ /// Initialize the VTD Configuration
+ ///
+ Vtd->VtdDisable =3D 0;
+
+ MemConfig->RMT =3D 1;
+ MemConfig->UserPowerWeightsEn =3D 0;
+ MemConfig->RaplLim2WindY =3D 0x0A;
+ MemConfig->ExitOnFailure =3D 1;
+
+ MemConfigNoCrc->PlatformMemorySize =3D PEI_MIN_MEMORY_SIZE + TraceHubTot=
alMemSize + ProcessorTraceTotalMemSize;
+ DataSize =3D sizeof (mDefaultMemoryTypeInformation);
+ CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
+
+ if (BootMode !=3D BOOT_IN_RECOVERY_MODE) {
+ for (Index =3D 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATI=
ON); Index++) {
+ MemConfigNoCrc->PlatformMemorySize +=3D MemoryData[Index].NumberOfPa=
ges * EFI_PAGE_SIZE;
+ }
+
+ OcPreMemConfig->GtMaxOcRatio =3D 0;
+ OcPreMemConfig->GtVoltageMode =3D 0;
+ OcPreMemConfig->GtVoltageOverride =3D 0;
+ OcPreMemConfig->GtExtraTurboVoltage =3D 0;
+ OcPreMemConfig->GtVoltageOffset =3D 0;
+ OcPreMemConfig->SaVoltageOffset =3D 0;
+ OcPreMemConfig->GtusMaxOcRatio =3D 0;
+ OcPreMemConfig->GtusVoltageMode =3D 0;
+ OcPreMemConfig->GtusVoltageOverride =3D 0;
+ OcPreMemConfig->GtusExtraTurboVoltage =3D 0;
+ OcPreMemConfig->GtusVoltageOffset =3D 0;
+
+ ///
+ /// Build the GUID'd HOB for DXE
+ ///
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ MemoryData,
+ DataSize
+ );
+ }
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiSiPolicyUpdate.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c
new file mode 100644
index 0000000000..7233925379
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiSiPolicyUpdate.c
@@ -0,0 +1,169 @@
+/** @file
+ This file is SampleCode of the library for Intel Silicon PEI
+ Platform Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSiPolicyUpdate.h"
+#include <MeChipset.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ConfigBlockLib.h>
+
+STATIC SVID_SID_INIT_ENTRY mCdfSsidTablePtr[] =3D {
+ //
+ // SA Device(s)
+ //
+ {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ //
+ // PCH Device(s)
+ //
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, PCI_DE=
VICE_NUMBER_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, PCI_DE=
VICE_NUMBER_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, PCI_DE=
VICE_NUMBER_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, PCI_DE=
VICE_NUMBER_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1, PCI_DE=
VICE_NUMBER_CDF_PCH_SATA_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2, PCI_DE=
VICE_NUMBER_CDF_PCH_SATA_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3, PCI_DE=
VICE_NUMBER_CDF_PCH_SATA_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, PCI_DE=
VICE_NUMBER_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, PCI_DE=
VICE_NUMBER_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, PCI_DE=
VICE_NUMBER_PCH_TRACE_HUB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, PCI_DE=
VICE_NUMBER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, PCI_DE=
VICE_NUMBER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, PCI_DE=
VICE_NUMBER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S=
EGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PC=
I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P=
CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+};
+
+STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[] =3D {
+ //
+ // SA Device(s)
+ //
+ {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, SA_MC_BUS, 0,=
SA_SEG_NUM, 0}}, {0, 0},0},
+ //
+ // PCH Device(s)
+ //
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, PCI_DEVICE_NUMBE=
R_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH=
, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, PCI_DEVICE_NUMBE=
R_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH=
, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, PCI_DEVICE_NUMBE=
R_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH=
, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, PCI_DEVICE_NUMBE=
R_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH=
, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SATA, PCI_DEVICE_NUMBE=
R_PCH_SATA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH=
, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, PCI_DEVICE_NUMBE=
R_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH=
, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, PCI_DEVICE_NUMBE=
R_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH=
, 0}}, {0, 0},0},
+ //
+ // Skip PCH LAN controller
+ // PCH LAN SVID/SID may be loaded automatically from the NVM Word 0Ch/0B=
h upon power up or reset
+ // depending on the "Load Subsystem ID" bit field in NVM word 0Ah
+ //
+ //{{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LAN, PCI_DEVICE_NUM=
BER_PCH_LAN, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_P=
CH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, PCI_DEVICE=
_NUMBER_PCH_TRACE_HUB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE=
GMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_UART0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE=
GMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_UART1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE=
GMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_SPI0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE=
GMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_SPI1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE=
GMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_CNL_SCS_SDCARD, PCI_DEVICE_=
NUMBER_PCH_CNL_SCS_SDCARD, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGME=
NT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, PCI_DEVICE_NUMB=
ER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE=
R_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, PCI_DEVICE_NUMB=
ER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE=
R_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, PCI_DEVICE_NUMB=
ER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE=
R_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_ISH, PCI_DEVI=
CE_NUMBER_PCH_ISH, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG=
MENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24, PCI_=
DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI=
_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_I2C0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG=
MENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_I2C1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG=
MENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_I2C2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG=
MENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_I2C3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG=
MENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_UART2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG=
MENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_I2C5, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG=
MENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4, PCI_DEVICE=
_NUMBER_PCH_SERIAL_IO_I2C4, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG=
MENT_NUMBER_PCH, 0}}, {0, 0},0},
+ //
+ // ME Device(s)
+ //
+ {{{PCI_SVID_OFFSET, HECI_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC=
I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, HECI2_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC=
I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, IDER_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC=
I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, SOL_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC=
I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, HECI3_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC=
I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+ {{{PCI_SVID_OFFSET, HECI4_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC=
I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}
+};
+
+/**
+ This function performs Silicon PEI Policy initialization.
+
+ @param[in] SiPolicy The Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicy
+ )
+{
+ EFI_STATUS Status;
+ SI_CONFIG *SiConfig;
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &=
SiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ SiConfig->CsmFlag =3D 0;
+
+ if (IsCdfPch ()) {
+ SiConfig->SsidTablePtr =3D (UINT32*)(UINTN) mCdfSsidTablePtr;
+ SiConfig->NumberOfSsidTableEntry =3D (sizeof (mCdfSsidTablePtr) / size=
of (SVID_SID_INIT_ENTRY));
+ } else {
+ SiConfig->SsidTablePtr =3D (UINT32*)(UINTN) mSsidTablePtr;
+ SiConfig->NumberOfSsidTableEntry =3D (sizeof (mSsidTablePtr) / sizeof =
(SVID_SID_INIT_ENTRY));
+ }
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyU=
pdateLib/PeiSiPolicyUpdate.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/=
Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h
new file mode 100644
index 0000000000..a68cba3201
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi=
b/PeiSiPolicyUpdate.h
@@ -0,0 +1,18 @@
+/** @file
+ Header file for PEI SiPolicyUpdate.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_H_
+#define _PEI_SI_POLICY_UPDATE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/SiPolicy.h>
+
+#endif
+
--=20
2.16.2.windows.1
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From: "Kathappan Esakkithevar" <kathappan.esakkithevar@intel.com>
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Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
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Subject: [edk2-devel] [edk2-platforms] [PATCH v2 4/7]
CometlakeOpenBoardPkg/CometlakeURvp: Add library instances
Date: Wed, 12 Feb 2020 00:42:38 +0530
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280
CometlakeURvp library instances.
* BaseFuncLib - Board-specific VBT update routines.
* BaseGpioCheckConflictLib - Identifies GPIO pad conflicts.
* BaseGpioCheckConflictLibNull - NULL library instance.
* BasePlatformHookLib - Serial port initialization support.
* DxePolicyBoardConfigLib - Board-specific silicon policy configuration
in DXE.
* PeiBoardInitPostMemLib - PEI post-memory board-specific initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiBoardInitPreMemLib - PEI pre-memory board-specific initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiMultiBoardInitPostMemLib - PEI post-memory multi-board initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiMultiBoardInitPreMemLib - PEI pre-memory multi-board initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiPlatformHookLib - PEI board instance-specifc GPIO init.
* PeiPolicyBoardConfigLib - Board instance-specific policy init in PEI.
* SmmBoardAcpiEnableLib - Board instance-specific SMM ACPI enable support.
* SmmMultiBoardAcpiSupportLib - Multi-board ACPI support in SMM.
Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
---
.../Library/BaseFuncLib/BaseFuncLib.inf | 33 +
.../CometlakeURvp/Library/BaseFuncLib/Gop.c | 41 +
.../BaseGpioCheckConflictLib.c | 137 +
.../BaseGpioCheckConflictLib.inf | 35 +
.../BaseGpioCheckConflictLibNull.c | 37 +
.../BaseGpioCheckConflictLibNull.inf | 32 +
.../BasePlatformHookLib/BasePlatformHookLib.c | 156 +
.../BasePlatformHookLib/BasePlatformHookLib.inf | 53 +
.../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 63 +
.../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 50 +
.../BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c | 40 +
.../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 82 +
.../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 50 +
.../Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 170 ++
.../CometlakeURvp/Library/BoardInitLib/BoardFunc.c | 19 +
.../CometlakeURvp/Library/BoardInitLib/BoardFunc.h | 20 +
.../Library/BoardInitLib/BoardFuncInit.c | 26 +
.../Library/BoardInitLib/BoardFuncInitPreMem.c | 40 +
.../Library/BoardInitLib/BoardInitLib.h | 20 +
.../Library/BoardInitLib/BoardPchInitPreMemLib.c | 398 +++
.../Library/BoardInitLib/BoardSaConfigPreMem.h | 83 +
.../Library/BoardInitLib/BoardSaInitPreMemLib.c | 383 +++
.../BoardInitLib/CometlakeURvpHsioPtssTables.c | 32 +
.../Library/BoardInitLib/CometlakeURvpInit.h | 41 +
.../BoardInitLib/GpioTableCmlUlpddr3PreMem.c | 43 +
.../BoardInitLib/GpioTableCometlakeULpddr3Rvp.c | 254 ++
.../Library/BoardInitLib/GpioTableDefault.c | 213 ++
.../Library/BoardInitLib/PchHdaVerbTables.h | 3014 ++++++++++++++++=
++++
.../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 40 +
.../BoardInitLib/PeiBoardInitPostMemLib.inf | 57 +
.../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 106 +
.../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 118 +
.../Library/BoardInitLib/PeiCometlakeURvpDetect.c | 63 +
.../BoardInitLib/PeiCometlakeURvpInitPostMemLib.c | 436 +++
.../BoardInitLib/PeiCometlakeURvpInitPreMemLib.c | 562 ++++
.../BoardInitLib/PeiMultiBoardInitPostMemLib.c | 41 +
.../BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 207 ++
.../BoardInitLib/PeiMultiBoardInitPreMemLib.c | 83 +
.../BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 300 ++
.../DxePolicyBoardConfigLib/DxePolicyBoardConfig.h | 19 +
.../DxePolicyBoardConfigLib.inf | 45 +
.../DxeSaPolicyBoardConfig.c | 36 +
.../PeiPlatformHookLib/PeiPlatformHooklib.c | 299 ++
.../PeiPlatformHookLib/PeiPlatformHooklib.inf | 95 +
.../PeiCpuPolicyBoardConfig.c | 49 +
.../PeiCpuPolicyBoardConfigPreMem.c | 29 +
.../PeiMePolicyBoardConfig.c | 36 +
.../PeiMePolicyBoardConfigPreMem.c | 37 +
.../PeiPchPolicyBoardConfig.c | 36 +
.../PeiPchPolicyBoardConfigPreMem.c | 37 +
.../PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h | 22 +
.../PeiPolicyBoardConfigLib.inf | 71 +
.../PeiSaPolicyBoardConfig.c | 36 +
.../PeiSaPolicyBoardConfigPreMem.c | 37 +
.../PeiSiPolicyBoardConfig.c | 27 +
55 files changed, 8489 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BaseFuncLib/BaseFuncLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BaseFuncLib/Gop.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardAcpiLib/SmmBoardAcpiEnableLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/BoardFunc.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/BoardFunc.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/BoardFuncInit.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/BoardFuncInitPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/BoardInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/BoardPchInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/BoardSaConfigPreMem.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/BoardSaInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/CometlakeURvpHsioPtssTables.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/CometlakeURvpInit.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/GpioTableCmlUlpddr3PreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/GpioTableCometlakeULpddr3Rvp.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/GpioTableDefault.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PchHdaVerbTables.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiCometlakeURvpDetect.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiCometlakeURvpInitPostMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiCometlakeURvpInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiMultiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiMultiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPlatformHookLib/PeiPlatformHooklib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPlatformHookLib/PeiPlatformHooklib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr=
ary/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas=
eFuncLib/BaseFuncLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeUR=
vp/Library/BaseFuncLib/BaseFuncLib.inf
new file mode 100644
index 0000000000..2dad67a1e5
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLi=
b/BaseFuncLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Component information file for Board Functions Library.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D BaseBoardFuncInitLib
+ FILE_GUID =3D 7ad17b6c-b9b6-4d88-85c4-7366a2bd12a3
+ MODULE_TYPE =3D PEIM
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D NULL|PEIM
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+
+[Packages]
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ Gop.c
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas=
eFuncLib/Gop.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library=
/BaseFuncLib/Gop.c
new file mode 100644
index 0000000000..8b8089c3c0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLi=
b/Gop.c
@@ -0,0 +1,41 @@
+/** @file
+ Others Board's PCD function hook.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <GopConfigLib.h>
+
+//
+// Null function for nothing GOP VBT update.
+//
+VOID
+EFIAPI
+GopVbtSpecificUpdateNull (
+ IN CHILD_STRUCT **ChildStructPtr
+ )
+{
+ return;
+}
+
+//
+// for CFL U DDR4
+//
+VOID
+EFIAPI
+CflUDdr4GopVbtSpecificUpdate(
+ IN CHILD_STRUCT **ChildStructPtr
+)
+{
+ ChildStructPtr[1]->DeviceClass =3D DISPLAY_PORT_ONLY;
+ ChildStructPtr[1]->DVOPort =3D DISPLAY_PORT_B;
+ ChildStructPtr[2]->DeviceClass =3D DISPLAY_PORT_HDMI_DVI_COMPATIBLE;
+ ChildStructPtr[2]->DVOPort =3D DISPLAY_PORT_C;
+ ChildStructPtr[2]->AUX_Channel =3D AUX_CHANNEL_C;
+ ChildStructPtr[3]->DeviceClass =3D NO_DEVICE;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas=
eGpioCheckConflictLib/BaseGpioCheckConflictLib.c b/Platform/Intel/Cometlake=
OpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckCo=
nflictLib.c
new file mode 100644
index 0000000000..e42bb7cb91
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCh=
eckConflictLib/BaseGpioCheckConflictLib.c
@@ -0,0 +1,137 @@
+/** @file
+ Implementation of BaseGpioCheckConflictLib.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioCheckConflictLib.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Private/Library/GpioPrivateLib.h>
+
+/**
+ Check Gpio PadMode conflict and report it.
+
+ @retval none.
+**/
+VOID
+GpioCheckConflict (
+ VOID
+ )
+{
+ EFI_HOB_GUID_TYPE *GpioCheckConflictHob;
+ GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
+ UINT32 HobDataSize;
+ UINT32 GpioCount;
+ UINT32 GpioIndex;
+ GPIO_CONFIG GpioActualConfig;
+
+ GpioCheckConflictHob =3D NULL;
+ GpioCheckConflictHobData =3D NULL;
+
+ DEBUG ((DEBUG_INFO, "GpioCheckConflict Start..\n"));
+
+ //
+ //Use Guid to find HOB.
+ //
+ GpioCheckConflictHob =3D (EFI_HOB_GUID_TYPE *) GetFirstGuidHob (&gGpioCh=
eckConflictHobGuid);
+ if (GpioCheckConflictHob =3D=3D NULL) {
+ DEBUG ((DEBUG_INFO, "[Gpio Hob Check] Can't find Gpio Hob.\n"));
+ } else {
+ while (GpioCheckConflictHob !=3D NULL) {
+ //
+ // Find the Data area pointer and Data size from the Hob
+ //
+ GpioCheckConflictHobData =3D (GPIO_PAD_MODE_INFO *) GET_GUID_HOB_DAT=
A (GpioCheckConflictHob);
+ HobDataSize =3D GET_GUID_HOB_DATA_SIZE (GpioCheckConflictHob);
+
+ GpioCount =3D HobDataSize / sizeof (GPIO_PAD_MODE_INFO);
+ DEBUG ((DEBUG_INFO, "[Hob Check] Hob : GpioCount =3D %d\n", GpioCou=
nt));
+
+ //
+ // Probe Gpio entries in Hob and compare which are conflicted
+ //
+ for (GpioIndex =3D 0; GpioIndex < GpioCount ; GpioIndex++) {
+ GpioGetPadConfig (GpioCheckConflictHobData[GpioIndex].GpioPad, &Gp=
ioActualConfig);
+ if (GpioCheckConflictHobData[GpioIndex].GpioPadMode !=3D GpioActua=
lConfig.PadMode) {
+ DEBUG ((DEBUG_ERROR, "[Gpio Check] Identified conflict on pad %a=
\n", GpioName (GpioCheckConflictHobData[GpioIndex].GpioPad)));
+ }
+ }
+ //
+ // Find next Hob and return the Hob pointer by the specific Hob Guid
+ //
+ GpioCheckConflictHob =3D GET_NEXT_HOB (GpioCheckConflictHob);
+ GpioCheckConflictHob =3D GetNextGuidHob (&gGpioCheckConflictHobGuid,=
GpioCheckConflictHob);
+ }
+
+ DEBUG ((DEBUG_INFO, "GpioCheckConflict End.\n"));
+ }
+
+ return;
+}
+
+/**
+ This libaray will create one Hob for each Gpio config table
+ without PadMode is GpioHardwareDefault
+
+ @param[in] GpioDefinition Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+ @retval none.
+**/
+VOID
+CreateGpioCheckConflictHob (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+
+ UINT32 Index;
+ UINT32 GpioIndex;
+ GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
+ UINT16 GpioCount;
+
+ GpioCount =3D 0;
+ GpioIndex =3D 0;
+
+ DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob Start \n"));
+
+ for (Index =3D 0; Index < GpioTableCount ; Index++) {
+ if (GpioDefinition[Index].GpioConfig.PadMode =3D=3D GpioHardwareDefaul=
t) {
+ continue;
+ } else {
+ //
+ // Calculate how big size the Hob Data needs
+ //
+ GpioCount++;
+ }
+ }
+
+ //
+ // Build a HOB tagged with a GUID for identification and returns
+ // the start address of GUID HOB data.
+ //
+ GpioCheckConflictHobData =3D (GPIO_PAD_MODE_INFO *) BuildGuidHob (&gGpio=
CheckConflictHobGuid , GpioCount * sizeof (GPIO_PAD_MODE_INFO));
+
+ //
+ // Record Non Default Gpio entries to the Hob
+ //
+ for (Index =3D 0; Index < GpioTableCount; Index++) {
+ if (GpioDefinition[Index].GpioConfig.PadMode =3D=3D GpioHardwareDefaul=
t) {
+ continue;
+ } else {
+ GpioCheckConflictHobData[GpioIndex].GpioPad =3D GpioDefinition[Index=
].GpioPad;
+ GpioCheckConflictHobData[GpioIndex].GpioPadMode =3D GpioDefinition[I=
ndex].GpioConfig.PadMode;
+ GpioIndex++;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob End \n"));
+ return;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas=
eGpioCheckConflictLib/BaseGpioCheckConflictLib.inf b/Platform/Intel/Cometla=
keOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheck=
ConflictLib.inf
new file mode 100644
index 0000000000..a95faa200f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCh=
eckConflictLib/BaseGpioCheckConflictLib.inf
@@ -0,0 +1,35 @@
+## @file
+# Component information file for BaseGpioCheckConflictLib.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D BaseGpioCheckConflictLib
+ FILE_GUID =3D C19A848A-F013-4DBF-9C23-F0F74DEA6F14
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D GpioCheckConflictLib
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ BaseGpioCheckConflictLib.c
+
+[Guids]
+ gGpioCheckConflictHobGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas=
eGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c b/Platform/Intel/C=
ometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/Bas=
eGpioCheckConflictLibNull.c
new file mode 100644
index 0000000000..525a9b3e0f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCh=
eckConflictLibNull/BaseGpioCheckConflictLibNull.c
@@ -0,0 +1,37 @@
+/** @file
+ Implementation of BaseGpioCheckConflicLibNull.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioCheckConflictLib.h>
+
+/**
+ Check Gpio PadMode conflict and report it.
+**/
+VOID
+GpioCheckConflict (
+ VOID
+ )
+{
+ return;
+}
+
+/**
+ This libaray will create one Hob for each Gpio config table
+ without PadMode is GpioHardwareDefault
+
+ @param[in] GpioDefinition Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+**/
+VOID
+CreateGpioCheckConflictHob (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ return;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas=
eGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf b/Platform/Intel=
/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/B=
aseGpioCheckConflictLibNull.inf
new file mode 100644
index 0000000000..0a028ef0ca
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCh=
eckConflictLibNull/BaseGpioCheckConflictLibNull.inf
@@ -0,0 +1,32 @@
+## @file
+# Component information file for BaseGpioCheckConflictLib.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D BaseGpioCheckConflictLibNull
+ FILE_GUID =3D C19A848A-F013-4DBF-9C23-F0F74DEA6F14
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D GpioCheckConflictLib
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ BaseGpioCheckConflictLibNull.c
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas=
ePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/CometlakeOpenBoardP=
kg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..a80e790a86
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatfo=
rmHookLib/BasePlatformHookLib.c
@@ -0,0 +1,156 @@
+/** @file
+ Platform Hook Library instances
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/PlatformHookLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PcdLib.h>
+#include <SystemAgent/Include/SaAccess.h>
+#include <SioRegs.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Register/PchRegsLpc.h>
+#include <PchAccess.h>
+
+#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E
+#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F
+
+#define IT8628_ENTER_CONFIG_WRITE_SEQ_0 0x87
+#define IT8628_ENTER_CONFIG_WRITE_SEQ_1 0x01
+#define IT8628_ENTER_CONFIG_WRITE_SEQ_2 0x55
+#define IT8628_ENTER_CONFIG_WRITE_SEQ_3 0x55
+#define IT8628_EXIT_CONFIG 0x2
+#define IT8628_CHIPID_BYTE1 0x86
+#define IT8628_CHIPID_BYTE2 0x28
+
+typedef struct {
+ UINT8 Register;
+ UINT8 Value;
+} EFI_SIO_TABLE;
+
+//
+// IT8628
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] =
=3D {
+ {0x023, 0x09}, // Clock Selection register
+ {0x007, 0x01}, // Com1 Logical Device Number select
+ {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register
+ {0x060, 0x03}, // Serial Port 1 Base Address LSB Register
+ {0x070, 0x04}, // Serial Port 1 Interrupt Level Select
+ {0x030, 0x01}, // Serial Port 1 Activate
+ {0x007, 0x02}, // Com1 Logical Device Number select
+ {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register
+ {0x060, 0x02}, // Serial Port 2 Base Address MSB Register
+ {0x070, 0x03}, // Serial Port 2 Interrupt Level Select
+ {0x030, 0x01} // Serial Port 2 Activate
+};
+
+/**
+ Check whether the IT8628 SIO present on LPC. If yes, enable its serial p=
orts
+**/
+STATIC
+VOID
+It8628SioSerialPortInit (
+ VOID
+ )
+{
+ UINT8 ChipId0;
+ UINT8 ChipId1;
+ UINT16 LpcIoDecondeRangeSet;
+ UINT16 LpcIoDecoodeSet;
+ UINT8 Index;
+ UINT64 LpcBaseAddr;
+
+ ChipId0 =3D 0;
+ ChipId1 =3D 0;
+ LpcIoDecondeRangeSet =3D 0;
+ LpcIoDecoodeSet =3D 0;
+
+ //
+ // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2=
Eh/2Fh.
+ //
+ LpcBaseAddr =3D PCI_SEGMENT_LIB_ADDRESS (
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ 0
+ );
+
+ LpcIoDecondeRangeSet =3D (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_=
CFG_IOD);
+ LpcIoDecoodeSet =3D (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_I=
OE);
+ PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOD), (LpcIoDecondeRangeSet =
| ((V_LPC_CFG_IOD_COMB_2F8 << 4) | V_LPC_CFG_IOD_COMA_3F8)));
+ PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOE), (LpcIoDecoodeSet | (B_=
LPC_CFG_IOE_SE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE|B_LPC_CFG_IOE_KE)));
+
+ //
+ // Enter MB PnP Mode
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_0);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_1);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_2);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_3);
+
+ //
+ // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);
+ ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
+
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);
+ ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
+
+ //
+ // Enable Serial Port 1, Port 2
+ //
+ if ((ChipId0 =3D=3D IT8628_CHIPID_BYTE1) && (ChipId1 =3D=3D IT8628_CHIPI=
D_BYTE2)) {
+ for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof =
(EFI_SIO_TABLE); Index++) {
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[In=
dex].Register);
+ IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Ind=
ex].Value);
+ }
+ }
+
+ //
+ // Exit MB PnP Mode
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_EXIT_CONFIG);
+ IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, IT8628_EXIT_CONFIG);
+
+ return;
+}
+
+/**
+ Performs platform specific initialization required for the CPU to access
+ the hardware associated with a SerialPortLib instance. This function do=
es
+ not initialize the serial port hardware itself. Instead, it initializes
+ hardware devices that are required for the CPU to access the serial port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succee=
ded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could =
not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E=
h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ // Configure Sio IT8628
+ It8628SioSerialPortInit ();
+
+ return RETURN_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas=
ePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/CometlakeOpenBoar=
dPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..ca723a92cb
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatfo=
rmHookLib/BasePlatformHookLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Platform Hook Library instance for Cometlake Mobile/Desktop CRB.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D BasePlatformHookLib
+ FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D BASE
+ LIBRARY_CLASS =3D PlatformHookLib
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciSegmentLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSU=
MES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSU=
MES
+ gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSU=
MES
+
+[FixedPcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding #=
# CONSUMES
+
+[Sources]
+ BasePlatformHookLib.c
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Co=
metlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
new file mode 100644
index 0000000000..a1ed0230ed
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL=
ib/SmmBoardAcpiEnableLib.c
@@ -0,0 +1,63 @@
+/** @file
+ Comet Lake U LP3 SMM Board ACPI Enable library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return CometlakeURvpBoardEnableAcpi(EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return CometlakeURvpBoardDisableAcpi(DisableSci);
+}
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/=
CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
new file mode 100644
index 0000000000..d67ac1885c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL=
ib/SmmBoardAcpiEnableLib.inf
@@ -0,0 +1,50 @@
+## @file
+# Comet Lake U LP3 SMM Board ACPI Enable library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D SmmBoardAcpiEnableLib
+ FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58AD
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D BASE
+ LIBRARY_CLASS =3D BoardAcpiEnableLib
+
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ MmPciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUM=
ES
+
+[Protocols]
+
+[Sources]
+ SmmCometlakeURvpAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmBoardAcpiEnableLib.c
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdAcpiLib/SmmCometlakeURvpAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoa=
rdPkg/CometlakeURvp/Library/BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c
new file mode 100644
index 0000000000..b0d431a08c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL=
ib/SmmCometlakeURvpAcpiEnableLib.c
@@ -0,0 +1,40 @@
+/** @file
+ Comet Lake LP3 SMM Board ACPI Enable library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardEnableAcpi(
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDisableAcpi(
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/CometlakeOpenBoard=
Pkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..e0d8645f29
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL=
ib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,82 @@
+/** @file
+ Comet Lake U LP3 SMM Multi-Board ACPI Support library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardEnableAcpi(
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDisableAcpi(
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpMultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return CometlakeURvpBoardEnableAcpi(EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpMultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return CometlakeURvpBoardDisableAcpi(DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC mCometlakeURvpBoardAcpiEnableFunc =3D {
+ CometlakeURvpMultiBoardEnableAcpi,
+ CometlakeURvpMultiBoardDisableAcpi,
+};
+
+EFI_STATUS
+EFIAPI
+SmmCometlakeURvpMultiBoardAcpiSupportLibConstructor (
+ VOID
+ )
+{
+ if (LibPcdGetSku () =3D=3D BoardIdCometLakeULpddr3Rvp) {
+ return RegisterBoardAcpiEnableFunc (&mCometlakeURvpBoardAcpiEnableFunc=
);
+ }
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/CometlakeOpenBoa=
rdPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..b23485be2b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL=
ib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,50 @@
+## @file
+# Comet Lake U LP3 SMM Multi-Board ACPI Support library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D SmmCometlakeURvpMultiBoardAcpiSupport=
Lib
+ FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D BASE
+ LIBRARY_CLASS =3D NULL
+ CONSTRUCTOR =3D SmmCometlakeURvpMultiBoardAcpiSupport=
LibConstructor
+
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUM=
ES
+
+[Protocols]
+
+[Sources]
+ SmmCometlakeURvpAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoardPkg/=
CometlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..ffa8738d6b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL=
ib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,170 @@
+/** @file
+ Comet Lake U LP3 SMM Silicon ACPI Enable library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PchAccess.h>
+#include <Library/MmPciLib.h>
+#include <Library/PmcLib.h>
+
+/**
+ Clear Port 80h
+
+ SMI handler to enable ACPI mode
+
+ Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+ SCI mode is then enabled.
+
+ Clear SLP SMI status
+ Enable SLP SMI
+
+ Disable SW SMI Timer
+
+ Clear all ACPI event status and disable all ACPI events
+
+ Disable PM sources except power button
+ Clear status bits
+
+ Disable GPE0 sources
+ Clear status bits
+
+ Disable GPE1 sources
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+
+ UINT32 OutputValue;
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINTN LpcBaseAddress;
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ 0
+ );
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr =3D PmcGetAcpiBase();
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing=
control to the
+ // OS in order to prevent the host from issuing global resets and resett=
ing ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Res=
et
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ IoWrite8 (0x80, 0);
+
+ //
+ // Disable SW SMI Timer and clean the status
+ //
+ SmiEn =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN);
+ SmiEn &=3D ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |=
B_ACPI_IO_SMI_EN_LEGACY_USB);
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
+
+ SmiSts =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS);
+ SmiSts |=3D B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | =
B_ACPI_IO_SMI_EN_LEGACY_USB;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled
+ //
+ ULKMC =3D MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_UL=
KMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC=
_64WEN | B_LPC_CFG_ULKMC_A20PASSEN);
+ MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
+
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
+ IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
+
+ //
+ // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
+ //
+ OutputValue =3D IoRead32 (AcpiBaseAddr + 0x38);
+ OutputValue =3D OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPos=
ition));
+ IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt |=3D B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr =3D PmcGetAcpiBase();
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/BoardFunc.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/=
Library/BoardInitLib/BoardFunc.c
new file mode 100644
index 0000000000..fa6a186045
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/BoardFunc.c
@@ -0,0 +1,19 @@
+/** @file
+ Board's PCD function hook.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+EFI_STATUS
+PeiBoardSpecificInitPostMemNull (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/BoardFunc.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/=
Library/BoardInitLib/BoardFunc.h
new file mode 100644
index 0000000000..9e8930755d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/BoardFunc.h
@@ -0,0 +1,20 @@
+/** @file
+ Header file for Board Hook function intance.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BOARD_FUNC_H_
+#define _BOARD_FUNC_H_
+
+#include <Uefi.h>
+
+EFI_STATUS
+PeiBoardSpecificInitPostMemNull (
+ VOID
+ );
+
+#endif // _BOARD_FUNC_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/BoardFuncInit.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeU=
Rvp/Library/BoardInitLib/BoardFuncInit.c
new file mode 100644
index 0000000000..43896af760
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/BoardFuncInit.c
@@ -0,0 +1,26 @@
+/** @file
+ Source code for the board configuration init function in Post Memory ini=
t phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BoardFunc.h"
+
+/**
+ Board's PCD function hook init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardFunctionInit (
+ IN UINT16 BoardId
+)
+{
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/BoardFuncInitPreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/Come=
tlakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
new file mode 100644
index 0000000000..6181cf45ff
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/BoardFuncInitPreMem.c
@@ -0,0 +1,40 @@
+/** @file
+ Source code for the board configuration init function in Post Memory ini=
t phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <GopConfigLib.h>
+//
+// Null function for nothing GOP VBT update.
+//
+VOID
+GopVbtSpecificUpdateNull(
+ IN CHILD_STRUCT **ChildStructPtr
+);
+//
+// for CFL U DDR4
+//
+VOID
+CflUDdr4GopVbtSpecificUpdate(
+ IN CHILD_STRUCT **ChildStructPtr
+);
+/**
+ Board's PCD function hook init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardFunctionInitPreMem (
+ IN UINT16 BoardId
+ )
+{
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/BoardInitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeUR=
vp/Library/BoardInitLib/BoardInitLib.h
new file mode 100644
index 0000000000..758cbaa0b6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/BoardInitLib.h
@@ -0,0 +1,20 @@
+/** @file
+ Header file for board Init function for Post Memory Init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_BOARD_INIT_LIB_H_
+#define _PEI_BOARD_INIT_LIB_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+#endif // _PEI_BOARD_INIT_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Co=
metlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..f9e7aeecb9
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/BoardPchInitPreMemLib.c
@@ -0,0 +1,398 @@
+/** @file
+ Source code for the board PCH configuration Pcd init functions for Pre-Me=
mory Init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "CometlakeURvpInit.h"
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <PlatformBoardConfig.h> // for USB 20 AFE & Root Port Clk =
Info.
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+
+/**
+ Board Root Port Clock Info configuration init function for PEI pre-memor=
y phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+RootPortClkInfoInit (
+ IN UINT16 BoardId
+ )
+{
+ PCD64_BLOB *Clock;
+ UINT32 Index;
+
+ Clock =3D AllocateZeroPool (16 * sizeof (PCD64_BLOB));
+ ASSERT (Clock !=3D NULL);
+ if (Clock =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ //
+ // The default clock assignment will be FREE_RUNNING, which corresponds =
to PchClockUsageUnspecified
+ // This is safe but power-consuming setting. If Platform code doesn't co=
ntain port-clock map for a given board,
+ // the clocks will keep on running anyway, allowing PCIe devices to oper=
ate. Downside is that clocks will
+ // continue to draw power. To prevent this, remember to provide port-clo=
ck map for every board.
+ //
+ for (Index =3D 0; Index < 16; Index++) {
+ Clock[Index].PcieClock.ClkReqSupported =3D TRUE;
+ Clock[Index].PcieClock.ClockUsage =3D FREE_RUNNING;
+ }
+
+ ///
+ /// Assign ClkReq signal to root port. (Base 0)
+ /// For LP, Set 0 - 5
+ /// For H, Set 0 - 15
+ /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai=
lable for Root Port.
+ ///
+ switch (BoardId) {
+ // CLKREQ
+ case BoardIdCometLakeULpddr3Rvp:
+ Clock[0].PcieClock.ClockUsage =3D PCIE_PCH + 1;
+ Clock[1].PcieClock.ClockUsage =3D PCIE_PCH + 8;
+ Clock[2].PcieClock.ClockUsage =3D LAN_CLOCK;
+ Clock[3].PcieClock.ClockUsage =3D PCIE_PCH + 13;
+ Clock[4].PcieClock.ClockUsage =3D PCIE_PCH + 4;
+ Clock[5].PcieClock.ClockUsage =3D PCIE_PCH + 14;
+ break;
+
+ default:
+ break;
+ }
+
+ PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
+ PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
+ PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
+ PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
+ PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
+ PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
+ PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
+ PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
+ PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
+ PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
+ PcdSet64S (PcdPcieClock10, Clock[10].Blob);
+ PcdSet64S (PcdPcieClock11, Clock[11].Blob);
+ PcdSet64S (PcdPcieClock12, Clock[12].Blob);
+ PcdSet64S (PcdPcieClock13, Clock[13].Blob);
+ PcdSet64S (PcdPcieClock14, Clock[14].Blob);
+ PcdSet64S (PcdPcieClock15, Clock[15].Blob);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board USB related configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+UsbConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ PCD32_BLOB *UsbPort20Afe;
+
+ UsbPort20Afe =3D AllocateZeroPool (PCH_MAX_USB2_PORTS * sizeof (PCD32_BL=
OB));
+ ASSERT (UsbPort20Afe !=3D NULL);
+ if (UsbPort20Afe =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // USB2 AFE settings.
+ //
+ UsbPort20Afe[0].Info.Petxiset =3D 7;
+ UsbPort20Afe[0].Info.Txiset =3D 5;
+ UsbPort20Afe[0].Info.Predeemp =3D 3;
+ UsbPort20Afe[0].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[1].Info.Petxiset =3D 7;
+ UsbPort20Afe[1].Info.Txiset =3D 5;
+ UsbPort20Afe[1].Info.Predeemp =3D 3;
+ UsbPort20Afe[1].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[2].Info.Petxiset =3D 7;
+ UsbPort20Afe[2].Info.Txiset =3D 5;
+ UsbPort20Afe[2].Info.Predeemp =3D 3;
+ UsbPort20Afe[2].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[3].Info.Petxiset =3D 7;
+ UsbPort20Afe[3].Info.Txiset =3D 5;
+ UsbPort20Afe[3].Info.Predeemp =3D 3;
+ UsbPort20Afe[3].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[4].Info.Petxiset =3D 7;
+ UsbPort20Afe[4].Info.Txiset =3D 5;
+ UsbPort20Afe[4].Info.Predeemp =3D 3;
+ UsbPort20Afe[4].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[5].Info.Petxiset =3D 7;
+ UsbPort20Afe[5].Info.Txiset =3D 5;
+ UsbPort20Afe[5].Info.Predeemp =3D 3;
+ UsbPort20Afe[5].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[6].Info.Petxiset =3D 7;
+ UsbPort20Afe[6].Info.Txiset =3D 5;
+ UsbPort20Afe[6].Info.Predeemp =3D 3;
+ UsbPort20Afe[6].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[7].Info.Petxiset =3D 7;
+ UsbPort20Afe[7].Info.Txiset =3D 5;
+ UsbPort20Afe[7].Info.Predeemp =3D 3;
+ UsbPort20Afe[7].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[8].Info.Petxiset =3D 7;
+ UsbPort20Afe[8].Info.Txiset =3D 5;
+ UsbPort20Afe[8].Info.Predeemp =3D 3;
+ UsbPort20Afe[8].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[9].Info.Petxiset =3D 7;
+ UsbPort20Afe[9].Info.Txiset =3D 5;
+ UsbPort20Afe[9].Info.Predeemp =3D 3;
+ UsbPort20Afe[9].Info.Pehalfbit =3D 0;
+
+ //
+ // USB Port Over Current Pin
+ //
+ PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinMax);
+
+ PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinMax);
+
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinSkip);
+
+ PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinSkip);
+
+ // USB2.0 AFE settings
+ UsbPort20Afe[0].Info.Petxiset =3D 4;
+ UsbPort20Afe[0].Info.Txiset =3D 0;
+ UsbPort20Afe[0].Info.Predeemp =3D 3;
+ UsbPort20Afe[0].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[1].Info.Petxiset =3D 4;
+ UsbPort20Afe[1].Info.Txiset =3D 0;
+ UsbPort20Afe[1].Info.Predeemp =3D 3;
+ UsbPort20Afe[1].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[2].Info.Petxiset =3D 4;
+ UsbPort20Afe[2].Info.Txiset =3D 0;
+ UsbPort20Afe[2].Info.Predeemp =3D 3;
+ UsbPort20Afe[2].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[3].Info.Petxiset =3D 4;
+ UsbPort20Afe[3].Info.Txiset =3D 0;
+ UsbPort20Afe[3].Info.Predeemp =3D 3;
+ UsbPort20Afe[3].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[4].Info.Petxiset =3D 4;
+ UsbPort20Afe[4].Info.Txiset =3D 0;
+ UsbPort20Afe[4].Info.Predeemp =3D 3;
+ UsbPort20Afe[4].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[5].Info.Petxiset =3D 4;
+ UsbPort20Afe[5].Info.Txiset =3D 0;
+ UsbPort20Afe[5].Info.Predeemp =3D 3;
+ UsbPort20Afe[5].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[6].Info.Petxiset =3D 4;
+ UsbPort20Afe[6].Info.Txiset =3D 0;
+ UsbPort20Afe[6].Info.Predeemp =3D 3;
+ UsbPort20Afe[6].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[7].Info.Petxiset =3D 4;
+ UsbPort20Afe[7].Info.Txiset =3D 0;
+ UsbPort20Afe[7].Info.Predeemp =3D 3;
+ UsbPort20Afe[7].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[8].Info.Petxiset =3D 4;
+ UsbPort20Afe[8].Info.Txiset =3D 0;
+ UsbPort20Afe[8].Info.Predeemp =3D 3;
+ UsbPort20Afe[8].Info.Pehalfbit =3D 0;
+
+ UsbPort20Afe[9].Info.Petxiset =3D 4;
+ UsbPort20Afe[9].Info.Txiset =3D 0;
+ UsbPort20Afe[9].Info.Predeemp =3D 3;
+ UsbPort20Afe[9].Info.Pehalfbit =3D 0;
+ break;
+ }
+
+ //
+ // Save USB2.0 AFE blobs
+ //
+ PcdSet32S (PcdUsb20Port0Afe, UsbPort20Afe[ 0].Blob);
+ PcdSet32S (PcdUsb20Port1Afe, UsbPort20Afe[ 1].Blob);
+ PcdSet32S (PcdUsb20Port2Afe, UsbPort20Afe[ 2].Blob);
+ PcdSet32S (PcdUsb20Port3Afe, UsbPort20Afe[ 3].Blob);
+ PcdSet32S (PcdUsb20Port4Afe, UsbPort20Afe[ 4].Blob);
+ PcdSet32S (PcdUsb20Port5Afe, UsbPort20Afe[ 5].Blob);
+ PcdSet32S (PcdUsb20Port6Afe, UsbPort20Afe[ 6].Blob);
+ PcdSet32S (PcdUsb20Port7Afe, UsbPort20Afe[ 7].Blob);
+ PcdSet32S (PcdUsb20Port8Afe, UsbPort20Afe[ 8].Blob);
+ PcdSet32S (PcdUsb20Port9Afe, UsbPort20Afe[ 9].Blob);
+ PcdSet32S (PcdUsb20Port10Afe, UsbPort20Afe[10].Blob);
+ PcdSet32S (PcdUsb20Port11Afe, UsbPort20Afe[11].Blob);
+ PcdSet32S (PcdUsb20Port12Afe, UsbPort20Afe[12].Blob);
+ PcdSet32S (PcdUsb20Port13Afe, UsbPort20Afe[13].Blob);
+ PcdSet32S (PcdUsb20Port14Afe, UsbPort20Afe[14].Blob);
+ PcdSet32S (PcdUsb20Port15Afe, UsbPort20Afe[15].Blob);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board GPIO Group Tier configuration init function for PEI pre-memory pha=
se.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+GpioGroupTierInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // GPIO Group Tier
+ //
+
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdGpioGroupToGpeDw0, GPIO_CNL_LP_GROUP_GPP_G);
+ PcdSet32S (PcdGpioGroupToGpeDw1, GPIO_CNL_LP_GROUP_SPI);
+ PcdSet32S (PcdGpioGroupToGpeDw2, GPIO_CNL_LP_GROUP_GPP_E);
+ break;
+
+ default:
+ PcdSet32S (PcdGpioGroupToGpeDw0, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw1, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw2, 0);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ GPIO init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+GpioTablePreMemInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // GPIO Table Init.
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableCmlULpddr3PreM=
em);
+ PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTableCmlULpddr3PreMemSi=
ze);
+ PcdSet32S(PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableCmlU=
Lpddr3WwanOnEarlyPreMem);
+ PcdSet16S(PcdBoardGpioTableWwanOnEarlyPreMemSize, mGpioTableCmlULpdd=
r3WwanOnEarlyPreMemSize);
+ PcdSet32S(PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableCml=
ULpddr3WwanOffEarlyPreMem);
+ PcdSet16S(PcdBoardGpioTableWwanOffEarlyPreMemSize, mGpioTableCmlULpd=
dr3WwanOffEarlyPreMemSize);
+ break;
+
+ default:
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ PmConfig init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+PchPmConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update PmCofig policy: output voltage of VCCPRIMCORE RAIL when SLP_S0=
# is asserted based on board HW design
+ // 1) Discete VR or Non Premium PMIC: 0.75V (PcdSlpS0Vm075VSupport)
+ // 2) Premium PMIC: runtime control for voltage (PcdSlpS0VmRuntimeContro=
l)
+ // Only applys to board with PCH-LP. Board with Discrete PCH doesn't nee=
d this setting.
+ //
+ switch (BoardId) {
+ // Discrete VR solution
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm075VSupport, TRUE);
+ break;
+
+ default:
+ PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm075VSupport, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/BoardSaConfigPreMem.h b/Platform/Intel/CometlakeOpenBoardPkg/Come=
tlakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h
new file mode 100644
index 0000000000..9ab340c7e1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/BoardSaConfigPreMem.h
@@ -0,0 +1,83 @@
+/** @file
+ PEI Boards Configurations for PreMem phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
+#define _BOARD_SA_CONFIG_PRE_MEM_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h> // for MRC Configurati=
on
+#include <ConfigBlock/SwitchableGraphicsConfig.h> // for PCIE RTD3 GPIO
+#include <GpioPinsCnlLp.h> // for GPIO definition
+#include <GpioPinsCnlH.h>
+#include <SaAccess.h> // for Root Port number
+#include <PchAccess.h> // for Root Port number
+
+//
+// The following section contains board-specific CMD/CTL/CLK and DQ/DQS ma=
pping, needed for LPDDR3/LPDDR4
+//
+
+//
+// DQByteMap[0] - ClkDQByteMap:
+// If clock is per rank, program to [0xFF, 0xFF]
+// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+// If clock is shared by 2 ranks but does not go to all bytes,
+// Entry[i] defines which DQ bytes Group i services
+// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN=
/CAB
+// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS=
/CAB
+// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE =
/CAB
+// For DDR, DQByteMap[3:1] =3D [0xFF, 0]
+// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have=
1 CTL / rank
+// Variable only exists to make the code eas=
ier to use
+// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have=
1 CA Vref
+// Variable only exists to make the code eas=
ier to use
+//
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for BoardIdCometLak=
eULpddr3Rvp
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapCmlULpddr3Rvp[2][6][2] =
=3D {
+ // Channel 0:
+ {
+ { 0xF0, 0x0F },
+ { 0x00, 0x0F },
+ { 0xF0, 0x0F },
+ { 0xF0, 0x00 },
+ { 0xFF, 0x00 },
+ { 0xFF, 0x00 }
+ },
+ // Channel 1:
+ {
+ { 0x0F, 0xF0 },
+ { 0x00, 0xF0 },
+ { 0x0F, 0xF0 },
+ { 0x0F, 0x00 },
+ { 0xFF, 0x00 },
+ { 0xFF, 0x00 }
+ }
+};
+
+//
+// DQS byte swizzling between CPU and DRAM - for CML-U LPDDR3 RVP
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqsMapCpu2DramCmlULpddr3Rvp[2][8=
] =3D {
+ { 5, 6, 7, 4, 1, 0, 2, 3 }, // Channel 0
+ { 2, 3, 1, 0, 6, 4, 5, 7 } // Channel 1
+};
+
+
+//
+// Reference RCOMP resistors on motherboard - for CML-U LPDDR3 RVP
+//
+const UINT16 RcompResistorCmlULpKc[SA_MRC_MAX_RCOMP] =3D { 200, 81, 162 };
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for CM=
L-U LPDDR3 RVP
+//
+const UINT16 RcompTargetCmlULpKc[SA_MRC_MAX_RCOMP_TARGETS] =3D { 100, 40, =
40, 23, 40 };
+
+#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Com=
etlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..3d5fce20d9
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/BoardSaInitPreMemLib.c
@@ -0,0 +1,383 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memo=
ry init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BoardSaConfigPreMem.h"
+#include "SaPolicyCommon.h"
+#include "CometlakeURvpInit.h"
+#include <PlatformBoardConfig.h>
+#include <Library/CpuPlatformLib.h>
+//
+// LPDDR3 178b 8Gb die, DDP, x32
+// Micron MT52L512M32D2PF-093
+// 2133, 16-20-20-45
+// 2 ranks per channel, 2 SDRAMs per rank, 4x8Gb =3D 4GB total per channel
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr3Ddp8Gb178b2133Spd[] =3D {
+ 0x24, // 512 SPD bytes used, 512 total
+ 0x01, // SPD Revision 0.1
+ 0x0F, // DRAM Type: LPDDR3 SDRAM
+ 0x0E, // Module Type: Non-DIMM Solution
+ 0x15, // 8 Banks, 8 Gb SDRAM density
+ 0x19, // 15 Rows, 10 Columns
+ 0x90, // SDRAM Package Type: DDP, 1 Channel per package
+ 0x00, // SDRAM Optional Features: none, tMAW =3D 8192 * tREFI
+ 0x00, // SDRAM Thermal / Refresh options: none
+ 0x00, // Other SDRAM Optional Features: none
+ 0x00, // Reserved
+ 0x0B, // Module Nominal Voltage, VDD =3D 1.2v
+ 0x0B, // SDRAM width: 32 bits, 2 Ranks
+ 0x03, // SDRAM bus width: 1 Channel, 64 bits channel width
+ 0x00, // Module Thermal Sensor: none
+ 0x00, // Extended Module Type: Reserved
+ 0x00, // Signal Loading: Unspecified
+ 0x00, // MTB =3D 0.125ns, FTB =3D 1 ps
+ 0x08, // tCKmin =3D 0.938 ns (LPDDR3-2133)
+ 0xFF, // tCKmax =3D 32.002 ns
+ 0xD4, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (First Byte)
+ 0x01, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Second Byte)
+ 0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Third Byte)
+ 0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Fourth Byte)
+ 0x78, // Minimum CAS Latency (tAAmin) =3D 15.008 ns
+ 0x00, // Read and Write Latency Set options: none
+ 0x90, // Minimum RAS-to-CAS delay (tRCDmin) =3D 18 ns
+ 0xA8, // Row precharge time for all banks (tRPab) =3D 21 ns
+ 0x90, // Minimum row precharge time (tRPmin) =3D 18 ns
+ 0x90, // tRFCab =3D 210 ns (8 Gb)
+ 0x06, // tRFCab MSB
+ 0xD0, // tRFCpb =3D 90 ns (8 Gb)
+ 0x02, // tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, // 33-39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 40-49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 50-59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 60-69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 70-79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 80-89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 90-99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 100-109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 110-119
+ 0x00, // FTB for Row precharge time per bank (tR=
Ppb) =3D 18 ns
+ 0x00, // FTB for Row precharge time for all bank=
s (tRPab) =3D 21 ns
+ 0x00, // FTB for Minimum RAS-to-CAS delay (tRCDm=
in) =3D 18 ns
+ 0x08, // FTB for tAAmin =3D 15.008 ns (LPDDR3-21=
33)
+ 0x7F, // FTB for tCKmax =3D 32.002 ns
+ 0xC2, // FTB for tCKmin =3D 0.938 ns (LPDDR3-213=
3)
+ 0, 0, 0, 0, // 126-129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 130-139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 140-149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 150-159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 160-169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 170-179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 180-189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 190-199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 200-209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 210-219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 220-229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 230-239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 240-249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 250-259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 260-269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 270-279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 280-289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 290-299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 300-309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 310-319
+ 0, 0, 0, 0, 0, // 320-324
+ 0x55, 0, 0, 0, // 325-328: Module ID: Module Serial Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, // 329-333: Module Part Number: Unused byt=
es coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, // 334-338: Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, // 339-343: Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, // 344-348: Module Part Number
+ 0x00, // 349 Module Revision Code
+ 0x00, // 350 DRAM Manufacturer ID Code, Least Si=
gnificant Byte
+ 0x00, // 351 DRAM Manufacturer ID Code, Most Sig=
nificant Byte
+ 0x00, // 352 DRAM Stepping
+ 0, 0, 0, 0, 0, 0, 0, // 353 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 430 - 439
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 440 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 500 - 509
+ 0, 0 // 510 - 511
+};
+
+//
+// Display DDI settings for WHL ERB
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mWhlErbRowDisplayDdiConfig[9] =
=3D {
+ DdiPortAEdp, // DDI Port A Config : DdiPortADisabled =3D Disabled, D=
diPortAEdp =3D eDP, DdiPortAMipiDsi =3D MIPI DSI
+ DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable =3D Disable, DdiHpdEn=
able =3D Enable HPD
+ DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable =3D Disable, DdiHpdEn=
able =3D Enable HPD
+ DdiHpdDisable, // DDI Port D HPD : DdiHpdDisable =3D Disable, DdiHpdEn=
able =3D Enable HPD
+ DdiHpdDisable, // DDI Port F HPD : DdiHpdDisable =3D Disable, DdiHpdEn=
able =3D Enable HPD
+ DdiDdcEnable, // DDI Port B DDC : DdiDisable =3D Disable, DdiDdcEnabl=
e =3D Enable DDC
+ DdiDdcEnable, // DDI Port C DDC : DdiDisable =3D Disable, DdiDdcEnabl=
e =3D Enable DDC
+ DdiDdcEnable, // DDI Port D DDC : DdiDisable =3D Disable, DdiDdcEnabl=
e =3D Enable DDC
+ DdiDisable // DDI Port F DDC : DdiDisable =3D Disable, DdiDdcEnabl=
e =3D Enable DDC
+};
+
+/**
+ MRC configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaMiscConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // UserBd
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ //
+ // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUs=
er4 for ULT platforms.
+ // This is required to skip Memory voltage programming based on GPIO=
's in MRC
+ //
+ PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platf=
orm
+ break;
+
+ default:
+ // MiscPeiPreMemConfig.UserBd =3D 0 by default.
+ break;
+ }
+
+ PcdSet16S (PcdSaDdrFreqLimit, 0);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board Memory Init related configuration init function for PEI pre-memory=
phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+MrcConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ CPU_FAMILY CpuFamilyId;
+
+ CpuFamilyId =3D GetCpuFamily();
+
+ if (CpuFamilyId =3D=3D EnumCpuCflDtHalo) {
+ PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
+ } else {
+ PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE);
+ }
+
+ //
+ // Example policy for DIMM slots implementation boards:
+ // 1. Assign Smbus address of DIMMs and SpdData will be updated later
+ // by reading from DIMM SPD.
+ // 2. No need to apply hardcoded SpdData buffers here for such board.
+ //
+ // Comet Lake U LP3 has removable DIMM slots.
+ // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to =
0.
+ // Example:
+ // PcdMrcSpdData =3D 0
+ // PcdMrcSpdDataSize =3D 0
+ // PcdMrcSpdAddressTable0 =3D 0xA0
+ // PcdMrcSpdAddressTable1 =3D 0xA2
+ // PcdMrcSpdAddressTable2 =3D 0xA4
+ // PcdMrcSpdAddressTable3 =3D 0xA6
+ //
+ // If a board has soldered down memory. It should use the following set=
tings.
+ // Example:
+ // PcdMrcSpdAddressTable0 =3D 0
+ // PcdMrcSpdAddressTable1 =3D 0
+ // PcdMrcSpdAddressTable2 =3D 0
+ // PcdMrcSpdAddressTable3 =3D 0
+ // PcdMrcSpdData =3D static data buffer
+ // PcdMrcSpdDataSize =3D sizeof (static data buffer)
+ //
+
+ //
+ // SPD Address Table
+ //
+ PcdSet32S (PcdMrcSpdData, (UINTN)mLpddr3Ddp8Gb178b2133Spd);
+ PcdSet16S (PcdMrcSpdDataSize, sizeof(mLpddr3Ddp8Gb178b2133Spd));
+ PcdSet8S (PcdMrcSpdAddressTable0, 0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0);
+ PcdSet8S (PcdMrcSpdAddressTable2, 0);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0);
+
+ //
+ // DRAM SPD Data & related configuration
+ //
+ // Setting the PCD's to default value (CML LP3). It will be overriden to=
board specific settings below.
+ PcdSet32S(PcdMrcDqByteMap, (UINTN) DqByteMapCmlULpddr3Rvp);
+ PcdSet16S (PcdMrcDqByteMapSize, sizeof (DqByteMapCmlULpddr3Rvp));
+ PcdSet32S(PcdMrcDqsMapCpu2Dram, (UINTN) DqsMapCpu2DramCmlULpddr3Rvp);
+ PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (DqsMapCpu2DramCmlULpddr3Rvp=
));
+
+ switch (BoardId) {
+
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorCmlULpKc);
+ PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetCmlULpKc);
+ PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE);
+ PcdSetBoolS(PcdMrcDqPinsInterleaved, FALSE);
+ break;
+
+ default:
+ break;
+ }
+
+ //
+ // CA Vref routing: board-dependent
+ // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
+ // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
+ // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards
+ break;
+
+ default:
+ PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board SA related GPIO configuration init function for PEI pre-memory pha=
se.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaGpioConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update board's GPIO for PEG slot reset
+ //
+ PcdSetBoolS (PcdPegGpioResetControl, TRUE);
+ PcdSetBoolS (PcdPegGpioResetSupoort, FALSE);
+ PcdSet32S (PcdPeg0ResetGpioPad, 0);
+ PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE);
+ PcdSet32S (PcdPeg3ResetGpioPad, 0);
+ PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE);
+
+ //
+ // PCIE RTD3 GPIO
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S(PcdRootPortIndex, 4);
+ PcdSet8S (PcdPcie0GpioSupport, PchGpio);
+ PcdSet32S (PcdPcie0WakeGpioNo, 0);
+ PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15);
+ PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14);
+ PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie1GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie1WakeGpioNo, 0);
+ PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie2GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie2WakeGpioNo, 0);
+ PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
+ break;
+
+ default:
+ PcdSet8S(PcdRootPortIndex, 0xFF);
+ PcdSet8S (PcdPcie0GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie0WakeGpioNo, 0);
+ PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie0HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie0PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie1GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie1WakeGpioNo, 0);
+ PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie2GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie2WakeGpioNo, 0);
+ PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ SA Display DDI configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaDisplayConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update Display DDI Config
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mWhlErbRowDisplayDdiConf=
ig);
+ PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mWhlErbRowDisplayDdi=
Config));
+ break;
+
+ default:
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/CometlakeURvpHsioPtssTables.c b/Platform/Intel/CometlakeOpenBoard=
Pkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpHsioPtssTables.c
new file mode 100644
index 0000000000..15fc18c7ae
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/CometlakeURvpHsioPtssTables.c
@@ -0,0 +1,32 @@
+/** @file
+ CometlakeURvp HSIO PTSS H File
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef COMETLAKE_RVP3_HSIO_PTSS_H_
+#define COMETLAKE_RVP3_HSIO_PTSS_H_
+
+#include <PchHsioPtssTables.h>
+
+#ifndef HSIO_PTSS_TABLE_SIZE
+#define HSIO_PTSS_TABLE_SIZE(A) A##_Size =3D sizeof (A) / sizeof (HSIO_PTS=
S_TABLES)
+#endif
+
+//BoardId CometlakeURvp
+HSIO_PTSS_TABLES PchLpHsioPtss_Cx_CometlakeURvp[] =3D {
+ {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0}
+};
+
+UINT16 PchLpHsioPtss_Cx_CometlakeURvp_Size =3D sizeof(PchLpHsioPtss_Cx_Com=
etlakeURvp) / sizeof(HSIO_PTSS_TABLES);
+
+HSIO_PTSS_TABLES PchLpHsioPtss_Bx_CometlakeURvp[] =3D {
+ {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0},
+};
+
+UINT16 PchLpHsioPtss_Bx_CometlakeURvp_Size =3D sizeof(PchLpHsioPtss_Bx_Com=
etlakeURvp) / sizeof(HSIO_PTSS_TABLES);
+
+#endif // COMETLAKE_RVP_HSIO_PTSS_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/CometlakeURvpInit.h b/Platform/Intel/CometlakeOpenBoardPkg/Cometl=
akeURvp/Library/BoardInitLib/CometlakeURvpInit.h
new file mode 100644
index 0000000000..cbfa60907c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/CometlakeURvpInit.h
@@ -0,0 +1,41 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _COMET_LAKE_U_RVP_INIT_H_
+#define _COMET_LAKE_U_RVP_INIT_H_
+
+#include <Uefi.h>
+#include <IoExpander.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/SiliconInitLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchHsioPtssTables.h>
+
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_CometlakeURvp[];
+extern UINT16 PchLpHsioPtss_Bx_CometlakeURvp_Size;
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_CometlakeURvp[];
+extern UINT16 PchLpHsioPtss_Cx_CometlakeURvp_Size;
+
+
+extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3PreMem[];
+extern UINT16 mGpioTableCmlULpddr3PreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOnEarlyPreMem[];
+extern UINT16 mGpioTableCmlULpddr3WwanOnEarlyPreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOffEarlyPreMem[];
+extern UINT16 mGpioTableCmlULpddr3WwanOffEarlyPreMemSize;
+
+extern GPIO_INIT_CONFIG mGpioTableDefault[];
+extern UINT16 mGpioTableDefaultSize;
+extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3[];
+extern UINT16 mGpioTableCmlULpddr3Size;
+
+#endif // _COMET_LAKE_U_LP3_INIT_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/GpioTableCmlUlpddr3PreMem.c b/Platform/Intel/CometlakeOpenBoardPk=
g/CometlakeURvp/Library/BoardInitLib/GpioTableCmlUlpddr3PreMem.c
new file mode 100644
index 0000000000..9becd139e6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/GpioTableCmlUlpddr3PreMem.c
@@ -0,0 +1,43 @@
+/** @file
+ GPIO definition table for Comet Lake U LP3 RVP Pre-Memory
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <GpioPinsCnlLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+
+GPIO_INIT_CONFIG mGpioTableCmlULpddr3PreMem[] =3D
+{
+ {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R=
ST_N
+ {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_P=
WREN_N
+ {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA=
ND_RST_N
+ {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA=
ND_PWREN_N
+};
+UINT16 mGpioTableCmlULpddr3PreMemSize =3D sizeof (mGpioTableCmlULpddr3PreM=
em) / sizeof (GPIO_INIT_CONFIG);
+
+GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOnEarlyPreMem[] =3D
+{
+ // Turn on WWAN power and de-assert reset pins by default
+ {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn=
v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu2=
0K, GpioPadConfigUnlock}}, //WWAN_WAKE_N
+ {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone=
, GpioOutputStateUnlock}}, //WWAN_FCP_OFF
+ {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone=
, GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS
+ {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone=
, GpioOutputStateUnlock}}, //WWAN_PERST
+ {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone=
, GpioOutputStateUnlock}}, //WWAN_RST_N
+ {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone=
, GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL
+ {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone=
, GpioOutputStateUnlock}}, //WWAN_DISABLE_N
+};
+UINT16 mGpioTableCmlULpddr3WwanOnEarlyPreMemSize =3D sizeof(mGpioTableCmlU=
Lpddr3WwanOnEarlyPreMem) / sizeof(GPIO_INIT_CONFIG);
+
+
+GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOffEarlyPreMem[] =3D
+{
+ // Assert reset pins and then turn off WWAN power
+ {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone=
, GpioOutputStateUnlock}}, //WWAN_RST_N
+ {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone=
, GpioOutputStateUnlock}}, //WWAN_PERST
+ {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone=
, GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS
+};
+UINT16 mGpioTableCmlULpddr3WwanOffEarlyPreMemSize =3D sizeof(mGpioTableCml=
ULpddr3WwanOffEarlyPreMem) / sizeof(GPIO_INIT_CONFIG);
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/GpioTableCometlakeULpddr3Rvp.c b/Platform/Intel/CometlakeOpenBoar=
dPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCometlakeULpddr3Rvp.c
new file mode 100644
index 0000000000..a0b466ba01
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/GpioTableCometlakeULpddr3Rvp.c
@@ -0,0 +1,254 @@
+/** @file
+ GPIO definition table for Comet Lake U LP3 RVP
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include <GpioPinsCnlLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+
+GPIO_INIT_CONFIG mGpioTableCmlULpddr3[] =3D
+{
+// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, =
GPIRoutConfig, PadRstCfg, Term,
+ //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }},
+ //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_IO_0
+ //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_IO_1
+ //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_IO_2
+ //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_IO_2
+ //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_CSB
+ //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //GPPC_A6_SERIRQ
+ // TPM interrupt
+ {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi=
oOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K,=
GpioPadConfigUnlock }}, //SPI_TPM_INT_N
+ //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }},
+ //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwn=
Gpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset=
, GpioTermNone }}, //eSPI_CLK
+ //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi=
oDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTer=
mNone }},
+ //{GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn=
Inv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTe=
rmWpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N
+ // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, Gp=
ioTermNone }}, //SLATEMODE_HALLOUT
+ {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp=
ioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL=
_SLOT1
+ //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOw=
nGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRese=
t, GpioTermNone }}, //eSPI_Reset
+ {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SP=
KR_PD_N
+ //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermNone }}, //SD_PWREN
+ //A18-A23 -> Under GPIO table for GPIO Termination -20K WPU
+ {GPIO_CNL_LP_GPP_A18, { GpioHardwareDefault, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW=
pu20K }}, //ACCEL_INT
+ {GPIO_CNL_LP_GPP_A19, { GpioHardwareDefault, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW=
pu20K }}, //ALS_INT
+ {GPIO_CNL_LP_GPP_A20, { GpioHardwareDefault, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW=
pu20K }}, //HUMAN_PRESENCE_INT
+ {GPIO_CNL_LP_GPP_A21, { GpioHardwareDefault, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW=
pu20K }}, //HALL_SENSOR_INT
+ {GPIO_CNL_LP_GPP_A22, { GpioHardwareDefault, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW=
pu20K }}, //IVCAM_WAKE
+ {GPIO_CNL_LP_GPP_A23, { GpioHardwareDefault, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW=
pu20K }}, //SHARED_INT
+ //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe=
rmNone }}, //CORE_VID0
+ //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe=
rmNone }}, //CORE_VID0
+ {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio=
OutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, Gp=
ioPadUnlock }}, //FORCE_PAD_INT
+ {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gpi=
oOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioOutputStateUnlo=
ck} }, //BT_DISABLE_N
+ //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //WWAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //PCIE_NAND_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //LAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //WLAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //PCIE_SLOT1_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ
+ {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }},
+ //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa=
ult, GpioTermNone }}, //PM_SLP_S0_N
+ //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa=
ult, GpioTermNone }}, //PLT_RST_N
+ {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_=
PWR_EN
+ //B15 -Unused pin -> Under GPIO table for GPIO Termination - Input sensi=
ng disable
+ {GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi=
oOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, G=
pioPadConfigUnlock } }, //FPS_INT_N
+ {GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp=
ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock=
} }, //FPS_RESET_N
+ // B15 -Unused pin -> No Reboot Straps
+ //{GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // NO_REBOOT
+ //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GSPI1_CS_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GSPI1_CLK_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GSPI1_MISO_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GSPI1_MOSI_FPS
+ {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOu=
t, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone, GpioPa=
dUnlock }}, //EC_SLP_S0_CS_N
+ //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset=
, GpioTermNone }}, //SMB_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset=
, GpioTermNone }}, //SMB_DATA
+ {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioOutputStat=
eUnlock }}, //WIFI_RF_KILL_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermNone }}, //SML0_CLK
+ //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermNone }}, //SML0_DATA
+ {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,=
GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTerm=
None, GpioPadConfigUnlock }}, //WIFI_WAKE_N
+ //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefaul=
t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp=
ioTermNone }},
+ //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefaul=
t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp=
ioTermNone }},
+ {GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio , GpioDirIn , Gp=
ioOutDefault , GpioIntLevel | GpioIntApic , GpioPlatformReset, GpioTermWpu2=
0K }}, //CODEC_INT_N
+ {GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, G=
pioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K, GpioPadConfig=
Unlock }}, //TBT_CIO_PLUG_EVENT_N
+ {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUn=
lock }}, //TBT_FORCE_PWR
+ //move to premem phase for early power turn on
+ // {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir=
Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE=
_NAND_RST_N
+ // {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir=
Out, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCI=
E_NAND_PWREN_N
+ // {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir=
Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT=
1_PWREN_N
+ // {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir=
Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT=
1_RST_N
+
+ //Only clear Reset pins in Post-Mem
+ {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA=
ND_RST_N
+
+ //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //I2C0_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //I2C0_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //I2C1_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //I2C1_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //UART2_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //UART2_TXD
+ //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //UART2_RTS
+ //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //UART2_CTS
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //SPI1_TCH_PNL_CS0_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //SPI1_TCH_PNL_CLK_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //SPI1_TCH_PNL_MISO
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //SPI1_TCH_PNL_MOSI
+ //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRes=
et, GpioTermNone }}, //IMGCLKOUT
+ //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //ISH_I2C0_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //ISH_I2C0_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //ISH_I2C1_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //ISH_I2C1_SCL
+ {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL=
2_RST_N
+ {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, =
GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermN=
one, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N
+ {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn=
v , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioHostDeepReset, GpioTe=
rmWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N
+ //(Not used) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio,=
GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermN=
one }}, //Former NFC_RST_N
+ //{GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu=
t, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PW=
REN
+ {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PN=
L_RST_N
+ //(Not used) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio,=
GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //Former NFC_INT_N
+ //{GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn=
, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermN=
one, GpioPadConfigUnlock }}, //WIGIG_WAKE_N
+ //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //DMIC_CLK_1
+ //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //DMIC_DATA_1
+ //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //DMIC_CLK_0
+ //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //DMIC_DATA_0
+ //(CSME control) {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostO=
wnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //SPI1_TCH_PNL_IO2
+ //(CSME control) {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostO=
wnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //SPI1_TCH_PNL_IO3
+ //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset,=
GpioTermNone }}, //SSP_MCLK
+ //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, =
GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, =
GpioTermWpu20K }}, //Reserved for SATA/PCIE detect
+ //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnG=
pio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformRe=
set, GpioTermNone }}, //M.2_SSD_DET
+ {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, =
GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Rese=
rved for SATA HP val
+ {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, =
GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone,=
GpioPadUnlock}}, //EC_SMI_N
+ {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, =
GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone=
, GpioPadConfigUnlock }}, //DGPU_PWROK
+ //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla=
tformReset, GpioTermNone }}, //SSD_DEVSLP
+ //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla=
tformReset, GpioTermNone }}, //HDD_DEVSLP
+ {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn=
, GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTe=
rmNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N
+ //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefa=
ult, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset,=
GpioTermNone }}, //SATA_LED_N
+ //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefa=
ult, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gpi=
oTermNone }}, //BSSB_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDef=
ault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp=
ioTermNone }}, //BSSB_DI
+ //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //USB_OC_2
+ //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //USB_OC_3
+ //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI1_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI2_HPD_EC
+ //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI3_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //EDP_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI1_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI1_CTRL_DATA
+ //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI2_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI2_CTRL_DATA
+ //F0- unused pin-Input Sensing disable F4-F7 -> Under GPIO table for GP=
IO Termination -20K WPU
+ {GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNo=
ne, GpioOutHigh, GpioIntLevel, GpioResumeReset, GpioTermNone }}, //GPP=
_F0_COEX3
+ //{GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N
+ {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K }}, //S=
ATA_HDD_PWREN
+ {GPIO_CNL_LP_GPP_F4, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //CNV_BRI_DT_UART0_RTSB
+ {GPIO_CNL_LP_GPP_F5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //CNV_BRI_RSP_UART0_RXD
+ {GPIO_CNL_LP_GPP_F6, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //CNV_RGI_DT_UART0_TXD
+ {GPIO_CNL_LP_GPP_F7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //CNV_RGI_RSP_UART0_CTSB
+ //{GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW=
pu20K }}, //CNV_MFUART2_RXD
+ //{GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW=
pu20K }}, //CNV_MFUART2_TXD
+
+ //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be=
used at IsRecoveryMode()
+ {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, =
GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K}}, /=
/BIOS_REC
+
+ //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F11_EMMC_CMD
+ //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F12_EMMC_DATA0
+ //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F13_EMMC_DATA1
+ //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F14_EMMC_DATA2
+ //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F15_EMMC_DATA3
+ //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F16_EMMC_DATA4
+ //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F17_EMMC_DATA5
+ //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F18_EMMC_DATA6
+ //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F19_EMMC_DATA7
+ //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F20_EMMC_RCLK
+ //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F21_EMMC_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F22_EMMC_RESETB
+ //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi=
oDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTerm=
None }}, //GPP_F_23
+ //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_0_SD3_CMD
+ //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P
+ //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N
+ //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_3_SD3_D2
+ //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_4_SD3_D3
+ {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //GPP_G_5_SD3_CDB
+ //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNone }}, //GPP_G_6_SD3_CLK
+ {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
d20K }}, //GPP_G_7_SD3_WP
+ //@todo - GPP-H0-3 are connected to M2 slot for discrete/integrated CNV =
solution, dynamic detection should be done before programming. For CNVi, RC=
will configure pins //Platform: RestrictedContent
+ //H0-H3 -> Under GPIO table for GPIO Termination -20K WPU
+ {GPIO_CNL_LP_GPP_H0, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //GPP_H_0_SSP2_SCLK
+ {GPIO_CNL_LP_GPP_H1, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //GPP_H_1_SSP2_SFRM
+ {GPIO_CNL_LP_GPP_H2, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //GPP_H_2_SSP2_TXD
+ {GPIO_CNL_LP_GPP_H3, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //GPP_H_3_SSP2_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_4_I2C2_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_5_I2C2_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_6_I2C3_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_7_I2C3_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_8_I2C4_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_9_I2C4_SCL
+ {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV=
CAM_PWREN
+ {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV=
CAM_RECOVERY
+ {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV=
CAM_MUX_SEL0
+ {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I=
VCAM_KEY
+ //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDe=
fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //DDI4_CTRL_CLK
+ //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDe=
fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //DDI4_CTRL_DATA
+ //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOw=
nGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //VCCIO_LPM
+ {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I=
VCAM_MUX_SEL1
+ //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDe=
fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GPP_H21
+ //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDe=
fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GPP_H23
+ //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_BATLOW_N
+ //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //BC_ACOK
+ //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //LAN_WAKE
+ //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_PWRBTN_N
+ //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_SLP_S3_N
+ //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_SLP_S4_N
+ //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //SLP_A_N
+ //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDi=
rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon=
e }}, //GPD_7
+ //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //SUS_CLK
+ //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_SLP_WLAN_N
+ //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnG=
pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_SLP_S5_N
+ //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnG=
pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //LANPHY_EN
+ {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDir=
Default, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd=
20K }}, // 20K PD for PECI
+ //
+ // CML Delta GPIO Start
+ //
+
+ // Bluetooth start
+ {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi=
oOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, G=
pioPadUnlock } }, //BT_UART_WAKE
+ // Bluetooth end
+
+ // VRALERT start
+ //(RC control) {GPIO_CNL_LP_GPP_B2,{ GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //VRALERT
+ // VRALERT end
+
+ // Camera start
+ {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioD=
irOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,=
GpioTermNone }}, //Camera / IRIS_STROBE on CNL U
+ {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioD=
irOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,=
GpioTermNone }}, //Camera / UF_CAM_PRIVACY_LED on CNL U
+ {GPIO_CNL_LP_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset,=
GpioTermNone }}, //Camera / RC Control on CNL U
+ {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //WRF_IMG=
_RST2
+ {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioD=
irOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, Gp=
ioTermWpu20K }}, //WRF_IMG_PWR0_ENABLE
+ {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioD=
irOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,=
GpioTermWpu20K }}, //WRF_IMG_PWR1_ENABLE
+ {GPIO_CNL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, // WRF_IM=
G_PWR_CTRL
+ {GPIO_CNL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, // WRF_IM=
G_PWR2_ENABLE
+ // Below is commented since D16 is used for EN_V3.3A_WWAN_LS, so cannot =
be used for Camera HDR now.
+ // This need to be corrected in SR'19 SKU schematic to us eit for Camera=
HDR.
+ //{GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, Gpi=
oDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformRese=
t, GpioTermWpu20K }}, //WRF_IMG_CLK_ENABLE
+ // Camera end
+
+ // x4 slot start
+ {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R=
ST_N
+ // x4 slot end
+
+ // TBT Start
+ { GPIO_CNL_LP_GPP_D15,{ GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp=
ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //TBT_CIO_PWR_=
EN
+ // TBT End
+
+ // EC
+ { GPIO_CNL_LP_GPP_E16,{ GpioPadModeGpio, GpioHostOwnAcpi, GpioDi=
rInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, Gpi=
oTermWpu20K, GpioPadConfigUnlock } }, //SMC_RUNTIME_SCI_N
+ // Unused start
+ {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioD=
irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset,=
GpioTermWpu20K }}, //Unused so disabled / WF_CLK_EN on CNL U
+ // Unused end
+
+ //
+ // CML Delta GPIO End
+ //
+};
+
+UINT16 mGpioTableCmlULpddr3Size =3D sizeof (mGpioTableCmlULpddr3) / sizeof=
(GPIO_INIT_CONFIG);
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/GpioTableDefault.c b/Platform/Intel/CometlakeOpenBoardPkg/Cometla=
keURvp/Library/BoardInitLib/GpioTableDefault.c
new file mode 100644
index 0000000000..9cc8b50023
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/GpioTableDefault.c
@@ -0,0 +1,213 @@
+/** @file
+ GPIO definition table
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <GpioPinsCnlLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+//
+// CNL U DRR4 Board GPIO table configuration is used as default
+//
+GPIO_INIT_CONFIG mGpioTableDefault[] =3D
+{
+// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, =
GPIRoutConfig, PadRstCfg, Term,
+ //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }},
+ //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_IO_0
+ //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_IO_1
+ //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_IO_2
+ //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_IO_2
+ //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //eSPI_CSB
+ //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //GPPC_A6_SERIRQ
+ {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, =
GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpu=
20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N
+ //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }},
+ //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwn=
Gpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset=
, GpioTermNone }}, //eSPI_CLK
+ //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi=
oDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTer=
mNone }},
+ {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn=
v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTerm=
Wpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N
+ // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, Gp=
ioTermNone }}, //SLATEMODE_HALLOUT
+ {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp=
ioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL=
_SLOT1
+ //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOw=
nGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRese=
t, GpioTermNone }}, //eSPI_Reset
+ {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SP=
KR_PD_N
+ {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WFC=
AM_PWREN
+ //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermNone }}, //SD_PWREN
+ //(RC control) {GPIO_CNL_LP_GPP_A18, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermWpu20K }}, //ACCEL_INT
+ //(RC control) {GPIO_CNL_LP_GPP_A19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermWpu20K }}, //ALS_INT
+ //(RC control) {GPIO_CNL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermWpu20K }}, //HUMAN_PRESENCE_INT
+ //(RC control) {GPIO_CNL_LP_GPP_A21, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermWpu20K }}, //HALL_SENSOR_INT
+ //(RC control) {GPIO_CNL_LP_GPP_A22, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //IVCAM_WAKE
+ //(RC control) {GPIO_CNL_LP_GPP_A23, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermWpu20K }}, //SHARED_INT
+ //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe=
rmNone }}, //CORE_VID0
+ //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe=
rmNone }}, //CORE_VID0
+ {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio=
OutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, Gp=
ioPadConfigUnlock | GpioOutputStateUnlock } }, //BT_UART_WAKE
+ {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio=
OutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, Gp=
ioPadConfigUnlock | GpioOutputStateUnlock }}, //FORCE_PAD_INT
+ {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gpi=
oOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioPadConfigUnlock=
} }, //BT_DISABLE_N
+ //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //WWAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //PCIE_NAND_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //LAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //WLAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //PCIE_SLOT1_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ
+ {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }},
+ //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa=
ult, GpioTermNone }}, //PM_SLP_S0_N
+ //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa=
ult, GpioTermNone }}, //PLT_RST_N
+ {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_=
PWR_EN
+ //(CSME Pad) {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefau=
lt, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNon=
e }}, //NFC_DFU
+ { GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp=
ioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, =
GpioPadConfigUnlock } }, //FPS_INT_N
+ { GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G=
pioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnloc=
k} }, //FPS_RESET_N
+ {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp=
ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TBT_CIO_PWR_EN
+ //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GSPI1_CS_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GSPI1_CLK_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GSPI1_MISO_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GSPI1_MOSI_FPS
+ {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOu=
t, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone}}, //E=
C_SLP_S0_CS_N
+ //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset=
, GpioTermNone }}, //SMB_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset=
, GpioTermNone }}, //SMB_DATA
+ {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone }}, //WIFI_RF_=
KILL_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermNone }}, //SML0_CLK
+ //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, =
GpioTermNone }}, //SML0_DATA
+ {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,=
GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTerm=
None, GpioPadConfigUnlock }}, //WIFI_WAKE_N
+ //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefaul=
t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp=
ioTermNone }},
+ //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefaul=
t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp=
ioTermNone }},
+ { GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, =
GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu2=
0K } }, //CODEC_INT_N
+ { GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, =
GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K=
, GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N
+ {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //TBT_=
FORCE_PWR
+ {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,=
GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermWpu2=
0K, GpioPadConfigUnlock } }, //IVCAM_WAKE_N
+ {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAN=
D_RST_N
+ {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA=
ND_PWREN_N
+ {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PW=
REN_N
+ {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R=
ST_N
+ //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //I2C0_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //I2C0_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //I2C1_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //I2C1_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //UART2_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //UART2_TXD
+ //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //UART2_RTS
+ //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //UART2_CTS
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //SPI1_TCH_PNL_CS0_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //SPI1_TCH_PNL_CLK_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //SPI1_TCH_PNL_MISO
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDef=
ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //SPI1_TCH_PNL_MOSI
+ //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRes=
et, GpioTermNone }}, //IMGCLKOUT
+ //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //ISH_I2C0_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //ISH_I2C0_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //ISH_I2C1_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset=
, GpioTermNone }}, //ISH_I2C1_SCL
+ {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL=
2_RST_N
+ {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, =
GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermN=
one, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N
+ {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn=
v , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioPlatformReset, GpioTe=
rmWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio,=
GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermN=
one }}, //NFC_RST_N
+ {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PWREN
+ {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PN=
L_RST_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio,=
GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //NFC_INT_N
+ {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, =
GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNon=
e, GpioPadConfigUnlock }}, //WIGIG_WAKE_N
+ //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //DMIC_CLK_1
+ //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //DMIC_DATA_1
+ //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //DMIC_CLK_0
+ //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //DMIC_DATA_0
+ {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnDefault, GpioD=
irInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNon=
e }}, //SPI1_TCH_PNL_IO2
+ {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnDefault, GpioD=
irInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNon=
e }}, //SPI1_TCH_PNL_IO3
+ //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset,=
GpioTermNone }}, //SSP_MCLK
+ //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, =
GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, =
GpioTermWpu20K }}, //Reserved for SATA/PCIE detect
+ //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnG=
pio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformRe=
set, GpioTermNone }}, //M.2_SSD_DET
+ {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, =
GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Rese=
rved for SATA HP val
+ {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, =
GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone}=
}, //EC_SMI_N
+ {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, =
GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone=
, GpioPadConfigUnlock }}, //DGPU_PWROK
+ //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla=
tformReset, GpioTermNone }}, //SSD_DEVSLP
+ //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla=
tformReset, GpioTermNone }}, //HDD_DEVSLP
+ {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn=
, GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTe=
rmNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N
+ //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefa=
ult, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset,=
GpioTermNone }}, //SATA_LED_N
+ //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefa=
ult, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gpi=
oTermNone }}, //BSSB_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDef=
ault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp=
ioTermNone }}, //BSSB_DI
+ //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //USB_OC_2
+ //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe=
set, GpioTermNone }}, //USB_OC_3
+ //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI1_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI2_HPD_EC
+ //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI3_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI4_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //EDP_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI1_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI1_CTRL_DATA
+ //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI2_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI2_CTRL_DATA
+ //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI3_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //DDI3_CTRL_DATA
+ //(Not used){GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault=
, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTe=
rmNone }}, //GPP_F0_COEX3
+ {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp=
ioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N
+ {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SAT=
A_HDD_PWREN
+ {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, =
GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF_C=
LK_EN
+ //(RC control) {GPIO_CNL_LP_GPP_F4, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul=
t, GpioTermNone }}, //CNV_BRI_DT_UART0_RTSB
+ //(RC control) {GPIO_CNL_LP_GPP_F5, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul=
t, GpioTermNone }}, //CNV_BRI_RSP_UART0_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_F6, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul=
t, GpioTermNone }}, //CNV_RGI_DT_UART0_TXD
+ //(RC control) {GPIO_CNL_LP_GPP_F7, { GpioPadModeNative1, GpioHostOwnD=
efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul=
t, GpioTermNone }}, //CNV_RGI_RSP_UART0_CTSB
+ {GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDi=
rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon=
e }}, //CNV_MFUART2_RXD
+ {GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDi=
rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon=
e }}, //CNV_MFUART2_TXD
+
+ //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be=
used at IsRecoveryMode()
+ {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, =
GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //B=
IOS_REC
+
+ //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F11_EMMC_CMD
+ //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F12_EMMC_DATA0
+ //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F13_EMMC_DATA1
+ //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F14_EMMC_DATA2
+ //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F15_EMMC_DATA3
+ //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F16_EMMC_DATA4
+ //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F17_EMMC_DATA5
+ //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F18_EMMC_DATA6
+ //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F19_EMMC_DATA7
+ //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F20_EMMC_RCLK
+ //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F21_EMMC_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOw=
nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR=
eset, GpioTermNone }}, //GPP_F22_EMMC_RESETB
+ //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi=
oDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTerm=
None }}, //GPP_F_23
+ //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_0_SD3_CMD
+ //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P
+ //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N
+ //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_3_SD3_D2
+ //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNative }}, //GPP_G_4_SD3_D3
+ {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
u20K }}, //GPP_G_5_SD3_CDB
+ //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau=
lt, GpioTermNone }}, //GPP_G_6_SD3_CLK
+ {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD=
irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp=
d20K }}, //GPP_G_7_SD3_WP
+ //{GPIO_CNL_LP_GPP_H0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //GPP_H_0_SSP2_SCLK
+ //{GPIO_CNL_LP_GPP_H1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //GPP_H_1_SSP2_SFRM
+ //{GPIO_CNL_LP_GPP_H2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //GPP_H_2_SSP2_TXD
+ //{GPIO_CNL_LP_GPP_H3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio=
DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm=
None }}, //GPP_H_3_SSP2_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_4_I2C2_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_5_I2C2_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_6_I2C3_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_7_I2C3_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_8_I2C4_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //GPP_H_9_I2C4_SCL
+ {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV=
CAM_PWREN
+ {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV=
CAM_RECOVERY
+ {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IR=
IS_STROBE
+ {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV=
CAM_MUX_SEL0
+ {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadU=
nlock }}, //UF_CAM_PRIVACY_LED
+ {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I=
VCAM_KEY
+ //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDe=
fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //DDI4_CTRL_CLK
+ //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDe=
fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //DDI4_CTRL_DATA
+ //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOw=
nGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, =
GpioTermNone }}, //VCCIO_LPM
+ {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I=
VCAM_MUX_SEL1
+ //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeNative1, GpioHostOwn=
Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe=
set, GpioTermNone }}, //IMGCLKOUT_WF_CAM
+ //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDe=
fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GPP_H21
+ {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,=
GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF=
_CAM_RST
+ //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDe=
fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese=
t, GpioTermNone }}, //GPP_H23
+ //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_BATLOW_N
+ //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //BC_ACOK
+ //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //LAN_WAKE
+ //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_PWRBTN_N
+ //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_SLP_S3_N
+ //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_SLP_S4_N
+ //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //SLP_A_N
+ //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDi=
rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon=
e }}, //GPD_7
+ //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //SUS_CLK
+ //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGp=
io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_SLP_WLAN_N
+ //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnG=
pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //PM_SLP_S5_N
+ //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnG=
pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, =
GpioTermNone }}, //LANPHY_EN
+ {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDir=
Default, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd=
20K }}, // 20K PD for PECI
+};
+UINT16 mGpioTableDefaultSize =3D sizeof (mGpioTableDefault) / sizeof (GPIO=
_INIT_CONFIG);
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PchHdaVerbTables.h b/Platform/Intel/CometlakeOpenBoardPkg/Cometla=
keURvp/Library/BoardInitLib/PchHdaVerbTables.h
new file mode 100644
index 0000000000..2e4bef3246
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PchHdaVerbTables.h
@@ -0,0 +1,3014 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_HDA_VERB_TABLES_H_
+#define _PCH_HDA_VERB_TABLES_H_
+
+#include <Ppi/SiPolicy.h>
+
+HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: CFL Display Audio Codec
+ // Revision ID =3D 0xFF
+ // Codec Vendor: 0x8086280B
+ //
+ 0x8086, 0x280B,
+ 0xFF, 0xFF,
+ //
+ // Display Audio Verb Table
+ //
+ // For GEN9, the Vendor Node ID is 08h
+ // Port to be exposed to the inbox driver in the vanilla mode: PORT C - =
BIT[7:6] =3D 01b
+ 0x00878140,
+ // Pin Widget 5 - PORT B - Configuration Default: 0x18560010
+ 0x00571C10,
+ 0x00571D00,
+ 0x00571E56,
+ 0x00571F18,
+ // Pin Widget 6 - PORT C - Configuration Default: 0x18560020
+ 0x00671C20,
+ 0x00671D00,
+ 0x00671E56,
+ 0x00671F18,
+ // Pin Widget 7 - PORT D - Configuration Default: 0x18560030
+ 0x00771C30,
+ 0x00771D00,
+ 0x00771E56,
+ 0x00771F18,
+ // Disable the third converter and third Pin (NID 08h)
+ 0x00878140
+);
+
+//
+//codecs verb tables
+//
+HDAUDIO_VERB_TABLE HdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC700)
+ // Revision ID =3D 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0700
+ //
+ 0x10EC, 0x0700,
+ 0xFF, 0xFF,
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC700
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11030
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40622005
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211020
+ // NID 0x29 : 0x411111F0
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //HDA Codec Subsystem ID : 0x10EC10F2
+ 0x001720F2,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C30,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C05,
+ 0x01D71D20,
+ 0x01D71E62,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205004A,
+ 0x0204201B,
+ //Widget node 0x20 - 1 :
+ 0x05850000,
+ 0x05843888,
+ 0x0205006F,
+ 0x02042C0B,
+
+
+ //Widget node 0X20 for ALC1305 20160603 update
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040600,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FFD0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02040DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x0204005D,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040442,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040005,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040006,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040008,
+ 0x02050028,
+ 0x0204B000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204002E,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C3,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204D4A0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204400A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040320,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040039,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003B,
+ 0x02050028,
+ 0x0204FFFF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02041DFE,
+ 0x02050029,
+ 0x0204B024,
+ //
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C0,
+ 0x02050028,
+ 0x020401FA,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C1,
+ 0x02050028,
+ 0x0204DE23,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C2,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C3,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C4,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C5,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C6,
+ 0x02050028,
+ 0x020403F5,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C7,
+ 0x02050028,
+ 0x0204AF1B,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C8,
+ 0x02050028,
+ 0x02041E0A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C9,
+ 0x02050028,
+ 0x0204368E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CA,
+ 0x02050028,
+ 0x020401FA,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CB,
+ 0x02050028,
+ 0x0204DE23,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CC,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CD,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CE,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CF,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D0,
+ 0x02050028,
+ 0x020403F5,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D1,
+ 0x02050028,
+ 0x0204AF1B,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D2,
+ 0x02050028,
+ 0x02041E0A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D3,
+ 0x02050028,
+ 0x0204368E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040040,
+ 0x02050028,
+ 0x0204800F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040062,
+ 0x02050028,
+ 0x02048000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040063,
+ 0x02050028,
+ 0x02044848,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040064,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040065,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040066,
+ 0x02050028,
+ 0x02044004,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040067,
+ 0x02050028,
+ 0x02040802,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040068,
+ 0x02050028,
+ 0x0204890F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040069,
+ 0x02050028,
+ 0x0204E021,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040070,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040071,
+ 0x02050000,
+ 0x02043330,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040072,
+ 0x02050000,
+ 0x02043333,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040073,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040074,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040075,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040076,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040050,
+ 0x02050028,
+ 0x020402EC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040051,
+ 0x02050028,
+ 0x02044909,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040052,
+ 0x02050028,
+ 0x020440B0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040046,
+ 0x02050028,
+ 0x0204C22E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040047,
+ 0x02050028,
+ 0x02040C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040048,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040049,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004A,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004B,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204721F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204009E,
+ 0x02050028,
+ 0x02040001,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040500,
+ 0x02050029,
+ 0x0204B024
+); // HdaVerbTableAlc700
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc701 =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC701)
+ // Revision ID =3D 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0701
+ //
+ 0x10EC, 0x0701,
+ 0xFF, 0xFF,
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC701
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11030
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40610041
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211020
+ // NID 0x29 : 0x411111F0
+
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //HDA Codec Subsystem ID : 0x10EC1124
+ 0x00172024,
+ 0x00172111,
+ 0x001722EC,
+ 0x00172310,
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C30,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C41,
+ 0x01D71D00,
+ 0x01D71E61,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205004A,
+ 0x0204201B,
+ //Widget node 0x20 - 1 :
+ 0x05850000,
+ 0x05843888,
+ 0x0205006F,
+ 0x02042C0B
+); // HdaVerbTableAlc701
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc274 =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC274)
+ // Revision ID =3D 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0274
+ //
+ 0x10EC, 0x0274,
+ 0xFF, 0xFF,
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC274
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6
+ //The number of verb command block : 16
+
+ // NID 0x12 : 0x40000000
+ // NID 0x13 : 0x411111F0
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x411111F0
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11020
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40451B05
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211010
+
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //,DA Codec Subsystem ID : 0x10EC10F6
+ 0x001720F6,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371CF0,
+ 0x01371D11,
+ 0x01371E11,
+ 0x01371F41,
+ //Pin widget 0x14 - NPC
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S_OUT2
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S_OUT1
+ 0x01771CF0,
+ 0x01771D11,
+ 0x01771E11,
+ 0x01771F41,
+ //Pin widget 0x18 - I2S_IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C20,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C05,
+ 0x01D71D1B,
+ 0x01D71E45,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C10,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205006F,
+ 0x02042C0B,
+ //Widget node 0x20 - 1 :
+ 0x02050035,
+ 0x02048968,
+ 0x05B50001,
+ 0x05B48540,
+ //Widget node 0x20 - 2 :
+ 0x05850000,
+ 0x05843888,
+ 0x05850000,
+ 0x05843888,
+ //Widget node 0x20 - 3 :
+ 0x0205004A,
+ 0x0204201B,
+ 0x0205004A,
+ 0x0204201B
+); //HdaVerbTableAlc274
+
+//
+// CFL S Audio Codec
+//
+STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_IN=
IT (
+ //
+ // VerbTable: (Realtek ALC700) CFL S RVP
+ // Revision ID =3D 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0700
+ //
+ 0x10EC, 0x0700,
+ 0xFF, 0xFF,
+
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.1
+ //Realtek HD Audio Codec : ALC700
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x90A60130
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x03011010
+ // NID 0x17 : 0x90170120
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A1103E
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x03A11040
+ // NID 0x1D : 0x40600001
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x0421102F
+ // NID 0x29 : 0x411111F0
+
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //HDA Codec Subsystem ID : 0x10EC112C
+ 0x0017202C,
+ 0x00172111,
+ 0x001722EC,
+ 0x00172310,
+
+
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C30,
+ 0x01271D01,
+ 0x01271EA6,
+ 0x01271F90,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671C10,
+ 0x01671D10,
+ 0x01671E01,
+ 0x01671F03,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C20,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C3E,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71C40,
+ 0x01B71D10,
+ 0x01B71EA1,
+ 0x01B71F03,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C01,
+ 0x01D71D00,
+ 0x01D71E60,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C2F,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+
+ //Widget node 0x20 - 0 FAKE JD unplug
+ 0x02050008,
+ 0x0204A80F,
+ 0x02050008,
+ 0x0204A80F,
+ //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of=
NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14)
+ 0x0205006B,
+ 0x02044260,
+ 0x0205006B,
+ 0x02044260,
+ //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700
+ 0x05B50010,
+ 0x05B45C1D,
+ 0x0205006F,
+ 0x02040F8B, //Zeek, 0F8Bh
+ //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent co=
ntrol
+ 0x02050045,
+ 0x02045089,
+ 0x0205004A,
+ 0x0204201B,
+ //Widget node 0x20 - 4 From JD detect
+ 0x02050008,
+ 0x0204A807,
+ 0x02050008,
+ 0x0204A807,
+ //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and en=
able I2S BCLK first
+ 0x02050090,
+ 0x02040424,
+ 0x00171620,
+ 0x00171720,
+
+ 0x00171520,
+ 0x01770740,
+ 0x01770740,
+ 0x01770740,
+
+
+ //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove ALC=
1305 EQ setting
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02045548,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02041000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040600,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FFD0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02040DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x0204005D,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040442,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040005,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040006,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040008,
+ 0x02050028,
+ 0x0204B000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204002E,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C3,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204D4A0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204400A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040320,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040039,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003B,
+ 0x02050028,
+ 0x0204FFFF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x020400C0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCF0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C0,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C1,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C2,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C3,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C4,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C5,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C6,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C7,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C8,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C9,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CA,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CB,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CC,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CD,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CE,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CF,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D0,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D1,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D2,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D3,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040062,
+ 0x02050028,
+ 0x02048000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040063,
+ 0x02050028,
+ 0x02045F5F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040064,
+ 0x02050028,
+ 0x02042000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040065,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040066,
+ 0x02050028,
+ 0x02044004,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040067,
+ 0x02050028,
+ 0x02040802,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040068,
+ 0x02050028,
+ 0x0204890F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040069,
+ 0x02050028,
+ 0x0204E021,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040070,
+ 0x02050028,
+ 0x02048012,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040071,
+ 0x02050028,
+ 0x02043450,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040072,
+ 0x02050028,
+ 0x02040123,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040073,
+ 0x02050028,
+ 0x02044543,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040074,
+ 0x02050028,
+ 0x02042100,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040075,
+ 0x02050028,
+ 0x02044321,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040076,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040050,
+ 0x02050028,
+ 0x02048200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040051,
+ 0x02050028,
+ 0x02040707,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040052,
+ 0x02050028,
+ 0x02044090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204721F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040012,
+ 0x02050028,
+ 0x0204DFDF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204009E,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040500,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040060,
+ 0x02050028,
+ 0x02042213,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02041DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02043000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040040,
+ 0x02050028,
+ 0x0204000C,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040046,
+ 0x02050028,
+ 0x0204C22E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004B,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024
+);
+
+
+//
+// WHL codecs verb tables
+//
+HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC700) WHL RVP
+ // Revision ID =3D 0xff
+ // Codec Verb Table for WHL PCH boards
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0700
+ //
+ 0x10EC, 0x0700,
+ 0xFF, 0xFF,
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.1
+ //Realtek HD Audio Codec : ALC700
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x02A19040
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40638029
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x02211020
+ // NID 0x29 : 0x411111F0
+
+ //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D
+ //HDA Codec Subsystem ID : 0x10EC10F2
+ 0x001720F2,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271CF0,
+ 0x01271D11,
+ 0x01271E11,
+ 0x01271F41,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C40,
+ 0x01971D90,
+ 0x01971EA1,
+ 0x01971F02,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C29,
+ 0x01D71D80,
+ 0x01D71E63,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F02,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 - 0 FAKE JD unplug
+ 0x02050008,
+ 0x0204A80F,
+ 0x02050008,
+ 0x0204A80F,
+
+ //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 byp=
ass DAC02 DRE(NID5B bit14)
+ 0x05B50010,
+ 0x05B45C1D,
+ 0x0205006F,
+ 0x02040F8B, //Zeek, 0F8Bh
+
+ //Widget node 0x20 -2:
+ 0x02050045,
+ 0x02045089,
+ 0x0205004A,
+ 0x0204201B,
+
+ //Widget node 0x20 - 3 From JD detect
+ 0x02050008,
+ 0x0204A807,
+ 0x02050008,
+ 0x0204A807,
+
+ //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and en=
able I2S BCLK first
+ 0x02050090,
+ 0x02040424,
+ 0x00171620,
+ 0x00171720,
+
+ 0x00171520,
+ 0x01770740,
+ 0x01770740,
+ 0x01770740,
+
+ //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove ALC=
1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02045548,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02041000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040600,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FFD0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02040DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x0204005D,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040442,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040005,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040006,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040008,
+ 0x02050028,
+ 0x0204B000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204002E,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C3,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204D4A0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204400A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040320,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040039,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003B,
+ 0x02050028,
+ 0x0204FFFF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x020400C0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCF0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C0,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C1,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C2,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C3,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C4,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C5,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C6,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C7,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C8,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C9,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CA,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CB,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CC,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CD,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CE,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CF,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D0,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D1,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D2,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D3,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040062,
+ 0x02050028,
+ 0x02048000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040063,
+ 0x02050028,
+ 0x02045F5F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040064,
+ 0x02050028,
+ 0x02042000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040065,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040066,
+ 0x02050028,
+ 0x02044004,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040067,
+ 0x02050028,
+ 0x02040802,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040068,
+ 0x02050028,
+ 0x0204890F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040069,
+ 0x02050028,
+ 0x0204E021,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040070,
+ 0x02050028,
+ 0x02048012,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040071,
+ 0x02050028,
+ 0x02043450,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040072,
+ 0x02050028,
+ 0x02040123,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040073,
+ 0x02050028,
+ 0x02044543,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040074,
+ 0x02050028,
+ 0x02042100,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040075,
+ 0x02050028,
+ 0x02044321,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040076,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040050,
+ 0x02050028,
+ 0x02048200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040051,
+ 0x02050028,
+ 0x02040707,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040052,
+ 0x02050028,
+ 0x02044090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204721F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040012,
+ 0x02050028,
+ 0x0204DFDF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204009E,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040500,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040060,
+ 0x02050028,
+ 0x0204E213,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02041DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02043000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040040,
+ 0x02050028,
+ 0x0204000C,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040046,
+ 0x02050028,
+ 0x0204422E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004B,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024
+); // WhlHdaVerbTableAlc700
+
+#endif // _PCH_HDA_VERB_TABLES_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/C=
ometlakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..74581ac6bd
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiBoardInitPostMemLib.c
@@ -0,0 +1,40 @@
+/** @file
+ Comet Lake U LP3 Board Initialization Post-Memory library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ CometlakeURvpBoardInitBeforeSiliconInit();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterSiliconInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/CometlakeOpenBoardPkg=
/CometlakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..458242a5f7
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiBoardInitPostMemLib.inf
@@ -0,0 +1,57 @@
+## @file
+# Component information file for CometlakeURvpInitLib in PEI post memory p=
hase.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D PeiBoardPostMemInitLib
+ FILE_GUID =3D 7fcc3900-d38d-419f-826b-72481e8b5509
+ MODULE_TYPE =3D PEIM
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D BoardInitLib
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ GpioExpanderLib
+ GpioLib
+ HdaVerbTableLib
+ MemoryAllocationLib
+ PcdLib
+ SiliconInitLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ PeiCometlakeURvpInitPostMemLib.c
+ PeiBoardInitPostMemLib.c
+ GpioTableDefault.c
+ GpioTableCometlakeULpddr3Rvp.c
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Co=
metlakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..137b7353e4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiBoardInitPreMemLib.c
@@ -0,0 +1,106 @@
+/** @file
+ Comet Lake U LP3 Board Initialization Pre-Memory library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+CometlakeURvpBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+BoardDetect (
+ VOID
+ )
+{
+ CometlakeURvpBoardDetect();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardDebugInit (
+ VOID
+ )
+{
+ CometlakeURvpBoardDebugInit();
+ return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+BoardBootModeDetect (
+ VOID
+ )
+{
+ return CometlakeURvpBoardBootModeDetect();
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ CometlakeURvpBoardInitBeforeMemoryInit();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterMemoryInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeTempRamExit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterTempRamExit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/=
CometlakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..b7f96f1b99
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiBoardInitPreMemLib.inf
@@ -0,0 +1,118 @@
+## @file
+# Component information file for PEI CometlakeURvp Board Init Pre-Mem Libr=
ary
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D PeiBoardInitPreMemLib
+ FILE_GUID =3D ec3675bc-1470-417d-826e-37378140213d
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D BoardInitLib
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ SiliconInitLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ PeiCometlakeURvpDetect.c
+ PeiCometlakeURvpInitPreMemLib.c
+ CometlakeURvpHsioPtssTables.c
+ PeiBoardInitPreMemLib.c
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+ # PCH-LP HSIO PTSS Table
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ # SA Misc Config
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # PEG Reset By GPIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive
+
+
+ # SPD Address Table
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+ # USB 2.0 Port AFE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe
+
+ # USB 2.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+
+ # USB 3.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+
+ # Misc
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiCometlakeURvpDetect.c b/Platform/Intel/CometlakeOpenBoardPkg/C=
ometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpDetect.c
new file mode 100644
index 0000000000..e113ac3ae0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiCometlakeURvpDetect.c
@@ -0,0 +1,63 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+
+#include "CometlakeURvpInit.h"
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h>
+
+BOOLEAN
+CometlakeURvp(
+ VOID
+ )
+{
+ return TRUE;
+}
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDetect(
+ VOID
+ )
+{
+ if (LibPcdGetSku () !=3D 0) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_INFO, "CometlakeURvpDetectionCallback\n"));
+
+ if (CometlakeURvp()) {
+ LibPcdSetSku (BoardIdCometLakeULpddr3Rvp);
+
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ ASSERT (LibPcdGetSku() =3D=3D BoardIdCometLakeULpddr3Rvp);
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiCometlakeURvpInitPostMemLib.c b/Platform/Intel/CometlakeOpenBo=
ardPkg/CometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpInitPostMemLib.c
new file mode 100644
index 0000000000..306ffbf21b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiCometlakeURvpInitPostMemLib.c
@@ -0,0 +1,436 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+#include <IoExpander.h>
+#include <AttemptUsbFirst.h>
+#include <PeiPlatformHookLib.h>
+#include <Library/PeiPolicyInitLib.h>
+#include <Library/PchInfoLib.h>
+#include <FirwmareConfigurations.h>
+#include "CometlakeURvpInit.h"
+#include <Library/ConfigBlockLib.h>
+
+EFI_STATUS
+BoardFunctionInit (
+ IN UINT16 BoardId
+ );
+
+/**
+ GPIO init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardGpioInit(
+ IN UINT16 BoardId
+ )
+{
+ //
+ // GPIO Table Init.
+ //
+ switch (BoardId) {
+
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableCmlULpddr3);
+ PcdSet16S (PcdBoardGpioTableSize, mGpioTableCmlULpddr3Size);
+ PcdSet32S (PcdBoardGpioTable2, 0);
+ PcdSet16S (PcdBoardGpioTable2Size, 0);
+ break;
+
+ default:
+ DEBUG ((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...=
\n"));
+ PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableDefault);
+ PcdSet16S (PcdBoardGpioTableSize, mGpioTableDefaultSize);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Touch panel GPIO init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+TouchPanelGpioInit (
+ IN UINT16 BoardId
+ )
+{
+ switch (BoardId) {
+ default:
+ PcdSet32S (PcdBoardGpioTableTouchPanel, 0);
+ break;
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Misc. init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardMiscInit (
+ IN UINT16 BoardId
+ )
+{
+ PcdSetBoolS (PcdDebugUsbUartEnable, FALSE);
+
+ switch (BoardId) {
+
+ case BoardIdCometLakeULpddr3Rvp:
+
+ PcdSetBoolS(PcdMipiCamGpioEnable, FALSE);
+ break;
+
+ default:
+ PcdSetBoolS(PcdMipiCamGpioEnable, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Security GPIO init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardSecurityInit (
+ IN UINT16 BoardId
+ )
+{
+ switch (BoardId) {
+
+ case BoardIdCometLakeULpddr3Rvp:
+
+ // TPM interrupt connects to GPIO_CNL_H_GPP_A_7
+ PcdSet32S (PcdTpm2CurrentIrqNum, 0x1F);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board configuration initialization in the post-memory boot phase.
+**/
+VOID
+BoardConfigInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT16 BoardId;
+
+ BoardId =3D BoardIdCometLakeULpddr3Rvp;
+
+ Status =3D BoardGpioInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D TouchPanelGpioInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D HdaVerbTableInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D BoardMiscInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D BoardFunctionInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D BoardSecurityInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Create the HOB for hotkey status for 'Attempt USB First' feature
+
+ @retval EFI_SUCCESS HOB Creating successful.
+ @retval Others HOB Creating failed.
+**/
+EFI_STATUS
+CreateAttemptUsbFirstHotkeyInfoHob (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo;
+
+ Status =3D EFI_SUCCESS;
+
+ ZeroMem (
+ &AttemptUsbFirstHotkeyInfo,
+ sizeof (AttemptUsbFirstHotkeyInfo)
+ );
+
+ AttemptUsbFirstHotkeyInfo.RevisonId =3D 0;
+ AttemptUsbFirstHotkeyInfo.HotkeyTriggered =3D FALSE;
+
+ ///
+ /// Build HOB for Attempt USB First feature
+ ///
+ BuildGuidDataHob (
+ &gAttemptUsbFirstHotkeyInfoHobGuid,
+ &(AttemptUsbFirstHotkeyInfo),
+ sizeof (ATTEMPT_USB_FIRST_HOTKEY_INFO)
+ );
+
+ return Status;
+}
+
+/**
+ Search and identify the physical address of a
+ file module inside the FW_BINARIES_FV_SIGNED FV
+
+ @retval EFI_SUCCESS If address has been found
+ @retval Others If address has not been found
+**/
+EFI_STATUS
+FindModuleInFlash2 (
+ IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader,
+ IN EFI_GUID *GuidPtr,
+ IN OUT UINT32 *ModulePtr,
+ IN OUT UINT32 *ModuleSize
+ )
+{
+ EFI_FFS_FILE_HEADER *FfsHeader;
+ EFI_FV_FILE_INFO FileInfo;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_COMMON_SECTION_HEADER *SectionHeader;
+ VOID *FileBuffer;
+ EFI_STATUS Status;
+
+ FfsHeader =3D NULL;
+ FileHandle =3D NULL;
+ SectionHeader =3D NULL;
+ FileBuffer =3D NULL;
+
+ while (TRUE) {
+ //
+ // Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware vol=
ume
+ //
+ Status =3D PeiServicesFfsFindNextFile (EFI_FV_FILETYPE_FIRMWARE_VOLUME=
_IMAGE, FvHeader, &FileHandle);
+ if (EFI_ERROR (Status)) {
+ // unable to find FV_IMAGE file in this FV
+ break;
+ }
+
+ FfsHeader =3D (EFI_FFS_FILE_HEADER*)FileHandle;
+ DEBUG ((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
+ DEBUG ((DEBUG_INFO, " Name =3D 0x%g\n", &FfsHeader->Name));
+ DEBUG ((DEBUG_INFO, " Type =3D 0x%X\n", FfsHeader->Type));
+ if (IS_FFS_FILE2 (FfsHeader)) {
+ DEBUG ((DEBUG_INFO, " Size =3D 0x%X\n", FFS_FILE2_SIZE(FfsHeader)));
+ }
+ else {
+ DEBUG ((DEBUG_INFO, " Size =3D 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
+ }
+
+ //
+ // Locate FW_BINARIES_FV FV_IMAGE Section
+ //
+ Status =3D PeiServicesFfsFindSectionData (EFI_SECTION_FIRMWARE_VOLUME_=
IMAGE, FileHandle, &FileBuffer);
+ if (EFI_ERROR (Status)) {
+ // continue to search for the next FV_IMAGE file
+ DEBUG ((DEBUG_INFO, "FW_BINARIES_FV section not found. Status =3D %r=
\n", Status));
+ continue;
+ }
+
+ SectionHeader =3D (EFI_COMMON_SECTION_HEADER *)FileBuffer;
+ DEBUG ((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
+ (UINT32)(UINT8 *)SectionHeader));
+ if (IS_SECTION2(SectionHeader)) {
+ DEBUG ((DEBUG_INFO, " Guid =3D 0x%g\n",
+ &((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->SectionDefinitionGu=
id));
+ DEBUG ((DEBUG_INFO, " DataOfset =3D 0x%X\n",
+ ((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset));
+ }
+ else {
+ DEBUG ((DEBUG_INFO, " Guid =3D 0x%g\n",
+ &((EFI_GUID_DEFINED_SECTION *)SectionHeader)->SectionDefinitionGui=
d));
+ DEBUG ((DEBUG_INFO, " DataOfset =3D 0x%X\n",
+ ((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset));
+ }
+ DEBUG ((DEBUG_INFO, " Type =3D 0x%X\n", SectionHeader->Type));
+
+ //
+ // Locate Firmware File System file within Firmware Volume
+ //
+ Status =3D PeiServicesFfsFindFileByName (GuidPtr, FileBuffer, (VOID **=
)&FfsHeader);
+ if (EFI_ERROR (Status)) {
+ // continue to search for the next FV_IMAGE file
+ DEBUG ((DEBUG_INFO, "Module not found. Status =3D %r\n", Status));
+ continue;
+ }
+
+ *ModulePtr =3D (UINT32)((UINT8 *)FfsHeader + sizeof(EFI_FFS_FILE_HEADE=
R));
+
+ //
+ // Get File Information
+ //
+ Status =3D PeiServicesFfsGetFileInfo (FfsHeader, &FileInfo);
+ if (!EFI_ERROR (Status)) {
+ *ModuleSize =3D (UINT32)FileInfo.BufferSize;
+ DEBUG ((DEBUG_INFO, "Module {0x%g} found at =3D 0x%X, Size =3D 0x%X\=
n",
+ &FfsHeader->Name, *ModulePtr, *ModuleSize));
+ return Status;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Get the ChipsetInit Binary pointer.
+
+ @retval EFI_SUCCESS - ChipsetInit Binary found.
+ @retval EFI_NOT_FOUND - ChipsetInit Binary not found.
+**/
+EFI_STATUS
+UpdateChipsetInitPtr (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ PCH_STEPPING PchStep;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ EFI_GUID *ChipsetInitBinaryGuidPtr;
+ SI_POLICY_PPI *SiPolicyPpi;
+ PCH_HSIO_CONFIG *HsioConfig;
+ UINT32 ModuleAddr;
+ UINT32 ModuleSize;
+
+ ModuleAddr =3D 0;
+ ModuleSize =3D 0;
+ PchStep =3D PchStepping ();
+
+ Status =3D PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SiPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GetConfigBlock ((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID =
*)&HsioConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ ChipsetInitBinaryGuidPtr =3D NULL;
+ if (IsPchLp()) {
+ switch (PchStep) {
+ case PCH_A0:
+ case PCH_D0:
+ case PCH_D1:
+ ChipsetInitBinaryGuidPtr =3D &gCnlPchLpChipsetInitTableDxGuid;
+ DEBUG ((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table \n"));
+ break;
+ default:
+ return EFI_NOT_FOUND;
+ }
+ } else {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Locate Firmware Volume header
+ //
+ FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32 (PcdFlashFvPos=
tMemoryBase);
+ Status =3D FindModuleInFlash2 (FvHeader, ChipsetInitBinaryGuidPtr, &Modu=
leAddr, &ModuleSize);
+ //
+ // Get ChipsetInit Binary Pointer
+ //
+ HsioConfig->ChipsetInitBinPtr =3D ModuleAddr;
+
+ //
+ // Get File Size
+ //
+ HsioConfig->ChipsetInitBinLen =3D ModuleSize;
+
+ DEBUG ((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig->Chi=
psetInitBinPtr));
+ DEBUG ((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig->Chipset=
InitBinLen));
+
+ return Status;
+}
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardInitBeforeSiliconInit(
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT8 FwConfig;
+
+ BoardConfigInit ();
+ //
+ // Configure GPIO and SIO
+ //
+ Status =3D BoardInit ();
+ ASSERT_EFI_ERROR (Status);
+
+ FwConfig =3D FwConfigProduction;
+ PeiPolicyInit (FwConfig);
+
+ //
+ // Create USB Boot First hotkey information HOB
+ //
+ CreateAttemptUsbFirstHotkeyInfoHob ();
+
+ //
+ // Initializing Platform Specific Programming
+ //
+ Status =3D PlatformSpecificInit ();
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Update ChipsetInitPtr
+ //
+ Status =3D UpdateChipsetInitPtr ();
+
+ ///
+ /// Do Late PCH init
+ ///
+ LateSiliconInit ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiCometlakeURvpInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoa=
rdPkg/CometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpInitPreMemLib.c
new file mode 100644
index 0000000000..af80a69ee4
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiCometlakeURvpInitPreMemLib.c
@@ -0,0 +1,562 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+
+#include "CometlakeURvpInit.h"
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Register/PchRegsPcr.h>
+#include <Library/PchResetLib.h>
+#include <Register/PchRegsLpc.h>
+#include <Library/StallPpiLib.h>
+#include <Library/PeiPolicyInitLib.h>
+#include <Ppi/Reset.h>
+#include <PlatformBoardConfig.h>
+#include <GpioPinsCnlLp.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <PeiPlatformHookLib.h>
+#include <FirwmareConfigurations.h>
+#include <Library/OcWdtLib.h>
+
+///
+/// Reset Generator I/O Port
+///
+#define RESET_GENERATOR_PORT 0xCF9
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINT64 Length;
+} MEMORY_MAP;
+
+//
+// Reference RCOMP resistors on motherboard - for WHL RVP1
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX=
_RCOMP] =3D { 200, 81, 162 };
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for WH=
L RVP1
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_R=
COMP_TARGETS] =3D { 100, 40, 40, 23, 40 };
+
+GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] =3D {
+ { FixedPcdGet64 (PcdApicLocalAddress), FixedPcdGet32 (PcdApicLocalMmioS=
ize) },
+ { FixedPcdGet64 (PcdMchBaseAddress), FixedPcdGet32 (PcdMchMmioSize) },
+ { FixedPcdGet64 (PcdDmiBaseAddress), FixedPcdGet32 (PcdDmiMmioSize) },
+ { FixedPcdGet64 (PcdEpBaseAddress), FixedPcdGet32 (PcdEpMmioSize) },
+ { FixedPcdGet64 (PcdGdxcBaseAddress), FixedPcdGet32 (PcdGdxcMmioSize) }
+};
+
+EFI_STATUS
+MrcConfigInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+SaGpioConfigInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+SaMiscConfigInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+RootPortClkInfoInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+UsbConfigInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+GpioGroupTierInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+GpioTablePreMemInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+PchPmConfigInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+SaDisplayConfigInit (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+BoardFunctionInitPreMem (
+ IN UINT16 BoardId
+ );
+
+EFI_STATUS
+EFIAPI
+PlatformInitPreMemCallBack (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+PchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+static EFI_PEI_RESET_PPI mResetPpi =3D {
+ PchReset
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] =3D {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiResetPpiGuid,
+ &mResetPpi
+ }
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList =3D {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA=
TE_LIST),
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA=
TE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify
+};
+
+/**
+ Board misc init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardMiscInitPreMem (
+ IN UINT16 BoardId
+ )
+{
+ PCD64_BLOB PcdData;
+
+ //
+ // RecoveryMode GPIO
+ //
+ PcdData.Blob =3D 0;
+ PcdData.BoardGpioConfig.Type =3D BoardGpioTypeNotSupported;
+
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdData.BoardGpioConfig.Type =3D BoardGpioTypePch;
+ PcdData.BoardGpioConfig.u.Pin =3D GPIO_CNL_LP_GPP_F10;
+ break;
+
+ default:
+ break;
+ }
+
+ //
+ // Configure WWAN Full Card Power Off and reset pins
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ //
+ // According to board default settings, GPP_D16 is used to enable/di=
sable modem
+ // power. An alternative way to contol modem power is to toggle FCP_=
OFF via GPP_D13
+ // but board rework is required.
+ //
+ PcdSet32S (PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16);
+ PcdSet32S (PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
+ PcdSet32S (PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
+ PcdSet8S (PcdWwanPerstGpioPolarity, 1);
+ break;
+
+ default:
+ break;
+ }
+
+ PcdSet64S (PcdRecoveryModeGpio, PcdData.Blob);
+
+ //
+ // Pc8374SioKbc Present
+ //
+ PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board configuration initialization in the pre-memory boot phase.
+**/
+VOID
+BoardConfigInitPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT16 BoardId;
+
+ BoardId =3D BoardIdCometLakeULpddr3Rvp;
+
+ Status =3D MrcConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D SaGpioConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D SaMiscConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D RootPortClkInfoInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D UsbConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GpioGroupTierInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D GpioTablePreMemInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D PchPmConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D BoardMiscInitPreMem (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D SaDisplayConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status =3D BoardFunctionInitPreMem (BoardId);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ This function handles PlatformInit task after PeiReadOnlyVariable2 PPI p=
roduced
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification=
event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this f=
unction.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others Failure
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitPreMemCallBack (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ UINT8 FwConfig;
+
+ //
+ // Init Board Config Pcd.
+ //
+ BoardConfigInitPreMem ();
+
+ DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the confi=
guration to production mode!\n"));
+ FwConfig =3D FwConfigProduction;
+ PcdSetBoolS (PcdPcieWwanEnable, FALSE);
+ PcdSetBoolS (PcdWwanResetWorkaround, FALSE);
+
+ //
+ // Early Board Configuration before memory is ready.
+ //
+ Status =3D BoardInitEarlyPreMem ();
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// If there was unexpected reset but no WDT expiration and no resume fr=
om S3/S4,
+ /// clear unexpected reset status and enforce expiration. This is to inf=
orm Firmware
+ /// which has no access to unexpected reset status bit, that something w=
ent wrong.
+ ///
+ OcWdtResetCheck ();
+
+ Status =3D OcWdtInit ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize Intel PEI Platform Policy
+ //
+ PeiPolicyInitPreMem (FwConfig);
+
+ ///
+ /// Configure GPIO and SIO
+ ///
+ Status =3D BoardInitPreMem ();
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Install Pre Memory PPIs
+ ///
+ Status =3D PeiServicesInstallPpi (&mPreMemPpiList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Provide hard reset PPI service.
+ To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xC=
F9).
+
+ @param[in] PeiServices General purpose services available to ever=
y PEIM.
+
+ @retval Not return System reset occured.
+ @retval EFI_DEVICE_ERROR Device error, could not reset the system.
+**/
+EFI_STATUS
+EFIAPI
+PchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
+ IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
+
+ CpuDeadLoop ();
+
+ ///
+ /// System reset occured, should never reach at this line.
+ ///
+ ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+ return EFI_DEVICE_ERROR;
+}
+
+/**
+ Install Firmware Volume Hob's once there is main memory
+
+ @param[in] PeiServices General purpose services available to ever=
y PEIM.
+ @param[in] NotifyDescriptor Notify that this module published.
+ @param[in] Ppi PPI that was installed.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINTN Index;
+ UINT8 PhysicalAddressBits;
+ UINT32 RegEax;
+ MEMORY_MAP PcieMmioMap;
+
+ Index =3D 0;
+
+ Status =3D PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
+ if (RegEax >=3D 0x80000008) {
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+ PhysicalAddressBits =3D (UINT8)RegEax;
+ }
+ else {
+ PhysicalAddressBits =3D 36;
+ }
+
+ ///
+ /// Create a CPU hand-off information
+ ///
+ BuildCpuHob (PhysicalAddressBits, 16);
+
+ ///
+ /// Build Memory Mapped IO Resource which is used to build E820 Table in=
LegacyBios.
+ ///
+ PcieMmioMap.BaseAddress =3D FixedPcdGet64 (PcdPciExpressBaseAddress);
+ PcieMmioMap.Length =3D PcdGet32 (PcdPciExpressRegionLength);
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ PcieMmioMap.BaseAddress,
+ PcieMmioMap.Length
+ );
+ BuildMemoryAllocationHob (
+ PcieMmioMap.BaseAddress,
+ PcieMmioMap.Length,
+ EfiMemoryMappedIO
+ );
+ for (Index =3D 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP)); Index+=
+) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ MmioMap[Index].BaseAddress,
+ MmioMap[Index].Length
+ );
+ BuildMemoryAllocationHob (
+ MmioMap[Index].BaseAddress,
+ MmioMap[Index].Length,
+ EfiMemoryMappedIO
+ );
+ }
+
+ //
+ // Report resource HOB for flash FV
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
+ );
+
+ BuildMemoryAllocationHob (
+ (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaSize),
+ EfiMemoryMappedIO
+ );
+
+ BuildFvHob (
+ (UINTN)FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN)FixedPcdGet32 (PcdFlashAreaSize)
+ );
+
+ return Status;
+}
+
+/**
+ Board configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER The parameter is NULL.
+**/
+EFI_STATUS
+EFIAPI
+CometlakeURvpInitPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Install Stall PPI
+ ///
+ Status =3D InstallStallPpi ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install PCH RESET PPI and EFI RESET2 PeiService
+ //
+ Status =3D PchInitializeReset ();
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI=
produced
+ ///
+ Status =3D PeiServicesNotifyPpi (&mPreMemNotifyList);
+
+ ///
+ /// After code reorangized, memorycallback will run because the PPI is a=
lready
+ /// installed when code run to here, it is supposed that the InstallEfiM=
emory is
+ /// done before.
+ ///
+ Status =3D PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure GPIO and SIO before memory ready
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardInitBeforeMemoryInit(
+ VOID
+ )
+{
+ ///
+ /// Do basic PCH init
+ ///
+ SiliconInit ();
+
+ CometlakeURvpInitPreMem();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDebugInit(
+ VOID
+ )
+{
+ ///
+ /// Do Early PCH init
+ ///
+ EarlySiliconInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+CometlakeURvpBoardBootModeDetect(
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/CometlakeOpenBoard=
Pkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..560f05380c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,41 @@
+/** @file
+ Comet Lake U LP3 Multi-Board Initialization Post-Memory library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardInitBeforeSiliconInit(
+ VOID
+ );
+
+BOARD_POST_MEM_INIT_FUNC mCometlakeURvpBoardInitFunc =3D {
+ CometlakeURvpBoardInitBeforeSiliconInit,
+ NULL, // BoardInitAfterSiliconInit
+};
+
+EFI_STATUS
+EFIAPI
+PeiCometlakeURvpMultiBoardInitLibConstructor (
+ VOID
+ )
+{
+ if (LibPcdGetSku () =3D=3D BoardIdCometLakeULpddr3Rvp) {
+ return RegisterBoardPostMemInit (&mCometlakeURvpBoardInitFunc);
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/CometlakeOpenBoa=
rdPkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..b3b121e9e8
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,207 @@
+## @file
+# Component information file for CometlakeURvpInitLib in PEI post memory p=
hase.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D PeiCometlakeURvpMultiBoardInitLib
+ FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF9017499280
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D NULL
+ CONSTRUCTOR =3D PeiCometlakeURvpMultiBoardInitLibCons=
tructor
+
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ GpioExpanderLib
+ PcdLib
+ MultiBoardInitSupportLib
+ HdaVerbTableLib
+ PeiPlatformHookLib
+ PeiPolicyInitLib
+ PchInfoLib
+ SiliconInitLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ PeiCometlakeURvpInitPostMemLib.c
+ PeiMultiBoardInitPostMemLib.c
+ BoardFunc.c
+ BoardFuncInit.c
+ GpioTableDefault.c
+ GpioTableCometlakeULpddr3Rvp.c
+
+[FixedPcd]
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize
+
+ #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase
+ # Board Init Table List
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemS=
ize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem=
Size
+
+ # WWAN Full Card Power Off and reset pins
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity
+
+ # SA Misc Config
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit
+
+ # Display DDI
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable #=
# PRODUCES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize #=
# PRODUCES
+
+ # PEG Reset By GPIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive
+
+ # PCIE RTD3 GPIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive
+
+ # CA Vref Configuration
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig
+
+ # PCIe Clock Info
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15
+
+ # USB 2.0 Port AFE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe
+
+ # USB 2.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
+
+ # USB 3.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9
+
+ # GPIO Group Tier
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ # Pch PmConfig Policy
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport
+
+ # Misc
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable
+
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 =
## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size =
## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable
+ # TPM interrupt
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
+
+[Guids]
+ gAttemptUsbFirstHotkeyInfoHobGuid ## CONSUMES
+ gCnlPchLpChipsetInitTableDxGuid ## CONSUMES
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardP=
kg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..37df5c0e35
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,83 @@
+/** @file
+ Comet Lake U LP3 Multi-Board Initialization Pre-Memory library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDetect(
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpMultiBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+CometlakeURvpBoardBootModeDetect(
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDebugInit(
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardInitBeforeMemoryInit(
+ VOID
+ );
+
+BOARD_DETECT_FUNC mCometlakeURvpBoardDetectFunc =3D {
+ CometlakeURvpMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC mCometlakeURvpBoardPreMemInitFunc =3D {
+ CometlakeURvpBoardDebugInit,
+ CometlakeURvpBoardBootModeDetect,
+ CometlakeURvpBoardInitBeforeMemoryInit,
+ NULL, // BoardInitAfterMemoryInit
+ NULL, // BoardInitBeforeTempRamExit
+ NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpMultiBoardDetect(
+ VOID
+ )
+{
+ CometlakeURvpBoardDetect();
+ if (LibPcdGetSku () =3D=3D BoardIdCometLakeULpddr3Rvp) {
+ RegisterBoardPreMemInit (&mCometlakeURvpBoardPreMemInitFunc);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiCometlakeURvpMultiBoardInitPreMemLibConstructor (
+ VOID
+ )
+{
+ return RegisterBoardDetect (&mCometlakeURvpBoardDetectFunc);
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa=
rdInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/CometlakeOpenBoar=
dPkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..636816ad81
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL=
ib/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,300 @@
+## @file
+# Component information file for PEI CometlakeURvp Board Init Pre-Mem Libr=
ary
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D PeiCometlakeURvpMultiBoardInitPreMemL=
ib
+ FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574F
+ MODULE_TYPE =3D BASE
+ VERSION_STRING =3D 1.0
+ LIBRARY_CLASS =3D NULL
+ CONSTRUCTOR =3D PeiCometlakeURvpMultiBoardInitPreMemL=
ibConstructor
+
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ GpioLib
+ MemoryAllocationLib
+ MultiBoardInitSupportLib
+ OcWdtLib
+ PcdLib
+ PchResetLib
+ PeiPlatformHookLib
+ PeiPolicyInitLib
+ PlatformHookLib
+ SiliconInitLib
+ StallPpiLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ PeiCometlakeURvpInitPreMemLib.c
+ CometlakeURvpHsioPtssTables.c
+ PeiMultiBoardInitPreMemLib.c
+ PeiCometlakeURvpDetect.c
+ BoardSaInitPreMemLib.c
+ BoardPchInitPreMemLib.c
+ BoardFuncInitPreMem.c
+ GpioTableCmlUlpddr3PreMem.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid
+ gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES
+ gEfiPeiResetPpiGuid ## PRODUCES
+
+[Guids]
+ gPchGeneralPreMemConfigGuid ## CONSUMES
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+ # PCH-LP HSIO PTSS Table
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ # PCH-H HSIO PTSS Table
+ #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+
+ # SA Misc Config
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # PEG Reset By GPIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive
+
+
+ # SPD Address Table
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+ # USB 2.0 Port AFE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe
+
+ # USB 2.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+
+ # USB 3.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+
+ # Misc
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
+
+ #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+ # Board Init Table List
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemS=
ize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem=
Size
+
+ # WWAN Full Card Power Off and reset pins
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity
+
+ # SA Misc Config
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit
+
+ # Display DDI
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable #=
# PRODUCES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize #=
# PRODUCES
+
+ # PEG Reset By GPIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive
+
+ # PCIE RTD3 GPIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive
+
+ # CA Vref Configuration
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig
+
+ # PCIe Clock Info
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15
+
+ # USB 2.0 Port AFE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe
+
+ # USB 2.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
+
+ # USB 3.0 Port Over Current Pin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9
+
+ # GPIO Group Tier
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ # Pch PmConfig Policy
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport
+
+ # Misc
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable
+
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround ## PRODUC=
ES
+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress
+
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdMchMmioSize ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpMmioSize ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize ## CONSUMES
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Dxe=
PolicyBoardConfigLib/DxePolicyBoardConfig.h b/Platform/Intel/CometlakeOpenB=
oardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h
new file mode 100644
index 0000000000..c420873002
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyB=
oardConfigLib/DxePolicyBoardConfig.h
@@ -0,0 +1,19 @@
+/** @file
+ Header file for DxePolicyBoardConfig library instance.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_POLICY_BOARD_CONFIG_H_
+#define _DXE_POLICY_BOARD_CONFIG_H_
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/DxePolicyBoardConfigLib.h>
+
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Dxe=
PolicyBoardConfigLib/DxePolicyBoardConfigLib.inf b/Platform/Intel/Cometlake=
OpenBoardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardCo=
nfigLib.inf
new file mode 100644
index 0000000000..b4da7162c1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyB=
oardConfigLib/DxePolicyBoardConfigLib.inf
@@ -0,0 +1,45 @@
+## @file
+# Module Information file for DxePolicyBoardConfigLib Library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D DxePolicyBoardConfigLib
+ FILE_GUID =3D 17836E9F-7188-4640-80A3-B4441585FFE9
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D DXE_DRIVER
+ LIBRARY_CLASS =3D DxePolicyUpdateLib|DXE_DRIVER
+
+#
+# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC
+#
+
+[Sources]
+ DxeSaPolicyBoardConfig.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseLib
+ BaseMemoryLib
+ PcdLib
+ DebugLib
+ HobLib
+ ConfigBlockLib
+
+[Guids]
+ gMemoryDxeConfigGuid ## CONSUMES
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Dxe=
PolicyBoardConfigLib/DxeSaPolicyBoardConfig.c b/Platform/Intel/CometlakeOpe=
nBoardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardCon=
fig.c
new file mode 100644
index 0000000000..78edbab5ad
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyB=
oardConfigLib/DxeSaPolicyBoardConfig.c
@@ -0,0 +1,36 @@
+/** @file
+ Intel DXE SA Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "DxePolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs DXE SA Policy update by board configuration.
+
+ @param[in, out] DxeSaPolicy DXE SA Policy
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicyBoardConfig (
+ IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy
+ )
+{
+ EFI_STATUS Status;
+ MEMORY_DXE_CONFIG *MemoryDxeConfig;
+
+ DEBUG((DEBUG_INFO, "Updating SA Policy by board config in DXE\n"));
+
+ Status =3D GetConfigBlock ((VOID *)DxeSaPolicy, &gMemoryDxeConfigGuid, (=
VOID *)&MemoryDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/CometlakeOpenBoardPkg=
/CometlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
new file mode 100644
index 0000000000..6a47a9bd09
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPlatfor=
mHookLib/PeiPlatformHooklib.c
@@ -0,0 +1,299 @@
+/** @file
+ PEI Library Functions. Initialize GPIOs
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <PeiPlatformHookLib.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PeiPlatformLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <PchAccess.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <Library/PchInfoLib.h>
+#include <Library/CnviLib.h>
+#include <SioRegs.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PchPcrLib.h>
+#include <Library/GpioCheckConflictLib.h>
+
+#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
+
+#define RECOVERY_MODE_GPIO_PIN 0 // =
Platform specific @todo use PCD
+
+#define MANUFACTURE_MODE_GPIO_PIN 0 // =
Platform specific @todo use PCD
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+
+ CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount);
+
+
+ GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+ Configure GPIO group GPE tier.
+
+ @retval none.
+**/
+VOID
+GpioGroupTierInitHook(
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n"));
+
+ if (PcdGet32 (PcdGpioGroupToGpeDw0)) {
+ GpioSetGroupToGpeDwX (PcdGet32 (PcdGpioGroupToGpeDw0),
+ PcdGet32 (PcdGpioGroupToGpeDw1),
+ PcdGet32 (PcdGpioGroupToGpeDw2));
+ }
+ DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n"));
+}
+
+/**
+ Configure single GPIO pad for touchpanel interrupt
+**/
+VOID
+TouchpanelGpioInit (
+ VOID
+ )
+{
+ GPIO_INIT_CONFIG* TouchpanelPad;
+ GPIO_PAD_OWN PadOwnVal;
+
+ PadOwnVal =3D 0;
+ TouchpanelPad =3D (VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableTouchPanel=
);
+ if (TouchpanelPad !=3D NULL) {
+ GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);
+ if (PadOwnVal =3D=3D GpioPadOwnHost) {
+ GpioConfigurePads (1, TouchpanelPad);
+ }
+ }
+}
+
+/**
+ Configure GPIO Before Memory is not ready.
+
+**/
+VOID
+GpioInitPreMem (
+ VOID
+ )
+{
+ if (PcdGet32 (PcdBoardGpioTablePreMem) !=3D 0 && PcdGet16 (PcdBoardGpioT=
ablePreMemSize) !=3D 0) {
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTablePreMem), (U=
INTN) PcdGet16 (PcdBoardGpioTablePreMemSize));
+ }
+}
+
+/**
+ Basic GPIO configuration before memory is ready
+
+**/
+VOID
+GpioInitEarlyPreMem (
+ VOID
+ )
+{
+ GPIO_CONFIG BbrstConfig;
+ UINT32 WwanBbrstGpio;
+
+ WwanBbrstGpio =3D PcdGet32 (PcdWwanBbrstGpio);
+
+ if (WwanBbrstGpio) {
+ //
+ // BIOS needs to put modem in OFF state for the two scenarios below.
+ // 1. Modem RESET# is not asserted via PLTRST# in the previous sleep s=
tate
+ // 2. Modem is disabled via setup option
+ //
+ GpioGetPadConfig (WwanBbrstGpio, &BbrstConfig);
+ if ((PcdGetBool (PcdPcieWwanEnable) =3D=3D FALSE) ||
+ (PcdGetBool (PcdWwanResetWorkaround) =3D=3D TRUE &&
+ BbrstConfig.Direction =3D=3D GpioDirOut &&
+ BbrstConfig.OutputState =3D=3D GpioOutHigh)) {
+ //
+ // Assert FULL_CARD_POWER_OFF#, RESET# and PERST# GPIOs
+ //
+ if (PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem) !=3D 0 && PcdGet1=
6 (PcdBoardGpioTableWwanOffEarlyPreMemSize) !=3D 0) {
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOff=
EarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize));
+ }
+ if (PcdGetBool (PcdPcieWwanEnable) =3D=3D TRUE && PcdGetBool (PcdWwa=
nResetWorkaround) =3D=3D TRUE) {
+ MicroSecondDelay (1 * 1000); // Delay by 1ms
+ }
+ }
+
+ //
+ // Turn ON modem power and de-assert RESET# and PERST# GPIOs
+ //
+ if (PcdGetBool (PcdPcieWwanEnable) =3D=3D TRUE) {
+ if (PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem) !=3D 0 && PcdGet16=
(PcdBoardGpioTableWwanOnEarlyPreMemSize) !=3D 0) {
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOnE=
arlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize));
+ }
+ }
+ }
+}
+
+/**
+ Configure GPIO
+
+**/
+VOID
+GpioInit (
+ VOID
+ )
+{
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) Pc=
dGet16 (PcdBoardGpioTableSize));
+
+ if (PcdGet32 (PcdBoardGpioTable2)) {
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable2), (UINTN)=
PcdGet16 (PcdBoardGpioTable2Size));
+ }
+
+ TouchpanelGpioInit();
+
+ //
+ // Lock pads after initializing platform GPIO.
+ // Pads which were requested to be unlocked during configuration
+ // will not be locked.
+ //
+ GpioLockPads ();
+
+ return;
+}
+
+/**
+ Configure Super IO
+
+**/
+VOID
+SioInit (
+ VOID
+ )
+{
+ //
+ // Program and Enable Default Super IO Configuration Port Addresses and =
range
+ //
+ PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x1=
0);
+
+ PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
+ return;
+}
+
+/**
+ Configure GPIO and SIO before memory ready
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+ VOID
+ )
+{
+ //
+ // Obtain Platform Info from HOB.
+ //
+ GpioInitPreMem ();
+ GpioGroupTierInitHook ();
+ SioInit ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ VOID
+ )
+{
+
+ GpioInit ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Do platform specific programming post-memory.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+
+EFI_STATUS
+PlatformSpecificInit (
+ VOID
+ )
+{
+ GPIO_CONFIG GpioConfig;
+
+ if (IsCnlPch ()) {
+
+ //
+ // Tristate unused pins by audio link mode.
+ //
+ ZeroMem(&GpioConfig, sizeof(GPIO_CONFIG));
+ GpioConfig.PadMode =3D GpioPadModeGpio;
+ GpioConfig.HostSoftPadOwn =3D GpioHostOwnGpio;
+ GpioConfig.Direction =3D GpioDirNone;
+ GpioConfig.OutputState =3D GpioOutDefault;
+ GpioConfig.InterruptConfig =3D GpioIntDis;
+ GpioConfig.PowerConfig =3D GpioPlatformReset;
+ GpioConfig.ElectricalConfig =3D GpioTermNone;
+
+ GpioSetPadConfig (GPIO_CNL_LP_SSP1_SFRM, &GpioConfig);
+ GpioSetPadConfig (GPIO_CNL_LP_SSP1_TXD, &GpioConfig);
+
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Early Board Configuration before memory is ready
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+ VOID
+ )
+{
+ GpioInitEarlyPreMem ();
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/CometlakeOpenBoardP=
kg/CometlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
new file mode 100644
index 0000000000..193ccc841f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPlatfor=
mHookLib/PeiPlatformHooklib.inf
@@ -0,0 +1,95 @@
+## @file
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PeiPlatformHookLib
+ FILE_GUID =3D AD901798-B0DA-4B20-B90C-283F886E76D0
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D PEIM
+ LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+ DebugLib
+ BaseMemoryLib
+ IoLib
+ HobLib
+ PcdLib
+ TimerLib
+ PchCycleDecodingLib
+ GpioLib
+ CpuPlatformLib
+ PeiServicesLib
+ ConfigBlockLib
+ PeiSaPolicyLib
+ GpioExpanderLib
+ PmcLib
+ PchPcrLib
+ PciSegmentLib
+ GpioCheckConflictLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress =
## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel #=
# CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemS=
ize
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem=
Size
+
+ # GPIO Group Tier
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 #=
# CONSUMES
+
+ # Misc
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio #=
# CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable #=
# CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround
+
+[Sources]
+ PeiPlatformHooklib.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gSiPolicyPpiGuid ## CONSUMES
+
+[Guids]
+ gSaDataHobGuid ## CONSUMES
+ gEfiGlobalVariableGuid ## CONSUMES
+ gGpioCheckConflictHobGuid ## CONSUMES
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c b/Platform/Intel/CometlakeOp=
enBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardC=
onfig.c
new file mode 100644
index 0000000000..d1d1920823
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiCpuPolicyBoardConfig.c
@@ -0,0 +1,49 @@
+/** @file
+ Intel PEI CPU Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI CPU Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_CONFIG *CpuConfig;
+
+ DEBUG((DEBUG_INFO, "Updating CPU Policy by board config in Post Mem\n"));
+
+ Status =3D PeiServicesLocatePpi(
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SiPreMemPolicyPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC=
onfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID =
*) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c b/Platform/Intel/Comet=
lakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicy=
BoardConfigPreMem.c
new file mode 100644
index 0000000000..2b80a268e6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
@@ -0,0 +1,29 @@
+/** @file
+ Intel PEI CPU Pre-Memory Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI CPU Pre-Memory Policy update by board configu=
ration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiMePolicyBoardConfig.c b/Platform/Intel/CometlakeOpe=
nBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardCon=
fig.c
new file mode 100644
index 0000000000..cff2b03ca9
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiMePolicyBoardConfig.c
@@ -0,0 +1,36 @@
+/** @file
+ Intel PEI ME Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI ME Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ ME_PEI_CONFIG *MePeiConfig;
+
+ DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Post Mem\n"));
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI=
D *) &MePeiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c b/Platform/Intel/Cometl=
akeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBo=
ardConfigPreMem.c
new file mode 100644
index 0000000000..610b6b8cb5
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiMePolicyBoardConfigPreMem.c
@@ -0,0 +1,37 @@
+/** @file
+ Intel PEI ME Pre-Memory Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI ME Pre-Memory Policy update by board configur=
ation.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig;
+
+ DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Pre Mem\n"));
+
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMePeiPreMemConf=
igGuid, (VOID *) &MePeiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiPchPolicyBoardConfig.c b/Platform/Intel/CometlakeOp=
enBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardC=
onfig.c
new file mode 100644
index 0000000000..a3b3a63eec
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiPchPolicyBoardConfig.c
@@ -0,0 +1,36 @@
+/** @file
+ Intel PEI PCH Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI PCH Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ PCH_GENERAL_CONFIG *PchGeneralConfig;
+
+ DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Post Mem\n"));
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid,=
(VOID *) &PchGeneralConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c b/Platform/Intel/Comet=
lakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicy=
BoardConfigPreMem.c
new file mode 100644
index 0000000000..01bb75525b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiPchPolicyBoardConfigPreMem.c
@@ -0,0 +1,37 @@
+/** @file
+ Intel PEI PCH Pre-Memory Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI PCH Pre-Memory Policy update by board configu=
ration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
+
+ DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Pre Mem\n"));
+
+ Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMe=
mConfigGuid, (VOID *) &PchGeneralPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiPolicyBoardConfig.h b/Platform/Intel/CometlakeOpenB=
oardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
new file mode 100644
index 0000000000..64f6c67639
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiPolicyBoardConfig.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for PeiPolicyBoardConfig library instance.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_POLICY_BOARD_CONFIG_H_
+#define _PEI_POLICY_BOARD_CONFIG_H_
+
+#include <PiPei.h>
+#include <ConfigBlock/MePeiConfig.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf b/Platform/Intel/Cometlake=
OpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardCo=
nfigLib.inf
new file mode 100644
index 0000000000..9eb7c5eef0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiPolicyBoardConfigLib.inf
@@ -0,0 +1,71 @@
+## @file
+# Module Information file for PeiPolicyBoardConfigLib Library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PeiPolicyBoardConfigLib
+ FILE_GUID =3D B1E959E3-9DCA-4D6F-938C-420C3BF5D820
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D PEIM
+ LIBRARY_CLASS =3D PeiPolicyBoardConfigLib|PEIM PEI_CORE=
SEC
+
+[Sources]
+ PeiCpuPolicyBoardConfigPreMem.c
+ PeiCpuPolicyBoardConfig.c
+ PeiMePolicyBoardConfigPreMem.c
+ PeiMePolicyBoardConfig.c
+ PeiPchPolicyBoardConfigPreMem.c
+ PeiPchPolicyBoardConfig.c
+ PeiSaPolicyBoardConfigPreMem.c
+ PeiSaPolicyBoardConfig.c
+ PeiSiPolicyBoardConfig.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ HobLib
+ ConfigBlockLib
+ IoLib
+ BaseCryptLib
+ BaseMemoryLib
+
+[Guids]
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gMePeiPreMemConfigGuid ## CONSUMES
+ gPchGeneralPreMemConfigGuid ## CONSUMES
+ gSaMiscPeiPreMemConfigGuid ## CONSUMES
+ gCpuConfigGuid ## CONSUMES
+ gPchGeneralConfigGuid ## CONSUMES
+ gEfiTpmDeviceInstanceTpm20DtpmGuid
+ gEfiTpmDeviceInstanceTpm12Guid
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES
+
+[FixedPcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
## CONSUMES
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiSaPolicyBoardConfig.c b/Platform/Intel/CometlakeOpe=
nBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardCon=
fig.c
new file mode 100644
index 0000000000..a8f6860bd0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiSaPolicyBoardConfig.c
@@ -0,0 +1,36 @@
+/** @file
+ Intel PEI SA Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI SA Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+
+ DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Post Mem\n"));
+
+ Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid=
, (VOID *)&GtConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c b/Platform/Intel/Cometl=
akeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBo=
ardConfigPreMem.c
new file mode 100644
index 0000000000..aef2c8958f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiSaPolicyBoardConfigPreMem.c
@@ -0,0 +1,37 @@
+/** @file
+ Intel PEI SA Pre-Memory Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI SA Pre-Memory Policy update by board configur=
ation.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+
+ DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Pre Mem\n"));
+
+ Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC=
onfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei=
PolicyBoardConfigLib/PeiSiPolicyBoardConfig.c b/Platform/Intel/CometlakeOpe=
nBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardCon=
fig.c
new file mode 100644
index 0000000000..e8dd2b9609
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB=
oardConfigLib/PeiSiPolicyBoardConfig.c
@@ -0,0 +1,27 @@
+/** @file
+ Intel PEI SA Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+
+/**
+ This function performs PEI SI Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully update=
d.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ return EFI_SUCCESS;
+}
+
--=20
2.16.2.windows.1
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Subject: [edk2-devel] [edk2-platforms] [PATCH v2 5/7] CometlakeOpenBoardPkg:
Add modules
Date: Wed, 12 Feb 2020 00:42:39 +0530
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280
Modules shared across board instances.
* BoardAcpiDxe - Performs DXE board ACPI initialization.
* PciHotPlug - Performs PCI-e resource configuration.
* PeiTbtInit - Initializes Thunderbolt policy in PEI.
* PolicyInitDxe - Initializes policy in DXE.
* TbtDxe - Performs Thunderbolt initialization in DXE.
* TbtSmm - Performs Thunderbolt initialization in SMM.
* BiosInfo - Provides the BIOS informations in PEI.
Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
---
.../Acpi/BoardAcpiDxe/AcpiGnvsInit.c | 96 +
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 290 +++
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 73 +
.../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 20 +
.../Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL | 37 +
.../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl | 516 ++++++
.../Acpi/BoardAcpiDxe/Dsdt/PciTree.asl | 309 ++++
.../Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 76 +
.../CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 93 +
.../CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf | 49 +
.../Features/PciHotPlug/PciHotPlug.c | 353 ++++
.../Features/PciHotPlug/PciHotPlug.h | 130 ++
.../Features/PciHotPlug/PciHotPlug.inf | 63 +
.../Features/Tbt/AcpiTables/Rtd3PcieTbt.asl | 405 +++++
.../Features/Tbt/AcpiTables/Tbt.asl | 1877 ++++++++++++++++=
++++
.../Features/Tbt/TbtInit/Dxe/TbtDxe.c | 228 +++
.../Features/Tbt/TbtInit/Dxe/TbtDxe.inf | 51 +
.../Features/Tbt/TbtInit/Pei/PeiTbtInit.c | 211 +++
.../Features/Tbt/TbtInit/Pei/PeiTbtInit.inf | 47 +
.../Features/Tbt/TbtInit/Smm/TbtSmiHandler.c | 1609 +++++++++++++++++
.../Features/Tbt/TbtInit/Smm/TbtSmiHandler.h | 180 ++
.../Features/Tbt/TbtInit/Smm/TbtSmm.c | 1765 ++++++++++++++++=
++
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 80 +
.../Policy/PolicyInitDxe/BoardInitLib.c | 608 +++++++
.../Policy/PolicyInitDxe/BoardInitLib.h | 32 +
.../Policy/PolicyInitDxe/CpuPolicyInitDxe.c | 46 +
.../Policy/PolicyInitDxe/CpuPolicyInitDxe.h | 38 +
.../Policy/PolicyInitDxe/GopPolicyInitDxe.c | 174 ++
.../Policy/PolicyInitDxe/GopPolicyInitDxe.h | 41 +
.../Policy/PolicyInitDxe/PchPolicyInitDxe.c | 55 +
.../Policy/PolicyInitDxe/PchPolicyInitDxe.h | 52 +
.../Policy/PolicyInitDxe/PolicyInitDxe.c | 88 +
.../Policy/PolicyInitDxe/PolicyInitDxe.h | 45 +
.../Policy/PolicyInitDxe/PolicyInitDxe.inf | 176 ++
.../Policy/PolicyInitDxe/SaPolicyInitDxe.c | 60 +
.../Policy/PolicyInitDxe/SaPolicyInitDxe.h | 56 +
.../Policy/PolicyInitDxe/SiliconPolicyInitDxe.c | 46 +
.../Policy/PolicyInitDxe/SiliconPolicyInitDxe.h | 37 +
38 files changed, 10112 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/=
AcpiGnvsInit.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/=
BoardAcpiDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/=
BoardAcpiDxe.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/=
Dsdt/AMLUPD.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/=
Dsdt/DSDT.ASL
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/=
Dsdt/HostBus.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/=
Dsdt/PciTree.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/=
Dsdt/Platform.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.=
inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlu=
g/PciHotPlug.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlu=
g/PciHotPlug.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlu=
g/PciHotPlug.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiT=
ables/Rtd3PcieTbt.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiT=
ables/Tbt.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtIn=
it/Dxe/TbtDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtIn=
it/Dxe/TbtDxe.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtIn=
it/Pei/PeiTbtInit.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtIn=
it/Pei/PeiTbtInit.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtIn=
it/Smm/TbtSmiHandler.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtIn=
it/Smm/TbtSmiHandler.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtIn=
it/Smm/TbtSmm.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtIn=
it/Smm/TbtSmm.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/BoardInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/BoardInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/CpuPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/CpuPolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/GopPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/GopPolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/PchPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/PchPolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/PolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/PolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/PolicyInitDxe.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/SaPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/SaPolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/SiliconPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD=
xe/SiliconPolicyInitDxe.h
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnv=
sInit.c b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsIn=
it.c
new file mode 100644
index 0000000000..452b300690
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
@@ -0,0 +1,96 @@
+/** @file
+ Acpi Gnvs Init Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <PchAccess.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/MpService.h>
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] GlobalNvs - Pointer of Global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **GlobalNvs
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GNVS;
+ EFI_MP_SERVICES_PROTOCOL *MpService;
+ UINTN NumberOfCPUs;
+ UINTN NumberOfEnabledCPUs;
+
+ Pages =3D EFI_SIZE_TO_PAGES (sizeof (EFI_GLOBAL_NVS_AREA));
+ Address =3D 0xffffffff; // allocate address below 4G.
+
+ Status =3D gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //
+ // Locate the MP services protocol
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be =
there.
+ //
+ Status =3D gBS->LocateProtocol (
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **) &MpService
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Determine the number of processors
+ //
+ MpService->GetNumberOfProcessors (
+ MpService,
+ &NumberOfCPUs,
+ &NumberOfEnabledCPUs
+ );
+
+ *GlobalNvs =3D (VOID *) (UINTN) Address;
+ SetMem (*GlobalNvs, sizeof (EFI_GLOBAL_NVS_AREA), 0);
+
+ //
+ // GNVS default value init here...
+ //
+ GNVS =3D (EFI_GLOBAL_NVS_AREA_PROTOCOL *) &Address;
+
+ GNVS->Area->ThreadCount =3D (UINT8)NumberOfEnabledCPUs;
+
+ //
+ // Miscellaneous
+ //
+ GNVS->Area->PL1LimitCS =3D 0;
+ GNVS->Area->PL1LimitCSValue =3D 4500;
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAc=
piDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiD=
xe.c
new file mode 100644
index 0000000000..7fc71bca64
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
@@ -0,0 +1,290 @@
+/** @file
+ ACPI Platform Driver
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/AslUpdateLib.h>
+
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/AcpiTable.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mG=
lobalNvsArea;
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] GlobalNvs - Pointer of Global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **GlobalNvs
+ );
+
+//
+// Function implementations
+//
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI tab=
le
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] Instance Return pointer to the first instance of th=
e protocol.
+ @param[in] Type TRUE if the desired protocol is a FV proto=
col.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the=
protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID *gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ //
+ // Locate protocol.
+ //
+ Status =3D gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+ for (Index =3D 0; Index < NumberOfHandles; Index++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status =3D gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (!Type) {
+
+ //
+ // Not looking for the FV protocol, so find the first instance of the
+ // protocol. There should not be any errors because our handle buff=
er
+ // should always contain at least one or LocateHandleBuffer would ha=
ve
+ // returned not found.
+ //
+ break;
+ }
+ //
+ // See if it has the ACPI storage file
+ //
+ Size =3D 0;
+ FvStatus =3D 0;
+ Status =3D ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ gEfiAcpiMult=
iTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+ //
+ // If we found it, then we are done
+ //
+ if (Status =3D=3D EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operatio=
ns
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID *gEfiAcpiMultiTableStorageGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance =3D 0;
+ TableHandle =3D 0;
+ CurrentTable =3D NULL;
+ FwVol =3D NULL;
+
+ //
+ // Find the AcpiSupport protocol
+ //
+ Status =3D LocateSupportProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &AcpiTable,
+ FALSE
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status =3D LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &FwVol,
+ TRUE
+ );
+
+ //
+ // Read tables from the storage file.
+ //
+
+ while (Status =3D=3D EFI_SUCCESS) {
+ Status =3D FwVol->ReadSection (
+ FwVol,
+ gEfiAcpiMultiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+ //
+ // Add the table
+ //
+ TableHandle =3D 0;
+
+ Status =3D AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable =3D NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not=
complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiBoard (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ AcpiGnvsInit((VOID **) &mGlobalNvsArea.Area);
+
+ //
+ // This PCD set must be done before PublishAcpiTablesFromFv.
+ // The PCD data will be used there.
+ //
+ PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mGlobalNvsArea.Area);
+
+ //
+ // Platform ACPI Tables
+ //
+ PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
+
+ //
+ // This protocol publish must be done after PublishAcpiTablesFromFv.
+ // The NVS data is be updated there.
+ //
+ Handle =3D NULL;
+ Status =3D gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiGlobalNvsAreaProtocolGuid,
+ &mGlobalNvsArea,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAc=
piDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcp=
iDxe.inf
new file mode 100644
index 0000000000..09b67376fb
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.i=
nf
@@ -0,0 +1,73 @@
+## @file
+# Component information file for AcpiPlatform module
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010005
+ BASE_NAME =3D BoardAcpiDxe
+ FILE_GUID =3D E269E77D-6163-4F5D-8E59-21EAF114D307
+ MODULE_TYPE =3D DXE_DRIVER
+ VERSION_STRING =3D 1.0
+ ENTRY_POINT =3D InstallAcpiBoard
+
+[Sources.common]
+ BoardAcpiDxe.c
+ AcpiGnvsInit.c
+ Dsdt/DSDT.ASL
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ PcAtChipsetPkg/PcAtChipsetPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ HobLib
+ AslUpdateLib
+ BoardAcpiTableLib
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gEfiMpServiceProtocolGuid ## CONSUMES
+ gEfiGlobalNvsAreaProtocolGuid
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid AND
+ gEfiPciRootBridgeIoProtocolGuid AND
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AM=
LUPD.asl b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLU=
PD.asl
new file mode 100644
index 0000000000..db9d0f7062
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
@@ -0,0 +1,20 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//////////////////////////////////////////////////////////////////////////=
/////////
+//Values are set like this to have ASL compiler reserve enough space for o=
bjects
+//////////////////////////////////////////////////////////////////////////=
/////////
+//
+// Available Sleep states
+//
+Name(SS1,0)
+Name(SS2,0)
+Name(SS3,1)
+Name(SS4,1)
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DS=
DT.ASL b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.A=
SL
new file mode 100644
index 0000000000..e2482489a3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
@@ -0,0 +1,37 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformBoardId.h"
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x02, // DSDT revision.
+ // A Revision field value greater than or equal to 2 signifies tha=
t integers
+ // declared within the Definition Block are to be evaluated as 64-=
bit values
+ "INTEL", // OEM ID (6 byte string)
+ "CML ",// OEM table ID (8 byte string)
+ 0x0 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ // Miscellaneous services enabled in Project
+ Include ("AMLUPD.asl")
+ Include ("PciTree.asl")
+ Include ("Platform.asl")
+
+ Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state
+ if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})}
+ if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})}
+ if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})}
+ Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state
+
+}// End of ASL File
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Ho=
stBus.asl b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Hos=
tBus.asl
new file mode 100644
index 0000000000..1fc89728c1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.a=
sl
@@ -0,0 +1,516 @@
+/** @file
+ This file contains the SystemAgent PCI Configuration space
+ definition.
+ It defines various System Agent PCI Configuration Space registers
+ which will be used to dynamically produce all resources in the Host Bus.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Define various System Agent (SA) PCI Configuration Space
+// registers which will be used to dynamically produce all
+// resources in the Host Bus _CRS.
+//
+OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
+Field (HBUS, DWordAcc, NoLock, Preserve)
+{
+ Offset(0x40), // EPBAR (0:0:0:40)
+ EPEN, 1, // Enable
+ , 11,
+ EPBR, 20, // EPBAR [31:12]
+
+ Offset(0x48), // MCHBAR (0:0:0:48)
+ MHEN, 1, // Enable
+ , 14,
+ MHBR, 17, // MCHBAR [31:15]
+
+ Offset(0x50), // GGC (0:0:0:50)
+ GCLK, 1, // GGCLCK
+
+ Offset(0x54), // DEVEN (0:0:0:54)
+ D0EN, 1, // DEV0 Enable
+ D1F2, 1, // DEV1 FUN2 Enable
+ D1F1, 1, // DEV1 FUN1 Enable
+ D1F0, 1, // DEV1 FUN0 Enable
+
+ Offset(0x60), // PCIEXBAR (0:0:0:60)
+ PXEN, 1, // Enable
+ PXSZ, 2, // PCI Express Size
+ , 23,
+ PXBR, 6, // PCI Express BAR [31:26]
+
+ Offset(0x68), // DMIBAR (0:0:0:68)
+ DIEN, 1, // Enable
+ , 11,
+ DIBR, 20, // DMIBAR [31:12]
+
+ Offset(0x70), // MESEG_BASE (0:0:0:70)
+ , 20,
+ MEBR, 12, // MESEG_BASE [31:20]
+
+ Offset(0x80), // PAM0 Register (0:0:0:80)
+ PMLK, 1, // PAM Lock bit.
+ , 3,
+ PM0H, 2, // PAM 0, High Nibble
+ , 2,
+
+ Offset(0x81), // PAM1 Register (0:0:0:81)
+ PM1L, 2, // PAM1, Low Nibble
+ , 2,
+ PM1H, 2, // PAM1, High Nibble
+ , 2,
+
+ Offset(0x82), // PAM2 Register (0:0:0:82)
+ PM2L, 2, // PAM2, Low Nibble
+ , 2,
+ PM2H, 2, // PAM2, High Nibble
+ , 2,
+
+ Offset(0x83), // PAM3 Register (0:0:0:83)
+ PM3L, 2, // PAM3, Low Nibble
+ , 2,
+ PM3H, 2, // PAM3, High Nibble
+ , 2,
+
+ Offset(0x84), // PAM4 Register (0:0:0:84)
+ PM4L, 2, // PAM4, Low Nibble
+ , 2,
+ PM4H, 2, // PAM4, High Nibble
+ , 2,
+
+ Offset(0x85), // PAM5 Register (0:0:0:85)
+ PM5L, 2, // PAM5, Low Nibble
+ , 2,
+ PM5H, 2, // PAM5, High Nibble
+ , 2,
+
+ Offset(0x86), // PAM6 Register (0:0:0:86)
+ PM6L, 2, // PAM6, Low Nibble
+ , 2,
+ PM6H, 2, // PAM6, High Nibble
+ , 2,
+
+ Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8)
+ , 20,
+ TUUD, 19, // TOUUD [38:20]
+
+ Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC)
+ , 20,
+ TLUD, 12, // TOLUD [31:20]
+
+ Offset(0xC8), // ERRSTS register (0:0:0:C8)
+ , 7,
+ HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR
+}
+
+//
+// Define a buffer that will store all the bus, memory, and IO information
+// relating to the Host Bus. This buffer will be dynamically altered in
+// the _CRS and passed back to the OS.
+//
+Name(BUF0,ResourceTemplate()
+{
+ //
+ // Bus Number Allocation: Bus 0 to 0xFF
+ //
+ WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
+ 0x0000,0x00FF,0x00,0x0100,,,PB00)
+
+ //
+ // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
+
+ //
+ // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+ //
+ Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+
+ //
+ // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
+
+ //
+ // Video Buffer Area ( 0xA0000 - 0xBFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
+
+ //
+ // BIOS Extension Area ( 0xE0000 - 0xE3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
+
+ //
+ // BIOS Extension Area ( 0xE4000 - 0xE7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
+
+ //
+ // BIOS Extension Area ( 0xE8000 - 0xEBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
+
+ //
+ // BIOS Extension Area ( 0xEC000 - 0xEFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
+
+ //
+ // BIOS Area ( 0xF0000 - 0xFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
+
+// //
+// // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
+// //
+// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
+
+ //
+ // PCI Memory Region ( TOLUD - 0xDFFFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x00000000,0xDFFFFFFF,0x00,0xE0000000,,,PM01)
+
+ //
+ // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) )
+ // (This is dummy range for OS compatibility, will patch it in _CRS)
+ //
+ QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02)
+
+ //
+ // PCH reserved resources ( 0xFC800000 - 0xFE7FFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0xFC800000,0xFE7FFFFF,0x00,0x2000000,,,PM03)
+})
+
+Name(EP_B, 0) // to store EP BAR
+Name(MH_B, 0) // to store MCH BAR
+Name(PC_B, 0) // to store PCIe BAR
+Name(PC_L, 0) // to store PCIe BAR Length
+Name(DM_B, 0) // to store DMI BAR
+
+//
+// Get EP BAR
+//
+Method(GEPB,0,Serialized)
+{
+ if(LEqual(EP_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.EPBR,12,EP_B)
+ }
+ Return(EP_B)
+}
+
+//
+// Get MCH BAR
+//
+Method(GMHB,0,Serialized)
+{
+ if(LEqual(MH_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.MHBR,15,MH_B)
+ }
+ Return(MH_B)
+}
+
+//
+// Get PCIe BAR
+//
+Method(GPCB,0,Serialized)
+{
+ if(LEqual(PC_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.PXBR,26,PC_B)
+ }
+ Return(PC_B)
+}
+
+//
+// Get PCIe Length
+//
+Method(GPCL,0,Serialized)
+{
+ if(LEqual(PC_L,0)) {
+ ShiftRight(0x10000000, \_SB.PCI0.PXSZ,PC_L)
+ }
+ Return(PC_L)
+}
+
+//
+// Get DMI BAR
+//
+Method(GDMB,0,Serialized)
+{
+ if(LEqual(DM_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.DIBR,12,DM_B)
+ }
+ Return(DM_B)
+}
+
+
+Method(_CRS,0,Serialized)
+{
+ //
+ // Fix up Max Bus Number and Length
+ //
+ Store(\_SB.PCI0.GPCL(),Local0)
+ CreateWordField(BUF0, ^PB00._MAX, PBMX)
+ Store(Subtract(ShiftRight(Local0,20),2), PBMX)
+ CreateWordField(BUF0, ^PB00._LEN, PBLN)
+ Store(Subtract(ShiftRight(Local0,20),1), PBLN)
+ //
+ // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF.
+ //
+ If(PM1L) // \_SB.PCI0
+ {
+ // PAMx !=3D 0. Set length =3D 0.
+
+ CreateDwordField(BUF0, ^C000._LEN,C0LN)
+ Store(Zero,C0LN)
+ }
+
+ If(LEqual(PM1L,1))
+ {
+ CreateBitField(BUF0, ^C000._RW,C0RW)
+ Store(Zero,C0RW)
+ }
+
+ If(PM1H)
+ {
+ CreateDwordField(BUF0, ^C400._LEN,C4LN)
+ Store(Zero,C4LN)
+ }
+
+ If(LEqual(PM1H,1))
+ {
+ CreateBitField(BUF0, ^C400._RW,C4RW)
+ Store(Zero,C4RW)
+ }
+
+ If(PM2L)
+ {
+ CreateDwordField(BUF0, ^C800._LEN,C8LN)
+ Store(Zero,C8LN)
+ }
+
+ If(LEqual(PM2L,1))
+ {
+ CreateBitField(BUF0, ^C800._RW,C8RW)
+ Store(Zero,C8RW)
+ }
+
+ If(PM2H)
+ {
+ CreateDwordField(BUF0, ^CC00._LEN,CCLN)
+ Store(Zero,CCLN)
+ }
+
+ If(LEqual(PM2H,1))
+ {
+ CreateBitField(BUF0, ^CC00._RW,CCRW)
+ Store(Zero,CCRW)
+ }
+
+ If(PM3L)
+ {
+ CreateDwordField(BUF0, ^D000._LEN,D0LN)
+ Store(Zero,D0LN)
+ }
+
+ If(LEqual(PM3L,1))
+ {
+ CreateBitField(BUF0, ^D000._RW,D0RW)
+ Store(Zero,D0RW)
+ }
+
+ If(PM3H)
+ {
+ CreateDwordField(BUF0, ^D400._LEN,D4LN)
+ Store(Zero,D4LN)
+ }
+
+ If(LEqual(PM3H,1))
+ {
+ CreateBitField(BUF0, ^D400._RW,D4RW)
+ Store(Zero,D4RW)
+ }
+
+ If(PM4L)
+ {
+ CreateDwordField(BUF0, ^D800._LEN,D8LN)
+ Store(Zero,D8LN)
+ }
+
+ If(LEqual(PM4L,1))
+ {
+ CreateBitField(BUF0, ^D800._RW,D8RW)
+ Store(Zero,D8RW)
+ }
+
+ If(PM4H)
+ {
+ CreateDwordField(BUF0, ^DC00._LEN,DCLN)
+ Store(Zero,DCLN)
+ }
+
+ If(LEqual(PM4H,1))
+ {
+ CreateBitField(BUF0, ^DC00._RW,DCRW)
+ Store(Zero,DCRW)
+ }
+
+ If(PM5L)
+ {
+ CreateDwordField(BUF0, ^E000._LEN,E0LN)
+ Store(Zero,E0LN)
+ }
+
+ If(LEqual(PM5L,1))
+ {
+ CreateBitField(BUF0, ^E000._RW,E0RW)
+ Store(Zero,E0RW)
+ }
+
+ If(PM5H)
+ {
+ CreateDwordField(BUF0, ^E400._LEN,E4LN)
+ Store(Zero,E4LN)
+ }
+
+ If(LEqual(PM5H,1))
+ {
+ CreateBitField(BUF0, ^E400._RW,E4RW)
+ Store(Zero,E4RW)
+ }
+
+ If(PM6L)
+ {
+ CreateDwordField(BUF0, ^E800._LEN,E8LN)
+ Store(Zero,E8LN)
+ }
+
+ If(LEqual(PM6L,1))
+ {
+ CreateBitField(BUF0, ^E800._RW,E8RW)
+ Store(Zero,E8RW)
+ }
+
+ If(PM6H)
+ {
+ CreateDwordField(BUF0, ^EC00._LEN,ECLN)
+ Store(Zero,ECLN)
+ }
+
+ If(LEqual(PM6H,1))
+ {
+ CreateBitField(BUF0, ^EC00._RW,ECRW)
+ Store(Zero,ECRW)
+ }
+
+ If(PM0H)
+ {
+ CreateDwordField(BUF0, ^F000._LEN,F0LN)
+ Store(Zero,F0LN)
+ }
+
+ If(LEqual(PM0H,1))
+ {
+ CreateBitField(BUF0, ^F000._RW,F0RW)
+ Store(Zero,F0RW)
+ }
+
+ //
+ // Create pointers to Memory Sizing values.
+ //
+ CreateDwordField(BUF0, ^PM01._MIN,M1MN)
+ CreateDwordField(BUF0, ^PM01._MAX,M1MX)
+ CreateDwordField(BUF0, ^PM01._LEN,M1LN)
+
+ //
+ // Set Memory Size Values. TLUD represents bits 31:20 of phyical
+ // TOM, so shift these bits into the correct position and fix up
+ // the Memory Region available to PCI.
+ //
+ Add (Subtract (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPc=
iReservedMemBase)), 1, M1LN)
+ Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)
+ Store (FixedPcdGet32(PcdPciReservedMemLimit), M1MX)
+
+ //
+ // Create pointers to Memory Sizing values.
+ // Patch PM02 range basing on memory size and OS type
+ //
+ CreateQwordField(BUF0, ^PM02._LEN,MSLN)
+ //
+ // Set resource length to 0
+ //
+ Store (0, MSLN)
+
+ D8XH (0, 0xC5)
+ D8XH (1, 0xAA)
+
+ Return(BUF0)
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pc=
iTree.asl b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pci=
Tree.asl
new file mode 100644
index 0000000000..111f120d89
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.a=
sl
@@ -0,0 +1,309 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Scope(\_SB) {
+ Name(PD00, Package(){
+// If the setting changed in PCH PxRcConfig policy, platform should also u=
pdate static assignment here.
+// PCI Bridge
+// D31: cAVS, SMBus, GbE, Nothpeak
+ Package(){0x001FFFFF, 0, 0, 11 },
+ Package(){0x001FFFFF, 1, 0, 10 },
+ Package(){0x001FFFFF, 2, 0, 11 },
+ Package(){0x001FFFFF, 3, 0, 11 },
+// D30: SerialIo and SCS - can't use PIC
+// D29: PCI Express Port 9-16
+ Package(){0x001DFFFF, 0, 0, 11 },
+ Package(){0x001DFFFF, 1, 0, 10 },
+ Package(){0x001DFFFF, 2, 0, 11 },
+ Package(){0x001DFFFF, 3, 0, 11 },
+// D28: PCI Express Port 1-8
+ Package(){0x001CFFFF, 0, 0, 11 },
+ Package(){0x001CFFFF, 1, 0, 10 },
+ Package(){0x001CFFFF, 2, 0, 11 },
+ Package(){0x001CFFFF, 3, 0, 11 },
+// D27: PCI Express Port 17-20
+ Package(){0x001BFFFF, 0, 0, 11 },
+ Package(){0x001BFFFF, 1, 0, 10 },
+ Package(){0x001BFFFF, 2, 0, 11 },
+ Package(){0x001BFFFF, 3, 0, 11 },
+// D25: SerialIo - can't use PIC
+// D23: SATA controller
+ Package(){0x0017FFFF, 0, 0, 11 },
+// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
+ Package(){0x0016FFFF, 0, 0, 11 },
+ Package(){0x0016FFFF, 1, 0, 10 },
+ Package(){0x0016FFFF, 2, 0, 11 },
+ Package(){0x0016FFFF, 3, 0, 11 },
+// D21: SerialIo - can't use PIC
+// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
+// D20: xHCI, OTG, CNVi WiFi, SDcard
+ Package(){0x0014FFFF, 0, 0, 11 },
+ Package(){0x0014FFFF, 1, 0, 10 },
+ Package(){0x0014FFFF, 2, 0, 11 },
+ Package(){0x0014FFFF, 3, 0, 11 },
+// D19: Integrated Sensor Hub - can't use PIC
+// D18: Thermal, UFS, SerialIo SPI2 - can't use PIC
+ Package(){0x0012FFFF, 0, 0, 11 },
+ Package(){0x0012FFFF, 1, 0, 10 },
+ Package(){0x0012FFFF, 2, 0, 11 },
+ Package(){0x0012FFFF, 3, 0, 11 },
+
+// Host Bridge
+// P.E.G. Root Port D1F0
+ Package(){0x0001FFFF, 0, 0, 11 },
+ Package(){0x0001FFFF, 1, 0, 10 },
+ Package(){0x0001FFFF, 2, 0, 11 },
+ Package(){0x0001FFFF, 3, 0, 11 },
+// P.E.G. Root Port D1F1
+// P.E.G. Root Port D1F2
+// SA IGFX Device
+ Package(){0x0002FFFF, 0, 0, 11 },
+// SA Thermal Device
+ Package(){0x0004FFFF, 0, 0, 11 },
+// SA IPU Device
+ Package(){0x0005FFFF, 0, 0, 11 },
+// SA GNA Device
+ Package(){0x0008FFFF, 0, 0, 11 },
+ })
+ Name(AR00, Package(){
+// PCI Bridge
+// D31: cAVS, SMBus, GbE, Nothpeak
+ Package(){0x001FFFFF, 0, 0, 16 },
+ Package(){0x001FFFFF, 1, 0, 17 },
+ Package(){0x001FFFFF, 2, 0, 18 },
+ Package(){0x001FFFFF, 3, 0, 19 },
+// D30: SerialIo and SCS
+ Package(){0x001EFFFF, 0, 0, 20 },
+ Package(){0x001EFFFF, 1, 0, 21 },
+ Package(){0x001EFFFF, 2, 0, 22 },
+ Package(){0x001EFFFF, 3, 0, 23 },
+// D29: PCI Express Port 9-16
+ Package(){0x001DFFFF, 0, 0, 16 },
+ Package(){0x001DFFFF, 1, 0, 17 },
+ Package(){0x001DFFFF, 2, 0, 18 },
+ Package(){0x001DFFFF, 3, 0, 19 },
+// D28: PCI Express Port 1-8
+ Package(){0x001CFFFF, 0, 0, 16 },
+ Package(){0x001CFFFF, 1, 0, 17 },
+ Package(){0x001CFFFF, 2, 0, 18 },
+ Package(){0x001CFFFF, 3, 0, 19 },
+// D27: PCI Express Port 17-20
+ Package(){0x001BFFFF, 0, 0, 16 },
+ Package(){0x001BFFFF, 1, 0, 17 },
+ Package(){0x001BFFFF, 2, 0, 18 },
+ Package(){0x001BFFFF, 3, 0, 19 },
+// D26: eMMC
+ Package(){0x001AFFFF, 0, 0, 16 },
+ Package(){0x001AFFFF, 1, 0, 17 },
+ Package(){0x001AFFFF, 2, 0, 18 },
+ Package(){0x001AFFFF, 3, 0, 19 },
+// D25: SerialIo
+ Package(){0x0019FFFF, 0, 0, 32 },
+ Package(){0x0019FFFF, 1, 0, 33 },
+ Package(){0x0019FFFF, 2, 0, 34 },
+// D23: SATA controller
+ Package(){0x0017FFFF, 0, 0, 16 },
+// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
+ Package(){0x0016FFFF, 0, 0, 16 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+ Package(){0x0016FFFF, 2, 0, 18 },
+ Package(){0x0016FFFF, 3, 0, 19 },
+// D21: SerialIo
+ Package(){0x0015FFFF, 0, 0, 16 },
+ Package(){0x0015FFFF, 1, 0, 17 },
+ Package(){0x0015FFFF, 2, 0, 18 },
+ Package(){0x0015FFFF, 3, 0, 19 },
+// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
+// D20: xHCI, OTG, CNVi WiFi, SDcard
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+// D19: Integrated Sensor Hub
+ Package(){0x0013FFFF, 0, 0, 20 },
+// D18: Thermal, UFS, SerialIo SPI 2
+ Package(){0x0012FFFF, 0, 0, 16 },
+ Package(){0x0012FFFF, 1, 0, 24 },
+ Package(){0x0012FFFF, 2, 0, 18 },
+ Package(){0x0012FFFF, 3, 0, 19 },
+
+// Host Bridge
+// P.E.G. Root Port D1F0
+ Package(){0x0001FFFF, 0, 0, 16 },
+ Package(){0x0001FFFF, 1, 0, 17 },
+ Package(){0x0001FFFF, 2, 0, 18 },
+ Package(){0x0001FFFF, 3, 0, 19 },
+// P.E.G. Root Port D1F1
+// P.E.G. Root Port D1F2
+// SA IGFX Device
+ Package(){0x0002FFFF, 0, 0, 16 },
+// SA Thermal Device
+ Package(){0x0004FFFF, 0, 0, 16 },
+// SA IPU Device
+ Package(){0x0005FFFF, 0, 0, 16 },
+// SA GNA Device
+ Package(){0x0008FFFF, 0, 0, 16 },
+ })
+ Name(PD04, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 10 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR04, Package(){
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PD05, Package(){
+ Package(){0x0000FFFF, 0, 0, 10 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR05, Package(){
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PD06, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 10 },
+ })
+ Name(AR06, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+ Name(PD07, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 10 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR07, Package(){
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+ Name(PD08, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 10 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR08, Package(){
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PD09, Package(){
+ Package(){0x0000FFFF, 0, 0, 10 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR09, Package(){
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PD0E, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 10 },
+ })
+ Name(AR0E, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+ Name(PD0F, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 10 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR0F, Package(){
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+ Name(PD02, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 10 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR02, Package(){
+// P.E.G. Port Slot x16
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PD0A, Package(){
+// P.E.G. Port Slot x8
+ Package(){0x0000FFFF, 0, 0, 10 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR0A, Package(){
+// P.E.G. Port Slot x8
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PD0B, Package(){
+// P.E.G. Port Slot x4
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 10 },
+ })
+ Name(AR0B, Package(){
+// P.E.G. Port Slot x4
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+//------------------------------------------------------------------------=
---
+// Begin PCI tree object scope
+//------------------------------------------------------------------------=
---
+ Device(PCI0) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 hos=
t hierarchy
+ Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't und=
erstand the new HID
+ Name(_SEG, 0)
+ Name(_ADR, 0x00000000)
+ Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for =
Peer PCI busses. Name can be overriden with control method placed directly =
under Device scope
+ Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root=
PCI Bus
+ Name(_UID, 0x0000) // Unique Bus ID, optional
+ Method(_PRT,0) {
+ If(PICM) {Return(AR00)} // APIC mode
+ Return (PD00) // PIC Mode
+ } // end _PRT
+
+ Include("HostBus.asl")
+ } // end PCI0 Bridge "Host Bridge"
+} // end _SB scope
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pl=
atform.asl b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pl=
atform.asl
new file mode 100644
index 0000000000..ad3e560b0d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.=
asl
@@ -0,0 +1,76 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+// Define Port 80 as an ACPI Operating Region to use for debugging. Please
+// note that the Intel CRBs have the ability to ouput a Word to
+// Port 80h for debugging purposes, so the model implemented here may not =
be
+// able to be used on OEM Designs.
+
+OperationRegion(PRT0,SystemIO,0x80,2)
+Field(PRT0,WordAcc,Lock,Preserve)
+{
+ P80B, 16
+}
+
+// Port 80h Update:
+// Update 2 bytes of Port 80h.
+//
+// Arguments:
+// Arg0: 0 =3D Write Port 80h
+// 1 =3D Write Port 81h
+// Arg1: 8-bit Value to write
+//
+// Return Value:
+// None
+
+Name(P80T, 0) // temp buffer for P80
+
+Method(D8XH,2,Serialized)
+{
+ If(LEqual(Arg0,0)) // Write Port 80h
+ {
+ Store(Or(And(P80T,0xFF00),Arg1),P80T)
+ }
+ If(LEqual(Arg0,1)) // Write Port 81h
+ {
+ Store(Or(And(P80T,0x00FF),ShiftLeft(Arg1,8)),P80T)
+ }
+ Store(P80T,P80B)
+}
+
+//
+// Define SW SMI port as an ACPI Operating Region to use for generate SW S=
MI.
+//
+OperationRegion(SPRT,SystemIO, 0xB2,2)
+Field (SPRT, ByteAcc, Lock, Preserve) {
+ SSMP, 8
+}
+
+// The _PIC Control Method is optional for ACPI design. It allows the
+// OS to inform the ASL code which interrupt controller is being used,
+// the 8259 or APIC. The reference code in this document will address
+// PCI IRQ Routing and resource allocation for both cases.
+//
+// The values passed into _PIC are:
+// 0 =3D 8259
+// 1 =3D IOAPIC
+
+Method(\_PIC,1)
+{
+ Store(Arg0,PICM)
+}
+
+Scope (\)
+{
+ //
+ // Global Name, returns current Interrupt controller mode;
+ // updated from _PIC control method
+ //
+ Name(PICM, 0)
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Pla=
tform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..c49dd4ed32
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,93 @@
+/** @file
+ Driver for BIOS Info support.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+
+#define INDEXPORT_TO_ADDRESS(x) (x)
+#define DATAPORT_TO_ADDRESS(x) ((x) << 16)
+#define PORTWIDTH_TO_ADDRESS(x) ((x) << 32)
+#define PORTBITNUMBER_TO_ADDRESS(x) ((x) << 40)
+#define PORTINDEXNUMBER_TO_ADDRESS(x) ((x) << 48)
+
+//
+// Internal
+//
+#pragma pack (1)
+
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[1];
+} BIOS_INFO;
+#pragma pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo =3D {
+ {
+ BIOS_INFO_SIGNATURE,
+ 1,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ }
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList =3D=
{
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi and builds BiosInfo HOB .
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi and HOB successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status =3D PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData =3D BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData !=3D NULL);
+ if (HobData =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/P=
latform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..9208aeda5d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,49 @@
+### @file
+# Module Information description file for BIOS Info Driver
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+###
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D BiosInfo
+ FILE_GUID =3D A842B2D2-5C88-44E9-A9E2-4830F26662B7
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D PEIM
+ ENTRY_POINT =3D BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ HobLib
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSU=
MES
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSU=
MES
+
+[Sources]
+ BiosInfo.c
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHo=
tPlug.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPl=
ug.c
new file mode 100644
index 0000000000..7124c1496d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
@@ -0,0 +1,353 @@
+/** @file
+ Pci Hotplug Driver : This file will perform specific PCI-EXPRESS
+ Devics resource configuration.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include "PciHotPlug.h"
+#include <Ppi/SiPolicy.h>
+#include <TbtBoardInfo.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/TbtCommonLib.h>
+
+#define PCIE_NUM (20)
+#define PEG_NUM (3)
+#define PADDING_BUS (1)
+#define PADDING_NONPREFETCH_MEM (1)
+#define PADDING_PREFETCH_MEM (1)
+#define PADDING_IO (1)
+#define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM + PADDING_PREFE=
TCH_MEM + PADDING_IO)
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION mPcieLocation[PCIE=
_NUM + PEG_NUM];
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount =3D 0;
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH mHotplugPcieDevice=
PathTemplate =3D {
+ ACPI,
+ PCI(0xFF, 0xFF), // Dummy Device no & Function no
+ END
+};
+
+/**
+ Entry point for the driver.
+
+ This routine reads the PlatformType GPI on FWH and produces a protocol
+ to be consumed by the chipset driver to effect those settings.
+
+ @param[in] ImageHandle An image handle.
+ @param[in] SystemTable A pointer to the system table.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+PciHotPlug (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ PCI_HOT_PLUG_INSTANCE *PciHotPlug;
+ UINTN Index;
+ UINTN RpDev;
+ UINTN RpFunc;
+ PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath;
+ UINT32 PcieRootPortHpeData =3D 0;
+
+ DEBUG ((DEBUG_INFO, "PciHotPlug Entry\n"));
+
+ PcieRootPortHpeData =3D PcdGet32 (PcdPchPcieRootPortHpe);
+ //
+ // PCH Rootports Hotplug device path creation
+ //
+ for (Index =3D 0; Index < PCIE_NUM; Index++) {
+ if (((PcieRootPortHpeData >> Index) & BIT0) =3D=3D BIT0) { // Check th=
e Rootport no's hotplug is set
+ Status =3D GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the a=
ctual device/function no corresponding to the Rootport no provided
+ ASSERT_EFI_ERROR (Status);
+
+ HotplugPcieDevicePath =3D NULL;
+ HotplugPcieDevicePath =3D AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE=
_PATH));
+ ASSERT (HotplugPcieDevicePath !=3D NULL);
+ if (HotplugPcieDevicePath =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, siz=
eof (PCIE_HOT_PLUG_DEVICE_PATH));
+ HotplugPcieDevicePath->PciRootPortNode.Device =3D (UINT8) RpDev; // =
Update real Device no
+ HotplugPcieDevicePath->PciRootPortNode.Function =3D (UINT8) RpFunc; =
// Update real Function no
+
+ mPcieLocation[mHpcCount].HpcDevicePath =3D (EFI_DEVICE_PATH_PROTOCOL=
*)HotplugPcieDevicePath;
+ mPcieLocation[mHpcCount].HpbDevicePath =3D (EFI_DEVICE_PATH_PROTOCOL=
*)HotplugPcieDevicePath;
+ mHpcCount++;
+
+ DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00, Device =
0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount=
, RpDev, RpFunc));
+ }
+ }
+
+
+ PciHotPlug =3D AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE));
+ ASSERT (PciHotPlug !=3D NULL);
+ if (PciHotPlug =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Initialize driver private data.
+ //
+ ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE));
+
+ PciHotPlug->Signature =3D PCI_HOT_PLUG_DRI=
VER_PRIVATE_SIGNATURE;
+ PciHotPlug->HotPlugInitProtocol.GetRootHpcList =3D GetRootHpcList;
+ PciHotPlug->HotPlugInitProtocol.InitializeRootHpc =3D InitializeRootHp=
c;
+ PciHotPlug->HotPlugInitProtocol.GetResourcePadding =3D GetResourcePaddi=
ng;
+
+ Status =3D gBS->InstallProtocolInterface (
+ &PciHotPlug->Handle,
+ &gEfiPciHotPlugInitProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &PciHotPlug->HotPlugInitProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This procedure returns a list of Root Hot Plug controllers that require
+ initialization during boot process
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLU=
G_INIT protocol.
+ @param[out] HpcCount The number of Root HPCs returned.
+ @param[out] HpcList The list of Root HPCs. HpcCount defines the number=
of elements in this list.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetRootHpcList (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ OUT UINTN *HpcCount,
+ OUT EFI_HPC_LOCATION **HpcList
+ )
+{
+ *HpcCount =3D mHpcCount;
+ *HpcList =3D mPcieLocation;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This procedure Initializes one Root Hot Plug Controller
+ This process may casue initialization of its subordinate buses
+
+ @param[in] This The pointer to the instance of the EFI_PCI_H=
OT_PLUG_INIT protocol.
+ @param[in] HpcDevicePath The Device Path to the HPC that is being ini=
tialized.
+ @param[in] HpcPciAddress The address of the Hot Plug Controller funct=
ion on the PCI bus.
+ @param[in] Event The event that should be signaled when the H=
ot Plug Controller initialization is complete. Set to NULL if the caller wa=
nts to wait until the entire initialization process is complete. The event =
must be of the type EFI_EVT_SIGNAL.
+ @param[out] HpcState The state of the Hot Plug Controller hardwar=
e. The type EFI_Hpc_STATE is defined in section 3.1.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+InitializeRootHpc (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
+ IN UINT64 HpcPciAddress,
+ IN EFI_EVENT Event, OPTIONAL
+ OUT EFI_HPC_STATE *HpcState
+ )
+{
+ if (Event) {
+ gBS->SignalEvent (Event);
+ }
+
+ *HpcState =3D EFI_HPC_STATE_INITIALIZED;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Returns the resource padding required by the PCI bus that is controlled =
by the specified Hot Plug Controller.
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HO=
T_PLUG_INIT protocol. initialized.
+ @param[in] HpcDevicePath The Device Path to the Hot Plug Controller.
+ @param[in] HpcPciAddress The address of the Hot Plug Controller functi=
on on the PCI bus.
+ @param[out] HpcState The state of the Hot Plug Controller hardware=
. The type EFI_HPC_STATE is defined in section 3.1.
+ @param[out] Padding This is the amount of resource padding requir=
ed by the PCI bus under the control of the specified Hpc. Since the caller =
does not know the size of this buffer, this buffer is allocated by the call=
ee and freed by the caller.
+ @param[out] Attribute Describes how padding is accounted for.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetResourcePadding (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
+ IN UINT64 HpcPciAddress,
+ OUT EFI_HPC_STATE *HpcState,
+ OUT VOID **Padding,
+ OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource;
+ EFI_STATUS Status;
+ UINT8 RsvdExtraBusNum =3D 0;
+ UINT16 RsvdPcieMegaMem =3D 10;
+ UINT8 PcieMemAddrRngMax =3D 0;
+ UINT16 RsvdPciePMegaMem =3D 10;
+ UINT8 PciePMemAddrRngMax =3D 0;
+ UINT8 RsvdTbtExtraBusNum =3D 0;
+ UINT16 RsvdTbtPcieMegaMem =3D 10;
+ UINT8 TbtPcieMemAddrRngMax =3D 0;
+ UINT16 RsvdTbtPciePMegaMem =3D 10;
+ UINT8 TbtPciePMemAddrRngMax =3D 0;
+ UINT8 RsvdPcieKiloIo =3D 4;
+ BOOLEAN SetResourceforTbt =3D FALSE;
+ UINTN RpIndex;
+ UINTN RpDev;
+ UINTN RpFunc;
+
+DEBUG ((DEBUG_INFO, "GetResourcePadding : Start \n"));
+
+ PaddingResource =3D AllocatePool (PADDING_NUM * sizeof (EFI_ACPI_ADDRESS=
_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
+ ASSERT (PaddingResource !=3D NULL);
+ if (PaddingResource =3D=3D NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ *Padding =3D (VOID *) PaddingResource;
+
+ RpDev =3D (UINTN) ((HpcPciAddress >> 16) & 0xFF);
+ RpFunc =3D (UINTN) ((HpcPciAddress >> 8) & 0xFF);
+
+ // Get the actual Rootport no corresponding to the device/function no pr=
ovided
+ if (RpDev =3D=3D SA_PEG_DEV_NUM) {
+ // PEG
+ RpIndex =3D PCIE_NUM + RpFunc;
+ DEBUG ((DEBUG_INFO, "GetResourcePadding : PEG Rootport no %02d Bus 0x0=
0, Device 0x%x, Function 0x%x \n", (RpIndex-PCIE_NUM), RpDev, RpFunc));
+ } else {
+ // PCH
+ Status =3D GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex);
+ DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH Rootport no %02d Bus 0x0=
0, Device 0x%x, Function 0x%x \n", RpIndex, RpDev, RpFunc));
+ }
+
+ GetRootporttoSetResourcesforTbt(RpIndex, &RsvdTbtExtraBusNum, &RsvdTbtPc=
ieMegaMem ,&TbtPcieMemAddrRngMax ,&RsvdTbtPciePMegaMem ,&TbtPciePMemAddrRng=
Max, &SetResourceforTbt);
+ if (SetResourceforTbt) {
+ RsvdExtraBusNum =3D RsvdTbtExtraBusNum;
+ RsvdPcieMegaMem =3D RsvdTbtPcieMegaMem;
+ PcieMemAddrRngMax =3D TbtPcieMemAddrRngMax;
+ RsvdPciePMegaMem =3D RsvdTbtPciePMegaMem;
+ PciePMemAddrRngMax =3D TbtPciePMemAddrRngMax;
+ }
+
+ //
+ // Padding for bus
+ //
+ ZeroMem (PaddingResource, PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_D=
ESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
+ *Attributes =3D EfiPaddingPciBus;
+
+ PaddingResource->Desc =3D 0x8A;
+ PaddingResource->Len =3D 0x2B;
+ PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_BUS;
+ PaddingResource->GenFlag =3D 0x0;
+ PaddingResource->SpecificFlag =3D 0;
+ PaddingResource->AddrRangeMin =3D 0;
+ PaddingResource->AddrRangeMax =3D 0;
+ PaddingResource->AddrLen =3D RsvdExtraBusNum;
+
+ //
+ // Padding for non-prefetchable memory
+ //
+ PaddingResource++;
+ PaddingResource->Desc =3D 0x8A;
+ PaddingResource->Len =3D 0x2B;
+ PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM;
+ PaddingResource->GenFlag =3D 0x0;
+ if (SetResourceforTbt) {
+ PaddingResource->AddrSpaceGranularity =3D 32;
+ } else {
+ PaddingResource->AddrSpaceGranularity =3D 32;
+ }
+ PaddingResource->SpecificFlag =3D 0;
+ //
+ // Pad non-prefetchable
+ //
+ PaddingResource->AddrRangeMin =3D 0;
+ PaddingResource->AddrLen =3D RsvdPcieMegaMem * 0x100000;
+ if (SetResourceforTbt) {
+ PaddingResource->AddrRangeMax =3D (1 << PcieMemAddrRngMax) - 1;
+ } else {
+ PaddingResource->AddrRangeMax =3D 1;
+ }
+
+ //
+ // Padding for prefetchable memory
+ //
+ PaddingResource++;
+ PaddingResource->Desc =3D 0x8A;
+ PaddingResource->Len =3D 0x2B;
+ PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM;
+ PaddingResource->GenFlag =3D 0x0;
+ if (SetResourceforTbt) {
+ PaddingResource->AddrSpaceGranularity =3D 32;
+ } else {
+ PaddingResource->AddrSpaceGranularity =3D 32;
+ }
+ PaddingResource->SpecificFlag =3D 06;
+ //
+ // Padding for prefetchable memory
+ //
+ PaddingResource->AddrRangeMin =3D 0;
+ if (SetResourceforTbt) {
+ PaddingResource->AddrLen =3D RsvdPciePMegaMem * 0x100000;
+ } else {
+ PaddingResource->AddrLen =3D RsvdPcieMegaMem * 0x100000;
+ }
+ //
+ // Pad 16 MB of MEM
+ //
+ if (SetResourceforTbt) {
+ PaddingResource->AddrRangeMax =3D (1 << PciePMemAddrRngMax) - 1;
+ } else {
+ PaddingResource->AddrRangeMax =3D 1;
+ }
+ //
+ // Alignment
+ //
+ // Padding for I/O
+ //
+ PaddingResource++;
+ PaddingResource->Desc =3D 0x8A;
+ PaddingResource->Len =3D 0x2B;
+ PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO;
+ PaddingResource->GenFlag =3D 0x0;
+ PaddingResource->SpecificFlag =3D 0;
+ PaddingResource->AddrRangeMin =3D 0;
+ PaddingResource->AddrLen =3D RsvdPcieKiloIo * 0x400;
+ //
+ // Pad 4K of IO
+ //
+ PaddingResource->AddrRangeMax =3D 1;
+ //
+ // Alignment
+ //
+ // Terminate the entries.
+ //
+ PaddingResource++;
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc =3D ACPI_END=
_TAG_DESCRIPTOR;
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum =3D 0x0;
+
+ *HpcState =3D EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHo=
tPlug.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPl=
ug.h
new file mode 100644
index 0000000000..09465b2757
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
@@ -0,0 +1,130 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCI_HOT_PLUG_H_
+#define _PCI_HOT_PLUG_H_
+
+//
+// External include files do NOT need to be explicitly specified in real E=
DKII
+// environment
+//
+#include <Base.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <IndustryStandard/Acpi10.h>
+#include <Protocol/PciHotPlugInit.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Library/DevicePathLib.h>
+#include <Library/UefiLib.h>
+#include <Guid/HobList.h>
+#include <Library/HobLib.h>
+#include <Protocol/SaPolicy.h>
+
+#define PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('G', 'U', 'L',=
'P')
+
+#define ACPI \
+ { \
+ { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH))=
, (UINT8) \
+ ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (0x0A03), 0 \
+ }
+
+#define PCI(device, function) \
+ { \
+ { HARDWARE_DEVICE_PATH, HW_PCI_DP, { (UINT8) (sizeof (PCI_DEVICE_PATH)=
), (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) } }, \
+ (UINTN) function, (UINTN) device \
+ }
+
+#define END \
+ { \
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PAT=
H_LENGTH, 0 } \
+ }
+
+#define LPC(eisaid, function) \
+ { \
+ { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH))=
, (UINT8) \
+ ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (eisaid), fu=
nction \
+ }
+
+typedef struct PCIE_HOT_PLUG_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeNode;
+ PCI_DEVICE_PATH PciRootPortNode;
+ EFI_DEVICE_PATH_PROTOCOL EndDeviceNode;
+} PCIE_HOT_PLUG_DEVICE_PATH;
+
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle; // Handle for protocol this driv=
er installs on
+ EFI_PCI_HOT_PLUG_INIT_PROTOCOL HotPlugInitProtocol;
+} PCI_HOT_PLUG_INSTANCE;
+
+/**
+ This procedure returns a list of Root Hot Plug controllers that require
+ initialization during boot process
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLU=
G_INIT protocol.
+ @param[out] HpcCount The number of Root HPCs returned.
+ @param[out] HpcList The list of Root HPCs. HpcCount defines the number=
of elements in this list.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetRootHpcList (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ OUT UINTN *PhpcCount,
+ OUT EFI_HPC_LOCATION **PhpcList
+ );
+
+/**
+ This procedure Initializes one Root Hot Plug Controller
+ This process may casue initialization of its subordinate buses
+
+ @param[in] This The pointer to the instance of the EFI_PCI_H=
OT_PLUG_INIT protocol.
+ @param[in] HpcDevicePath The Device Path to the HPC that is being ini=
tialized.
+ @param[in] HpcPciAddress The address of the Hot Plug Controller funct=
ion on the PCI bus.
+ @param[in] Event The event that should be signaled when the H=
ot Plug Controller initialization is complete. Set to NULL if the caller wa=
nts to wait until the entire initialization process is complete. The event =
must be of the type EFI_EVT_SIGNAL.
+ @param[out] HpcState The state of the Hot Plug Controller hardwar=
e. The type EFI_Hpc_STATE is defined in section 3.1.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+InitializeRootHpc (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath,
+ IN UINT64 PhpcPciAddress,
+ IN EFI_EVENT Event, OPTIONAL
+ OUT EFI_HPC_STATE *PhpcState
+ );
+
+/**
+ Returns the resource padding required by the PCI bus that is controlled =
by the specified Hot Plug Controller.
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HO=
T_PLUG_INIT protocol. initialized.
+ @param[in] HpcDevicePath The Device Path to the Hot Plug Controller.
+ @param[in] HpcPciAddress The address of the Hot Plug Controller functi=
on on the PCI bus.
+ @param[out] HpcState The state of the Hot Plug Controller hardware=
. The type EFI_HPC_STATE is defined in section 3.1.
+ @param[out] Padding This is the amount of resource padding requir=
ed by the PCI bus under the control of the specified Hpc. Since the caller =
does not know the size of this buffer, this buffer is allocated by the call=
ee and freed by the caller.
+ @param[out] Attribute Describes how padding is accounted for.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetResourcePadding (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath,
+ IN UINT64 PhpcPciAddress,
+ OUT EFI_HPC_STATE *PhpcState,
+ OUT VOID **Padding,
+ OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHo=
tPlug.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHot=
Plug.inf
new file mode 100644
index 0000000000..903e681443
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.i=
nf
@@ -0,0 +1,63 @@
+## @file
+# This module will perform specific PCI-Express devices
+# resource configuration.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PciHotPlug
+ FILE_GUID =3D 3022E512-B94A-4F12-806D-7EF1177899D8
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D DXE_DRIVER
+ ENTRY_POINT =3D PciHotPlug
+#
+# The following information is for reference only and not required by the =
build tools.
+#
+# VALID_ARCHITECTURES =3D IA32 X64 EBC
+#
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DevicePathLib
+ DebugLib
+ UefiLib
+ HobLib
+ PchPcieRpLib
+ ConfigBlockLib
+ TbtCommonLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ PciHotPlug.c
+ PciHotPlug.h
+
+[Protocols]
+ gEfiPciHotPlugInitProtocolGuid ## PRODUCES
+ gSaPolicyProtocolGuid ## CONSUMES
+
+[Guids]
+ gEfiHobListGuid ## CONSUMES
+ gPcieRpConfigGuid ## CONSUMES
+
+[Pcd]
+
+[Depex]
+ gDxeTbtPolicyProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/R=
td3PcieTbt.asl b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTabl=
es/Rtd3PcieTbt.asl
new file mode 100644
index 0000000000..804c947f7c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3Pcie=
Tbt.asl
@@ -0,0 +1,405 @@
+/** @file
+ ACPI RTD3 SSDT table for SPT PCIe
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#define PID_ICC 0xDC
+#define R_PCH_PCR_ICC_MSKCKRQ 0x100C =
///< Mask Control CLKREQ
+
+External(PCRA,MethodObj)
+External(PCRO,MethodObj)
+External(\MMRP, MethodObj)
+External(\MMTB, MethodObj)
+External(\TRDO, IntObj)
+External(\TRD3, IntObj)
+External(\TBPE, IntObj)
+External(\TOFF, IntObj)
+External(\TBSE, IntObj)
+External(\TBOD, IntObj)
+External(\TBRP, IntObj)
+External(\TBHR, IntObj)
+External(\RTBC, IntObj)
+External(\TBCD, IntObj)
+
+Name(G2SD, 0) // Go2Sx done, set by GO2S, cleaned by _ON
+
+Name(WKEN, 0)
+
+ Method(_S0W, 0)
+ {
+ /// This method returns the lowest D-state supported by PCIe root port d=
uring S0 state
+
+ ///- PMEs can be generated from D3hot for ULT
+ Return(4)
+
+ /** @defgroup pcie_s0W PCIE _S0W **/
+ } // End _S0W
+
+ Method (_DSD, 0) {
+ Return (
+ Package () {
+ ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
+ Package () {
+ Package (2) {"HotPlugSupportInD3", 1},
+ }
+ }
+ ) // End of Return ()
+ }
+
+ Method(_DSW, 3)
+ {
+ /// This method is used to enable/disable wake from PCIe (WKEN)
+ If (LGreaterEqual(Arg1, 1)) { /// If entering Sx, need to disable WA=
KE# from generating runtime PME
+ /// Also set 2 to TOFF.
+ Store(0, WKEN)
+ Store (2, TOFF)
+ } Else { /// If Staying in S0
+ If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake
+ { ///- Set PME
+ Store(1, WKEN)
+ Store (1, TOFF)
+ } Else { ///- Disable runtime PME, either because staying in D0 or=
disabling wake
+ Store(0, WKEN)
+ Store(0, TOFF)
+ }
+ }
+
+ /** @defgroup pcie_dsw PCIE _DSW **/
+ } // End _DSW
+
+
+ PowerResource(PXP, 0, 0)
+ {
+ /// Define the PowerResource for PCIe slot
+ /// Method: _STA(), _ON(), _OFF()
+ /** @defgroup pcie_pxp PCIE Power Resource **/
+
+ Method(_STA, 0)
+ {
+ Return(PSTA())
+ } /** @defgroup pcie_sta PCIE _STA method **/
+
+ Method(_ON) /// Turn on core power to PCIe Slot
+ {
+ Store(1, TRDO)
+ PON()
+ Store(0, TRDO)
+ } /** @defgroup pcie_on PCIE _ON method **/
+
+ Method(_OFF) /// Turn off core power to PCIe Slot
+ {
+ Store(1, TRD3)
+ POFF()
+ Store(0, TRD3)
+ } // End of Method_OFF
+ } // End PXP
+
+ Method(PSTA, 0)
+ {
+ /// Returns the status of PCIe slot core power
+ // detect power pin status
+ if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) {
+ if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ if(LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG,=
3)))){
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // GPIO mode
+ if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
+ if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(PWRG, 1)),DeRefOf(In=
dex(PWRG, 2))),DeRefOf(Index(PWRG, 3)))){
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // IOEX mode
+ }
+ // detect reset pin status
+ if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) {
+ if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
+ if(LEqual(\_SB.GGOV(DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG,=
3)))){
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // GPIO mode
+ if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
+ if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(RSTG, 1)),DeRefOf(In=
dex(RSTG, 2))),DeRefOf(Index(RSTG, 3)))){
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // IOEX mode
+ }
+ Return (0)
+ } /** @defgroup pcie_sta PCIE _STA method **/
+
+ Method (SXEX, 0, Serialized) {
+
+ Store(\MMTB(TBSE), Local7)
+ OperationRegion(TBDI, SystemMemory, Local7, 0x550)// TBT HR PCICFG M=
MIO
+ Field(TBDI,DWordAcc, NoLock, Preserve) {
+ DIVI, 32,
+ CMDR, 32,
+ Offset(0x548),
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(100, Local1)
+ Store(0x09, P2TB) // Write SX_EXIT_TBT_CONNECTED to PCIe2TBT
+ While (LGreater(Local1, 0)) {
+
+ Store(Subtract(Local1, 1), Local1)
+ Store(TB2P, Local2)
+ If (LEqual(Local2, 0xFFFFFFFF)) { // Device gone
+ Return()
+ }
+ If (And(Local2, 1)) { // Done
+ break
+ }
+ Sleep(5)
+ }
+ Store(0x0, P2TB) // Write 0 to PCIe2TBT
+
+ // Fast Link bring-up flow
+ Store(500, Local1)
+ While (LGreater(Local1, 0)) {
+ Store(Subtract(Local1, 1), Local1)
+ Store(TB2P, Local2)
+ If (LEqual(Local2, 0xFFFFFFFF)) {// Device gone
+ Return()
+ }
+ If (LNotEqual(DIVI, 0xFFFFFFFF)) {
+ break
+ }
+ Sleep(10)
+ }
+ } // End of Method(SXEX, 0, Serialized)
+
+ Method(PON) /// Turn on core power to PCIe Slot
+ {
+
+ Store(\MMRP(\TBSE), Local7)
+ OperationRegion(L23P,SystemMemory,Local7,0xE4)
+ Field(L23P,WordAcc, NoLock, Preserve)
+ {
+ Offset(0xA4),// PMCSR
+ PSD0, 2, // PowerState
+ Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable
+ , 2,
+ L2TE, 1, // 2, L23_Rdy Entry Request (L23ER)
+ L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
+ }
+
+ Store(\MMTB(\TBSE), Local6)
+ OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG M=
MIO
+ Field(TBDI,DWordAcc, NoLock, Preserve) {
+ DIVI, 32,
+ CMDR, 32,
+ Offset(0xA4),
+ TBPS, 2, // PowerState of TBT
+ Offset(0x548),
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(0, TOFF)
+ // Check RTD3 power enable, if already ON, no need to execute sx_exit
+ If (TBPE) {
+ Return()
+ }
+
+ Store(0,G2SD)
+ If (\RTBC) {
+ /// de-assert CLK_REQ MSK
+ if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enab=
led
+ PCRA(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,Not(DeRefOf(Index(SCLK, 1))))=
// And ~SCLK to clear bit
+ }
+ Sleep(\TBCD)
+ }
+
+ /// Turn ON Power for PCIe Slot
+ if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled
+ if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3)))
+ Store(1, TBPE)
+ Sleep(PEP0) /// Sleep for programmable delay
+ }
+ if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, =
2)),DeRefOf(Index(PWRG, 3)))
+ Store(1, TBPE)
+ Sleep(PEP0) /// Sleep for programmable delay
+ }
+ }
+
+ /// De-Assert Reset Pin
+ if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled
+ if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3)))
+ }
+ if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, =
2)),DeRefOf(Index(RSTG, 3)))
+ }
+ }
+
+ /// Clear DLSULPPGE, then set L23_Rdy to Detect Transition (L23R2DT)
+ Store(0, DPGE)
+ Store(1, L2TR)
+ Sleep(16)
+ Store(0, Local0)
+ /// Wait up to 12 ms for transition to Detect
+ While(L2TR) {
+ If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms
+ {
+ Break
+ }
+ Sleep(16)
+ Increment(Local0)
+ }
+ /// Once in Detect, wait up to 124 ms for Link Active (typically hap=
pens in under 70ms)
+ /// Worst case per PCIe spec from Detect to Link Active is:
+ /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config =
(24+2+2+2+2)
+ Store(1, DPGE)
+ Store(0, Local0)
+ While(LEqual(LASX,0)) {
+ If(Lgreater(Local0, 8))
+ {
+ Break
+ }
+ Sleep(16)
+ Increment(Local0)
+ }
+ Store(0, LEDM) /// Set PCIEDBG.DMIL1EDM (324[3]) =3D 0
+
+ // TBT special sleep.
+ Store(PSD0, Local1)
+ Store(0, PSD0)// D0
+ Store(20, Local2) // Poll for TBT, up to 200 ms
+
+ While (LGreater(Local2, 0)) {
+ Store(Subtract(Local2, 1), Local2)
+ Store(TB2P, Local3)
+ If (LNotEqual(Local3, 0xFFFFFFFF)) { // Done
+ break
+ }
+ Sleep(10)
+ }
+
+ If (LLessEqual(Local2, 0)) {
+ }
+ SXEX()
+ Store(Local1, PSD0) // Back to Local1
+ } /** @defgroup pcie_on PCIE _ON method **/
+
+ Method(POFF) { /// Turn off core power to PCIe Slot
+ If (LEqual(TOFF, 0)) {
+ Return()
+ }
+ Store(\MMRP(\TBSE), Local7)
+ OperationRegion(L23P, SystemMemory, Local7, 0xE4)
+ Field(L23P,WordAcc, NoLock, Preserve)
+ {
+ Offset(0xA4),// PMCSR
+ PSD0, 2, // PowerState
+ Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable
+ , 2,
+ L2TE, 1, // 2, L23_Rdy Entry Request (L23ER)
+ L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
+ }
+
+ Store(\MMTB(TBSE), Local6)
+ OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG M=
MIO
+ Field(TBDI,DWordAcc, NoLock, Preserve) {
+ DIVI, 32,
+ CMDR, 32,
+ Offset(0xA4),
+ TBPS, 2, // PowerState of TBT
+ Offset(0x548),
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(PSD0, Local1)
+ Store(0, PSD0)// D0
+
+ Store(P2TB, Local3)
+
+ If (Lgreater(TOFF, 1)) {
+ Sleep(10)
+ Store(Local1, PSD0) // Back to Local1
+ Return()
+ }
+ Store(0, TOFF)
+
+ Store(Local1, PSD0) // Back to Local1
+
+ /// Set L23_Rdy Entry Request (L23ER)
+ Store(1, L2TE)
+ Sleep(16)
+ Store(0, Local0)
+ While(L2TE) {
+ If(Lgreater(Local0, 4)) /// Debug - Wait for 5 ms
+ {
+ Break
+ }
+ Sleep(16)
+ Increment(Local0)
+ }
+ Store(1, LEDM) /// PCIEDBG.DMIL1EDM (324[3]) =3D 1
+
+ /// Assert Reset Pin
+ if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled
+ if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1))
+ }
+ if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, =
2)),Xor(DeRefOf(Index(RSTG, 3)),1))
+ }
+ }
+ If (\RTBC) {
+ /// assert CLK_REQ MSK
+ if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enab=
led
+ PCRO(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,DeRefOf(Index(SCLK, 1))) /=
/ Or SCLK to set bit
+ Sleep(16)
+ }
+ }
+
+ /// Power OFF for TBT
+ if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled
+ if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1))
+ }
+ if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, =
2)),Xor(DeRefOf(Index(PWRG, 3)),1))
+ }
+ }
+
+ Store(0, TBPE)
+
+ Store(1, LDIS) /// Set Link Disable
+ Store(0, LDIS) /// Toggle link disable
+
+ /// enable WAKE
+ If (WKEN) {
+ If (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { // if power gating ena=
bled
+ If (LEqual(DeRefOf(Index(WAKG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3)))
+ \_SB.SHPO(DeRefOf(Index(WAKG, 2)), 0) // set gpio ownership to=
ACPI(0=3DACPI mode, 1=3DGPIO mode)
+ }
+ If (LEqual(DeRefOf(Index(WAKG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(WAKG, 1)),DeRefOf(Index(WAKG=
, 2)),DeRefOf(Index(WAKG, 3)))
+ }
+ }
+ }
+ Sleep(\TBOD)
+ /** @defgroup pcie_off PCIE _OFF method **/
+ } // End of Method_OFF
+
+ Name(_PR0, Package(){PXP})
+ Name(_PR3, Package(){PXP})
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/T=
bt.asl b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.a=
sl
new file mode 100644
index 0000000000..12685e57bf
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
@@ -0,0 +1,1877 @@
+/** @file
+ Thunderbolt ACPI methods
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#define DTBT_CONTROLLER 0x00
+#define DTBT_TYPE_PCH 0x01
+#define DTBT_TYPE_PEG 0x02
+#define DTBT_SMI_HANDLER_NUMBER 0xF7
+#define TBT_SMI_ENUMERATION_FUNCTION 21
+#define TBT_SMI_RESET_SWITCH_FUNCTION 22
+#define TBT_SMI_DISABLE_MSI_FUNCTION 23
+#ifndef BIT29
+#define BIT29 0x20000000
+#endif
+
+Name(LDLY, 300) //300 ms
+Name (TNVB, 0xFFFF0000) // TBT NVS Base address
+Name (TNVL, 0xAA55) // TBT NVS Length
+Include ("Acpi/TbtNvs.asl")
+
+External(\_SB.PCI0.RP02.L23D, MethodObj)
+External(\_SB.PCI0.RP03.L23D, MethodObj)
+External(\_SB.PCI0.RP04.L23D, MethodObj)
+External(\_SB.PCI0.RP05.L23D, MethodObj)
+External(\_SB.PCI0.RP06.L23D, MethodObj)
+External(\_SB.PCI0.RP07.L23D, MethodObj)
+External(\_SB.PCI0.RP08.L23D, MethodObj)
+External(\_SB.PCI0.RP09.L23D, MethodObj)
+External(\_SB.PCI0.RP10.L23D, MethodObj)
+External(\_SB.PCI0.RP11.L23D, MethodObj)
+External(\_SB.PCI0.RP12.L23D, MethodObj)
+External(\_SB.PCI0.RP13.L23D, MethodObj)
+External(\_SB.PCI0.RP14.L23D, MethodObj)
+External(\_SB.PCI0.RP15.L23D, MethodObj)
+External(\_SB.PCI0.RP16.L23D, MethodObj)
+External(\_SB.PCI0.RP17.L23D, MethodObj)
+External(\_SB.PCI0.RP18.L23D, MethodObj)
+External(\_SB.PCI0.RP19.L23D, MethodObj)
+External(\_SB.PCI0.RP20.L23D, MethodObj)
+External(\_SB.PCI0.RP21.L23D, MethodObj)
+External(\_SB.PCI0.RP22.L23D, MethodObj)
+External(\_SB.PCI0.RP23.L23D, MethodObj)
+External(\_SB.PCI0.RP24.L23D, MethodObj)
+
+External(\_SB.PCI0.RP01.DL23, MethodObj)
+External(\_SB.PCI0.RP02.DL23, MethodObj)
+External(\_SB.PCI0.RP03.DL23, MethodObj)
+External(\_SB.PCI0.RP04.DL23, MethodObj)
+External(\_SB.PCI0.RP05.DL23, MethodObj)
+External(\_SB.PCI0.RP06.DL23, MethodObj)
+External(\_SB.PCI0.RP07.DL23, MethodObj)
+External(\_SB.PCI0.RP08.DL23, MethodObj)
+External(\_SB.PCI0.RP09.DL23, MethodObj)
+External(\_SB.PCI0.RP10.DL23, MethodObj)
+External(\_SB.PCI0.RP11.DL23, MethodObj)
+External(\_SB.PCI0.RP12.DL23, MethodObj)
+External(\_SB.PCI0.RP13.DL23, MethodObj)
+External(\_SB.PCI0.RP14.DL23, MethodObj)
+External(\_SB.PCI0.RP15.DL23, MethodObj)
+External(\_SB.PCI0.RP16.DL23, MethodObj)
+External(\_SB.PCI0.RP17.DL23, MethodObj)
+External(\_SB.PCI0.RP18.DL23, MethodObj)
+External(\_SB.PCI0.RP19.DL23, MethodObj)
+External(\_SB.PCI0.RP20.DL23, MethodObj)
+External(\_SB.PCI0.RP21.DL23, MethodObj)
+External(\_SB.PCI0.RP22.DL23, MethodObj)
+External(\_SB.PCI0.RP23.DL23, MethodObj)
+External(\_SB.PCI0.RP24.DL23, MethodObj)
+
+External(\_SB.PCI0.RTEN, MethodObj)
+External(\_SB.PCI0.RTDS, MethodObj)
+External(\_SB.PCI0.RP01.PON, MethodObj)
+External(\_SB.PCI0.RP02.PON, MethodObj)
+External(\_SB.PCI0.RP03.PON, MethodObj)
+External(\_SB.PCI0.RP04.PON, MethodObj)
+External(\_SB.PCI0.RP05.PON, MethodObj)
+External(\_SB.PCI0.RP06.PON, MethodObj)
+External(\_SB.PCI0.RP07.PON, MethodObj)
+External(\_SB.PCI0.RP08.PON, MethodObj)
+External(\_SB.PCI0.RP09.PON, MethodObj)
+External(\_SB.PCI0.RP10.PON, MethodObj)
+External(\_SB.PCI0.RP11.PON, MethodObj)
+External(\_SB.PCI0.RP12.PON, MethodObj)
+External(\_SB.PCI0.RP13.PON, MethodObj)
+External(\_SB.PCI0.RP14.PON, MethodObj)
+External(\_SB.PCI0.RP15.PON, MethodObj)
+External(\_SB.PCI0.RP16.PON, MethodObj)
+External(\_SB.PCI0.RP17.PON, MethodObj)
+External(\_SB.PCI0.RP18.PON, MethodObj)
+External(\_SB.PCI0.RP19.PON, MethodObj)
+External(\_SB.PCI0.RP20.PON, MethodObj)
+External(\_SB.PCI0.RP21.PON, MethodObj)
+External(\_SB.PCI0.RP22.PON, MethodObj)
+External(\_SB.PCI0.RP23.PON, MethodObj)
+External(\_SB.PCI0.RP24.PON, MethodObj)
+External(\_SB.PCI0.PEG0.PG00._ON, MethodObj)
+External(\_SB.PCI0.PEG1.PG01._ON, MethodObj)
+External(\_SB.PCI0.PEG2.PG02._ON, MethodObj)
+
+Name(TRDO, 0) // 1 during TBT RTD3 _ON
+Name(TRD3, 0) // 1 during TBT RTD3 _OFF
+Name(TBPE, 0) // Reflects RTD3_PWR_EN value
+Name(TOFF, 0) // param to TBT _OFF method
+
+ Method (TBON, 0, Serialized) {
+ // TBT On process before entering Sx state.
+ Store(1, TRDO)
+ Switch (ToInteger(\RPS0)) { // TBT Root port Selector
+ Case (1) {
+ If (CondRefOf(\_SB.PCI0.RP01.PON)) {
+ \_SB.PCI0.RP01.PON()
+ }
+ }
+ Case (2) {
+ If (CondRefOf(\_SB.PCI0.RP02.PON)) {
+ \_SB.PCI0.RP02.PON()
+ }
+ }
+ Case (3) {
+ If (CondRefOf(\_SB.PCI0.RP03.PON)) {
+ \_SB.PCI0.RP03.PON()
+ }
+ }
+ Case (4) {
+ If (CondRefOf(\_SB.PCI0.RP04.PON)) {
+ \_SB.PCI0.RP04.PON()
+ }
+ }
+ Case (5) {
+ If (CondRefOf(\_SB.PCI0.RP05.PON)) {
+ \_SB.PCI0.RP05.PON()
+ }
+ }
+ Case (6) {
+ If (CondRefOf(\_SB.PCI0.RP06.PON)) {
+ \_SB.PCI0.RP06.PON()
+ }
+ }
+ Case (7) {
+ If (CondRefOf(\_SB.PCI0.RP07.PON)) {
+ \_SB.PCI0.RP07.PON()
+ }
+ }
+ Case (8) {
+ If (CondRefOf(\_SB.PCI0.RP08.PON)) {
+ \_SB.PCI0.RP08.PON()
+ }
+ }
+ Case (9) {
+ If (CondRefOf(\_SB.PCI0.RP09.PON)) {
+ \_SB.PCI0.RP09.PON()
+ }
+ }
+ Case (10) {
+ If (CondRefOf(\_SB.PCI0.RP10.PON)) {
+ \_SB.PCI0.RP10.PON()
+ }
+ }
+ Case (11) {
+ If (CondRefOf(\_SB.PCI0.RP11.PON)) {
+ \_SB.PCI0.RP11.PON()
+ }
+ }
+ Case (12) {
+ If (CondRefOf(\_SB.PCI0.RP12.PON)) {
+ \_SB.PCI0.RP12.PON()
+ }
+ }
+ Case (13) {
+ If (CondRefOf(\_SB.PCI0.RP13.PON)) {
+ \_SB.PCI0.RP13.PON()
+ }
+ }
+ Case (14) {
+ If (CondRefOf(\_SB.PCI0.RP14.PON)) {
+ \_SB.PCI0.RP14.PON()
+ }
+ }
+ Case (15) {
+ If (CondRefOf(\_SB.PCI0.RP15.PON)) {
+ \_SB.PCI0.RP15.PON()
+ }
+ }
+ Case (16) {
+ If (CondRefOf(\_SB.PCI0.RP16.PON)) {
+ \_SB.PCI0.RP16.PON()
+ }
+ }
+ Case (17) {
+ If (CondRefOf(\_SB.PCI0.RP17.PON)) {
+ \_SB.PCI0.RP17.PON()
+ }
+ }
+ Case (18) {
+ If (CondRefOf(\_SB.PCI0.RP18.PON)) {
+ \_SB.PCI0.RP18.PON()
+ }
+ }
+ Case (19) {
+ If (CondRefOf(\_SB.PCI0.RP19.PON)) {
+ \_SB.PCI0.RP19.PON()
+ }
+ }
+ Case (20) {
+ If (CondRefOf(\_SB.PCI0.RP20.PON)) {
+ \_SB.PCI0.RP20.PON()
+ }
+ }
+ Case (21) {
+ If (CondRefOf(\_SB.PCI0.RP21.PON)) {
+ \_SB.PCI0.RP21.PON()
+ }
+ }
+ Case (22) {
+ If (CondRefOf(\_SB.PCI0.RP22.PON)) {
+ \_SB.PCI0.RP22.PON()
+ }
+ }
+ Case (23) {
+ If (CondRefOf(\_SB.PCI0.RP23.PON)) {
+ \_SB.PCI0.RP23.PON()
+ }
+ }
+ Case (24) {
+ If (CondRefOf(\_SB.PCI0.RP24.PON)) {
+ \_SB.PCI0.RP24.PON()
+ }
+ }
+ }//Switch(ToInteger(RPS0)) // TBT Selector
+ Store(0, TRDO)
+ } // End of TBON
+ //
+ // Name: TBTD
+ // Description: Function to return the TBT RP# device no
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ // Return: TBT RP# device no
+ //
+ Method(TBTD,2)
+ {
+ ADBG("TBTD")
+ If (LEqual(Arg1, DTBT_TYPE_PCH)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (Package () {1, 2, 3, 4, 5, 6, 7, 8})
+ {
+ Store(0x1C, Local0) //Device28-Function0...Function7 =3D 11100.0=
00...111
+ }
+ Case (Package () {9, 10, 11, 12, 13, 14, 15, 16})
+ {
+ Store(0x1D, Local0) //Device29-Function0...Function7 =3D 11101.0=
00...111
+ }
+ Case (Package () {17, 18, 19, 20, 21, 22, 23, 24})
+ {
+ Store(0x1B, Local0) //Device27-Function0...Function3 =3D 11011.0=
00...011
+ }
+ }
+ } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (Package () {1, 2, 3})
+ {
+ Store(0x1, Local0) //Device1-Function0...Function2 =3D 00001.000=
...010
+ }
+ }
+ } Else {
+ Store(0xFF, Local0)
+ }
+
+ ADBG("Device no")
+ ADBG(Local0)
+
+ Return(Local0)
+ } // End of Method(TBTD,1)
+
+ //
+ // Name: TBTF
+ // Description: Function to return the TBT RP# function no
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ // Return: TBT RP# function no
+ //
+ Method(TBTF,2)
+ {
+ ADBG("TBTF")
+ If (LEqual(Arg1, DTBT_TYPE_PCH)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (1)
+ {
+ Store(And(\RPA1,0xF), Local0) //Device28-Function0 =3D 11100.000
+ }
+ Case (2)
+ {
+ Store(And(\RPA2,0xF), Local0) //Device28-Function1 =3D 11100.001
+ }
+ Case (3)
+ {
+ Store(And(\RPA3,0xF), Local0) //Device28-Function2 =3D 11100.010
+ }
+ Case (4)
+ {
+ Store(And(\RPA4,0xF), Local0) //Device28-Function3 =3D 11100.011
+ }
+ Case (5)
+ {
+ Store(And(\RPA5,0xF), Local0) //Device28-Function4 =3D 11100.100
+ }
+ Case (6)
+ {
+ Store(And(\RPA6,0xF), Local0) //Device28-Function5 =3D 11100.101
+ }
+ Case (7)
+ {
+ Store(And(\RPA7,0xF), Local0) //Device28-Function6 =3D 11100.110
+ }
+ Case (8)
+ {
+ Store(And(\RPA8,0xF), Local0) //Device28-Function7 =3D 11100.111
+ }
+ Case (9)
+ {
+ Store(And(\RPA9,0xF), Local0) //Device29-Function0 =3D 11101.000
+ }
+ Case (10)
+ {
+ Store(And(\RPAA,0xF), Local0) //Device29-Function1 =3D 11101.001
+ }
+ Case (11)
+ {
+ Store(And(\RPAB,0xF), Local0) //Device29-Function2 =3D 11101.010
+ }
+ Case (12)
+ {
+ Store(And(\RPAC,0xF), Local0) //Device29-Function3 =3D 11101.011
+ }
+ Case (13)
+ {
+ Store(And(\RPAD,0xF), Local0) //Device29-Function4 =3D 11101.100
+ }
+ Case (14)
+ {
+ Store(And(\RPAE,0xF), Local0) //Device29-Function5 =3D 11101.101
+ }
+ Case (15)
+ {
+ Store(And(\RPAF,0xF), Local0) //Device29-Function6 =3D 11101.110
+ }
+ Case (16)
+ {
+ Store(And(\RPAG,0xF), Local0) //Device29-Function7 =3D 11101.111
+ }
+ Case (17)
+ {
+ Store(And(\RPAH,0xF), Local0) //Device27-Function0 =3D 11011.000
+ }
+ Case (18)
+ {
+ Store(And(\RPAI,0xF), Local0) //Device27-Function1 =3D 11011.001
+ }
+ Case (19)
+ {
+ Store(And(\RPAJ,0xF), Local0) //Device27-Function2 =3D 11011.010
+ }
+ Case (20)
+ {
+ Store(And(\RPAK,0xF), Local0) //Device27-Function3 =3D 11011.011
+ }
+ Case (21)
+ {
+ Store(And(\RPAL,0xF), Local0) //Device27-Function4 =3D 11011.100
+ }
+ Case (22)
+ {
+ Store(And(\RPAM,0xF), Local0) //Device27-Function5 =3D 11011.101
+ }
+ Case (23)
+ {
+ Store(And(\RPAN,0xF), Local0) //Device27-Function6 =3D 11011.110
+ }
+ Case (24)
+ {
+ Store(And(\RPAO,0xF), Local0) //Device27-Function7 =3D 11011.111
+ }
+ }
+ } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (1)
+ {
+ Store(0x0, Local0) //Device1-Function0 =3D 00001.000
+ }
+ Case (2)
+ {
+ Store(0x1, Local0) //Device1-Function1 =3D 00001.001
+ }
+ Case (3)
+ {
+ Store(0x2, Local0) //Device1-Function2 =3D 00001.010
+ }
+ }
+ } Else {
+ Store(0xFF, Local0)
+ }
+
+ ADBG("Function no")
+ ADBG(Local0)
+
+ Return(Local0)
+ } // End of Method(TBTF,1)
+
+ //
+ // Name: MMRP
+ // Description: Function to return the Pci base address of TBT rootport
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(MMRP, 2, Serialized)
+ {
+ Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
+ Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
+ Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
+
+ Return(Local0)
+ } // End of Method(MMRP)
+
+ //
+ // Name: MMRP
+ // Description: Function to return the Pci base address of TBT Up stream=
port
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+ Method(MMTB, 2, Serialized)
+ {
+ ADBG("MMTB")
+
+ Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
+
+ Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
+ Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
+
+ OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
+ Field (MMMM, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x19),
+ SBUS, 8
+ }
+ Store(SBUS, Local2)
+ Store(\_SB.PCI0.GPCB(), Local0)
+ Multiply(Local2, 0x100000, Local2)
+ Add(Local2, Local0, Local0) // TBT HR US port
+
+ ADBG("TBT-US-ADR")
+ ADBG(Local0)
+
+ Return(Local0)
+ } // End of Method(MMTB, 1, Serialized)
+ //
+ // Name: FFTB
+ // Description: Function to Check for FFFF in TBT PCIe
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ // Return: 1 if TBT PCIe space has value FFFF, 0 if not
+ //
+ Method(FFTB, 2, Serialized)
+ {
+ ADBG("FFTB")
+
+ Add(MMTB(Arg0, Arg1), 0x548, Local0)
+ OperationRegion(PXVD,SystemMemory,Local0,0x08)
+ Field(PXVD,DWordAcc, NoLock, Preserve)
+ {
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(TB2P, Local1)
+
+ If(LEqual(Local1, 0xFFFFFFFF))
+ {
+ ADBG("FFTb 1")
+ Return (1)
+ }
+ Else
+ {
+ ADBG("FFTb 0")
+ Return (0)
+ }
+ } // End of Method(FFTB)
+
+Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory buffer, =
fixed up during POST
+
+Scope(\_GPE)
+{
+ //
+ //
+ //OS up Mail Box command execution to host router upstream port each time
+ //exiting from Sx State .Avoids intermediate
+ //PCIe Scan by OS during resorce allocation
+ // Arg0 : PCIe Base address
+ // Arg1 : Controller Type 0x00 : DTBT
+ //Developer notes: Called twice
+ // 1. During OS INIT (booting to OS from S3-S5/Reboot)
+ // 2. Up on Hot plug
+ //
+ Method(OSUP, 2, Serialized)
+ {
+ ADBG("OSUP")
+
+ Add(Arg0, 0x540, Local0)
+ OperationRegion(PXVD,SystemMemory,Local0,0x10)
+ Field(PXVD,DWordAcc, NoLock, Preserve)
+ {
+ IT2P, 32,
+ IP2T, 32,
+ DT2P, 32,
+ DP2T, 32
+ }
+
+ Store(100, Local1)
+ Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT
+
+ While(LGreater(Local1, 0))
+ {
+ Store(Subtract(Local1, 1), Local1)
+ Store(DT2P, Local2)
+
+ If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1, DTBT_CONTROLLER)))//=
Device gone
+ {
+ ADBG("Dev gone")
+ Return(2)
+ }
+ If(And(Local2, 1)) // Done
+ {
+ ADBG("Cmd acknowledged")
+ break
+ }
+ Sleep(50)
+ }
+ If(LEqual(TRWA,1))
+ {
+ Store(0xC, DP2T) // Write OSUP to PCIe2TBT
+ }
+ Else
+ {
+ Store(0x0, DP2T) // Write 0 to PCIe2TBT
+ }
+
+ //Store(0x00, P2TB) // Write 0 to PCIe2TBT
+
+ ADBG("End-of-OSUP")
+
+ Return(1)
+ } // End of Method(OSUP, 1, Serialized)
+
+ //
+ // Check for FFFF in TBT
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(TBFF, 2, Serialized)
+ {
+ ADBG("TBFF")
+
+ Store(MMTB(Arg0, Arg1), Local0)
+ OperationRegion (PXVD, SystemMemory, Local0, 0x8)
+ Field (PXVD, DWordAcc, NoLock, Preserve) {
+ VEDI, 32, // Vendor/Device ID
+ CMDR, 32 // CMD register
+ }
+
+ Store(VEDI, Local1)
+
+ If (LEqual(Local1, 0xFFFFFFFF)) {
+ If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode?
+ If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone
+ Return (2)// Notify only
+ }
+ Return (1)// Exit w/o notify
+ } Else {
+ Return (OSUP(Local0, DTBT_CONTROLLER))
+ }
+ } Else
+ {
+ ADBG("Dev Present")
+ Return (0)
+ }
+ } // End of Method(TBFF, 1, Serialized)
+
+ //
+ // Secondary bus of TBT RP
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(TSUB, 2, Serialized)
+ {
+ ADBG("TSUB")
+
+ Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
+
+ Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
+ Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
+
+ ADBG("ADR")
+ ADBG(Local0)
+
+ OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
+ Field (MMMM, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x19),
+ SBUS, 8
+ }
+
+ ADBG("Sec Bus")
+ ADBG(SBUS)
+
+ Return(SBUS)
+ } // End of Method(TSUB, 0, Serialized)
+
+ //
+ // Pmem of TBT RP
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(TSUP, 2, Serialized)
+ {
+ ADBG("TSUB")
+
+ Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
+
+ Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
+ Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
+
+ ADBG("ADR:")
+ ADBG(Local0)
+
+ OperationRegion (MMMM, SystemMemory, Local0, 0x30)
+ Field (MMMM, AnyAcc, NoLock, Preserve)
+ {
+ CMDS, 32,
+ Offset(0x19),
+ SBUS, 8,
+ SBU5, 8,
+ Offset(0x1C),
+ SEIO, 32,
+ MMBL, 32,
+ PMBL, 32,
+
+ }
+
+ ADBG("Pmem of TBT RP:")
+ ADBG(PMBL)
+
+ Return(PMBL)
+ } // End of Method(TSUP, 0, Serialized)
+
+ //
+ // Wait for secondary bus in TBT RP
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(WSUB, 2, Serialized)
+ {
+ ADBG(Concatenate("WSUB=3D", ToHexString(Arg0)))
+ ADBG(ToHexString(Timer))
+
+ Store(0, Local0)
+ Store(0, Local1)
+ While(1)
+ {
+ Store(TSUP(Arg0, Arg1), Local1)
+ If(LGreater(Local1, 0x1FFF1))
+ {
+ ADBG("WSUB-Finished")
+ Break
+ }
+ Else
+ {
+ Add(Local0, 1, Local0)
+ If(LGreater(Local0, 1000))
+ {
+ Sleep(1000)
+ ADBG("WSUB-Deadlock")
+ }
+ Else
+ {
+ Sleep(16)
+ }
+ }
+ }
+ ADBG(Concatenate("WSUb=3D", ToHexString(Local1)))
+ } // End of Method(WSUB)
+
+ // Wait for _WAK finished
+ Method(WWAK)
+ {
+ ADBG("WWAK")
+
+ Wait(WFEV, 0xFFFF)
+ Signal(WFEV) // Set it, to enter on next HP
+ } // End of Method(WWAK)
+
+ Method(NTFY, 2, Serialized)
+ {
+ ADBG("NTFY")
+
+ If(LEqual(NOHP,1))
+ {
+ If (LEqual(Arg1, DTBT_TYPE_PCH)) {
+ Switch(ToInteger(Arg0)) // TBT Selector
+ {
+ Case (1)
+ {
+ ADBG("Notify RP01")
+ Notify(\_SB.PCI0.RP01,0)
+ }
+ Case (2)
+ {
+ ADBG("Notify RP02")
+ Notify(\_SB.PCI0.RP02,0)
+ }
+ Case (3)
+ {
+ ADBG("Notify RP03")
+ Notify(\_SB.PCI0.RP03,0)
+ }
+ Case (4)
+ {
+ ADBG("Notify RP04")
+ Notify(\_SB.PCI0.RP04,0)
+ }
+ Case (5)
+ {
+ ADBG("Notify RP05")
+ Notify(\_SB.PCI0.RP05,0)
+ }
+ Case (6)
+ {
+ ADBG("Notify RP06")
+ Notify(\_SB.PCI0.RP06,0)
+ }
+ Case (7)
+ {
+ ADBG("Notify RP07")
+ Notify(\_SB.PCI0.RP07,0)
+ }
+ Case (8)
+ {
+ ADBG("Notify RP08")
+ Notify(\_SB.PCI0.RP08,0)
+ }
+ Case (9)
+ {
+ ADBG("Notify RP09")
+ Notify(\_SB.PCI0.RP09,0)
+ }
+ Case (10)
+ {
+ ADBG("Notify RP10")
+ Notify(\_SB.PCI0.RP10,0)
+ }
+ Case (11)
+ {
+ ADBG("Notify RP11")
+ Notify(\_SB.PCI0.RP11,0)
+ }
+ Case (12)
+ {
+ ADBG("Notify RP12")
+ Notify(\_SB.PCI0.RP12,0)
+ }
+ Case (13)
+ {
+ ADBG("Notify RP13")
+ Notify(\_SB.PCI0.RP13,0)
+ }
+ Case (14)
+ {
+ ADBG("Notify RP14")
+ Notify(\_SB.PCI0.RP14,0)
+ }
+ Case (15)
+ {
+ ADBG("Notify RP15")
+ Notify(\_SB.PCI0.RP15,0)
+ }
+ Case (16)
+ {
+ ADBG("Notify RP16")
+ Notify(\_SB.PCI0.RP16,0)
+ }
+ Case (17)
+ {
+ ADBG("Notify RP17")
+ Notify(\_SB.PCI0.RP17,0)
+ }
+ Case (18)
+ {
+ ADBG("Notify RP18")
+ Notify(\_SB.PCI0.RP18,0)
+ }
+ Case (19)
+ {
+ ADBG("Notify RP19")
+ Notify(\_SB.PCI0.RP19,0)
+ }
+ Case (20)
+ {
+ ADBG("Notify RP20")
+ Notify(\_SB.PCI0.RP20,0)
+ }
+ Case (21)
+ {
+ ADBG("Notify RP21")
+ Notify(\_SB.PCI0.RP21,0)
+ }
+ Case (22)
+ {
+ ADBG("Notify RP22")
+ Notify(\_SB.PCI0.RP22,0)
+ }
+ Case (23)
+ {
+ ADBG("Notify RP23")
+ Notify(\_SB.PCI0.RP23,0)
+ }
+ Case (24)
+ {
+ ADBG("Notify RP24")
+ Notify(\_SB.PCI0.RP24,0)
+ }
+ }//Switch(ToInteger(TBSS)) // TBT Selector
+ } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (1)
+ {
+ ADBG("Notify PEG0")
+ Notify(\_SB.PCI0.PEG0,0)
+ }
+ Case (2)
+ {
+ ADBG("Notify PEG1")
+ Notify(\_SB.PCI0.PEG1,0)
+ }
+ Case (3)
+ {
+ ADBG("Notify PEG2")
+ Notify(\_SB.PCI0.PEG2,0)
+ }
+ }
+ }//Switch(ToInteger(TBSS)) // TBT Selector
+ }//If(NOHP())
+ P8XH(0,0xC2)
+ P8XH(1,0xC2)
+ }// End of Method(NTFY)
+
+//
+// TBT BIOS, GPIO 5 filtering,
+// Hot plug of 12V USB devices, into TBT host router, cause electrical no=
ise on PCH GPIOs,
+// This noise cause false hot-plug events, and negatively influence BIOS =
assisted hot-plug.
+// WHL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS=
) on any GPIO pad. Native functions have to implement their own digital gli=
tch-filter logic
+// if needed. As HW filter was not implemented on WHL PCH, because of tha=
t SW workaround should be implemented in BIOS.
+// Register 0x544(Bios mailbox) bit 0 definition:
+// if BIOS reads bit as 1, BIOS will clear the bit and continue normal fl=
ow, if bit is 0 BIOS will exit from method
+//
+
+ Method(GNIS,2, Serialized)
+ {
+
+ ADBG("GNIS")
+ If(LEqual(GP5F, 0))
+ {
+ ADBG("GNIS_Dis=3D0")
+ Return(0)
+ }
+ //
+ // BIOS mailbox command for GPIO filter
+ //
+ Add(MMTB(Arg0, Arg1), 0x544, Local0)
+ OperationRegion(PXVD,SystemMemory,Local0,0x08)
+
+ Field(PXVD,DWordAcc, NoLock, Preserve)
+ {
+ HPFI, 1,
+ Offset(0x4),
+ TB2P, 32
+ }
+ Store(TB2P, Local1)
+ ADBG(Concatenate("TB2P=3D", ToHexString(Local1)))
+ If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect?
+ {
+ ADBG("GNIS=3D0")
+ Return(0)
+ }
+ Store(HPFI, Local2)
+ ADBG(Concatenate("HPFI=3D", ToHexString(Local2)))
+ If(LEqual(Local2, 0x01))
+ {
+ Store(0x00, HPFI)
+ ADBG("GNIS=3D0")
+ Return(0)
+ }
+ // Any other values treated as a GPIO noise
+ ADBG("GNIS=3D1")
+ Return(1)
+ }
+
+ Method(CHKP,2, Serialized)
+ {
+ Add(MMTB(Arg0, Arg1), 0x544, Local0)
+ OperationRegion(PXVE,SystemMemory,Local0,0x08)
+
+ Field(PXVE,DWordAcc, NoLock, Preserve)
+ {
+ HPFI, 1,
+ Offset(0x4),
+ TB2P, 32
+ }
+ Store(TB2P, Local1)
+ And(Local1,BIT29,Local1)
+ ADBG(Concatenate("Local1=3D", ToHexString(Local1)))
+ //ADBG(Concatenate("BIT29=3D", ToHexString(LAnd(Local1,BIT29))))
+ If(LEqual(Local1, BIT29))
+ {
+ Return(1)
+ }
+ Else
+ {
+ Return(0)
+ }
+ }
+
+ //
+ // Method to Handle enumerate PCIe structure through
+ // SMI for Thunderbolt(TM) devices
+ //
+ Method(XTBT,2, Serialized)
+ {
+ ADBG("XTBT")
+ ADBG("RP :")
+ ADBG(Arg0)
+ Store(Arg0, DTCP) // Root port to enumerate
+ Store(Arg1, DTPT) // Root port Type
+ If(LEqual(Arg0, RPS0)) {
+ Store (1, Local0)
+ } ElseIf (LEqual(Arg0, RPS1)) {
+ Store (2, Local0)
+ } Else {
+ Store (0, Local0)
+ Return ()
+ }
+
+ If (TRDO) {
+ ADBG("Durng TBT_ON")
+ Return ()
+ }
+
+ If (TRD3) {
+ ADBG("During TBT_OFF")
+ Return ()
+ }
+ WWAK()
+ WSUB(Arg0, Arg1)
+ If(GNIS(Arg0, Arg1))
+ {
+ Return()
+ }
+
+ OperationRegion(SPRT,SystemIO, 0xB2,2)
+ Field (SPRT, ByteAcc, Lock, Preserve)
+ {
+ SSMP, 8
+ }
+
+ ADBG("TBT-HP-Handler")
+
+ Acquire(OSUM, 0xFFFF)
+ Store(TBFF(Arg0, Arg1), Local1)
+ If(LEqual(Local1, 1))// Only HR
+ {
+ Sleep(16)
+ Release(OSUM)
+ ADBG("OS_Up_Received")
+ Return ()
+ }
+ If(LEqual(Local1, 2)) // Disconnect
+ {
+ NTFY(Arg0, Arg1)
+ Sleep(16)
+ Release(OSUM)
+ ADBG("Disconnect")
+ Return ()
+ }
+
+ // HR and EP
+ If(LEqual(SOHP, 1))
+ {
+ // Trigger SMI to enumerate PCIe Structure
+ ADBG("TBT SW SMI")
+ Store(21, TBSF)
+ Store(0xF7, SSMP)
+ }
+ NTFY(Arg0, Arg1)
+ Sleep(16)
+ Release(OSUM)
+
+ ADBG("End-of-XTBT")
+ } // End of Method(XTBT)
+
+ //
+ // Calling Method to Handle enumerate PCIe structure through
+ // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs
+ // Used in Two ways ,
+ // If CIO GPIO(1 Tier) is Different for the Controllers, this will be us=
ed as 1 Tier GPIO Handler for 1st controller
+ // If CIO GPIO(1 Tier) is Same for all the controllers, this will be use=
d as 1 Tier GPIO Handler for All the controllers
+ //
+ Method(ATBT)
+ {
+ ADBG("ATBT")
+ //
+ // Calling Method to Handle enumerate PCIe structure through
+ //
+ If(LEqual(CGST,0)) { // If GPIO is Different for each controller
+ If(LEqual(RPN0,1))
+ {
+ XTBT(RPS0, RPT0)
+ }
+ } Else {
+ If(LEqual(RPN0,1))
+ {
+ XTBT(RPS0, RPT0)
+ }
+ ElseIf(LEqual(RPN1,1))
+ {
+ XTBT(RPS1, RPT1)
+ }
+ }
+ ADBG("End-of-ATBT")
+ } // End of Method(ATBT)
+
+ Method(BTBT)
+ {
+ ADBG("BTBT")
+ //
+ // Calling Method to Handle enumerate PCIe structure through
+ //
+ If(LEqual(CGST,0)) { // If GPIO is Different for each controller
+ If(LEqual(RPN1,1))
+ {
+ XTBT(RPS1, RPT1)
+ }
+ }
+ ADBG("End-of-BTBT")
+ } // End of Method(BTBT)
+ //
+ // Method to call OSPU Mail box command
+ // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT
+ // Arg1 : TBT RP Selector / DMA
+ // Arg2 : TBT Type (PCH or PEG)
+ //
+ Method(TINI, 3, Serialized)
+ {
+ ADBG("TINI")
+ If(Lequal (Arg0, DTBT_CONTROLLER))
+ {
+ //ADBG("DTBT")
+ Store(MMRP(Arg1, Arg2), Local0)
+ OperationRegion(RP_X,SystemMemory,Local0,0x20)
+ Field(RP_X,DWordAcc, NoLock, Preserve)
+ {
+ REG0, 32,
+ REG1, 32,
+ REG2, 32,
+ REG3, 32,
+ REG4, 32,
+ REG5, 32,
+ REG6, 32,
+ REG7, 32
+ }
+ Store(REG6, Local1)
+ Store(0x00F0F000, REG6)
+ Store(MMTB(Arg1, Arg2), Local2)
+ OSUP(Local2, DTBT_CONTROLLER)
+ Store(Local1, REG6)
+ }
+ ADBG("End-of-TINI")
+ }
+
+} // End of Scope (\_GPE)
+
+Scope (\_SB)
+{
+ //
+ // The code needs to be executed for TBT Hotplug Handler event (2-tier G=
PI GPE event architecture) is presented here
+ //
+ Method(THDR, 3, Serialized)
+ {
+ ADBG("THDR")
+ \_SB.CAGS(Arg0)
+ \_GPE.XTBT(Arg1, Arg2)
+ } // End of Method(THDR, 3, Serialized)
+} // End of Scope(\_SB)
+
+Scope (\_SB)
+{
+ //
+ // Name: CGWR [Combined GPIO Write]
+ // Description: Function to write into GPIO
+ // Input: Arg0 -> GpioPad / Expander pin
+ // Arg1 -> Value
+ // Return: Nothing
+ //
+ Method(CGWR, 2, Serialized)
+ {
+ // PCH
+ If (CondRefOf(\_SB.SGOV))
+ {
+ \_SB.SGOV(Arg0, Arg1)
+ }
+ } // End of Method(CGWR, 4, Serialized)
+
+ //
+ // Name: CGRD [Combined GPIO Read]
+ // Description: Function to read from GPIO
+ // Input: Arg0 -> GpioPad / Expander pin
+ // Arg1 -> 0: GPO [GPIO TX State]
+ // 1: GPI [GPIO RX State]
+ // Return: Value
+ //
+ Method(CGRD, 2, Serialized)
+ {
+ Store(1, Local0)
+ // PCH
+ If (LEqual(Arg1, 0))
+ {
+ // GPIO TX State
+ If (CondRefOf(\_SB.GGOV))
+ {
+ Store(\_SB.GGOV(Arg0), Local0)
+ }
+ }
+ ElseIf (LEqual(Arg1, 1))
+ {
+ // GPIO RX State
+ If (CondRefOf(\_SB.GGIV))
+ {
+ Store(\_SB.GGIV(Arg0), Local0)
+ }
+ }
+ Return(Local0)
+ } // End of Method(CGRD, 4, Serialized)
+ //
+ // Name: WRGP [GPIO Write]
+ // Description: Function to write into GPIO
+ // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
+ // Arg1 -> Value
+ // Return: Nothing
+ //
+ Method(WRGP, 2, Serialized)
+ {
+ Store(Arg0, Local0)
+ Store(Arg0, Local1)
+ And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
+ ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
+ If (LEqual(And(Local0, 0xFF), 1))
+ {
+ // PCH
+ \_SB.CGWR(Local1, Arg1)
+ }
+ } // End of Method(WRGP, 2, Serialized)
+
+ //
+ // Name: RDGP [GPIO Read]
+ // Description: Function to write into GPIO
+ // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
+ // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State indic=
ator}
+ // Return: Value
+ //
+ Method(RDGP, 2, Serialized)
+ {
+ Store(1, Local7)
+ Store(Arg0, Local0)
+ Store(Arg0, Local1)
+ And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
+ ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
+ If (LEqual(And(Local0, 0xFF), 1))
+ {
+ // PCH
+ Store(\_SB.CGRD(Local1, Arg1), Local7)
+ }
+ Return(Local7)
+ } // End of Method(RDGP, 2, Serialized)
+
+} // End of Scope(\_SB)
+
+Scope(\_SB)
+{
+ // Asserts/De-asserts TBT force power
+ Method(TBFP, 2)
+ {
+ If(Arg0)
+ {
+ // Implementation dependent way to assert TBT force power
+ If(LEqual(Arg1, 1)) {
+ CGWR(FPG0, FP0L)
+ }
+ Else {
+ CGWR(FPG1, FP1L)
+ }
+ }
+ Else
+ {
+ // Implementation dependent way to de-assert TBT force power
+ If(LEqual(Arg1, 1)) {
+ CGWR(FPG0, LNot(FP0L))
+ }
+ Else {
+ CGWR(FPG1, LNot(FP1L))
+ }
+ }
+ }
+
+ // WMI ACPI device to control TBT force power
+ Device(WMTF)
+ {
+ // pnp0c14 is pnp id assigned to WMI mapper
+ Name(_HID, "PNP0C14")
+ Name(_UID, "TBFP")
+
+ Name(_WDG, Buffer() {
+ // {86CCFD48-205E-4A77-9C48-2021CBEDE341}
+ 0x48, 0xFD, 0xCC, 0x86,
+ 0x5E, 0x20,
+ 0x77, 0x4A,
+ 0x9C, 0x48,
+ 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41,
+ 84, 70, // Object Id (TF)
+ 1, // Instance Count
+ 0x02 // Flags (WMIACPI_REGFLAG_METHOD)
+ })
+
+ // Set TBT force power
+ // Arg2 is force power value
+ Method(WMTF, 3)
+ {
+ CreateByteField(Arg2,0,FP)
+
+ If(FP)
+ {
+ TBFP(1, 1)
+ }
+ Else
+ {
+ TBFP(0, 1)
+ }
+ }
+ }
+} // End of Scope(\_SB)
+
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1))))
+{
+ Scope(\_SB.PCI0.RP01)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP01)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2))))
+{
+ Scope(\_SB.PCI0.RP02)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP02)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3))))
+{
+ Scope(\_SB.PCI0.RP03)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP03)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4))))
+{
+ Scope(\_SB.PCI0.RP04)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP04)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5))))
+{
+ Scope(\_SB.PCI0.RP05)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP05)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6))))
+{
+ Scope(\_SB.PCI0.RP06)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP06)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7))))
+{
+ Scope(\_SB.PCI0.RP07)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP07)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8))))
+{
+ Scope(\_SB.PCI0.RP08)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP08)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9))))
+{
+ Scope(\_SB.PCI0.RP09)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP09)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10))))
+{
+ Scope(\_SB.PCI0.RP10)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP10)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11))))
+{
+ Scope(\_SB.PCI0.RP11)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP11)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12))))
+{
+ Scope(\_SB.PCI0.RP12)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP12)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13))))
+{
+ Scope(\_SB.PCI0.RP13)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP13)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14))))
+{
+ Scope(\_SB.PCI0.RP14)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP14)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15))))
+{
+ Scope(\_SB.PCI0.RP15)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP15)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16))))
+{
+ Scope(\_SB.PCI0.RP16)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP16)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17))))
+{
+ Scope(\_SB.PCI0.RP17)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP17)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18))))
+{
+ Scope(\_SB.PCI0.RP18)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP18)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19))))
+{
+ Scope(\_SB.PCI0.RP19)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP19)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20))))
+{
+ Scope(\_SB.PCI0.RP20)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP20)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21))))
+{
+ Scope(\_SB.PCI0.PEG0)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.PEG0)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22))))
+{
+ Scope(\_SB.PCI0.PEG1)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.PEG1)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23))))
+{
+ Scope(\_SB.PCI0.PEG2)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.PEG2)
+}
+
+Scope(\_SB)
+{
+ //
+ // Name: PERB
+ // Description: Function to read a Byte from PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Return: Byte data read from PCIE-MMIO
+ //
+ Method(PERB,5,Serialized)
+ {
+ ADBG("PERB")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 1)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 8
+ }
+
+ Return(TEMP)
+ } // End of Method(PERB,5,Serialized)
+
+ //
+ // Name: PEWB
+ // Description: Function to write a Byte into PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Arg5 -> Data
+ // Return: Nothing
+ //
+ Method(PEWB,6,Serialized)
+ {
+ ADBG("PEWB")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 1)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 8
+ }
+
+ Store(Arg5,TEMP)
+ } // End of Method(PEWB,6,Serialized)
+
+ //
+ // Name: PERW
+ // Description: Function to read a Word from PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Return: Word data read from PCIE-MMIO
+ //
+ Method(PERW,5,Serialized)
+ {
+ ADBG("PERW")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 2)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 16
+ }
+
+ Return(TEMP)
+ } // End of Method(PERW,5,Serialized)
+
+ //
+ // Name: PEWW
+ // Description: Function to write a Word into PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Arg5 -> Data
+ // Return: Nothing
+ //
+ Method(PEWW,6,Serialized)
+ {
+ ADBG("PEWW")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 2)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 16
+ }
+
+ Store(Arg5,TEMP)
+ } // End of Method(PEWW,6,Serialized)
+
+ //
+ // Name: PERD
+ // Description: Function to read a Dword from PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Return: Dword data read from PCIE-MMIO
+ //
+ Method(PERD,5,Serialized)
+ {
+ ADBG("PERD")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 4)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 32
+ }
+
+ Return(TEMP)
+ } // End of Method(PERD,5,Serialized)
+
+ //
+ // Name: PEWD
+ // Description: Function to write a Dword into PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Arg5 -> Data
+ // Return: Nothing
+ //
+ Method(PEWD,6,Serialized)
+ {
+ ADBG("PEWD")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 4)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 32
+ }
+
+ Store(Arg5,TEMP)
+ } // End of Method(PEWD,6,Serialized)
+
+ //
+ // Name: STDC
+ // Description: Function to get Standard Capability Register Offset
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Capability ID
+ // Return: Capability Register Offset data
+ //
+ Method(STDC,5,Serialized)
+ {
+ ADBG("STDC")
+
+ //Check for Referenced device is present or not
+ Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID regist=
er
+ If(LEqual(Local7, 0xFFFF))
+ {
+ ADBG("Referenced device is not present")
+ Return(0)
+ }
+
+ Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status re=
gister
+ If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List
+ {
+ //No Capabilities linked list is available
+ ADBG("No Capabilities linked list is available")
+ Return(0)
+ }
+
+ //Local1 is for storing CapabilityID
+ //Local2 is for storing CapabilityPtr
+ Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr
+
+ While(1)
+ {
+ And(Local2, 0xFC, Local2) //Each capability must be DWORD aligned
+
+ If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate=
the last capability in the list
+ {
+ ADBG("Capability ID is not found")
+ Return(0)
+ }
+
+ Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID
+
+ If(LEqual(Arg4, Local1)) //CapabilityID match
+ {
+ ADBG("Capability ID is found")
+ ADBG("Capability Offset : ")
+ ADBG(Local2)
+ Return(Local2)
+ }
+ Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2) //Capa=
bilityPtr
+ Return(0)
+ }
+ } // End of Method(STDC,5,Serialized)
+
+} // End Scope(\_SB)
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/=
TbtDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/Tb=
tDxe.c
new file mode 100644
index 0000000000..ef6201de94
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
@@ -0,0 +1,228 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/TbtCommonLib.h>
+#include <Library/DxeTbtPolicyLib.h>
+#include <TbtBoardInfo.h>
+#include <Protocol/DxeTbtPolicy.h>
+#include <Protocol/TbtNvsArea.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Uefi/UefiSpec.h>
+#include <Library/PcdLib.h>
+#include <Library/AslUpdateLib.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA_PROTOCOL mT=
btNvsAreaProtocol;
+GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *g=
TbtInfoHob =3D NULL;
+
+/**
+ TBT NVS Area Initialize
+
+**/
+
+VOID
+TbtNvsAreaInit (
+ IN VOID **mTbtNvsAreaPtr
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol;
+ DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig;
+
+ DEBUG ((DEBUG_INFO, "TbtNvsAreaInit Start\n"));
+ Status =3D gBS->LocateProtocol (
+ &gDxeTbtPolicyProtocolGuid,
+ NULL,
+ (VOID **) &DxeTbtConfig
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Pages =3D EFI_SIZE_TO_PAGES (sizeof (TBT_NVS_AREA));
+ Address =3D 0xffffffff; // allocate address below 4G.
+
+ Status =3D gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ *mTbtNvsAreaPtr =3D (VOID *) (UINTN) Address;
+ SetMem (*mTbtNvsAreaPtr, sizeof (TBT_NVS_AREA), 0);
+
+ //
+ // TBTNvsAreaProtocol default value init here
+ //
+ TbtNvsAreaProtocol =3D (TBT_NVS_AREA_PROTOCOL *) &Address;
+
+ //
+ // Initialize default values
+ //
+ TbtNvsAreaProtocol->Area->WAKFinished =3D 0;
+ TbtNvsAreaProtocol->Area->DiscreteTbtSupport =3D ((gTbtInfoHob-> DT=
btControllerConfig.DTbtControllerEn =3D=3D 1 ) ? TRUE : FALSE);
+ TbtNvsAreaProtocol->Area->TbtAcpiRemovalSupport =3D 0;
+ TbtNvsAreaProtocol->Area->TbtGpioFilter =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.Gpio5Filter;
+// TbtNvsAreaProtocol->Area->TrOsup =3D (UINT8) DxeTbtCo=
nfig->TbtCommonConfig.TrA0OsupWa;
+ TbtNvsAreaProtocol->Area->TbtFrcPwrEn =3D gTbtInfoHob->DTbtC=
ommonConfig.Gpio3ForcePwr;
+ TbtNvsAreaProtocol->Area->TbtAspm =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.TbtAspm;
+// TbtNvsAreaProtocol->Area->TbtL1SubStates =3D (UINT8) DxeTbtCo=
nfig->TbtCommonConfig.TbtL1SubStates;
+ TbtNvsAreaProtocol->Area->TbtSetClkReq =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.TbtSetClkReq;
+ TbtNvsAreaProtocol->Area->TbtLtr =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.TbtLtr;
+// TbtNvsAreaProtocol->Area->TbtPtm =3D (UINT8) DxeTbtCo=
nfig->TbtCommonConfig.TbtPtm;
+ TbtNvsAreaProtocol->Area->TbtWakeupSupport =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.TbtWakeupSupport;
+ TbtNvsAreaProtocol->Area->TbtAcDcSwitch =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.TbtAcDcSwitch;
+ TbtNvsAreaProtocol->Area->Rtd3TbtSupport =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.Rtd3Tbt; // TBT RTD3 Enable.
+ TbtNvsAreaProtocol->Area->Rtd3TbtOffDelay =3D (UINT16) DxeTbtCon=
fig->TbtCommonConfig.Rtd3TbtOffDelay; // TBT RTD3 Off delay in ms.
+ TbtNvsAreaProtocol->Area->Rtd3TbtClkReq =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.Rtd3TbtClkReq; // TBT RTD3 ClkReq Mask Enable.
+ TbtNvsAreaProtocol->Area->Rtd3TbtClkReqDelay =3D (UINT16) DxeTbtCon=
fig->TbtCommonConfig.Rtd3TbtClkReqDelay; // TBT RTD3 ClkReq mask delay in m=
s.
+ TbtNvsAreaProtocol->Area->TbtWin10Support =3D (UINT8) DxeTbtConf=
ig->TbtCommonConfig.Win10Support; // TBT FW Execution Mode
+
+ //
+ // DTBT Controller 1
+ //
+ TbtNvsAreaProtocol->Area->DTbtControllerEn0 =3D gTbtInfoHob-> DTbt=
ControllerConfig.DTbtControllerEn;
+ TbtNvsAreaProtocol->Area->RootportSelected0 =3D gTbtInfoHob-> DTbt=
ControllerConfig.PcieRpNumber;
+ TbtNvsAreaProtocol->Area->RootportSelected0Type =3D gTbtInfoHob-> DTbt=
ControllerConfig.Type;
+ TbtNvsAreaProtocol->Area->RootportEnabled0 =3D gTbtInfoHob-> DTbt=
ControllerConfig.DTbtControllerEn;
+ TbtNvsAreaProtocol->Area->TbtFrcPwrGpioNo0 =3D gTbtInfoHob-> DTbt=
ControllerConfig.ForcePwrGpio.GpioPad;
+ TbtNvsAreaProtocol->Area->TbtFrcPwrGpioLevel0 =3D gTbtInfoHob-> DTbt=
ControllerConfig.ForcePwrGpio.GpioLevel;
+ TbtNvsAreaProtocol->Area->TbtCioPlugEventGpioNo0 =3D gTbtInfoHob-> DTbt=
ControllerConfig.CioPlugEventGpio.GpioPad;
+ TbtNvsAreaProtocol->Area->TbtPcieRstGpioNo0 =3D gTbtInfoHob-> DTbt=
ControllerConfig.PcieRstGpio.GpioPad;
+ TbtNvsAreaProtocol->Area->TbtPcieRstGpioLevel0 =3D gTbtInfoHob-> DTbt=
ControllerConfig.PcieRstGpio.GpioLevel;
+
+ TbtNvsAreaProtocol->Area->TBtCommonGpioSupport =3D gTbtInfoHob->DTbtC=
ommonConfig.DTbtSharedGpioConfiguration;
+
+ DEBUG ((DEBUG_INFO, "TbtNvsAreaInit End\n"));
+}
+
+/**
+ This function gets registered as a callback to patch TBT ASL code
+
+ @param[in] Event - A pointer to the Event that triggered the callbac=
k.
+ @param[in] Context - A pointer to private data registered with the cal=
lback function.
+ can we put this also in read me
+**/
+VOID
+EFIAPI
+TbtAcpiEndOfDxeCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Address;
+ UINT16 Length;
+ UINT32 Signature;
+
+ Status =3D InitializeAslUpdateLib ();
+ ASSERT_EFI_ERROR (Status);
+
+ Address =3D (UINT32) (UINTN) mTbtNvsAreaProtocol.Area;
+ Length =3D (UINT16) sizeof (TBT_NVS_AREA);
+ DEBUG ((DEBUG_INFO, "Patch TBT NvsAreaAddress: TBT NVS Address %x Length=
%x\n", Address, Length));
+ Status =3D UpdateNameAslCode (SIGNATURE_32 ('T','N','V','B'), &Address,=
sizeof (Address));
+ ASSERT_EFI_ERROR (Status);
+ Status =3D UpdateNameAslCode (SIGNATURE_32 ('T','N','V','L'), &Length, =
sizeof (Length));
+ ASSERT_EFI_ERROR (Status);
+
+ if (gTbtInfoHob !=3D NULL) {
+ if (gTbtInfoHob-> DTbtControllerConfig.DTbtControllerEn =3D=3D 1) {
+ if (gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSigna=
turePorting =3D=3D TRUE) {
+ DEBUG ((DEBUG_INFO, "Patch ATBT Method Name\n"));
+ Signature =3D gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.=
AcpiGpeSignature;
+ Status =3D UpdateNameAslCode (SIGNATURE_32 ('A','T','B','T'), &Si=
gnature, sizeof (Signature));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ }
+
+ return;
+}
+
+/**
+ Initialize Thunderbolt(TM) SSDT ACPI tables
+
+ @retval EFI_SUCCESS ACPI tables are initialized successfully
+ @retval EFI_NOT_FOUND ACPI tables not found
+**/
+
+EFI_STATUS
+EFIAPI
+TbtDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ // EFI_EVENT EndOfDxeEvent;
+
+ DEBUG ((DEBUG_INFO, "TbtDxeEntryPoint \n"));
+
+ //
+ // Get TBT INFO HOB
+ //
+ gTbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
+ if (gTbtInfoHob =3D=3D NULL) {
+ return EFI_NOT_FOUND;
+ }
+ InstallTbtPolicy (ImageHandle);
+ //
+ // Update DXE TBT Policy
+ //
+ UpdateTbtPolicyCallback ();
+
+ //
+ // Print DXE TBT Policy
+ //
+ TbtPrintDxePolicyConfig ();
+
+ //
+ // Initialize Tbt Nvs Area
+ //
+ TbtNvsAreaInit ((VOID **) &mTbtNvsAreaProtocol.Area);
+
+
+ //
+ // [ACPI] Thunderbolt ACPI table
+ //
+
+
+ Handle =3D NULL;
+
+ Status =3D gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gTbtNvsAreaProtocolGuid,
+ &mTbtNvsAreaProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register an end of DXE event for TBT ACPI to do some patch can be put=
as description
+ //
+ /**
+ Status =3D gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ TbtAcpiEndOfDxeCallback,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &EndOfDxeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+**/
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/=
TbtDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/=
TbtDxe.inf
new file mode 100644
index 0000000000..75da20fcb1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.=
inf
@@ -0,0 +1,51 @@
+## @file
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D TbtDxe
+ FILE_GUID =3D 19C9762C-3A88-41B0-906F-8C4C2895A887
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D DXE_DRIVER
+ ENTRY_POINT =3D TbtDxeEntryPoint
+
+[LibraryClasses]
+ DebugLib
+ BaseMemoryLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ UefiDriverEntryPoint
+ HobLib
+ UefiLib
+ TbtCommonLib
+ DxeTbtPolicyLib
+ AslUpdateLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ TbtDxe.c
+
+[Protocols]
+ gTbtNvsAreaProtocolGuid ## CONSUMES
+ gDxeTbtPolicyProtocolGuid
+
+[Guids]
+ gTbtInfoHobGuid ## CONSUMES
+
+[Depex]
+ gEfiVariableWriteArchProtocolGuid AND
+ gEfiVariableArchProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/=
PeiTbtInit.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pe=
i/PeiTbtInit.c
new file mode 100644
index 0000000000..5aaf600795
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtI=
nit.c
@@ -0,0 +1,211 @@
+/** @file
+ Source code file for TBT Init PEI module
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiTbtPolicyLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/PeiTbtPolicy.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <TbtBoardInfo.h>
+#include <Private/Library/PeiDTbtInitLib.h>
+/*
+/**
+ This function Update and Print PEI TBT Policy after TbtPolicyBoardInitDo=
ne
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification =
event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this fu=
nction.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+
+
+/**
+ This function pass PEI TBT Policy to Hob at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification =
event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this fu=
nction.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+
+
+EFI_STATUS
+EFIAPI
+PassTbtPolicyToHob (
+VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ TBT_INFO_HOB *TbtInfoHob;
+ PEI_TBT_POLICY *PeiTbtConfig;
+
+ DEBUG ((DEBUG_INFO, "PassTbtPolicyToHob\n"));
+
+ Status =3D PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+ if (BootMode =3D=3D BOOT_ON_S3_RESUME ) {
+ return EFI_SUCCESS;
+ }
+
+ Status =3D PeiServicesLocatePpi (
+ &gPeiTbtPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiTbtConfig
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Create HOB for TBT Data
+ //
+ Status =3D PeiServicesCreateHob (
+ EFI_HOB_TYPE_GUID_EXTENSION,
+ sizeof (TBT_INFO_HOB),
+ (VOID **) &TbtInfoHob
+ );
+ DEBUG ((DEBUG_INFO, "TbtInfoHob Created \n"));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize the TBT INFO HOB data.
+ //
+ TbtInfoHob->EfiHobGuidType.Name =3D gTbtInfoHobGuid;
+
+ //
+ // Update DTBT Policy
+ //
+ TbtInfoHob-> DTbtControllerConfig.DTbtControllerEn =3D PeiTbtConfig-> DT=
btControllerConfig.DTbtControllerEn;
+ TbtInfoHob-> DTbtControllerConfig.Type =3D PeiTbtConfig-> DTbtController=
Config.Type;
+ TbtInfoHob-> DTbtControllerConfig.PcieRpNumber =3D PeiTbtConfig-> DTbtCo=
ntrollerConfig.PcieRpNumber;
+ TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioPad =3D PeiTbtConfig-=
> DTbtControllerConfig.ForcePwrGpio.GpioPad;
+ TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioLevel =3D PeiTbtConfi=
g-> DTbtControllerConfig.ForcePwrGpio.GpioLevel;
+ TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D PeiTbtCon=
fig-> DTbtControllerConfig.CioPlugEventGpio.GpioPad;
+ TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =3D =
PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature;
+ TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorti=
ng =3D PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignatur=
ePorting;
+ TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioPad =3D PeiTbtConfig->=
DTbtControllerConfig.PcieRstGpio.GpioPad;
+ TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioLevel =3D PeiTbtConfig=
-> DTbtControllerConfig.PcieRstGpio.GpioLevel;
+
+ TbtInfoHob->DTbtCommonConfig.TbtBootOn =3D PeiTbtConfig->DTbtCommonConfi=
g.TbtBootOn;
+ TbtInfoHob->DTbtCommonConfig.TbtUsbOn =3D PeiTbtConfig->DTbtCommonConfig=
.TbtUsbOn;
+ TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwr =3D PeiTbtConfig->DTbtCommonC=
onfig.Gpio3ForcePwr;
+ TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwrDly =3D PeiTbtConfig->DTbtComm=
onConfig.Gpio3ForcePwrDly;
+ TbtInfoHob->DTbtCommonConfig.DTbtSharedGpioConfiguration =3D PeiTbtConfi=
g->DTbtCommonConfig.DTbtSharedGpioConfiguration;
+ TbtInfoHob->DTbtCommonConfig.PcieRstSupport =3D PeiTbtConfig->DTbtCommon=
Config.PcieRstSupport;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function handles TbtInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification =
event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this fu=
nction.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+
+EFI_STATUS
+EFIAPI
+TbtInitEndOfPei (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN DTbtExisted;
+ PEI_TBT_POLICY *PeiTbtConfig;
+
+ DEBUG ((DEBUG_INFO, "TbtInitEndOfPei Entry\n"));
+
+ Status =3D EFI_SUCCESS;
+ PeiTbtConfig =3D NULL;
+ DTbtExisted =3D FALSE;
+
+ Status =3D PeiServicesLocatePpi (
+ &gPeiTbtPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiTbtConfig
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ if (PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn =3D=3D 1) {
+ DTbtExisted =3D TRUE;
+ }
+
+ if (DTbtExisted =3D=3D TRUE) {
+ //
+ // Call Init function
+ //
+ Status =3D TbtInit ();
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ TBT Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to e=
very PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa=
se
+**/
+EFI_STATUS
+EFIAPI
+TbtInitEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "TBT PEI EntryPoint\n"));
+
+ //
+ // Install PEI TBT Policy
+ //
+ Status =3D InstallPeiTbtPolicy ();
+ ASSERT_EFI_ERROR (Status);
+
+
+ UpdatePeiTbtPolicy ();
+
+ TbtPrintPeiPolicyConfig ();
+ //
+ // Performing PassTbtPolicyToHob and TbtInitEndOfPei
+ //
+ Status =3D PassTbtPolicyToHob ();
+
+ Status =3D TbtInitEndOfPei ();
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/=
PeiTbtInit.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/=
Pei/PeiTbtInit.inf
new file mode 100644
index 0000000000..c9a09e1095
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtI=
nit.inf
@@ -0,0 +1,47 @@
+## @file
+# Component information file for the TBT Init PEI module.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PeiTbtInit
+ FILE_GUID =3D 90BF2BFB-F998-4cbc-AD72-008D4D047A4B
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D PEIM
+ ENTRY_POINT =3D TbtInitEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ HobLib
+ PeiServicesLib
+ PeiTbtPolicyLib
+ PeiDTbtInitLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiTbtInit.c
+
+[Guids]
+ gTbtInfoHobGuid ## CONSUMES
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gPeiTbtPolicyBoardInitDonePpiGuid ## CONSUMES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/=
TbtSmiHandler.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit=
/Smm/TbtSmiHandler.c
new file mode 100644
index 0000000000..f80215b4b5
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiH=
andler.c
@@ -0,0 +1,1609 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "TbtSmiHandler.h"
+#include <Library/IoLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Protocol/SmmVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/PciSegmentLib.h>
+#define MEM_PER_SLOT (DEF_RES_MEM_PER_DEV << 4)
+#define PMEM_PER_SLOT (DEF_RES_PMEM_PER_DEV << 4)
+#define IO_PER_SLOT (DEF_RES_IO_PER_DEV << 2)
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN gDeviceBaseAddress;
+//
+//US(X:0:0), DS(X+1:3:0),DS(X+1:4:0),DS(X+1:5:0),DS(X+1:6:0)
+//
+GLOBAL_REMOVE_IF_UNREFERENCED BRDG_CONFIG HrConfigs[MAX_CFG_PORT=
S];
+
+extern UINT8 gCurrentDiscreteTbtRootPort;
+extern UINT8 gCurrentDiscreteTbtRootPortType;
+
+BOOLEAN isLegacyDevice =3D FALSE;
+STATIC UINT8 TbtSegment =3D 0;
+
+STATIC
+VOID
+PortInfoInit (
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ PortInfo->BusNumLimit =3D 4;
+}
+
+STATIC
+VOID
+UnsetVesc (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun
+ )
+{
+ UINT8 Dbus;
+ UINT32 Data32;
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fu=
n, 0);
+
+ //
+ // Check for abcence of DS bridge
+ //
+ if(0xFFFF =3D=3D PciSegmentRead16(gDeviceBaseAddress + PCI_DEVICE_ID_OFF=
SET)) {
+ return;
+ }
+
+ //
+ // Unset vesc_reg2[23] bit (to have an option to access below DS)
+ //
+ Data32 =3D PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2);
+ Data32 &=3D 0xFF7FFFFF;
+ PciSegmentWrite32(gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32);
+ //
+ // Go to Device behind DS
+ //
+ Dbus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_=
REGISTER_OFFSET);
+ DEBUG((DEBUG_INFO, "Dbus =3D %d\n",Dbus));
+ //
+ // Check if there is something behind this Downstream Port (Up or Ep)
+ // If there nothing behind Downstream Port Set vesc_reg2[23] bit -> thi=
s will flush all future MemWr
+ //
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Dbus, 0x00, =
0x00, 0);
+ if(0xFFFF =3D=3D PciSegmentRead16(gDeviceBaseAddress + PCI_DEVICE_ID_OFF=
SET))
+ {
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fu=
n, 0);
+ Data32 =3D PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2);
+ Data32 |=3D 0x00800000;
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32);
+ }
+}// Unset_VESC_REG2
+
+STATIC
+UINT16
+MemPerSlot (
+ IN UINT16 CurrentUsage
+ )
+{
+ if (CurrentUsage =3D=3D 0) {
+ return 0;
+ }
+
+ if (CurrentUsage <=3D 16) {
+ return 16;
+ }
+
+ if (CurrentUsage <=3D 64) {
+ return 64;
+ }
+
+ if (CurrentUsage <=3D 128) {
+ return 128;
+ }
+
+ if (CurrentUsage <=3D 256) {
+ return 256;
+ }
+
+ if (CurrentUsage <=3D 512) {
+ return 512;
+ }
+
+ if (CurrentUsage <=3D 1024) {
+ return 1024;
+ }
+
+ return CurrentUsage;
+} // MemPerSlot
+
+STATIC
+UINT64
+PMemPerSlot (
+ IN UINT64 CurrentUsage
+ )
+{
+ if (CurrentUsage =3D=3D 0) {
+ return 0;
+ }
+
+ if (CurrentUsage <=3D 1024ULL) {
+ return 1024ULL;
+ }
+
+ if (CurrentUsage <=3D 4096ULL) {
+ return 4096ULL;
+ }
+
+ return CurrentUsage;
+} // PMemPerSlot
+
+STATIC
+VOID
+SetPhyPortResources (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 SubBus,
+ IN INT8 Depth,
+ IN PORT_INFO *CurrentPi,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Cmd;
+ UINT16 DeltaMem;
+ UINT64 DeltaPMem;
+
+ Cmd =3D CMD_BUS_MASTER;
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0x=
00, 0);
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIST=
ER_OFFSET, SubBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+
+ DeltaMem =3D PortInfo->MemBase - CurrentPi->MemBase;
+ if (isLegacyDevice) {
+ if (Depth >=3D 0 && (DeltaMem < MEM_PER_SLOT)) {
+ PortInfo->MemBase +=3D MEM_PER_SLOT - DeltaMem;
+ }
+ } else {
+ if (DeltaMem < MemPerSlot (DeltaMem)) {
+ PortInfo->MemBase +=3D MemPerSlot (DeltaMem) - DeltaMem;
+ }
+ }
+
+ if (PortInfo->MemBase > CurrentPi->MemBase && (PortInfo->MemBase - 0x10)=
<=3D PortInfo->MemLimit) {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryBase), CurrentPi->MemBase);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryLimit), PortInfo->MemBase - 0x10);
+ Cmd |=3D CMD_BM_MEM;
+ } else {
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryBase), DISBL_MEM32_REG20);
+ PortInfo->MemBase =3D CurrentPi->MemBase;
+ }
+
+ DeltaPMem =3D PortInfo->PMemBase64 - CurrentPi->PMemBase64;
+ if (isLegacyDevice) {
+ if ((Depth >=3D 0) && ((UINTN)DeltaPMem < (UINTN)PMEM_PER_SLOT)) {
+ PortInfo->PMemBase64 +=3D PMEM_PER_SLOT - DeltaPMem;
+ }
+ } else {
+ if (DeltaPMem < PMemPerSlot (DeltaPMem)) {
+ PortInfo->PMemBase64 +=3D PMemPerSlot (DeltaPMem) - DeltaPMem;
+ }
+ }
+
+ if (PortInfo->PMemBase64 > CurrentPi->PMemBase64 && (PortInfo->PMemBase6=
4 - 0x10) <=3D PortInfo->PMemLimit64) {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryBase), (UINT16) (CurrentPi->PMemBase64 & 0xFFFF));
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryLimit), (UINT16) ((PortInfo->PMemBase64 - 0x10) & 0xFFFF)=
);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableBaseUpper32), (UINT32) (CurrentPi->PMemBase64 >> 16));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableLimitUpper32), (UINT32) ((PortInfo->PMemBase64 - 0x10) >> 16));
+ Cmd |=3D CMD_BM_MEM;
+ } else {
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryBase), DISBL_PMEM_REG24);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableBaseUpper32), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableLimitUpper32), 0);
+ PortInfo->PMemBase64 =3D CurrentPi->PMemBase64;
+ }
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA=
CHE_LINE_SIZE);
+} // SetPhyPortResources
+
+STATIC
+UINT32
+SaveSetGetRestoreBar (
+ IN UINTN Bar
+ )
+{
+ UINT32 BarReq;
+ UINT32 OrigBar;
+
+ OrigBar =3D PciSegmentRead32(Bar); // Save BAR
+ PciSegmentWrite32(Bar, 0xFFFFFFFF); // Set BAR
+ BarReq =3D PciSegmentRead32(Bar); // Get BAR
+ PciSegmentWrite32(Bar, OrigBar); // Restore BAR
+
+ return BarReq;
+} // SaveSetGetRestoreBar
+
+STATIC
+VOID
+SetIoBar (
+ IN UINTN BAR,
+ IN UINT32 BarReq,
+ IN OUT UINT8 *Cmd,
+ IN OUT IO_REGS *IoReg
+ )
+{
+ UINT16 Alignment;
+ UINT16 Size;
+ UINT16 NewBase;
+
+ Alignment =3D ~(BarReq & 0xFFFC);
+ Size =3D Alignment + 1;
+
+ if (IoReg->Base > IoReg->Limit || !Size) {
+ return ;
+
+ }
+
+ NewBase =3D BAR_ALIGN (IoReg->Base, Alignment);
+ if (NewBase > IoReg->Limit || NewBase + Size - 1 > IoReg->Limit) {
+ return ;
+
+ }
+ PciSegmentWrite16(BAR, NewBase);
+ IoReg->Base =3D NewBase + Size; // Advance to new position
+ *Cmd |=3D CMD_BM_IO; // Set Io Space Enable
+} // SetIoBar
+
+STATIC
+VOID
+SetMemBar (
+ IN UINTN BAR,
+ IN UINT32 BarReq,
+ IN OUT UINT8 *Cmd,
+ IN OUT MEM_REGS *MemReg
+ )
+{
+ UINT32 Alignment;
+ UINT32 Size;
+ UINT32 NewBase;
+
+ Alignment =3D ~(BarReq & 0xFFFFFFF0);
+ Size =3D Alignment + 1;
+
+ if (MemReg->Base > MemReg->Limit || !Size) {
+ return ;
+
+ }
+
+ NewBase =3D BAR_ALIGN (MemReg->Base, Alignment);
+ if (NewBase > MemReg->Limit || NewBase + Size - 1 > MemReg->Limit) {
+ return ;
+
+ }
+
+ PciSegmentWrite32(BAR, NewBase);
+ MemReg->Base =3D NewBase + Size; // Advance to new position
+ *Cmd |=3D CMD_BM_MEM; // Set Memory Space Enable
+} // SetMemBar
+
+STATIC
+VOID
+SetPMem64Bar (
+ IN UINTN BAR,
+ IN BOOLEAN IsMaxBar,
+ IN UINT32 BarReq,
+ IN OUT UINT8 *Cmd,
+ IN OUT PMEM_REGS *MemReg
+ )
+{
+ UINT32 Alignment;
+ UINT32 Size;
+ UINT64 NewBase;
+
+ Alignment =3D ~(BarReq & 0xFFFFFFF0);
+ Size =3D Alignment + 1;
+
+ if (MemReg->Base64 > MemReg->Limit64 || !Size) {
+ return ;
+ }
+
+ NewBase =3D BAR_ALIGN (MemReg->Base64, Alignment);
+ if (NewBase > MemReg->Limit64 || NewBase + Size - 1 > MemReg->Limit64) {
+ return ;
+ }
+ PciSegmentWrite32(BAR, (UINT32)(NewBase & 0xFFFFFFFF));
+ if (!IsMaxBar) {
+ BAR++;
+ PciSegmentWrite32(BAR, (UINT32)(NewBase >> 32));
+ }
+ MemReg->Base64 =3D NewBase + Size; // Advance to new position
+ *Cmd |=3D CMD_BM_MEM; // Set Memory Space Enable
+} // SetPMem64Bar
+
+STATIC
+VOID
+SetDevResources (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 MaxFun, // PCI_MAX_FUNC for devices, 1 for bridge
+ IN UINT8 MaxBar, // PCI_BAR5 for devices, PCI_BAR1 for br=
idge
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Fun;
+ UINT8 Reg;
+ UINT32 BarReq;
+ IO_REGS Io;
+ MEM_REGS Mem;
+ PMEM_REGS PMem;
+ UINT8 Cmd;
+
+ Io.Base =3D PortInfo->IoBase << 8;
+ Io.Limit =3D (PortInfo->IoLimit << 8) | 0xFF;
+ Mem.Base =3D PortInfo->MemBase << 16;
+ Mem.Limit =3D (PortInfo->MemLimit << 16) | 0xFFFF;
+ PMem.Base64 =3D PortInfo->PMemBase64 << 16;
+ PMem.Limit64 =3D (PortInfo->PMemLimit64 << 16) | 0xFFFF;
+
+ for (Fun =3D 0; Fun < MaxFun; ++Fun) {
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, =
Fun, 0);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BUS_MAS=
TER);
+ Cmd =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET);
+ if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID=
_OFFSET)) {
+ continue;
+
+ }
+
+ for (Reg =3D PCI_BASE_ADDRESSREG_OFFSET; Reg <=3D MaxBar; Reg +=3D 4) {
+ BarReq =3D SaveSetGetRestoreBar(gDeviceBaseAddress + Reg); // Perfor=
m BAR sizing
+
+ if (BarReq & BIT0) {
+ //
+ // I/O BAR
+ //
+ SetIoBar (
+ (gDeviceBaseAddress + Reg),
+ BarReq,
+ &Cmd,
+ &Io
+ );
+ continue;
+ }
+
+ if (BarReq & BIT3) {
+ //
+ // P-Memory BAR
+ //
+ SetPMem64Bar ((gDeviceBaseAddress + Reg), MaxBar =3D=3D Reg, BarRe=
q, &Cmd, &PMem);
+ } else {
+ SetMemBar ((gDeviceBaseAddress + Reg), BarReq, &Cmd, &Mem);
+ }
+
+ if (BIT2 =3D=3D (BarReq & (BIT2 | BIT1))) {
+ //
+ // Base address is 64 bits wide
+ //
+ Reg +=3D 4;
+ if (!(BarReq & BIT3)) {
+ //
+ // 64-bit memory bar
+ //
+ PciSegmentWrite32 (gDeviceBaseAddress + Reg, 0);
+ }
+ }
+ }
+
+ if (Cmd & BIT1) {
+ //
+ // If device uses I/O and MEM mapping use only MEM mepping
+ //
+ Cmd &=3D ~BIT0;
+ }
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_=
CACHE_LINE_SIZE);
+ }
+ //
+ // Update PortInfo if any changes
+ //
+ if (Io.Base > ((UINT32) PortInfo->IoBase << 8)) {
+ PortInfo->IoBase =3D (UINT8) (BAR_ALIGN (Io.Base, 0xFFF) >> 8);
+ }
+
+ if (Mem.Base > ((UINT32) PortInfo->MemBase << 16)) {
+ PortInfo->MemBase =3D (UINT16) (BAR_ALIGN (Mem.Base, 0xFFFFF) >> 16);
+ }
+
+ if (PMem.Base64 > (PortInfo->PMemBase64 << 16)) {
+ PortInfo->PMemBase64 =3D (BAR_ALIGN (PMem.Base64, 0xFFFFF) >> 16);
+ }
+} // SetDevResources
+
+STATIC
+VOID
+InitARHRConfigs(
+ IN HR_CONFIG *Hr_Config,
+ IN UINT8 BusNumLimit,
+ IN OUT BRDG_RES_CONFIG* HrResConf
+)
+{
+ UINT8 i,j;
+
+ //
+ // DS port for USB device
+ //
+ HrConfigs[AR_DS_PORT2].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[AR_DS_PORT2].DevId.Dev =3D 2;
+ HrConfigs[AR_DS_PORT2].DevId.Fun =3D 0;
+ HrConfigs[AR_DS_PORT2].PBus =3D HrConfigs[AR_DS_PORT2].DevId.Bus;
+ HrConfigs[AR_DS_PORT2].SBus =3D HrConfigs[AR_DS_PORT2].PBus + 1;
+ HrConfigs[AR_DS_PORT2].SubBus =3D HrConfigs[AR_DS_PORT2].PBus + 1;
+ //
+ // CIO port
+ //
+ HrConfigs[AR_DS_PORT1].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[AR_DS_PORT1].DevId.Dev =3D 1;
+ HrConfigs[AR_DS_PORT1].DevId.Fun =3D 0;
+ HrConfigs[AR_DS_PORT1].PBus =3D HrConfigs[AR_DS_PORT1].DevId.Bus;
+ HrConfigs[AR_DS_PORT1].SBus =3D HrConfigs[HR_DS_PORT0].SubBus + 1;
+ HrConfigs[AR_DS_PORT1].SubBus =3D BusNumLimit;
+
+ switch(Hr_Config->DeviceId)
+ {
+ //
+ // HR with 1 DS and 1 USB
+ //
+ case AR_HR_2C:
+ case AR_HR_LP:
+ case AR_HR_C0_2C:
+ case TR_HR_2C:
+ Hr_Config->MinDSNumber =3D HrConfigs[AR_DS_PORT1].DevId.Dev;
+ Hr_Config->MaxDSNumber =3D HrConfigs[AR_DS_PORT2].DevId.Dev;
+ Hr_Config->BridgeLoops =3D 4;
+ break;
+ //
+ // HR with 2 DS and 1 USB
+ //
+ case AR_HR_4C:
+ case TR_HR_4C:
+ case AR_HR_C0_4C:
+ Hr_Config->MinDSNumber =3D 1;
+ Hr_Config->MaxDSNumber =3D 4;
+ Hr_Config->BridgeLoops =3D 6;
+ for(j =3D 2, i =3D Hr_Config->MinDSNumber; j < count(HrConfigs) && i=
<=3D Hr_Config->MaxDSNumber; ++j, ++i)
+ {
+ HrConfigs[j].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[j].DevId.Dev =3D i;
+ HrConfigs[j].DevId.Fun =3D 0;
+ HrConfigs[j].PBus =3D HrConfigs[j].DevId.Bus;
+ HrConfigs[j].Res.Cls =3D DEF_CACHE_LINE_SIZE;
+ }
+ break;
+ }
+}//InitARHRConfigs
+
+
+STATIC
+VOID
+InitCommonHRConfigs (
+ IN HR_CONFIG *Hr_Config,
+ IN UINT8 BusNumLimit,
+ IN OUT BRDG_RES_CONFIG *HrResConf
+ )
+{
+ UINT8 i;
+
+ UINT8 j;
+ for(i =3D 0; i < count(HrConfigs); ++i) {
+ HrConfigs[i].IsDSBridge =3D TRUE;
+ }
+ //
+ // US(HRBus:0:0)
+ //
+ HrConfigs[HR_US_PORT].DevId.Bus =3D Hr_Config->HRBus;
+ HrConfigs[HR_US_PORT].DevId.Dev =3D 0;
+ HrConfigs[HR_US_PORT].DevId.Fun =3D 0;
+ HrConfigs[HR_US_PORT].Res =3D *HrResConf;
+ HrConfigs[HR_US_PORT].Res.IoBase =3D 0xF1;
+ HrConfigs[HR_US_PORT].Res.IoLimit =3D 0x01;
+ HrConfigs[HR_US_PORT].PBus =3D HrConfigs[HR_US_PORT].DevId.Bus;
+ HrConfigs[HR_US_PORT].SBus =3D HrConfigs[HR_US_PORT].PBus + 1;
+ HrConfigs[HR_US_PORT].SubBus =3D BusNumLimit;
+ HrConfigs[HR_US_PORT].IsDSBridge =3D FALSE;
+
+ //
+ // HIA resides here
+ //
+ HrConfigs[HR_DS_PORT0].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus =
+ 1;
+ HrConfigs[HR_DS_PORT0].DevId.Dev =3D 0;
+ HrConfigs[HR_DS_PORT0].DevId.Fun =3D 0;
+ HrConfigs[HR_DS_PORT0].Res =3D NOT_IN_USE_BRIDGE;
+ HrConfigs[HR_DS_PORT0].Res.MemBase =3D HrResConf->MemLimit;
+ HrConfigs[HR_DS_PORT0].Res.MemLimit =3D HrResConf->MemLimit;
+ HrResConf->MemLimit -=3D 0x10; //This 1 MB chunk will be =
used by HIA
+ HrConfigs[HR_DS_PORT0].Res.Cmd =3D CMD_BM_MEM;
+ HrConfigs[HR_DS_PORT0].Res.Cls =3D DEF_CACHE_LINE_SIZE;
+ HrConfigs[HR_DS_PORT0].PBus =3D HrConfigs[HR_DS_PORT0].DevId.Bus;
+ HrConfigs[HR_DS_PORT0].SBus =3D HrConfigs[HR_DS_PORT0].PBus + 1;
+ HrConfigs[HR_DS_PORT0].SubBus =3D HrConfigs[HR_DS_PORT0].PBus + 1;
+
+ switch (Hr_Config->DeviceId) {
+ //
+ // Alpine Ridge
+ //
+ case AR_HR_2C:
+ case AR_HR_C0_2C:
+ case AR_HR_LP:
+ case AR_HR_4C:
+ case AR_HR_C0_4C:
+ //
+ // Titan Ridge
+ //
+ case TR_HR_2C:
+ case TR_HR_4C:
+ InitARHRConfigs(Hr_Config, BusNumLimit, HrResConf);
+ break;
+
+ default:
+ //
+ // DS(HRBus+2:3-6:0)
+ //
+ Hr_Config->MinDSNumber =3D 3;
+ Hr_Config->MaxDSNumber =3D 6;
+ Hr_Config->BridgeLoops =3D count (HrConfigs);
+
+ for (j =3D 2, i =3D Hr_Config->MinDSNumber; j < count (HrConfigs) && i=
<=3D Hr_Config->MaxDSNumber; ++j, ++i) {
+ HrConfigs[j].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[j].DevId.Dev =3D i;
+ HrConfigs[j].DevId.Fun =3D 0;
+ HrConfigs[j].PBus =3D HrConfigs[j].DevId.Bus;
+ HrConfigs[j].Res.Cls =3D DEF_CACHE_LINE_SIZE;
+ }
+ }
+} // InitCommonHRConfigs
+
+STATIC
+VOID
+InitHRDSPort_Disable (
+ IN UINT8 id,
+ IN OUT BRDG_CONFIG *BrdgConf
+ )
+{
+ HrConfigs[id].Res =3D NOT_IN_USE_BRIDGE;
+ HrConfigs[id].SBus =3D BrdgConf->SBus;
+ HrConfigs[id].SubBus =3D BrdgConf->SBus;
+
+ BrdgConf->SBus++;
+} // InitHRDSPort_Disable
+
+//AR only
+
+STATIC
+VOID
+InitARDSPort_1Port(
+ IN OUT BRDG_CONFIG* BrdgConf
+)
+{
+ UINT16 MemBase =3D BrdgConf->Res.MemBase & 0xFFF0;
+ UINT64 PMemBase64 =3D BrdgConf->Res.PMemBase64 & ~0xFULL;
+ UINT8 BusRange =3D BrdgConf->SubBus - BrdgConf->PBus - 2;
+
+ HrConfigs[AR_DS_PORT1].Res =3D NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT1].Res.Cls =3D DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT1].Res.Cmd =3D CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT1].Res.MemBase =3D MemBase;
+ HrConfigs[AR_DS_PORT1].Res.MemLimit =3D BrdgConf->Res.MemLimit - 1;
+ HrConfigs[AR_DS_PORT1].Res.PMemBase64 =3D PMemBase64;
+ HrConfigs[AR_DS_PORT1].Res.PMemLimit64 =3D BrdgConf->Res.PMemLimit64;
+ HrConfigs[AR_DS_PORT1].SBus =3D BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT1].SubBus =3D BrdgConf->SBus + BusRange;
+
+ BrdgConf->SBus =3D HrConfigs[AR_DS_PORT1].SubBus + 1;
+
+ HrConfigs[AR_DS_PORT2].Res =3D NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT2].Res.Cls =3D DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT2].Res.Cmd =3D CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT2].Res.MemBase =3D BrdgConf->Res.MemLimit;
+ HrConfigs[AR_DS_PORT2].Res.MemLimit =3D BrdgConf->Res.MemLimit;
+ HrConfigs[AR_DS_PORT2].SBus =3D BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT2].SubBus =3D BrdgConf->SBus;
+
+ BrdgConf->SBus =3D HrConfigs[AR_DS_PORT2].SubBus + 1;
+}//InitARDSPort_1Port
+
+STATIC
+VOID
+InitARDSPort_2Port(
+ IN OUT BRDG_CONFIG* BrdgConf
+)
+{
+ UINT16 MemBase =3D BrdgConf->Res.MemBase & 0xFFF0;
+ UINT64 PMemBase64 =3D BrdgConf->Res.PMemBase64 & ~0xFULL;
+ UINT8 BusRange =3D BrdgConf->SubBus - BrdgConf->PBus - 3;
+
+ // Busses are split between ports 1 and 4
+ BusRange /=3D 2;
+
+ HrConfigs[AR_DS_PORT1].Res =3D NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT1].Res.Cls =3D DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT1].Res.Cmd =3D CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT1].Res.MemBase =3D MemBase;
+ HrConfigs[AR_DS_PORT1].Res.MemLimit =3D MemBase + 0x17F0 - 1;
+ HrConfigs[AR_DS_PORT1].Res.PMemBase64 =3D PMemBase64;
+ HrConfigs[AR_DS_PORT1].Res.PMemLimit64 =3D PMemBase64 + 0x2000 - 1;
+ HrConfigs[AR_DS_PORT1].SBus =3D BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT1].SubBus =3D BrdgConf->SBus + BusRange;
+
+ BrdgConf->SBus =3D HrConfigs[AR_DS_PORT1].SubBus + 1;
+
+ HrConfigs[AR_DS_PORT2].Res =3D NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT2].Res.Cls =3D DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT2].Res.Cmd =3D CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT2].Res.MemBase =3D MemBase + 0x17F0;
+ HrConfigs[AR_DS_PORT2].Res.MemLimit =3D MemBase + 0x1800 - 1;
+ HrConfigs[AR_DS_PORT2].SBus =3D BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT2].SubBus =3D BrdgConf->SBus;
+
+ BrdgConf->SBus =3D HrConfigs[AR_DS_PORT2].SubBus + 1;
+
+
+ HrConfigs[AR_DS_PORT4].Res =3D NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT4].Res.Cls =3D DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT4].Res.Cmd =3D CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT4].Res.MemBase =3D MemBase + 0x1800;
+ HrConfigs[AR_DS_PORT4].Res.MemLimit =3D BrdgConf->Res.MemLimit;
+ HrConfigs[AR_DS_PORT4].Res.PMemBase64 =3D PMemBase64 + 0x2000;
+ HrConfigs[AR_DS_PORT4].Res.PMemLimit64 =3D BrdgConf->Res.PMemLimit64;
+ HrConfigs[AR_DS_PORT4].SBus =3D BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT4].SubBus =3D BrdgConf->SubBus;
+
+ BrdgConf->SBus =3D HrConfigs[AR_DS_PORT4].SubBus + 1;
+}//InitARDSPort_2Port
+
+
+STATIC
+BOOLEAN
+CheckLimits (
+ IN BOOLEAN Is2PortDev,
+ IN BRDG_RES_CONFIG *HrResConf,
+ IN UINT8 BusRange
+ )
+{
+ UINT16 MemBase;
+ UINT16 MemLimit;
+ UINT64 PMemBase64;
+ UINT64 PMemLimit64;
+
+ MemBase =3D HrResConf->MemBase & 0xFFF0;
+ MemLimit =3D HrResConf->MemLimit & 0xFFF0;
+ PMemBase64 =3D HrResConf->PMemBase64 & 0xFFF0;
+ PMemLimit64 =3D HrResConf->PMemLimit64 & 0xFFF0;
+ //
+ // Check memoty alignment
+ //
+ if (MemBase & 0x3FF) {
+ DEBUG((DEBUG_INFO, "M alig\n"));
+ return FALSE;
+ }
+
+ if (PMemBase64 & 0xFFF) {
+ DEBUG((DEBUG_INFO, "PM alig\n"));
+ return FALSE;
+ }
+
+ if (Is2PortDev) {
+ //
+ // Check mem size
+ //
+ if (MemLimit + 0x10 - MemBase < 0x2E00) {
+ DEBUG((DEBUG_INFO, "M size\n"));
+ return FALSE;
+ }
+ //
+ // Check P-mem size
+ //
+ if (PMemLimit64 + 0x10 - PMemBase64 < 0x4A00) {
+ DEBUG((DEBUG_INFO, "PM size\n"));
+ return FALSE;
+ }
+ //
+ // Check bus range
+ //
+ if (BusRange < 106) {
+ DEBUG((DEBUG_INFO, "Bus range\n"));
+ return FALSE;
+ }
+ } else {
+ //
+ // Check mem size
+ //
+ if (MemLimit + 0x10 - MemBase < 0x1600) {
+ DEBUG((DEBUG_INFO, "M size\n"));
+ return FALSE;
+ }
+ //
+ // Check P-mem size
+ //
+ if (PMemLimit64 + 0x10 - PMemBase64 < 0x2200) {
+ DEBUG((DEBUG_INFO, "PM size\n"));
+ return FALSE;
+ }
+ //
+ // Check bus range
+ //
+ if (BusRange < 56) {
+ DEBUG((DEBUG_INFO, "Bus range\n"));
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+} // CheckLimits
+
+STATIC
+BOOLEAN
+InitHRResConfigs (
+ IN OUT HR_CONFIG *Hr_Config,
+ IN UINT8 BusNumLimit,
+ IN OUT BRDG_RES_CONFIG*HrResConf
+ )
+{
+ BRDG_CONFIG BrdgConf =3D { { 0 } };
+
+ InitCommonHRConfigs (Hr_Config, BusNumLimit, HrResConf);
+ BrdgConf.PBus =3D Hr_Config->HRBus + 2;// Take into account busses
+ BrdgConf.SBus =3D Hr_Config->HRBus + 3;// for US and DS of HIA
+ BrdgConf.SubBus =3D BusNumLimit;
+ BrdgConf.Res =3D *HrResConf;
+ while (TRUE) {
+ switch (Hr_Config->DeviceId) {
+ case AR_HR_4C:
+ case TR_HR_4C:
+ case AR_HR_C0_4C:
+ //
+ // 2 Port host
+ //
+ if (CheckLimits (TRUE, HrResConf, BusNumLimit - Hr_Config->HRBus)) {
+
+
+ InitARDSPort_2Port(&BrdgConf);
+ DEBUG((DEBUG_INFO, "AR2\n"));
+
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+ // AR only
+ case AR_HR_2C: // 1 port host
+ case AR_HR_C0_2C:
+ case AR_HR_LP:
+ case TR_HR_2C:
+ DEBUG((DEBUG_INFO, "AR1\n"));
+ InitARDSPort_1Port(&BrdgConf);
+ return TRUE;
+
+ default:
+ InitHRDSPort_Disable (HR_DS_PORT3, &BrdgConf);
+ InitHRDSPort_Disable (HR_DS_PORT4, &BrdgConf);
+ InitHRDSPort_Disable (HR_DS_PORT5, &BrdgConf);
+ InitHRDSPort_Disable (HR_DS_PORT6, &BrdgConf);
+ return FALSE;
+ }
+ }
+} // InitHRResConfigs
+
+STATIC
+BOOLEAN
+InitializeHostRouter (
+ OUT HR_CONFIG *Hr_Config,
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 BusNumLimit;
+ BRDG_RES_CONFIG HrResConf =3D { 0 };
+ UINT8 i;
+ BOOLEAN Ret;
+
+ Ret =3D TRUE;
+
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDe=
vice, RpFunction, 0);
+ Hr_Config->HRBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE=
_SECONDARY_BUS_REGISTER_OFFSET);
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, Hr_Config->=
HRBus, 0x00, 0x00, 0);
+ Hr_Config->DeviceId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVIC=
E_ID_OFFSET);
+ if (!(IsTbtHostRouter (Hr_Config->DeviceId))) {
+ return FALSE;
+ }
+ TbtSegment =3D (UINT8)RpSegment;
+
+ HrResConf.Cmd =3D CMD_BM_MEM;
+ HrResConf.Cls =3D DEF_CACHE_LINE_SIZE;
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, R=
pDevice, RpFunction, 0);
+ HrResConf.IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET_=
OF (PCI_TYPE01, Bridge.IoBase));
+ HrResConf.IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET_=
OF (PCI_TYPE01, Bridge.IoLimit));
+ HrResConf.MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET=
_OF (PCI_TYPE01, Bridge.MemoryBase));
+ HrResConf.MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET=
_OF (PCI_TYPE01, Bridge.MemoryLimit));
+ HrResConf.PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET=
_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase));
+ HrResConf.PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET=
_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit));
+ HrResConf.PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddress=
+ OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16;
+ HrResConf.PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddress=
+ OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16;
+ BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDI=
NATE_BUS_REGISTER_OFFSET);
+
+ Ret =3D InitHRResConfigs (Hr_Config, BusNumLimit, &HrResConf);
+
+ for (i =3D 0; i < Hr_Config->BridgeLoops; ++i) {
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ Bus =3D HrConfigs[i].DevId.Bus;
+ Dev =3D HrConfigs[i].DevId.Dev;
+ Fun =3D HrConfigs[i].DevId.Fun;
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, F=
un, 0);
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, HrCo=
nfigs[i].Res.Cls);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER=
_OFFSET, HrConfigs[i].PBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST=
ER_OFFSET, HrConfigs[i].SBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI=
STER_OFFSET, HrConfigs[i].SubBus);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryBase), HrConfigs[i].Res.MemBase);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryLimit), HrConfigs[i].Res.MemLimit);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryBase), (UINT16) (HrConfigs[i].Res.PMemBase64 & 0xFFFF));
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryLimit), (UINT16) (HrConfigs[i].Res.PMemLimit64 & 0xFFFF));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableBaseUpper32), (UINT32) (HrConfigs[i].Res.PMemBase64 >> 16));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableLimitUpper32), (UINT32) (HrConfigs[i].Res.PMemLimit64 >> 16));
+ PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I=
oBase), HrConfigs[i].Res.IoBase);
+ PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I=
oLimit), HrConfigs[i].Res.IoLimit);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
IoBaseUpper16), 0x00000000);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, HrConfigs[i=
].Res.Cmd);
+ }
+ if (Hr_Config->DeviceId =3D=3D AR_HR_2C || Hr_Config->DeviceId =3D=3D AR=
_HR_4C || Hr_Config->DeviceId =3D=3D AR_HR_LP) {
+ for (i =3D 0; i < Hr_Config->BridgeLoops; ++i) {
+ if(HrConfigs[i].IsDSBridge) {
+ UnsetVesc(HrConfigs[i].DevId.Bus, HrConfigs[i].DevId.Dev, HrConfig=
s[i].DevId.Fun);
+ }
+ }
+ }
+
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,(Hr_Config->H=
RBus + 2), 0x00, 0x00, 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PC=
I_BAR_IDX0 * 4), HrConfigs[HR_DS_PORT0].Res.MemLimit << 16);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PC=
I_BAR_IDX1 * 4), (HrConfigs[HR_DS_PORT0].Res.MemLimit + 0x4) << 16);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA=
CHE_LINE_SIZE);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BM_MEM);
+ return Ret;
+} // InitializeHostRouter
+STATIC
+UINT8
+ConfigureSlot (
+ IN UINT8 Bus,
+ IN UINT8 MAX_DEVICE,
+ IN INT8 Depth,
+ IN BOOLEAN ArPcie,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Device;
+ UINT8 SBus;
+ UINT8 UsedBusNumbers;
+ UINT8 RetBusNum;
+ PORT_INFO CurrentSlot;
+
+ RetBusNum =3D 0;
+
+ for (Device =3D 0; Device < MAX_DEVICE; Device++) {
+ //
+ // Continue if device is absent
+ //
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Devic=
e, 0x00, 0);
+ if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID=
_OFFSET)) {
+ continue;
+
+ }
+
+ if (P2P_BRIDGE !=3D PciSegmentRead16 (gDeviceBaseAddress + (PCI_CLASSC=
ODE_OFFSET + 1))) {
+ SetDevResources (
+ Bus,
+ Device,
+ PCI_MAX_FUNC,
+ PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX5 * 4),
+ PortInfo
+ );
+ continue;
+ }
+ //
+ // Else Bridge
+ //
+ CopyMem (&CurrentSlot, PortInfo, sizeof (PORT_INFO));
+
+ ++RetBusNum; // UP Bridge
+ SBus =3D Bus + RetBusNum; // DS Bridge
+
+ if (SBus + 1 >=3D PortInfo->BusNumLimit) {
+ continue;
+
+ }
+
+ SetDevResources (Bus, Device, 1, PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR=
_IDX1 * 4), PortInfo);
+
+ //
+ // Init UP Bridge to reach DS Bridge
+ //
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER=
_OFFSET, Bus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST=
ER_OFFSET, SBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI=
STER_OFFSET, PortInfo->BusNumLimit);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BM_MEM);
+
+ if(ArPcie) {
+ UnsetVesc(Bus, Device, 0x00);
+ }
+
+ UsedBusNumbers =3D ConfigureSlot(SBus, PCI_MAX_DEVICE + 1, -1, FALSE, Po=
rtInfo);
+ RetBusNum +=3D UsedBusNumbers;
+
+ SetPhyPortResources (
+ Bus,
+ Device,
+ SBus + UsedBusNumbers,
+ Depth,
+ &CurrentSlot,
+ PortInfo
+ );
+ }
+ //
+ // for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++)
+ //
+ return RetBusNum;
+} // ConfigureSlot
+
+STATIC
+VOID
+SetCioPortResources (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 SBus,
+ IN UINT8 SubBus,
+ IN PORT_INFO *portInfoBeforeChange,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Cmd;
+ Cmd =3D CMD_BUS_MASTER;
+
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, 0x0=
0, 0);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_O=
FFSET, Bus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER=
_OFFSET, SBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIST=
ER_OFFSET, SubBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+
+ if (PortInfo->IoBase <=3D PortInfo->IoLimit) {
+ PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I=
oBase), PortInfo->IoBase);
+ PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I=
oLimit), PortInfo->IoLimit);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
IoBaseUpper16), 0x00000000);
+ Cmd |=3D CMD_BM_IO;
+ } else {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
IoBase), DISBL_IO_REG1C);
+ }
+
+ if (PortInfo->MemBase <=3D PortInfo->MemLimit) {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryBase), PortInfo->MemBase);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryLimit), PortInfo->MemLimit);
+ Cmd |=3D CMD_BM_MEM;
+ } else {
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryBase), DISBL_MEM32_REG20);
+ }
+
+ if (PortInfo->PMemBase64 <=3D PortInfo->PMemLimit64) {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryBase), (UINT16) (PortInfo->PMemBase64 & 0xFFFF));
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryLimit), (UINT16) (PortInfo->PMemLimit64 & 0xFFFF));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableBaseUpper32), (UINT32) (PortInfo->PMemBase64 >> 16));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableLimitUpper32), (UINT32) (PortInfo->PMemLimit64 >> 16));
+ Cmd |=3D CMD_BM_MEM;
+ } else {
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryBase), DISBL_PMEM_REG24);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableBaseUpper32), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableLimitUpper32), 0);
+ }
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA=
CHE_LINE_SIZE);
+} // SetCioPortResources
+
+STATIC
+VOID
+SetSlotsAsUnused (
+ IN UINT8 Bus,
+ IN UINT8 MaxSlotNum,
+ IN UINT8 CioSlot,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Slot;
+ for (Slot =3D MaxSlotNum; Slot > CioSlot; --Slot) {
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Slot, =
0x00, 0);
+ if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID=
_OFFSET)) {
+ continue;
+ }
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_=
CACHE_LINE_SIZE);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER=
_OFFSET, Bus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST=
ER_OFFSET, PortInfo->BusNumLimit);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI=
STER_OFFSET, PortInfo->BusNumLimit);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
IoBase), DISBL_IO_REG1C);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
MemoryBase), DISBL_MEM32_REG20);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.=
PrefetchableMemoryBase), DISBL_PMEM_REG24);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BUS_MAS=
TER);
+ PortInfo->BusNumLimit--;
+ }
+} // SetSlotsAsUnused
+
+STATIC
+UINT16
+FindVendorSpecificHeader(
+ IN UINT8 Bus
+)
+{
+ PCI_EXP_EXT_HDR *ExtHdr;
+ UINT32 ExtHdrValue;
+ UINT16 ExtendedRegister;
+
+ ExtHdr =3D (PCI_EXP_EXT_HDR*) &ExtHdrValue;
+ ExtendedRegister =3D 0x100;
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x=
00, 0);
+ while (ExtendedRegister) {
+ ExtHdrValue =3D PciSegmentRead32 (gDeviceBaseAddress + ExtendedRegiste=
r);
+ if (ExtHdr->CapabilityId =3D=3D 0xFFFF) {
+ return 0x0000; // No Vendor-Specific Extended Capability header
+ }
+
+ if (PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID =3D=3D ExtHdr->=
CapabilityId) {
+ return ExtendedRegister;
+ }
+
+ ExtendedRegister =3D (UINT16) ExtHdr->NextCapabilityOffset;
+ }
+ return 0x0000; // No Vendor-Specific Extended Capability header
+}
+
+STATIC
+UINT8
+FindSsid_SsvidHeader (
+ IN UINT8 Bus
+ )
+{
+ UINT8 CapHeaderId;
+ UINT8 CapHeaderOffset;
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x=
00, 0);
+ CapHeaderOffset =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_CAPBILIT=
Y_POINTER_OFFSET);
+
+ while (CapHeaderOffset !=3D 0) {
+ CapHeaderId =3D PciSegmentRead8 (gDeviceBaseAddress + CapHeaderOffset);
+
+ if (CapHeaderId =3D=3D PCIE_CAP_ID_SSID_SSVID) {
+ return CapHeaderOffset;
+ }
+
+ CapHeaderOffset =3D PciSegmentRead8 (gDeviceBaseAddress + CapHeaderOff=
set + 1);
+ }
+
+ DEBUG((DEBUG_INFO, "SID0\n"));
+ return 0;
+} // FindSsid_SsvidHeader
+
+STATIC
+BOOLEAN
+GetCioSlotByDevId (
+ IN UINT8 Bus,
+ OUT UINT8 *CioSlot,
+ OUT UINT8 *MaxSlotNum,
+ OUT BOOLEAN *ArPcie
+ )
+{
+ UINT16 VSECRegister;
+ BRDG_CIO_MAP_REG BridgMap;
+ UINT32 BitScanRes;
+ UINT16 DevId;
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, 0x00, 0=
x00, 0);
+ DevId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_=
ID_OFFSET);
+
+ //
+ // Init out params in case device is not recognised
+ //
+ *CioSlot =3D 4;
+ *MaxSlotNum =3D 7;
+ *ArPcie =3D FALSE;
+
+ switch (DevId) {
+ //
+ // For known device IDs
+ //
+ case 0x1578:
+ *ArPcie =3D TRUE;
+ }
+
+ switch (DevId) {
+ //
+ // For known device IDs
+ //
+ case 0x1513:
+ case 0x151A:
+ case 0x151B:
+ case 0x1547:
+ case 0x1548:
+ return TRUE; // Just return
+ case 0x1549:
+ return FALSE; // Just return
+ }
+
+ VSECRegister =3D FindVendorSpecificHeader(Bus);
+ if (!VSECRegister) {
+ return TRUE; // Just return
+ }
+ //
+ // Go to Bridge/CIO map register
+ //
+ VSECRegister +=3D 0x18;
+ BridgMap.AB_REG =3D PciSegmentRead32(gDeviceBaseAddress + VSECRegister);
+ //
+ // Check for range
+ //
+ if (BridgMap.Bits.NumOfDSPorts < 1 || BridgMap.Bits.NumOfDSPorts > 27) {
+ return TRUE;
+ //
+ // Not a valid register
+ //
+ }
+ //
+ // Set OUT params
+ //
+ *MaxSlotNum =3D (UINT8) BridgMap.Bits.NumOfDSPorts;
+
+#ifdef _MSC_VER
+ if(!_BitScanForward(&BitScanRes, BridgMap.Bits.CioPortMap)) { // No DS b=
ridge which is CIO port
+ return FALSE;
+ }
+#else
+#ifdef __GNUC__
+ if (BridgMap.Bits.CioPortMap =3D=3D 0) {
+ return FALSE;
+ }
+ BitScanRes =3D __builtin_ctz (BridgMap.Bits.CioPortMap);
+#else
+#error Unsupported Compiler
+#endif
+#endif
+
+ *CioSlot =3D (UINT8)BitScanRes;
+ return TRUE;
+} // GetCioSlotByDevId
+
+#define TBT_LEGACY_SUB_SYS_ID 0x11112222
+
+STATIC
+BOOLEAN
+IsLegacyDevice (
+ IN UINT8 Bus
+ )
+{
+ UINT32 Sid;
+ UINT8 SidRegister;
+ UINT16 DevId;
+
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x=
00, 0);
+ DevId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_=
ID_OFFSET);
+ switch (DevId) {
+ //
+ // For known device IDs
+ //
+ case 0x1513:
+ case 0x151A:
+ case 0x151B:
+ DEBUG((DEBUG_INFO, "Legacy "));
+ DEBUG((DEBUG_INFO, "DevId =3D %d\n",DevId));
+ return TRUE;
+ //
+ // Legacy device by Device Id
+ //
+ }
+
+ SidRegister =3D FindSsid_SsvidHeader(Bus);
+
+ if (!SidRegister) {
+ return TRUE; // May be absent for legacy devices
+ }
+ //
+ // Go to register
+ //
+ SidRegister +=3D 0x4;
+ Sid =3D PciSegmentRead32(gDeviceBaseAddress + SidRegister);
+ DEBUG((DEBUG_INFO, "SID"));
+ DEBUG((DEBUG_INFO, " =3D %d\n", Sid));
+
+return TBT_LEGACY_SUB_SYS_ID =3D=3D Sid || 0 =3D=3D Sid;
+} // IsLegacyDevice
+
+STATIC
+VOID
+UnsetVescEp(
+ IN UINT8 Bus,
+ IN UINT8 MaxSlotNum
+ )
+{
+ UINT8 i;
+
+ for (i =3D 0; i <=3D MaxSlotNum; ++i)
+ {
+ UnsetVesc(Bus, i, 0);
+ }
+}// Unset_VESC_REG2_EP
+
+STATIC
+BOOLEAN
+ConfigureEP (
+ IN INT8 Depth,
+ IN OUT UINT8 *Bus,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 SBus;
+ UINT8 CioSlot;
+ UINT8 MaxSlotNum;
+ BOOLEAN ArPcie;
+ UINT8 MaxPHYSlots;
+ UINT8 UsedBusNumbers;
+ UINT8 cmd;
+ BOOLEAN CioSlotPresent;
+ BOOLEAN Continue;
+ PORT_INFO PortInfoOrg;
+ UINT8 CioBus;
+
+ CioSlot =3D 4;
+ MaxSlotNum =3D 7;
+ CopyMem (&PortInfoOrg, PortInfo, sizeof (PORT_INFO));
+
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, *Bus, 0x00, =
0x00, 0);
+ cmd =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_COMMAND_=
OFFSET);
+ // AR ONLY
+ // Endpoint on CIO slot, but not a bridge device
+ if (P2P_BRIDGE !=3D PciSegmentRead16 (gDeviceBaseAddress + (PCI_CLASSCOD=
E_OFFSET + 1))) {
+ DEBUG((DEBUG_INFO, "UEP\n"));
+ // Check whether EP already configured by examining CMD register
+ if(cmd & CMD_BUS_MASTER) // Yes, no need to touch this EP
+ {
+ DEBUG((DEBUG_INFO, "BMF\n"));
+ return FALSE;
+ }
+ // Configure it as regular PCIe device
+ ConfigureSlot(*Bus, PCI_MAX_DEVICE + 1, -1, FALSE, PortInfo);
+
+ return FALSE;
+ }
+
+ //
+ // Based on Device ID assign Cio slot and max number of PHY slots to scan
+ //
+ CioSlotPresent =3D GetCioSlotByDevId(*Bus, &CioSlot, &MaxSlotNum, &ArP=
cie);
+ MaxPHYSlots =3D MaxSlotNum;
+ //
+ // Check whether EP already configured by examining CMD register
+ //
+
+ if (cmd & CMD_BUS_MASTER) {
+ //
+ // Yes no need to touch this EP, just move to next one in chain
+ //
+ CioBus =3D *Bus + 1;
+ if(ArPcie){
+ UnsetVescEp(CioBus, MaxSlotNum);
+ }
+ if (!CioSlotPresent) {
+ //
+ // Cio slot is not present in EP, just return FALSE
+ //
+ DEBUG((DEBUG_INFO, "BMF\n"));
+ return FALSE;
+ }
+ //
+ // Take all resources from Cio slot and return
+ //
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,CioBus, Cio=
Slot, 0x00, 0);
+ PortInfo->BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_=
BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
+ PortInfo->IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFS=
ET_OF (PCI_TYPE01, Bridge.IoBase));
+ PortInfo->IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFS=
ET_OF (PCI_TYPE01, Bridge.IoLimit));
+ PortInfo->MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFF=
SET_OF (PCI_TYPE01, Bridge.MemoryBase));
+ PortInfo->MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFF=
SET_OF (PCI_TYPE01, Bridge.MemoryLimit));
+ PortInfo->PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFF=
SET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0;
+ PortInfo->PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFF=
SET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0;
+ PortInfo->PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddr=
ess + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16;
+ PortInfo->PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddr=
ess + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16;
+ PortInfo->PMemLimit64 |=3D 0xF;
+ //
+ // Jump to next EP
+ //
+ *Bus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BU=
S_REGISTER_OFFSET);
+ //
+ // Should we continue?
+ //
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus, 0x00,=
0x00, 0);
+ Continue =3D 0xFFFF !=3D PciSegmentRead16 (gDeviceBaseAddress=
+ PCI_DEVICE_ID_OFFSET);
+ return Continue;
+ }
+ //
+ // Set is legacy dvice
+ //
+ isLegacyDevice =3D IsLegacyDevice (*Bus);
+
+ SetCioPortResources (
+ *Bus,
+ 0, // Assign all available resources to US port of EP
+ *Bus + 1,
+ PortInfo->BusNumLimit,
+ 0,
+ PortInfo
+ );
+
+ SBus =3D *Bus + 1;// Jump to DS port
+
+ if (CioSlotPresent) {
+ MaxPHYSlots =3D CioSlot;
+ }
+
+ UsedBusNumbers =3D ConfigureSlot(SBus, MaxPHYSlots, Depth, ArPcie, PortI=
nfo);
+ if (!CioSlotPresent) {
+ return FALSE;
+ //
+ // Stop resource assignment on this chain
+ //
+ }
+ //
+ // Set rest of slots us unused
+ //
+ SetSlotsAsUnused (SBus, MaxSlotNum, CioSlot, PortInfo);
+
+ SetCioPortResources (
+ SBus,
+ CioSlot,
+ SBus + UsedBusNumbers + 1,
+ PortInfo->BusNumLimit,
+ &PortInfoOrg,
+ PortInfo
+ );
+ *Bus =3D SBus + UsedBusNumbers + 1;// Go to next EP
+ if(ArPcie) {
+ UnsetVesc(SBus, CioSlot, 0x00);
+ }
+ if (*Bus > PortInfo->BusNumLimit - 2) {
+ //
+ // In case of bus numbers are exhausted stop enumeration
+ //
+ return FALSE;
+ }
+ //
+ // Check whether we should continue on this chain
+ //
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus, 0x00, 0=
x00, 0);
+ Continue =3D 0xFFFF !=3D PciSegmentRead16 (gDeviceBaseAddress +=
PCI_DEVICE_ID_OFFSET);
+ return Continue;
+} // ConfigureEP
+
+STATIC
+VOID
+GetPortResources (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun=
, 0);
+ PortInfo->BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BR=
IDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
+ PortInfo->IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET=
_OF (PCI_TYPE01, Bridge.IoBase)) & 0xF0;
+ PortInfo->IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET=
_OF (PCI_TYPE01, Bridge.IoLimit)) & 0xF0;
+ PortInfo->MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE=
T_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xFFF0;
+ PortInfo->MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE=
T_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xFFF0;
+ PortInfo->PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE=
T_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0;
+ PortInfo->PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE=
T_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0;
+ PortInfo->PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddres=
s + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16;
+ PortInfo->PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddres=
s + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16;
+ PortInfo->IoLimit |=3D 0xF;
+ PortInfo->MemLimit |=3D 0xF;
+ PortInfo->PMemLimit64 |=3D 0xF;
+} // GetPortResources
+
+STATIC
+VOID
+ConfigurePort (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ INT8 i;
+ UINT8 USBusNum;
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun=
, 0);
+ USBusNum =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_S=
ECONDARY_BUS_REGISTER_OFFSET);
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, USBusNum, 0x=
00, 0x00, 0);
+ if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_O=
FFSET)) {
+ //
+ // Nothing to do if TBT device is not connected
+ //
+ return ;
+ }
+
+ GetPortResources(Bus, Dev, Fun, PortInfo);// Take reserved resources fro=
m DS port
+ //
+ // Assign resources to EPs
+ //
+ for (i =3D 0; i < MAX_TBT_DEPTH; ++i) {
+ PortInfo->ConfedEP++;
+ if (!ConfigureEP (i, &USBusNum, PortInfo)) {
+ return ;
+ }
+ }
+} // ConfigurePort
+
+VOID
+ThunderboltCallback (
+ IN UINT8 Type
+ )
+{
+ PORT_INFO PortInfoOrg =3D { 0 };
+ HR_CONFIG HrConfig =3D { 0 };
+ UINT8 i;
+ UINTN Segment =3D 0;
+ UINTN Bus =3D 0;
+ UINTN Device;
+ UINTN Function;
+
+ DEBUG((DEBUG_INFO, "ThunderboltCallback.Entry\n"));
+
+ DEBUG((DEBUG_INFO, "PortInfo Initialization\n"));
+ PortInfoInit (&PortInfoOrg);
+ if(Type =3D=3D DTBT_CONTROLLER) {
+ if (gCurrentDiscreteTbtRootPort =3D=3D 0) {
+ DEBUG((DEBUG_ERROR, "Invalid RP Input\n"));
+ return;
+ }
+ GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType, gCurrentDiscreteTbtRo=
otPort - 1, &Device, &Function);
+ DEBUG((DEBUG_INFO, "InitializeHostRouter. \n"));
+ if (!InitializeHostRouter (&HrConfig, Segment, Bus, Device, Function))=
{
+ return ;
+ }
+ //
+ // Configure DS ports
+ //
+ for (i =3D HrConfig.MinDSNumber; i <=3D HrConfig.MaxDSNumber; ++i) {
+ DEBUG((DEBUG_INFO, "ConfigurePort. \n"));
+ ConfigurePort (HrConfig.HRBus + 1, i,0, &PortInfoOrg);
+ }
+
+ DEBUG((DEBUG_INFO, "EndOfThunderboltCallback.\n"));
+ EndOfThunderboltCallback (Segment, Bus, Device, Function);
+
+ }
+ DEBUG((DEBUG_INFO, "ThunderboltCallback.Exit\n"));
+} // ThunderboltCallback
+
+VOID
+DisablePCIDevicesAndBridges (
+ IN UINT8 MinBus,
+ IN UINT8 MaxBus
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 RegVal;
+ //
+ // Disable PCI device First, and then Disable PCI Bridge
+ //
+ for (Bus =3D MaxBus; Bus > MinBus; --Bus) {
+ for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) {
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, De=
v, Fun, 0);
+ if (INVALID_PCI_DEVICE =3D=3D PciSegmentRead32 (gDeviceBaseAddress=
+ PCI_VENDOR_ID_OFFSET)) {
+ if (Fun =3D=3D 0) {
+ break;
+
+ }
+
+ continue;
+ }
+
+ RegVal =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_HEADER_TYPE_O=
FFSET);
+ if (HEADER_TYPE_DEVICE =3D=3D (RegVal & 1)) {
+ //
+ // ******** Disable PCI Device ********
+ // BIT0 I/O Space Enabled BIT1 Memory Space Enabled
+ // BIT2 Bus Master Enabled BIT4 Memory Write and Invalidatio=
n Enable
+ //
+ PciSegmentAnd8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, (UINT8)=
~(BIT0 | BIT1 | BIT2 | BIT4));
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS=
ET + (PCI_BAR_IDX0 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS=
ET + (PCI_BAR_IDX1 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS=
ET + (PCI_BAR_IDX2 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS=
ET + (PCI_BAR_IDX3 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS=
ET + (PCI_BAR_IDX4 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS=
ET + (PCI_BAR_IDX5 * 4), 0);
+ }
+ }
+ }
+ }
+ //
+ // now no more PCI dev on another side of PCI Bridge can safty disable P=
CI Bridge
+ //
+ for (Bus =3D MaxBus; Bus > MinBus; --Bus) {
+ for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) {
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, De=
v, Fun, 0);
+ if (INVALID_PCI_DEVICE =3D=3D PciSegmentRead32 (gDeviceBaseAddress=
+ PCI_VENDOR_ID_OFFSET)) {
+ if (Fun =3D=3D 0) {
+ break;
+ }
+
+ continue;
+ }
+
+ RegVal =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_HEADER_TYPE_O=
FFSET);
+ if (HEADER_TYPE_PCI_TO_PCI_BRIDGE =3D=3D (RegVal & BIT0)) {
+ PciSegmentAnd8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, (UINT8)=
~(BIT0 | BIT1 | BIT2 | BIT4));
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_RE=
GISTER_OFFSET, 0);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BU=
S_REGISTER_OFFSET, 0);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_=
REGISTER_OFFSET, 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, B=
ridge.PrefetchableBaseUpper32), 0);
+ }
+ } // for ( Fun .. )
+ } // for ( Dev ... )
+ } // for ( Bus ... )
+} // DisablePCIDevicesAndBridges
+
+VOID
+TbtDisablePCIDevicesAndBridges (
+ IN UINT8 Type
+ )
+{
+ UINTN Segment =3D 0;
+ UINTN Bus =3D 0;
+ UINTN Device;
+ UINTN Function;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+
+ MinBus =3D 1;
+ if(Type =3D=3D DTBT_CONTROLLER) {
+ //
+ // for(Dev =3D 0; Dev < 8; ++Dev)
+ // {
+ // PciOr8(PCI_LIB_ADDRESS(2, Dev, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSE=
T), 0x40);
+ // gBS->Stall(2000); // 2msec
+ // PciAnd8(PCI_LIB_ADDRESS(2, Dev, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFS=
ET), 0xBF);
+ // }
+ // gBS->Stall(200 * 1000); // 200 msec
+ //
+ if (gCurrentDiscreteTbtRootPort =3D=3D 0) {
+ DEBUG((DEBUG_ERROR, "Invalid RP Input\n"));
+ return;
+ }
+ GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType, gCurrentDiscreteTbtRo=
otPort - 1, &Device, &Function);
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, =
Function, 0);
+ MinBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE=
_SECONDARY_BUS_REGISTER_OFFSET);
+ MaxBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE=
_SUBORDINATE_BUS_REGISTER_OFFSET);
+ gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (Segment, MinBus, 0x00,=
0x00, 0);
+ DeviceId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVIC=
E_ID_OFFSET);
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+ TbtSegment =3D (UINT8)Segment;
+ MinBus++;
+ //
+ // @todo : Move this out when we dont have Loop for ITBT
+ //
+ DisablePCIDevicesAndBridges(MinBus, MaxBus);
+
+ }
+} // DisablePCIDevicesAndBridges
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/=
TbtSmiHandler.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit=
/Smm/TbtSmiHandler.h
new file mode 100644
index 0000000000..fa768f8279
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiH=
andler.h
@@ -0,0 +1,180 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_SMI_HANDLER_H_
+#define _TBT_SMI_HANDLER_H_
+
+#include <Library/TbtCommonLib.h>
+#include <Library/IoLib.h>
+#include <IndustryStandard/Pci.h>
+
+#ifdef PROGRESS_CODE
+#undef PROGRESS_CODE
+#endif
+
+#define MAX_TBT_DEPTH 6
+
+#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRID=
GE_P2P))
+
+#define BAR_ALIGN(v, a) ((((v) - 1) | (a)) + 1)
+
+#define CMD_BUS_MASTER BIT2
+#define CMD_BM_IO (CMD_BUS_MASTER | BIT0)
+#define CMD_BM_MEM (CMD_BUS_MASTER | BIT1)
+#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0)
+
+#define DEF_CACHE_LINE_SIZE 0x20
+#define DEF_RES_IO_PER_DEV 4
+#define DEF_RES_MEM_PER_DEV 32
+#define DEF_RES_PMEM_PER_DEV 32
+
+#define DOCK_BUSSES 8
+
+#define DISBL_IO_REG1C 0x01F1
+#define DISBL_MEM32_REG20 0x0000FFF0
+#define DISBL_PMEM_REG24 0x0001FFF1
+
+#define count(x) (sizeof (x) / sizeof ((x)[0]))
+
+#define PCIE_CAP_ID_SSID_SSVID 0x0D
+#define INVALID_PCI_DEVICE 0xFFFFFFFF
+#define PCI_TBT_VESC_REG2 0x510
+
+typedef struct _PortInfo {
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 MemBase;
+ UINT16 MemLimit;
+ UINT64 PMemBase64;
+ UINT64 PMemLimit64;
+ UINT8 BusNumLimit;
+ UINT8 ConfedEP;
+} PORT_INFO;
+
+typedef struct _MEM_REGS {
+ UINT32 Base;
+ UINT32 Limit;
+} MEM_REGS;
+
+typedef struct _PMEM_REGS {
+ UINT64 Base64;
+ UINT64 Limit64;
+} PMEM_REGS;
+
+typedef struct _IO_REGS {
+ UINT16 Base;
+ UINT16 Limit;
+} IO_REGS;
+
+typedef struct _BRDG_RES_CONFIG {
+ UINT8 Cmd;
+ UINT8 Cls;
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 MemBase;
+ UINT16 MemLimit;
+ UINT64 PMemBase64;
+ UINT64 PMemLimit64;
+} BRDG_RES_CONFIG;
+
+typedef struct _BRDG_CONFIG {
+ DEV_ID DevId;
+ UINT8 PBus;
+ UINT8 SBus;
+ UINT8 SubBus;
+ BOOLEAN IsDSBridge;
+ BRDG_RES_CONFIG Res;
+} BRDG_CONFIG;
+
+enum {
+ HR_US_PORT,
+ HR_DS_PORT0,
+ HR_DS_PORT3,
+ HR_DS_PORT4,
+ HR_DS_PORT5,
+ HR_DS_PORT6,
+ MAX_CFG_PORTS
+};
+
+enum {
+ HR_DS_PORT1 =3D HR_DS_PORT3
+};
+
+//
+// Alpine Ridge
+//
+enum {
+ AR_DS_PORT1 =3D HR_DS_PORT3,
+ AR_DS_PORT2,
+ AR_DS_PORT3,
+ AR_DS_PORT4
+};
+
+typedef struct _HR_CONFIG {
+ UINT16 DeviceId;
+ UINT8 HRBus;
+ UINT8 MinDSNumber;
+ UINT8 MaxDSNumber;
+ UINT8 BridgeLoops;
+} HR_CONFIG;
+
+STATIC const BRDG_RES_CONFIG NOT_IN_USE_BRIDGE =3D {
+ CMD_BUS_MASTER,
+ 0,
+ DISBL_IO_REG1C & 0xFF,
+ DISBL_IO_REG1C >> 8,
+ DISBL_MEM32_REG20 & 0xFFFF,
+ DISBL_MEM32_REG20 >> 16,
+ DISBL_PMEM_REG24 & 0xFFFF,
+ DISBL_PMEM_REG24 >> 16
+};
+
+typedef union _BRDG_CIO_MAP_REG {
+ UINT32 AB_REG;
+ struct {
+ UINT32 NumOfDSPorts : 5;
+ UINT32 CioPortMap : 27;
+ } Bits;
+} BRDG_CIO_MAP_REG;
+
+//
+// Functions
+//
+VOID
+ThunderboltCallback (
+ IN UINT8 Type
+ );
+
+VOID
+TbtDisablePCIDevicesAndBridges (
+ IN UINT8 Type
+ );
+
+VOID
+EndOfThunderboltCallback(
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+);
+
+VOID
+ConfigureTbtAspm(
+ IN UINT8 Type,
+ IN UINT16 Aspm
+);
+
+UINT8
+PcieFindCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/=
TbtSmm.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tb=
tSmm.c
new file mode 100644
index 0000000000..40de64297d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
@@ -0,0 +1,1765 @@
+/** @file
+
+` Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Module specific Includes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/BaseLib.h>
+#include <Library/GpioLib.h>
+#include <TbtBoardInfo.h>
+#include <Protocol/TbtNvsArea.h>
+#include <PchAccess.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/IoLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Protocol/SmmSxDispatch2.h>
+#include <Protocol/SmmSwDispatch2.h>
+#include <Uefi/UefiSpec.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Guid/HobList.h>
+#include "TbtSmiHandler.h"
+#include <PcieRegs.h>
+#include <Protocol/SaPolicy.h>
+#include <Protocol/DxeTbtPolicy.h>
+#include <Library/PchPmcLib.h>
+#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CL=
ASS_BRIDGE_P2P))
+
+#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0)
+
+#define DISBL_IO_REG1C 0x01F1
+#define DISBL_MEM32_REG20 0x0000FFF0
+#define DISBL_PMEM_REG24 0x0001FFF1
+
+#define DOCK_BUSSES 8
+
+#define PCI_CAPABILITY_ID_PCIEXP 0x10
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34
+
+#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom=
mended maximum value for Snoop Latency can we put like this ?
+#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom=
mended maximum value for Non-Snoop Latency can we put like this ?
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA *mTbtNvsAreaPtr;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscrete=
TbtRootPort;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscrete=
TbtRootPortType;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxSnoopLa=
tency;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxNoSnoop=
Latency;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gDTbtPcieRstSupp=
ort;
+GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *gTbtInfoHob =3D=
NULL;
+STATIC UINTN mPciExpressBaseA=
ddress;
+STATIC UINT8 TbtSegment =3D 0;
+VOID
+GpioWrite (
+ IN UINT32 GpioNumber,
+ IN BOOLEAN Value
+ )
+{
+ GpioSetOutputValue (GpioNumber, (UINT32)Value);
+}
+
+/**
+ Search and return the offset of desired Pci Express Capability ID
+ CAPID list:
+ 0x0001 =3D Advanced Error Reporting Capability
+ 0x0002 =3D Virtual Channel Capability
+ 0x0003 =3D Device Serial Number Capability
+ 0x0004 =3D Power Budgeting Capability
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId Extended CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT16
+PcieFindExtendedCapId (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT16 CapId
+ )
+{
+ UINT16 CapHeaderOffset;
+ UINT16 CapHeaderId;
+ UINT64 DeviceBase;
+
+ DeviceBase =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Functio=
n, 0);
+
+ ///
+ /// Start to search at Offset 0x100
+ /// Get Capability Header, A pointer value of 00h is used to indicate th=
e last capability in the list.
+ ///
+ CapHeaderId =3D 0;
+ CapHeaderOffset =3D 0x100;
+ while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D 0xFFFF) {
+ CapHeaderId =3D PciSegmentRead16 (DeviceBase + CapHeaderOffset);
+ if (CapHeaderId =3D=3D CapId) {
+ return CapHeaderOffset;
+ }
+ ///
+ /// Each capability must be DWORD aligned.
+ /// The bottom two bits of all pointers are reserved and must be imple=
mented as 00b
+ /// although software must mask them to allow for future uses of these=
bits.
+ ///
+ CapHeaderOffset =3D (PciSegmentRead16 (DeviceBase + CapHeaderOffset + =
2) >> 4) & ((UINT16) ~(BIT0 | BIT1));
+ }
+
+ return 0;
+}
+
+/**
+ Find the Offset to a given Capabilities ID
+ CAPID list:
+ 0x01 =3D PCI Power Management Interface
+ 0x04 =3D Slot Identification
+ 0x05 =3D MSI Capability
+ 0x10 =3D PCI Express Capability
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT8
+PcieFindCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ )
+{
+ UINT8 CapHeaderOffset;
+ UINT8 CapHeaderId;
+ UINT64 DeviceBase;
+
+ DeviceBase =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, =
0);
+
+ if ((PciSegmentRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) & EFI_PCI_=
STATUS_CAPABILITY) =3D=3D 0x00) {
+ ///
+ /// Function has no capability pointer
+ ///
+ return 0;
+ }
+
+ ///
+ /// Check the header layout to determine the Offset of Capabilities Poin=
ter Register
+ ///
+ if ((PciSegmentRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_LAYO=
UT_CODE) =3D=3D (HEADER_TYPE_CARDBUS_BRIDGE)) {
+ ///
+ /// If CardBus bridge, start at Offset 0x14
+ ///
+ CapHeaderOffset =3D 0x14;
+ } else {
+ ///
+ /// Otherwise, start at Offset 0x34
+ ///
+ CapHeaderOffset =3D 0x34;
+ }
+ ///
+ /// Get Capability Header, A pointer value of 00h is used to indicate th=
e last capability in the list.
+ ///
+ CapHeaderId =3D 0;
+ CapHeaderOffset =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset) & ((U=
INT8) ~(BIT0 | BIT1));
+ while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D 0xFF) {
+ CapHeaderId =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset);
+ if (CapHeaderId =3D=3D CapId) {
+ return CapHeaderOffset;
+ }
+ ///
+ /// Each capability must be DWORD aligned.
+ /// The bottom two bits of all pointers (including the initial pointer=
at 34h) are reserved
+ /// and must be implemented as 00b although software must mask them to=
allow for future uses of these bits.
+ ///
+ CapHeaderOffset =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset + 1)=
& ((UINT8) ~(BIT0 | BIT1));
+ }
+
+ return 0;
+}
+/**
+ This function configures the L1 Substates.
+ It can be used for Rootport and endpoint devices.
+
+ @param[in] DownstreamPort Indicates if the device about to=
be programmed is a downstream port
+ @param[in] DeviceBase Device PCI configuration base ad=
dress
+ @param[in] L1SubstateExtCapOffset Pointer to L1 Substate Capabilit=
y Structure
+ @param[in] PortL1SubstateCapSupport L1 Substate capability setting
+ @param[in] PortCommonModeRestoreTime Common Mode Restore Time
+ @param[in] PortTpowerOnValue Tpower_on Power On Wait Time
+ @param[in] PortTpowerOnScale Tpower-on Scale
+
+ @retval none
+**/
+VOID
+ConfigureL1s (
+ IN UINTN DeviceBase,
+ IN UINT16 L1SubstateExtCapOffset,
+ IN UINT32 PortL1SubstateCapSupport,
+ IN UINT32 PortCommonModeRestoreTime,
+ IN UINT32 PortTpowerOnValue,
+ IN UINT32 PortTpowerOnScale,
+ IN UINT16 MaxLevel
+ )
+{
+
+ PciSegmentAndThenOr32 (
+ DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) ~(0xFF00),
+ (UINT32) PortCommonModeRestoreTime << 8
+ );
+
+ PciSegmentAnd32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_=
OFFSET, 0xFFFFFF04);
+
+ PciSegmentOr32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_O=
FFSET,(UINT32) ((PortTpowerOnValue << N_PCIE_EX_L1SCTL2_POWT) | PortTpowerO=
nScale));
+
+ PciSegmentAndThenOr32 (
+ DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) ~(0xE3FF0000),
+ (UINT32) (BIT30 | BIT23 | BIT21)
+ );
+
+}
+
+VOID
+RootportL1sSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT16 RootL1SubstateExtCapOffset,
+ IN UINT16 MaxL1Level
+ )
+{
+ UINTN ComponentABaseAddress;
+ UINTN ComponentBBaseAddress;
+ UINT8 SecBus;
+ UINT32 PortL1SubstateCapSupport;
+ UINT32 PortCommonModeRestoreTime;
+ UINT32 PortTpowerOnValue;
+ UINT32 PortTpowerOnScale;
+ UINT16 ComponentBL1SubstateExtCapOffset;
+ UINT32 ComponentBL1Substates;
+ UINT32 ComponentBCommonModeRestoreTime;
+ UINT32 ComponentBTpowerOnValue;
+ UINT32 ComponentBTpowerOnScale;
+ UINT32 Data32;
+
+ PortL1SubstateCapSupport =3D 0;
+ PortCommonModeRestoreTime =3D 0;
+ PortTpowerOnValue =3D 0;
+ PortTpowerOnScale =3D 0;
+ Data32 =3D 0;
+
+ ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev=
, Fun, 0);
+ if (RootL1SubstateExtCapOffset !=3D 0) {
+ Data32 =3D PciSegmentRead32 (ComponentABaseAddress + RootL1SubstateExt=
CapOffset + R_PCIE_EX_L1SCAP_OFFSET);
+ PortL1SubstateCapSupport =3D (Data32) & 0x0F;
+ PortCommonModeRestoreTime =3D (Data32 >> 8) & 0xFF;
+ PortTpowerOnScale =3D (Data32 >> 16) & 0x3;
+ PortTpowerOnValue =3D (Data32 >> 19) & 0x1F;
+ } else {
+ MaxL1Level =3D 0; // If L1 Substates from Root Port sid=
e is disable, then Disable from Device side also.
+ }
+
+ SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B=
RIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0=
, 0, 0);
+
+ if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=
=3D 0xFFFF) {
+ ComponentBL1SubstateExtCapOffset =3D PcieFindExtendedCapId (
+ SecBus,
+ 0,
+ 0,
+ V_PCIE_EX_L1S_CID
+ );
+ if (ComponentBL1SubstateExtCapOffset !=3D 0) {
+ ComponentBL1Substates =3D PciSegmentRead32 (ComponentBBaseAddress + =
ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET);
+ ComponentBCommonModeRestoreTime =3D (ComponentBL1Substates >> 8) & 0=
xFF;
+ ComponentBTpowerOnScale =3D (ComponentBL1Substates >> 16) & =
0x3;
+ ComponentBTpowerOnValue =3D (ComponentBL1Substates >> 19) & =
0x1F;
+
+ if (MaxL1Level =3D=3D 3) {
+ if (Data32 >=3D ComponentBL1Substates) {
+ if (~(Data32 | BIT2)) {
+ MaxL1Level =3D 1;
+ }
+ }
+ else {
+ if (~(ComponentBL1Substates | BIT2)) {
+ MaxL1Level =3D 1;
+ }
+ }
+ }
+
+ if (MaxL1Level =3D=3D 3) {
+ ConfigureL1s (
+ ComponentABaseAddress,
+ RootL1SubstateExtCapOffset,
+ PortL1SubstateCapSupport,
+ ComponentBCommonModeRestoreTime,
+ ComponentBTpowerOnValue,
+ ComponentBTpowerOnScale,
+ MaxL1Level
+ );
+
+ ConfigureL1s (
+ ComponentBBaseAddress,
+ ComponentBL1SubstateExtCapOffset,
+ ComponentBL1Substates,
+ PortCommonModeRestoreTime,
+ PortTpowerOnValue,
+ PortTpowerOnScale,
+ MaxL1Level
+ );
+ }
+
+ if (MaxL1Level =3D=3D 1) {
+ PciSegmentOr32 (
+ ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L=
1SCTL1_OFFSET,
+ (UINT32) (BIT3 | BIT1)
+ );
+
+ PciSegmentOr32 (
+ ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCI=
E_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT3 | BIT1)
+ );
+ }
+ else {
+ if (RootL1SubstateExtCapOffset !=3D 0) {
+ PciSegmentOr32 (
+ ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX=
_L1SCTL1_OFFSET,
+ (UINT32) (BIT3 | BIT1)
+ );
+
+ PciSegmentOr32 (
+ ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX=
_L1SCTL1_OFFSET,
+ (UINT32) (BIT2 | BIT0)
+ );
+ }
+ if (ComponentBL1SubstateExtCapOffset !=3D 0) {
+ PciSegmentOr32 (
+ ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_P=
CIE_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT3 | BIT1)
+ );
+
+ PciSegmentOr32 (
+ ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_P=
CIE_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT2 | BIT0)
+ );
+ }
+ }
+ }
+ }
+}
+
+VOID
+MultiFunctionDeviceAspm (
+ IN UINT8 Bus,
+ IN UINT8 Dev
+ )
+{
+ UINT16 LowerAspm;
+ UINT16 AspmVal;
+ UINT8 Fun;
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+
+ LowerAspm =3D 3; // L0s and L1 Supported
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, F=
un, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=3D=
0xFFFF) {
+ // Device not present
+ continue;
+ }
+
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
+
+ AspmVal =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0=
x00C) >> 10) & 3;
+ if (LowerAspm > AspmVal) {
+ LowerAspm =3D AspmVal;
+ }
+ } //Fun
+
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, F=
un, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=3D=
0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
+
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xF=
FFC, LowerAspm);
+ } //Fun
+}
+
+UINT16
+LimitAspmLevel (
+ IN UINT16 SelectedAspm,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ SelectedAspm =3D SelectedAspm & MaxAspmLevel;
+
+ return SelectedAspm;
+}
+
+UINT16
+FindOptimalAspm (
+ IN UINT16 ComponentAaspm,
+ IN UINT16 ComponentBaspm
+ )
+{
+ UINT16 SelectedAspm;
+
+ SelectedAspm =3D ComponentAaspm & ComponentBaspm;
+
+ return SelectedAspm;
+}
+
+UINT16
+FindComponentBaspm (
+ IN UINT8 Bus,
+ IN UINT8 MaxBus
+ )
+{
+ UINT8 BusNo;
+ UINT8 DevNo;
+ UINT8 FunNo;
+ UINT64 DevBaseAddress;
+ UINT8 RegVal;
+ UINT8 SecBusNo;
+ UINT16 SelectedAspm; // No ASPM Support
+ UINT8 CapHeaderOffset_B;
+ BOOLEAN AspmFound;
+
+ SelectedAspm =3D 0;
+ AspmFound =3D FALSE;
+
+ for (BusNo =3D MaxBus; (BusNo !=3D 0xFF) && (!AspmFound); --BusNo) {
+ for (DevNo =3D 0; (DevNo <=3D PCI_MAX_DEVICE) && (!AspmFound); ++DevNo=
) {
+ for (FunNo =3D 0; (FunNo <=3D PCI_MAX_FUNC) && (!AspmFound); ++FunNo=
) {
+ //
+ // Check for Device availability
+ //
+ DevBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, BusNo, Dev=
No, FunNo, 0);
+ if (PciSegmentRead16 (DevBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=
=3D 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ RegVal =3D PciSegmentRead8 (DevBaseAddress + PCI_HEADER_TYPE_OFFSE=
T);
+ if ((RegVal & (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6)) !=
=3D 0x01) {
+ //
+ // Not a PCI-to-PCI bridges device
+ //
+ continue;
+ }
+
+ SecBusNo =3D PciSegmentRead8 (DevBaseAddress + PCI_BRIDGE_SECONDAR=
Y_BUS_REGISTER_OFFSET);
+
+ if (SecBusNo =3D=3D Bus) {
+ //
+ // This is the Rootbridge for the given 'Bus' device
+ //
+ CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, BusNo, DevNo, F=
unNo, 0x10);
+ SelectedAspm =3D (PciSegmentRead16 (DevBaseAddress + CapHea=
derOffset_B + 0x00C) >> 10) & 3;
+ AspmFound =3D TRUE;
+ }
+ } //FunNo
+ } //DevNo
+ } //BusNo
+
+ return (SelectedAspm);
+}
+
+VOID
+NoAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset
+ )
+{
+ UINT64 DeviceBaseAddress;
+
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun=
, 0);
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF=
C, 0x00);
+}
+
+VOID
+EndpointAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset,
+ IN UINT8 MaxBus,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ UINT64 DeviceBaseAddress;
+ UINT16 ComponentAaspm;
+ UINT16 ComponentBaspm;
+ UINT16 SelectedAspm;
+
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun=
, 0);
+ ComponentAaspm =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOf=
fset + 0x00C) >> 10) & 3;
+ ComponentBaspm =3D FindComponentBaspm (Bus, MaxBus);
+ SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm);
+ SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel);
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF=
C, SelectedAspm);
+}
+
+VOID
+UpstreamAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset,
+ IN UINT8 MaxBus,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ UINT64 DeviceBaseAddress;
+ UINT16 ComponentAaspm;
+ UINT16 ComponentBaspm;
+ UINT16 SelectedAspm;
+
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun=
, 0);
+ ComponentAaspm =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOf=
fset + 0x00C) >> 10) & 3;
+ ComponentBaspm =3D FindComponentBaspm (Bus, MaxBus);
+ SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm);
+ SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel);
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF=
C, SelectedAspm);
+}
+
+VOID
+DownstreamAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ UINT64 ComponentABaseAddress;
+ UINT64 ComponentBBaseAddress;
+ UINT16 ComponentAaspm;
+ UINT16 ComponentBaspm;
+ UINT16 SelectedAspm;
+ UINT8 SecBus;
+ UINT8 CapHeaderOffset_B;
+
+ ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,=
Fun, 0);
+ ComponentAaspm =3D (PciSegmentRead16 (ComponentABaseAddress + Cap=
HeaderOffset + 0x00C) >> 10) & 3;
+
+ SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B=
RIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0=
, 0, 0);
+ ComponentBaspm =3D 0; // No ASPM Support
+ if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) !=3D=
0xFFFF) {
+ CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10);
+ ComponentBaspm =3D (PciSegmentRead16 (ComponentBBaseAddress + CapHe=
aderOffset_B + 0x00C) >> 10) & 3;
+ }
+
+ SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm);
+ SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel);
+ PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0=
xFFFC, SelectedAspm);
+}
+
+VOID
+RootportAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ UINT64 ComponentABaseAddress;
+ UINT64 ComponentBBaseAddress;
+ UINT16 ComponentAaspm;
+ UINT16 ComponentBaspm;
+ UINT16 SelectedAspm;
+ UINT8 SecBus;
+ UINT8 CapHeaderOffset_B;
+
+ ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,=
Fun, 0);
+ ComponentAaspm =3D (PciSegmentRead16 (ComponentABaseAddress + Cap=
HeaderOffset + 0x00C) >> 10) & 3;
+
+ SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B=
RIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0=
, 0, 0);
+ ComponentBaspm =3D 0; // No ASPM Support
+ if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) !=3D=
0xFFFF) {
+ CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10);
+ ComponentBaspm =3D (PciSegmentRead16 (ComponentBBaseAddress + CapHe=
aderOffset_B + 0x00C) >> 10) & 3;
+ }
+
+ SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm);
+ SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel);
+ PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0=
xFFFC, SelectedAspm);
+}
+
+VOID
+ThunderboltEnableAspmWithoutLtr (
+ IN UINT16 MaxAspmLevel,
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 RootBus;
+ UINT8 RootDev;
+ UINT8 RootFun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+ UINT8 RegVal;
+ UINT8 CapHeaderOffset;
+ UINT16 DevicePortType;
+
+ MinBus =3D 0;
+ MaxBus =3D 0;
+
+ MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB=
us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment =3D (UINT8)RpSegment;
+
+ RootBus =3D (UINT8)RpBus;
+ RootDev =3D (UINT8)RpDevice;
+ RootFun =3D (UINT8)RpFunction;
+
+ //
+ // Enumerate all the bridges and devices which are available on TBT hos=
t controller
+ //
+ for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) {
+ for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,=
0, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=
=3D 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ RegVal =3D PciSegmentRead8 (DeviceBaseAddress + PCI_HEADER_TYPE_OFFS=
ET);
+ if ((RegVal & BIT7) =3D=3D 0) {
+ //
+ // Not a multi-function device
+ //
+ continue;
+ }
+
+ MultiFunctionDeviceAspm(Bus, Dev);
+ } //Dev
+ } //Bus
+
+
+ for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) {
+ for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) {
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De=
v, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =
=3D=3D 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10=
);
+ DevicePortType =3D (PciSegmentRead16 (DeviceBaseAddress + CapHead=
erOffset + 0x002) >> 4) & 0xF;
+ if(PciSegmentRead8 (DeviceBaseAddress + PCI_CLASSCODE_OFFSET) =3D=
=3D PCI_CLASS_SERIAL) {
+ MaxAspmLevel =3D (UINT16) 0x1;
+ }
+
+ switch (DevicePortType) {
+ case 0:
+ //
+ // PCI Express Endpoint
+ //
+ EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max=
AspmLevel);
+ break;
+
+ case 1:
+ //
+ // Legacy PCI Express Endpoint
+ //
+ EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max=
AspmLevel);
+ break;
+
+ case 4:
+ //
+ // Root Port of PCI Express Root Complex
+ //
+ RootportAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLeve=
l);
+ break;
+
+ case 5:
+ //
+ // Upstream Port of PCI Express Switch
+ //
+ UpstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max=
AspmLevel);
+ break;
+
+ case 6:
+ //
+ // Downstream Port of PCI Express Switch
+ //
+ DownstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLe=
vel);
+ break;
+
+ case 7:
+ //
+ // PCI Express to PCI/PCI-X Bridge
+ //
+ NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset);
+ break;
+
+ case 8:
+ //
+ // PCI/PCI-X to PCI Express Bridge
+ //
+ NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset);
+ break;
+
+ case 9:
+ //
+ // Root Complex Integrated Endpoint
+ //
+ EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max=
AspmLevel);
+ break;
+
+ case 10:
+ //
+ // Root Complex Event Collector
+ //
+ EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max=
AspmLevel);
+ break;
+
+ default:
+ break;
+ }
+ //
+ // switch(DevicePortType)
+ //
+ }
+ //
+ // Fun
+ //
+ }
+ //
+ // Dev
+ //
+ }
+ //
+ // Bus
+ //
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun=
, 0x10);
+ RootportAspmSupport (RootBus, RootDev, RootFun, CapHeaderOffset, MaxAspm=
Level);
+}
+
+
+
+VOID
+ThunderboltEnableL1Sub (
+ IN UINT16 MaxL1Level,
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT16 CapHeaderOffsetExtd;
+
+ RpBus =3D 0;
+
+ CapHeaderOffsetExtd =3D PcieFindExtendedCapId ((UINT8) RpBus, (UINT8) Rp=
Device, (UINT8) RpFunction, V_PCIE_EX_L1S_CID);
+ RootportL1sSupport ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction,=
CapHeaderOffsetExtd, MaxL1Level);
+}
+
+VOID
+ThunderboltDisableAspmWithoutLtr (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 RootBus;
+ UINT8 RootDev;
+ UINT8 RootFun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+
+ MinBus =3D 0;
+ MaxBus =3D 0;
+
+ MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB=
us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment =3D (UINT8)RpSegment;
+ RootBus =3D (UINT8)RpBus;
+ RootDev =3D (UINT8)RpDevice;
+ RootFun =3D (UINT8)RpFunction;
+
+ //
+ // Enumerate all the bridges and devices which are available on TBT hos=
t controller
+ //
+ for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) {
+ for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) {
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De=
v, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =
=3D=3D 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10=
);
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10,=
0xFFFC, 0x00);
+ } //Fun
+ } //Dev
+ } //Bus
+
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun=
, 0x10);
+ NoAspmSupport(RootBus, RootDev, RootFun, CapHeaderOffset);
+}
+
+VOID
+TbtProgramClkReq (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 ClkReqSetup
+ )
+{
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+ UINT16 Data16;
+
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, =
Function, 0);
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Device, Function, =
0x10);
+
+ //
+ // Check if CLKREQ# is supported
+ //
+ if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x0C) & BIT=
18) !=3D 0) {
+ Data16 =3D PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x0=
10);
+
+ if (ClkReqSetup) {
+ Data16 =3D Data16 | BIT8; // Enable Clock Power Management
+ } else {
+ Data16 =3D Data16 & (UINT16)(~BIT8); // Disable Clock Power Managem=
ent
+ }
+
+ PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x010, Data16=
);
+ }
+}
+VOID
+TbtProgramPtm(
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 PtmSetup,
+ IN BOOLEAN IsRoot
+)
+{
+ UINT64 DeviceBaseAddress;
+ UINT16 CapHeaderOffset;
+ UINT16 PtmControlRegister;
+ UINT16 PtmCapabilityRegister;
+
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(TbtSegment, Bus, Device, =
Function, 0);
+ CapHeaderOffset =3D PcieFindExtendedCapId(Bus, Device, Function, 0x001F=
/*V_PCIE_EX_PTM_CID*/);
+ if(CapHeaderOffset !=3D 0) {
+ PtmCapabilityRegister =3D PciSegmentRead16(DeviceBaseAddress + CapHe=
aderOffset + 0x04);
+ //
+ // Check if PTM Requester/ Responder capability for the EP/Down strea=
m etc
+ //
+ if ((PtmCapabilityRegister & (BIT1 | BIT0)) !=3D 0) {
+ PtmControlRegister =3D PciSegmentRead16(DeviceBaseAddress + CapHea=
derOffset + 0x08);
+
+ if (PtmSetup) {
+ PtmControlRegister =3D PtmControlRegister | BIT0; // Enable PTM
+ if(IsRoot) {
+ PtmControlRegister =3D PtmControlRegister | BIT1; // Enable P=
TM
+ }
+ PtmControlRegister =3D PtmControlRegister | (PtmCapabilityRegis=
ter & 0xFF00); // Programm Local Clock Granularity
+ } else {
+ PtmControlRegister =3D PtmControlRegister & (UINT16)(~(BIT0 | B=
IT1)); // Disable Clock Power Management
+ }
+
+ PciSegmentWrite16(DeviceBaseAddress + CapHeaderOffset + 0x08, PtmC=
ontrolRegister);
+ }
+ }
+}
+
+VOID
+ConfigureTbtPm (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction,
+ IN UINT8 Configuration // 1- Clk Request , 2- PTM ,
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+
+ MinBus =3D 0;
+ MaxBus =3D 0;
+
+ if ((Configuration !=3D 1) && (Configuration !=3D 2)) {
+ return;
+ }
+ MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB=
us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment =3D (UINT8)RpSegment;
+ //
+ // Enumerate all the bridges and devices which are available on TBT hos=
t controller
+ //
+ for (Bus =3D MaxBus; Bus >=3D MinBus; --Bus) {
+ for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) {
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De=
v, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =
=3D=3D 0xFFFF) {
+ if (Fun =3D=3D 0) {
+ //
+ // IF Fun is zero, stop enumerating other functions of the par=
ticular bridge
+ //
+ break;
+ }
+ //
+ // otherwise, just skip checking for CLKREQ support
+ //
+ continue;
+ }
+ switch (Configuration) {
+ case 1:
+ TbtProgramClkReq (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtSe=
tClkReq);
+ break;
+ case 2:
+ TbtProgramPtm (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtPtm, =
FALSE);
+ TbtProgramPtm((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunct=
ion, (UINT8) mTbtNvsAreaPtr->TbtPtm, TRUE);
+ break;
+ default:
+ break;
+ }
+ } //Fun
+ } // Dev
+ } // Bus
+}
+
+/**
+ 1) Check LTR support in device capabilities 2 register (bit 11).
+ 2) If supported enable LTR in device control 2 register (bit 10).
+
+**/
+VOID
+TbtProgramLtr (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 LtrSetup
+ )
+{
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+ UINT16 Data16;
+
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, =
Function, 0);
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Device, Function, =
0x10);
+
+ //
+ // Check if LTR# is supported
+ //
+ if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x24) & BIT=
11) !=3D 0) {
+ Data16 =3D PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x0=
28);
+
+ if (LtrSetup) {
+ Data16 =3D Data16 | BIT10; // LTR Mechanism Enable
+ } else {
+ Data16 =3D Data16 & (UINT16)(~BIT10); // LTR Mechanism Disable
+ }
+
+ PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x028, Data16=
);
+ }
+}
+
+VOID
+ConfigureLtr (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+
+ MinBus =3D 0;
+ MaxBus =3D 0;
+
+ MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB=
us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment =3D (UINT8)RpSegment;
+ //
+ // Enumerate all the bridges and devices which are available on TBT hos=
t controller
+ //
+ for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) {
+ for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) {
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De=
v, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =
=3D=3D 0xFFFF) {
+ if (Fun =3D=3D 0) {
+ //
+ // IF Fun is zero, stop enumerating other functions of the par=
ticular bridge
+ //
+ break;
+ }
+ //
+ // otherwise, just skip checking for LTR support
+ //
+ continue;
+ }
+
+ TbtProgramLtr (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtLtr);
+
+ } //Fun
+ } // Dev
+ } // Bus
+ TbtProgramLtr ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, (UIN=
T8) mTbtNvsAreaPtr->TbtLtr);
+}
+
+/*
+ US ports and endpoints which declare support must also have the LTR capa=
bility structure (cap ID 18h).
+ In this structure you need to enter the max snoop latency and max non-sn=
oop latency in accordance with the format specified in the PCIe spec.
+ The latency value itself is platform specific so you'll need to get it f=
rom the platform architect or whatever.
+*/
+VOID
+ThunderboltGetLatencyLtr (
+ VOID
+ )
+{
+ PCH_SERIES PchSeries;
+
+ PchSeries =3D GetPchSeries ();
+
+ if(gCurrentDiscreteTbtRootPortType =3D=3D DTBT_TYPE_PEG) {
+ // PEG selector
+ TbtLtrMaxSnoopLatency =3D LTR_MAX_SNOOP_LATENCY_VALUE;
+ TbtLtrMaxNoSnoopLatency =3D LTR_MAX_NON_SNOOP_LATENCY_VALUE;
+ } else if (gCurrentDiscreteTbtRootPortType =3D=3D DTBT_TYPE_PCH) {
+ // PCH selector
+
+ if (PchSeries =3D=3D PchLp) {
+ TbtLtrMaxSnoopLatency =3D 0x1003;
+ TbtLtrMaxNoSnoopLatency =3D 0x1003;
+ }
+ if (PchSeries =3D=3D PchH) {
+ TbtLtrMaxSnoopLatency =3D 0x0846;
+ TbtLtrMaxNoSnoopLatency =3D 0x0846;
+ }
+ }
+}
+
+VOID
+SetLatencyLtr (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT16 CapHeaderOffsetExtd,
+ IN UINT16 LtrMaxSnoopLatency,
+ IN UINT16 LtrMaxNoSnoopLatency
+ )
+{
+ UINT64 DeviceBaseAddress;
+ if(CapHeaderOffsetExtd =3D=3D 0) {
+ return;
+ }
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun=
, 0);
+ PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x004, LtrM=
axSnoopLatency);
+ PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x006, LtrM=
axNoSnoopLatency);
+}
+
+VOID
+ThunderboltSetLatencyLtr (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffsetStd;
+ UINT16 CapHeaderOffsetExtd;
+ UINT16 DevicePortType;
+
+ MinBus =3D 0;
+ MaxBus =3D 0;
+
+ MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus=
, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB=
us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment =3D (UINT8)RpSegment;
+
+ for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) {
+ for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) {
+ for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De=
v, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =
=3D=3D 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ CapHeaderOffsetStd =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0=
x10);
+ DevicePortType =3D (PciSegmentRead16 (DeviceBaseAddress + CapHead=
erOffsetStd + 0x002) >> 4) & 0xF;
+
+ CapHeaderOffsetExtd =3D PcieFindExtendedCapId (Bus, Dev, Fun, 0x00=
18);
+
+ switch (DevicePortType) {
+ case 0:
+ //
+ // PCI Express Endpoint
+ //
+ SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo=
pLatency, TbtLtrMaxNoSnoopLatency);
+ break;
+
+ case 1:
+ //
+ // Legacy PCI Express Endpoint
+ //
+ SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo=
pLatency, TbtLtrMaxNoSnoopLatency);
+ break;
+
+ case 4:
+ //
+ // Root Port of PCI Express Root Complex
+ //
+ // Do-nothing
+ break;
+
+ case 5:
+ //
+ // Upstream Port of PCI Express Switch
+ //
+ SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo=
pLatency, TbtLtrMaxNoSnoopLatency);
+ break;
+
+ case 6:
+ //
+ // Downstream Port of PCI Express Switch
+ //
+ // Do-nothing
+ break;
+
+ case 7:
+ //
+ // PCI Express to PCI/PCI-X Bridge
+ //
+ // Do-nothing
+ break;
+
+ case 8:
+ //
+ // PCI/PCI-X to PCI Express Bridge
+ //
+ // Do-nothing
+ break;
+
+ case 9:
+ //
+ // Root Complex Integrated Endpoint
+ //
+ // Do-nothing
+ break;
+
+ case 10:
+ //
+ // Root Complex Event Collector
+ //
+ // Do-nothing
+ break;
+
+ default:
+ break;
+ }
+ //
+ // switch(DevicePortType)
+ //
+ }
+ //
+ // Fun
+ //
+ }
+ //
+ // Dev
+ //
+ }
+ //
+ // Bus
+ //
+}
+
+static
+VOID
+Stall (
+ UINTN Usec
+ )
+{
+ UINTN Index;
+ UINT32 Data32;
+ UINT32 PrevData;
+ UINTN Counter;
+
+ Counter =3D (UINTN) ((Usec * 10) / 3);
+ //
+ // Call WaitForTick for Counter + 1 ticks to try to guarantee Counter ti=
ck
+ // periods, thus attempting to ensure Microseconds of stall time.
+ //
+ if (Counter !=3D 0) {
+
+ PrevData =3D IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_=
TMR);
+ for (Index =3D 0; Index < Counter;) {
+ Data32 =3D IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_=
TMR);
+ if (Data32 < PrevData) {
+ //
+ // Reset if there is a overlap
+ //
+ PrevData =3D Data32;
+ continue;
+ }
+
+ Index +=3D (Data32 - PrevData);
+ PrevData =3D Data32;
+ }
+ }
+
+ return ;
+}
+/**
+ Called during Sx entry, initates TbtSetPcie2TbtCommand HandShake to set =
GO2SX_NO_WAKE
+ for Tbt devices if WakeupSupport is not present.
+
+ @param[in] DispatchHandle - The unique handle assigned to this h=
andler by SmiHandlerRegister().
+ @param[in] DispatchContext - Points to an optional handler contex=
t which was specified when the
+ handler was registered.
+ @param[in, out] CommBuffer - A pointer to a collection of data in=
memory that will
+ be conveyed from a non-SMM environme=
nt into an SMM environment.
+ @param[in, out] CommBufferSize - The size of the CommBuffer.
+
+ @retval EFI_SUCCESS - The interrupt was handled successful=
ly.
+**/
+EFI_STATUS
+EFIAPI
+SxDTbtEntryCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ )
+{
+ UINT16 DeviceId;
+ UINT8 CableConnected;
+ UINT8 RootportSelected;
+ UINT8 HoustRouteBus;
+ volatile UINT32 *PowerState;
+ UINT32 PowerStatePrev;
+ BOOLEAN SecSubBusAssigned;
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+ UINTN RpDev;
+ UINTN RpFunc;
+ EFI_STATUS Status;
+ UINT32 Timeout;
+ UINT32 RegisterValue;
+ UINT64 Tbt2Pcie;
+ UINTN Index;
+ UINT32 TbtCioPlugEventGpioNo;
+ UINT32 TbtFrcPwrGpioNo;
+ UINT8 TbtFrcPwrGpioLevel;
+ UINT32 TbtPcieRstGpioNo;
+ UINT8 TbtPcieRstGpioLevel;
+ EFI_SMM_SX_REGISTER_CONTEXT *EntryDispatchContext;
+
+ CableConnected =3D 0;
+ HoustRouteBus =3D 3;
+ SecSubBusAssigned =3D FALSE;
+ Timeout =3D 600;
+ RootportSelected =3D 0;
+ TbtCioPlugEventGpioNo =3D 0;
+ TbtFrcPwrGpioNo =3D 0;
+ TbtFrcPwrGpioLevel =3D 0;
+ TbtPcieRstGpioNo =3D 0;
+ TbtPcieRstGpioLevel =3D 0;
+ Index =3D 0;
+
+ EntryDispatchContext =3D (EFI_SMM_SX_REGISTER_CONTEXT*) DispatchContext;
+
+// CableConnected =3D GetTbtHostRouterStatus ();
+ //SaveTbtHostRouterStatus (CableConnected & 0xF0);
+ //
+ // Get the Power State and Save
+ //
+ if (((mTbtNvsAreaPtr->DTbtControllerEn0 =3D=3D 0) && (Index =3D=3D 0))) =
{
+
+ RootportSelected =3D mTbtNvsAreaPtr->RootportSelected0;
+ TbtCioPlugEventGpioNo =3D mTbtNvsAreaPtr->TbtCioPlugEventGpioNo0;
+ TbtFrcPwrGpioNo =3D mTbtNvsAreaPtr->TbtFrcPwrGpioNo0;
+ TbtFrcPwrGpioLevel =3D mTbtNvsAreaPtr->TbtFrcPwrGpioLevel0;
+ TbtPcieRstGpioNo =3D mTbtNvsAreaPtr->TbtPcieRstGpioNo0;
+ TbtPcieRstGpioLevel =3D mTbtNvsAreaPtr->TbtPcieRstGpioLevel0;
+ }
+
+ Status =3D GetDTbtRpDevFun (gCurrentDiscreteTbtRootPortType, RootportSel=
ected - 1, &RpDev, &RpFunc);
+ ASSERT_EFI_ERROR (Status);
+ CapHeaderOffset =3D PcieFindCapId (TbtSegment, 0x00, (UINT8)RpDev, (UINT=
8)RpFunc, 0x01);
+ DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, 0x00, (UINT32=
)RpDev, (UINT32)RpFunc, 0);
+ PowerState =3D &*((volatile UINT32 *) (mPciExpressBaseAddress + D=
eviceBaseAddress + CapHeaderOffset + 4)); //PMCSR
+ PowerStatePrev =3D *PowerState;
+ *PowerState &=3D 0xFFFFFFFC;
+
+ HoustRouteBus =3D PciSegmentRead8 (DeviceBaseAddress + PCI_BRIDGE_SECOND=
ARY_BUS_REGISTER_OFFSET);
+ //
+ // Check the Subordinate bus .If it is Zero ,assign temporary bus to
+ // find the device presence .
+ //
+ if (HoustRouteBus =3D=3D 0) {
+ PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTE=
R_OFFSET, 0xF0);
+ PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIS=
TER_OFFSET, 0xF0);
+ HoustRouteBus =3D 0xF0;
+ SecSubBusAssigned =3D TRUE;
+ }
+ //
+ // Clear Interrupt capability of TBT CIO Plug Event Pin to make sure no =
SCI is getting generated,
+ // This GPIO will be reprogrammed while resuming as part of Platform GPI=
O Programming.
+ //
+ GpioSetPadInterruptConfig (TbtCioPlugEventGpioNo, GpioIntDis);
+ //
+ // Read the TBT Host router DeviceID
+ //
+ DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Hous=
tRouteBus, 0, 0, PCI_DEVICE_ID_OFFSET));
+
+ //
+ // Check For HostRouter Presence
+ //
+ if (IsTbtHostRouter (DeviceId)) {
+ // CableConnected =3D GetTbtHostRouterStatus ();
+ if (!((CableConnected & (DTBT_SAVE_STATE_OFFSET << Index)) =3D=3D (DTB=
T_SAVE_STATE_OFFSET << Index))) {
+ CableConnected =3D CableConnected | (DTBT_SAVE_STATE_OFFSET << Index=
);
+ // SaveTbtHostRouterStatus (CableConnected);
+ }
+ }
+
+ //
+ // Check value of Tbt2Pcie reg, if Tbt is not present, bios needs to app=
ly force power prior to sending mailbox command
+ //
+ GET_TBT2PCIE_REGISTER_ADDRESS(TbtSegment, HoustRouteBus, 0x00, 0x00, Tbt=
2Pcie)
+ RegisterValue =3D PciSegmentRead32 (Tbt2Pcie);
+ if (0xFFFFFFFF =3D=3D RegisterValue) {
+
+ GpioWrite (TbtFrcPwrGpioNo,TbtFrcPwrGpioLevel);
+
+ while (Timeout -- > 0) {
+ RegisterValue =3D PciSegmentRead32 (Tbt2Pcie);
+ if (0xFFFFFFFF !=3D RegisterValue) {
+ break;
+ }
+ Stall(1* (UINTN)1000);
+ }
+ //
+ // Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox =
command for AIC.
+ // However BIOS shall not execute go2sx mailbox command on S5/reboot c=
ycle.
+ //
+
+ if( (EntryDispatchContext->Type =3D=3D SxS3) || (EntryDispatchContext-=
>Type =3D=3D SxS4))
+ {
+ if(!mTbtNvsAreaPtr->TbtWakeupSupport) {
+ //Wake Disabled, GO2SX_NO_WAKE Command
+ TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0=
, TBT_5S_TIMEOUT);
+ } else {
+ //Wake Enabled, GO2SX Command
+ TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S=
_TIMEOUT);
+ }
+ }
+ if (mTbtNvsAreaPtr->TbtFrcPwrEn =3D=3D 0) {
+ GpioWrite (TbtFrcPwrGpioNo,!(TbtFrcPwrGpioLevel));
+ }
+ } else {
+ //
+ // Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox =
command for AIC.
+ // However BIOS shall not execute go2sx mailbox command on S5/reboot c=
ycle.
+ //
+ if( (EntryDispatchContext->Type =3D=3D SxS3) || (EntryDispatchContext-=
>Type =3D=3D SxS4))
+ {
+ if(!mTbtNvsAreaPtr->TbtWakeupSupport) {
+ //Wake Disabled, GO2SX_NO_WAKE Command
+ TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0=
, TBT_5S_TIMEOUT);
+ } else {
+ //Wake Enabled, GO2SX Command
+ TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S=
_TIMEOUT);
+ }
+ }
+ }
+ *PowerState =3D PowerStatePrev;
+ //
+ // Restore the bus number in case we assigned temporarily
+ //
+ if (SecSubBusAssigned) {
+ PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTE=
R_OFFSET, 0x00);
+ PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIS=
TER_OFFSET, 0x00);
+ }
+ if (gDTbtPcieRstSupport) {
+ GpioWrite (TbtPcieRstGpioNo,TbtPcieRstGpioLevel);
+ }
+ return EFI_SUCCESS;
+}
+
+VOID
+ThunderboltSwSmiCallback (
+ IN UINT8 Type
+ )
+{
+ UINT8 ThunderboltSmiFunction;
+
+ DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Entry\n"));
+ ThunderboltSmiFunction =3D mTbtNvsAreaPtr->ThunderboltSmiFunction;
+ DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback. ThunderboltSmiFunction=3D=
%d\n", ThunderboltSmiFunction));
+ if (Type =3D=3D DTBT_CONTROLLER) {
+ gCurrentDiscreteTbtRootPort =3D mTbtNvsAreaPtr->CurrentDiscreteTbt=
RootPort;
+ gCurrentDiscreteTbtRootPortType =3D mTbtNvsAreaPtr->CurrentDiscreteTbt=
RootPortType;
+ }
+
+ switch (ThunderboltSmiFunction) {
+ case 21:
+ ThunderboltCallback (Type);
+ break;
+
+ case 22:
+ TbtDisablePCIDevicesAndBridges (Type);
+ break;
+
+ case 23:
+ ConfigureTbtAspm (Type, (UINT16) 0x02);
+ break;
+
+ case 24:
+ ConfigureTbtAspm (Type, (UINT16) 0x01);
+ break;
+
+ default:
+ break;
+ }
+ DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Exit.\n"));
+}
+STATIC
+EFI_STATUS
+EFIAPI
+DiscreteThunderboltSwSmiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ )
+{
+ ThunderboltSwSmiCallback(DTBT_CONTROLLER);
+ return EFI_SUCCESS;
+}
+EFI_STATUS
+TbtRegisterHandlers (
+ IN BOOLEAN Type
+ )
+{
+ EFI_STATUS Status;
+ UINTN SmiInputValue;
+ EFI_SMM_HANDLER_ENTRY_POINT2 SxHandler;
+ EFI_SMM_HANDLER_ENTRY_POINT2 SwHandler;
+ EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatchProtocol;
+ EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
+ EFI_SMM_SX_REGISTER_CONTEXT EntryDispatchContext;
+ EFI_SMM_SW_REGISTER_CONTEXT SwContext;
+ EFI_HANDLE SwDispatchHandle;
+ EFI_HANDLE S3DispatchHandle;
+ EFI_HANDLE S4DispatchHandle;
+ EFI_HANDLE S5DispatchHandle;
+
+ Status =3D EFI_UNSUPPORTED;
+
+ if(Type =3D=3D DTBT_CONTROLLER) {
+ SxHandler =3D SxDTbtEntryCallback;
+ SwHandler =3D DiscreteThunderboltSwSmiCallback;
+ SmiInputValue =3D PcdGet8 (PcdSwSmiDTbtEnumerate);
+ gDTbtPcieRstSupport =3D gTbtInfoHob->DTbtCommonConfig.PcieRstSupport;
+ Status =3D EFI_SUCCESS;
+ }
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ SwDispatchHandle =3D NULL;
+ S3DispatchHandle =3D NULL;
+ S4DispatchHandle =3D NULL;
+ S5DispatchHandle =3D NULL;
+
+ Status =3D gSmst->SmmLocateProtocol (
+ &gEfiSmmSxDispatch2ProtocolGuid,
+ NULL,
+ (VOID **) &SxDispatchProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register S3 entry phase call back function
+ //
+ EntryDispatchContext.Type =3D SxS3;
+ EntryDispatchContext.Phase =3D SxEntry;
+ Status =3D SxDispatchProtocol->Register (
+ SxDispatchProtocol,
+ SxHandler,
+ &EntryDispatchContext,
+ &S3DispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register S4 entry phase call back function
+ //
+ EntryDispatchContext.Type =3D SxS4;
+ EntryDispatchContext.Phase =3D SxEntry;
+ Status =3D SxDispatchProtocol->Register (
+ SxDispatchProtocol,
+ SxHandler,
+ &EntryDispatchContext,
+ &S4DispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register S5 entry phase call back function
+ //
+ EntryDispatchContext.Type =3D SxS5;
+ EntryDispatchContext.Phase =3D SxEntry;
+ Status =3D SxDispatchProtocol->Register (
+ SxDispatchProtocol,
+ SxHandler,
+ &EntryDispatchContext,
+ &S5DispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Locate the SMM SW dispatch protocol
+ //
+ Status =3D gSmst->SmmLocateProtocol (
+ &gEfiSmmSwDispatch2ProtocolGuid,
+ NULL,
+ (VOID **) &SwDispatch
+ );
+
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register SWSMI handler
+ //
+ SwContext.SwSmiInputValue =3D SmiInputValue;
+ Status =3D SwDispatch->Register (
+ SwDispatch,
+ SwHandler,
+ &SwContext,
+ &SwDispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+EFI_STATUS
+InSmmFunction (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status =3D EFI_SUCCESS;
+
+ Status =3D TbtRegisterHandlers(DTBT_CONTROLLER);
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+TbtSmmEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "TbtSmmEntryPoint\n"));
+
+ mPciExpressBaseAddress =3D PcdGet64 (PcdPciExpressBaseAddress);
+ //
+ // Locate Tbt shared data area
+ //
+ Status =3D gBS->LocateProtocol (&gTbtNvsAreaProtocolGuid, NULL, (VOID **=
) &TbtNvsAreaProtocol);
+ ASSERT_EFI_ERROR (Status);
+ mTbtNvsAreaPtr =3D TbtNvsAreaProtocol->Area;
+
+ //
+ // Get TBT INFO HOB
+ //
+ gTbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
+ if (gTbtInfoHob =3D=3D NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ return InSmmFunction (ImageHandle, SystemTable);
+}
+
+VOID
+EndOfThunderboltCallback (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ if(mTbtNvsAreaPtr->TbtL1SubStates !=3D 0) {
+ ThunderboltEnableL1Sub (mTbtNvsAreaPtr->TbtL1SubStates, RpSegment, RpB=
us, RpDevice, RpFunction);
+ }
+ ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 1);
+ if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case
+ ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFuncti=
on);
+ } else { //Aspm enable case
+ ThunderboltEnableAspmWithoutLtr ((UINT16)mTbtNvsAreaPtr->TbtAspm, RpSe=
gment, RpBus, RpDevice, RpFunction);
+ }
+
+ if (mTbtNvsAreaPtr->TbtLtr) {
+ ThunderboltGetLatencyLtr ();
+ ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ }
+ ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 2);
+} // EndOfThunderboltCallback
+
+VOID
+ConfigureTbtAspm (
+ IN UINT8 Type,
+ IN UINT16 Aspm
+ )
+{
+ UINTN RpSegment =3D 0;
+ UINTN RpBus =3D 0;
+ UINTN RpDevice;
+ UINTN RpFunction;
+
+ if(Type =3D=3D DTBT_CONTROLLER) {
+ if (gCurrentDiscreteTbtRootPort =3D=3D 0) {
+ return;
+ }
+ GetDTbtRpDevFun(DTBT_CONTROLLER, gCurrentDiscreteTbtRootPort - 1, &RpD=
evice, &RpFunction);
+
+ ConfigureTbtPm (RpSegment, RpBus, RpDevice, RpFunction, 1);
+ if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case
+ ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFunc=
tion);
+ } else { //Aspm enable case
+ ThunderboltEnableAspmWithoutLtr ((UINT16) Aspm, RpSegment, RpBus, Rp=
Device, RpFunction);
+ }
+
+ if (mTbtNvsAreaPtr->TbtLtr) {
+ ThunderboltGetLatencyLtr ();
+ ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ }
+ ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ } // EndOfThunderboltCallback
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/=
TbtSmm.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/=
TbtSmm.inf
new file mode 100644
index 0000000000..e3fdd39816
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.=
inf
@@ -0,0 +1,80 @@
+## @file
+# Component information file for the ThunderBolt Smm module.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D TbtSmm
+ FILE_GUID =3D 5BDCD685-D80A-42E6-9867-A84CCE7F828E
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D DXE_SMM_DRIVER
+ PI_SPECIFICATION_VERSION =3D 1.10
+ ENTRY_POINT =3D TbtSmmEntryPoint
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ UefiRuntimeServicesTableLib
+ UefiBootServicesTableLib
+ IoLib
+ PciExpressLib
+ HobLib
+ ReportStatusCodeLib
+ PciSegmentLib
+ UefiLib
+ SmmServicesTableLib
+ GpioLib
+ PchInfoLib
+ TbtCommonLib
+ PchPmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+
+[Sources]
+ TbtSmiHandler.h
+ TbtSmiHandler.c
+ TbtSmm.c
+
+[Protocols]
+ gTbtNvsAreaProtocolGuid ## CONSUMES
+ gEfiSmmSxDispatch2ProtocolGuid ## CONSUMES
+ gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES
+ gEfiSmmVariableProtocolGuid ## CONSUMES
+ gDxeTbtPolicyProtocolGuid
+
+[Guids]
+ gTbtInfoHobGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+[Depex]
+ gEfiSmmBase2ProtocolGuid AND
+ gEfiSmmSxDispatch2ProtocolGuid AND
+ gEfiSmmSwDispatch2ProtocolGuid AND
+ gEfiGlobalNvsAreaProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid AND
+ gEfiVariableArchProtocolGuid AND
+ gEfiSmmVariableProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Boar=
dInitLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Boar=
dInitLib.c
new file mode 100644
index 0000000000..e8a160e2af
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLi=
b.c
@@ -0,0 +1,608 @@
+/** @file
+ Source code for the board configuration init function in DXE init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BoardInitLib.h"
+#include <Library/HobLib.h>
+#include <MemInfoHob.h>
+#include <Library/PchSerialIoLib.h>
+#include <PlatformBoardConfig.h>
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchEspiLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <TbtBoardInfo.h>
+#include <Library/CpuPlatformLib.h>
+#include <GopConfigLib.h>
+//
+// Null function for nothing GOP VBT update.
+//
+VOID
+GopVbtSpecificUpdateNull(
+ IN CHILD_STRUCT **ChildStructPtr
+);
+
+//
+// for CFL U DDR4
+//
+VOID
+CflUDdr4GopVbtSpecificUpdate(
+ IN CHILD_STRUCT **ChildStructPtr
+);
+
+/**
+ Updates DIMM slots status for Desktop,server and workstation boards
+
+**/
+VOID
+UpdateDimmPopulationConfig(
+ VOID
+ )
+{
+ MEMORY_INFO_DATA_HOB *MemInfo;
+ UINT8 Slot0;
+ UINT8 Slot1;
+ UINT8 Slot2;
+ UINT8 Slot3;
+ CONTROLLER_INFO *ControllerInfo;
+ EFI_HOB_GUID_TYPE *GuidHob;
+
+ GuidHob =3D NULL;
+ MemInfo =3D NULL;
+
+ GuidHob =3D GetFirstGuidHob (&gSiMemoryInfoDataGuid);
+ ASSERT (GuidHob !=3D NULL);
+ if (GuidHob !=3D NULL) {
+ MemInfo =3D (MEMORY_INFO_DATA_HOB *) GET_GUID_HOB_DATA (GuidHob);
+ }
+ if (MemInfo !=3D NULL) {
+ if (PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorDesktop ||
+ PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorUpServer ||
+ PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorWorkstation) {
+ ControllerInfo =3D &MemInfo->Controller[0];
+ Slot0 =3D ControllerInfo->ChannelInfo[0].DimmInfo[0].Status;
+ Slot1 =3D ControllerInfo->ChannelInfo[0].DimmInfo[1].Status;
+ Slot2 =3D ControllerInfo->ChannelInfo[1].DimmInfo[0].Status;
+ Slot3 =3D ControllerInfo->ChannelInfo[1].DimmInfo[1].Status;
+
+ //
+ // Channel 0 Channel 1
+ // Slot0 Slot1 Slot0 Slot1 - Population AIO=
board
+ // 0 0 0 0 - Invalid - In=
valid
+ // 0 0 0 1 - Valid - In=
valid
+ // 0 0 1 0 - Invalid - Va=
lid
+ // 0 0 1 1 - Valid - Va=
lid
+ // 0 1 0 0 - Valid - In=
valid
+ // 0 1 0 1 - Valid - In=
valid
+ // 0 1 1 0 - Invalid - In=
valid
+ // 0 1 1 1 - Valid - In=
valid
+ // 1 0 0 0 - Invalid - Va=
lid
+ // 1 0 0 1 - Invalid - In=
valid
+ // 1 0 1 0 - Invalid - Va=
lid
+ // 1 0 1 1 - Invalid - Va=
lid
+ // 1 1 0 0 - Valid - Va=
lid
+ // 1 1 0 1 - Valid - In=
valid
+ // 1 1 1 0 - Invalid - Va=
lid
+ // 1 1 1 1 - Valid - Va=
lid
+ //
+
+ if ((Slot0 && (Slot1 =3D=3D 0)) || (Slot2 && (Slot3 =3D=3D 0))) {
+ PcdSetBoolS (PcdDimmPopulationError, TRUE);
+ }
+ }
+ }
+}
+
+/**
+ Init Misc Platform Board Config Block.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardMiscInit (
+ IN UINT16 BoardId
+ )
+{
+// PcdSet64S (PcdFuncBoardHookPlatformSetupOverride, (UINT64) (UINTN) Boa=
rdHookPlatformSetup);
+
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdPssReadSN, TRUE);
+ PcdSet8S (PcdPssI2cSlaveAddress, 0x6E);
+ PcdSet8S (PcdPssI2cBusNumber, 0x04);
+ break;
+ default:
+ PcdSetBoolS (PcdPssReadSN, FALSE);
+ PcdSet8S (PcdPssI2cSlaveAddress, 0x6E);
+ PcdSet8S (PcdPssI2cBusNumber, 0x04);
+ break;
+ }
+
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Init Platform Board Config Block for ACPI platform.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+InitAcpiPlatformPcd (
+ IN UINT16 BoardId
+ )
+{
+ TBT_INFO_HOB *TbtInfoHob =3D NULL;
+
+ TbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
+
+ //
+ // Update OEM table ID
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ if ((TbtInfoHob !=3D NULL) && (TbtInfoHob->DTbtControllerConfig[0].D=
TbtControllerEn =3D=3D 1)) {
+ PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_',=
'c', 'm', 'u', 't', '3'));
+ } else {
+ PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_',=
'c', 'm', 'u', 'l', '3'));
+ }
+ break;
+ default:
+ PcdSet64S (PcdXhciAcpiTableSignature, 0);
+ break;
+ }
+
+ //
+ // Modify Preferred_PM_Profile field based on Board SKU's. Default is se=
t to Mobile
+ //
+ PcdSet8S (PcdPreferredPmProfile, EFI_ACPI_2_0_PM_PROFILE_MOBILE);
+
+ //
+ // Assign FingerPrint, Gnss, TouchPanel, Audio related GPIO.
+ //
+ switch(BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdFingerPrintSleepGpio, GPIO_CNL_LP_GPP_B17);
+ PcdSet32S (PcdFingerPrintIrqGpio, GPIO_CNL_LP_GPP_B16);
+ //
+ // Configure WWAN Reset pin
+ //
+ PcdSet32S (PcdGnssResetGpio, GPIO_CNL_LP_GPP_F1);
+ PcdSet32S (PcdTouchpanelIrqGpio, GPIO_CNL_LP_GPP_D10);
+ PcdSet32S (PcdTouchpadIrqGpio, GPIO_CNL_LP_GPP_B3);
+ PcdSet32S (PcdHdaI2sCodecIrqGpio, GPIO_CNL_LP_GPP_C8);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Configure GPIOs for discrete USB BT module
+ //
+ switch(BoardId) {
+
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdBtIrqGpio, GPIO_CNL_LP_GPP_C11);
+ PcdSet32S (PcdBtRfKillGpio, GPIO_CNL_LP_GPP_B4);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Board Specific Init
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS(PcdCmlURtd3TableEnable, TRUE);
+ PcdSet8S (PcdHdaI2sCodecI2cBusNumber, 0); // I2S Audio Codec conntec=
ted to I2C0
+ PcdSet8S (PcdBleUsbPortNumber, 9);
+ break;
+ default:
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Init Common Platform Board Config Block.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+InitCommonPlatformPcd (
+ IN UINT16 BoardId
+ )
+{
+ PCD64_BLOB Data64;
+
+ //
+ // Enable EC SMI# for SMI
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdEcSmiGpio, GPIO_CNL_LP_GPP_E3);
+ PcdSet32S (PcdEcLowPowerExitGpio, GPIO_CNL_LP_GPP_B23);
+ break;
+ };
+
+ //
+ // HID I2C Interrupt GPIO.
+ //
+ switch (BoardId) {
+ default:
+ // on all supported boards interrupt input is on same GPIO pad. How =
convenient.
+ PcdSet32S (PcdHidI2cIntPad, GPIO_CNL_LP_GPP_D10);
+ break;
+ }
+
+ //
+ // PS2 KB Specific Init for Sds Serial platform.
+ //
+ if (BoardId =3D=3D BoardIdCometLakeULpddr3Rvp) {
+ PcdSetBoolS (PcdDetectPs2KbOnCmdAck, TRUE);
+ } else {
+ PcdSetBoolS (PcdDetectPs2KbOnCmdAck, FALSE);
+ }
+
+ switch (BoardId) {
+ default:
+ PcdSetBoolS (PcdSpdAddressOverride, FALSE);
+ break;
+ }
+
+ //
+ // DDISelection
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdDDISelection, 1);
+ break;
+ default:
+ PcdSet8S (PcdDDISelection, 0);
+ break;
+ }
+
+ //
+ // GFX Detect
+ //
+ switch (BoardId) {
+ default:
+ // Not all the boards support GFX_CRB_DET. This is not an error.
+ Data64.BoardGpioConfig.Type =3D BoardGpioTypeNotSupported;
+ break;
+ }
+
+ PcdSet64S (PcdGfxCrbDetectGpio, Data64.Blob);
+
+ //
+ // USB Type-C
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS(PcdUsbTypeCSupport, TRUE);
+ // Discete Ports
+ PcdSet8S(PcdTypeCPortsSupported, 2);
+ // TBT Port 1 mapping and properties [TBT AIC]
+ PcdSet8S(PcdUsbTypeCPort1, 1);
+ PcdSet8S(PcdUsbTypeCPort1Pch, 5);
+ // TBT Port 2 mapping and properties [TBT AIC]
+ PcdSet8S(PcdUsbTypeCPort2, 2);
+ PcdSet8S(PcdUsbTypeCPort2Pch, 7);
+ break;
+ default:
+ PcdSetBoolS (PcdUsbTypeCSupport, FALSE);
+ break;
+ }
+
+ //
+ // Battery Present
+ //
+ switch (BoardId) {
+ default:
+ PcdSet8S (PcdBatteryPresent, BOARD_REAL_BATTERY_SUPPORTED | BOARD_VI=
RTUAL_BATTERY_SUPPORTED);
+ break;
+ }
+
+ //
+ // TS-on-DIMM temperature
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdTsOnDimmTemperature, TRUE);
+ break;
+ default:
+ PcdSetBoolS (PcdTsOnDimmTemperature, FALSE);
+ break;
+ }
+ //
+ // Real Battery 1 Control & Real Battery 2 Control
+ //
+ PcdSet8S (PcdRealBattery1Control, 1);
+ PcdSet8S (PcdRealBattery2Control, 2);
+
+ //
+ // Mipi Camera Sensor
+ //
+ PcdSetBoolS (PcdMipiCamSensor, FALSE);
+ //
+ // Mipi Camera Sensor Link Used
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdMipiCam0LinkUsed, 3);
+ PcdSet8S (PcdMipiCam1LinkUsed, 6);
+ PcdSet8S (PcdMipiCam2LinkUsed, 9);
+ PcdSet8S (PcdMipiCam3LinkUsed, 7);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // H8S2113 SIO
+ //
+ switch(BoardId) {
+ default:
+ PcdSetBoolS (PcdH8S2113SIO, FALSE);
+ break;
+ }
+
+
+ //
+ // NCT6776F COM, SIO & HWMON
+ //
+ PcdSetBoolS (PcdNCT6776FCOM, FALSE);
+ PcdSetBoolS (PcdNCT6776FSIO, FALSE);
+ PcdSetBoolS (PcdNCT6776FHWMON, FALSE);
+
+ //
+ // SMC Runtime Sci Pin
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdSmcRuntimeSciPin, (UINT32) GPIO_CNL_LP_GPP_E16);
+ break;
+ default:
+ PcdSet32S (PcdSmcRuntimeSciPin, 0x00);
+ break;
+ }
+
+ //
+ // Convertable Dock Support
+ //
+ switch (BoardId) {
+ default:
+ PcdSetBoolS (PcdConvertableDockSupport, FALSE);
+ break;
+ }
+
+ //
+ // Ec Hotkey F3, F4, F5, F6, F7 and F8 Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdEcHotKeyF3Support, 1);
+ PcdSet8S (PcdEcHotKeyF4Support, 1);
+ PcdSet8S (PcdEcHotKeyF5Support, 1);
+ PcdSet8S (PcdEcHotKeyF6Support, 1);
+ PcdSet8S (PcdEcHotKeyF7Support, 1);
+ PcdSet8S (PcdEcHotKeyF8Support, 1);
+ break;
+ default:
+ PcdSet8S (PcdEcHotKeyF3Support, 0);
+ PcdSet8S (PcdEcHotKeyF4Support, 0);
+ PcdSet8S (PcdEcHotKeyF5Support, 0);
+ PcdSet8S (PcdEcHotKeyF6Support, 0);
+ PcdSet8S (PcdEcHotKeyF7Support, 0);
+ PcdSet8S (PcdEcHotKeyF8Support, 0);
+ break;
+ }
+
+ //
+ // Virtual Button Volume Up & Done Support
+ // Virtual Button Home Button Support
+ // Virtual Button Rotation Lock Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, TRUE);
+ PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, TRUE);
+ PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, FALSE);
+ PcdSetBoolS (PcdVirtualButtonRotationLockSupport, FALSE);
+ break;
+ default:
+ PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, FALSE);
+ PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, FALSE);
+ PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, FALSE);
+ PcdSetBoolS (PcdVirtualButtonRotationLockSupport, FALSE);
+ break;
+ }
+
+ //
+ // Slate Mode Switch Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdSlateModeSwitchSupport, TRUE);
+ break;
+ default:
+ PcdSetBoolS (PcdSlateModeSwitchSupport, FALSE);
+ break;
+ }
+
+ //
+ // Ac Dc Auto Switch Support
+ //
+ switch (BoardId) {
+ default:
+ PcdSetBoolS (PcdAcDcAutoSwitchSupport, TRUE);
+ break;
+ }
+
+ //
+ // Pm Power Button Gpio Pin
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdPmPowerButtonGpioPin, (UINT32) GPIO_CNL_LP_GPD3);
+ break;
+ default:
+ PcdSet32S (PcdPmPowerButtonGpioPin, 0x00);
+ break;
+ }
+
+ //
+ // Acpi Enable All Button Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdAcpiEnableAllButtonSupport, TRUE);
+ break;
+ default:
+ PcdSetBoolS (PcdAcpiEnableAllButtonSupport, FALSE);
+ break;
+ }
+
+ //
+ // Acpi Hid Driver Button Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdAcpiHidDriverButtonSupport, TRUE);
+ break;
+ default:
+ PcdSetBoolS (PcdAcpiHidDriverButtonSupport, FALSE);
+ break;
+ }
+
+ //
+ // USB Type C EC less
+ //
+ switch (BoardId) {
+ default:
+ PcdSetBoolS (PcdUsbTypeCEcLess, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Check if given rootport has device connected and enable wake capability
+
+ @param[in] RpNum An unsigned integer represent the root port =
number.
+
+ @retval TRUE if endpoint was connected
+ @retval FALSE if no endpoint was detected
+**/
+BOOLEAN
+IsPcieEndPointPresent (
+ IN UINT8 RpNum
+ )
+{
+ EFI_STATUS Status;
+ UINTN RpDev;
+ UINTN RpFun;
+ UINT64 RpBaseAddress;
+
+ Status =3D GetPchPcieRpDevFun (RpNum, &RpDev, &RpFun);
+ if (!EFI_ERROR (Status)) {
+ //
+ // check if device is present
+ //
+ RpBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ RpDev,
+ RpFun,
+ 0
+ );
+
+ if ((PciSegmentRead16 (RpBaseAddress) !=3D 0xFFFF) &&
+ (PciSegmentRead16 (RpBaseAddress + R_PCH_PCIE_CFG_SLSTS) & B_PCIE_=
SLSTS_PDS)) {
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+
+}
+
+/**
+ Enable Tier2 GPIO Sci wake capability.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+Tier2GpioWakeSupport (
+ IN UINT16 BoardId
+ )
+{
+ BOOLEAN Tier2GpioWakeEnable;
+
+ Tier2GpioWakeEnable =3D FALSE;
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ //
+ // Root port #14: M.2 WLAN
+ //
+ if (IsPcieEndPointPresent (13)) {
+ Tier2GpioWakeEnable =3D TRUE;
+ }
+ break;
+ default:
+ break;
+ }
+ PcdSetBoolS (PcdGpioTier2WakeEnable, Tier2GpioWakeEnable);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board configuration init function for DXE phase.
+
+ @param Content pointer to the buffer contain init information for boar=
d init.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+BoardConfigInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT16 BoardId;
+
+ BoardId =3D BoardIdCometLakeULpddr3Rvp;
+
+ Status =3D InitAcpiPlatformPcd (BoardId);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D InitCommonPlatformPcd (BoardId);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D BoardMiscInit (BoardId);
+ ASSERT_EFI_ERROR(Status);
+
+ Status =3D Tier2GpioWakeSupport (BoardId);
+ ASSERT_EFI_ERROR(Status);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Boar=
dInitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Boar=
dInitLib.h
new file mode 100644
index 0000000000..f2eb75b9f3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLi=
b.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for board Init function for DXE Init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_BOARD_INIT_LIB_H_
+#define _DXE_BOARD_INIT_LIB_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+#include <Register/PchRegs.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Platform.h>
+
+EFI_STATUS
+EFIAPI
+BoardConfigInit (
+ VOID
+ );
+
+#endif // _DXE_BOARD_INIT_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuP=
olicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/=
CpuPolicyInitDxe.c
new file mode 100644
index 0000000000..0d58b73063
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyIn=
itDxe.c
@@ -0,0 +1,46 @@
+/** @file
+ This file is SampleCode for Intel Silicon DXE Platform Policy initialzat=
ion.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <CpuPolicyInitDxe.h>
+
+DXE_CPU_POLICY_PROTOCOL mCpuPolicyData;
+
+/**
+ Initialize Intel CPU DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize=
the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ ZeroMem(&mCpuPolicyData, sizeof (DXE_CPU_POLICY_PROTOCOL));
+ mCpuPolicyData.Revision =3D DXE_CPU_POLICY_PROTO=
COL_REVISION;
+
+ UpdateDxeSiCpuPolicy(&mCpuPolicyData);
+
+ //
+ // Install CpuInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So ple=
ase
+ // update and override any setting before calling this function.
+ //
+ Status =3D CpuInstallPolicyProtocol(ImageHandle, &mCpuPolicyData);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuP=
olicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/=
CpuPolicyInitDxe.h
new file mode 100644
index 0000000000..0857ca6f0e
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyIn=
itDxe.h
@@ -0,0 +1,38 @@
+/** @file
+ Header file for the SiliconPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_POLICY_INIT_DXE_H_
+#define _CPU_POLICY_INIT_DXE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+#include <Protocol/CpuPolicyProtocol.h>
+#include <Library/DxeCpuPolicyUpdateLib.h>
+
+
+/**
+ Initialize Intel CPU DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this drive=
r.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali=
ze the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopP=
olicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/=
GopPolicyInitDxe.c
new file mode 100644
index 0000000000..7dcae32069
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyIn=
itDxe.c
@@ -0,0 +1,174 @@
+/** @file
+ This file initialises and Installs GopPolicy Protocol.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "GopPolicyInitDxe.h"
+#include <Protocol/GopPolicy.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize =3D 0;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress =3D 0;
+
+//
+// Function implementations
+//
+
+/**
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+
+ @param[out] CurrentDockStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+EFI_STATUS
+EFIAPI
+GetPlatformDockStatus (
+ OUT DOCK_STATUS CurrentDockStatus
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+
+ @param[out] VbtAddress
+ @param[out] VbtSize
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+**/
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_STATUS Status;
+ UINTN FvProtocolCount;
+ EFI_HANDLE *FvHandles;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ UINTN Index;
+ UINT32 AuthenticationStatus;
+ UINT8 *Buffer;
+ UINTN VbtBufferSize;
+
+ Status =3D EFI_NOT_FOUND;
+ if ( mVbtAddress =3D=3D 0) {
+ Fv =3D NULL;
+ Buffer =3D 0;
+ FvHandles =3D NULL;
+ Status =3D gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &FvProtocolCount,
+ &FvHandles
+ );
+ if (!EFI_ERROR (Status)) {
+ for (Index =3D 0; Index < FvProtocolCount; Index++) {
+ Status =3D gBS->HandleProtocol (
+ FvHandles[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &Fv
+ );
+ VbtBufferSize =3D 0;
+ Status =3D Fv->ReadSection (
+ Fv,
+ PcdGetPtr(PcdIntelGraphicsVbtFileGuid),
+ EFI_SECTION_RAW,
+ 0,
+ (VOID **) &Buffer,
+ &VbtBufferSize,
+ &AuthenticationStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ *VbtAddress =3D (EFI_PHYSICAL_ADDRESS)Buffer;
+ *VbtSize =3D (UINT32)VbtBufferSize;
+ mVbtAddress =3D *VbtAddress;
+ mVbtSize =3D *VbtSize;
+ Status =3D EFI_SUCCESS;
+ break;
+ }
+ }
+ } else {
+ Status =3D EFI_NOT_FOUND;
+ }
+
+ if (FvHandles !=3D NULL) {
+ FreePool (FvHandles);
+ FvHandles =3D NULL;
+ }
+ } else {
+ *VbtAddress =3D mVbtAddress;
+ *VbtSize =3D mVbtSize;
+ Status =3D EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+/**
+Initialize GOP DXE Policy
+
+@param[in] ImageHandle Image handle of this driver.
+
+@retval EFI_SUCCESS Initialization complete.
+@retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize=
the driver.
+@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Initialize the EFI Driver Library
+ //
+ SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);
+
+ mGOPPolicy.Revision =3D GOP_POLICY_PROTOCOL_REVISION_03;
+ mGOPPolicy.GetPlatformLidStatus =3D GetPlatformLidStatus;
+ mGOPPolicy.GetVbtData =3D GetVbtData;
+ mGOPPolicy.GetPlatformDockStatus =3D GetPlatformDockStatus;
+
+ //
+ // Install protocol to allow access to this Policy.
+ //
+ Status =3D gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gGopPolicyProtocolGuid,
+ &mGOPPolicy,
+ NULL
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopP=
olicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/=
GopPolicyInitDxe.h
new file mode 100644
index 0000000000..0c90e68d38
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyIn=
itDxe.h
@@ -0,0 +1,41 @@
+/** @file
+Header file for the GopPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GOP_POLICY_INIT_DXE_H_
+#define _GOP_POLICY_INIT_DXE_H_
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+#include <Library/PcdLib.h>
+
+/**
+Initialize GOP DXE Policy
+
+@param[in] ImageHandle Image handle of this driver.
+
+@retval EFI_SUCCESS Initialization complete.
+@retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize=
the driver.
+@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe(
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchP=
olicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/=
PchPolicyInitDxe.c
new file mode 100644
index 0000000000..9de7d6b446
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyIn=
itDxe.c
@@ -0,0 +1,55 @@
+/** @file
+ This file is SampleCode for PCH DXE Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PchPolicyInitDxe.h"
+
+//
+// Function implementations
+//
+
+/**
+ Initialize PCH DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali=
ze the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+PchPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ PCH_POLICY_PROTOCOL *PchPolicy;
+
+ //
+ // Call CreatePchDxeConfigBlocks to create & initialize platform policy =
structure
+ // and get all Intel default policy settings.
+ //
+ Status =3D CreatePchDxeConfigBlocks (&PchPolicy);
+ DEBUG((DEBUG_INFO, "PchPolicy->TableHeader.NumberOfBlocks =3D 0x%x\n", P=
chPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR (Status);
+
+ if (mFirmwareConfiguration !=3D FwConfigDefault) {
+ UpdateDxePchPolicy (PchPolicy);
+ }
+
+ //
+ // Install PchInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So ple=
ase
+ // update and override any setting before calling this function.
+ //
+ Status =3D PchInstallPolicyProtocol (ImageHandle, PchPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchP=
olicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/=
PchPolicyInitDxe.h
new file mode 100644
index 0000000000..479e7434e3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyIn=
itDxe.h
@@ -0,0 +1,52 @@
+/** @file
+ Header file for the PchPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_POLICY_INIT_DXE_H_
+#define _PCH_POLICY_INIT_DXE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <FirwmareConfigurations.h>
+#include <Protocol/PchPolicy.h>
+#include <Library/DxePchPolicyLib.h>
+#include <Library/DxePchPolicyUpdateLib.h>
+
+extern UINT8 mFirmwareConfiguration;
+
+/**
+ <b>PCH DXE Policy Driver Entry Point</b> \n
+ - <b>Introduction</b> \n
+ Pch DXE drivers behavior can be controlled by platform policy without =
modifying reference code directly.
+ Platform policy Protocol is initialized with default settings in this =
funciton.
+ This policy Protocol has to be initialized prior to PCH initialization=
DXE drivers execution.
+
+ - @pre
+ - Runtime variable service should be ready if policy initialization re=
quired.
+
+ - @result
+ PCH_POLICY_PROTOCOL will be installed successfully and ready for Pch r=
eference code use.
+
+ - <b>Porting Recommendations</b> \n
+ Policy should be initialized basing on platform design or user selecti=
on (like BIOS Setup Menu)
+
+ @param[in] ImageHandle - Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize=
the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+PchPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Poli=
cyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Pol=
icyInitDxe.c
new file mode 100644
index 0000000000..27bd7fb9ae
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitD=
xe.c
@@ -0,0 +1,88 @@
+/** @file
+ This file is a wrapper for Platform Policy driver. Get Setup
+ Value to initialize Intel DXE Platform Policy.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PolicyInitDxe.h"
+#include <CpuSmm.h>
+#include "BoardInitLib.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mFirmwareConfiguration =3D =
0;
+
+/**
+ Initialize DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SystemTable Global system service table.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize=
the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+PolicyInitDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status =3D BoardConfigInit();
+
+ mFirmwareConfiguration =3D FwConfigProduction;
+ //
+ // SystemAgent Dxe Platform Policy Initialization
+ //
+ Status =3D SaPolicyInitDxe (ImageHandle);
+ DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization done=
\n"));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // PCH Dxe Platform Policy Initialization
+ //
+ Status =3D PchPolicyInitDxe (ImageHandle);
+ DEBUG ((DEBUG_INFO, "PCH Dxe Platform Policy Initialization done\n"));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Silicon Dxe Platform Policy Initialization
+ //
+ Status =3D SiliconPolicyInitDxe (ImageHandle);
+ DEBUG ((DEBUG_INFO, "Silicon Dxe Platform Policy Initialization done\n")=
);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // CPU DXE Platform Policy Initialization
+ //
+ Status =3D CpuPolicyInitDxe (ImageHandle);
+ DEBUG ((DEBUG_INFO, "Cpu Dxe Platform Policy Initialization done\n"));
+ ASSERT_EFI_ERROR (Status);
+
+
+ if (PcdGetBool(PcdIntelGopEnable)) {
+ //
+ // GOP Dxe Policy Initialization
+ //
+ Status =3D GopPolicyInitDxe(ImageHandle);
+ DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
+ ASSERT_EFI_ERROR(Status);
+ }
+ if (PcdGetBool(PcdTbtEnable)) {
+ //
+ // Update TBT Policy
+ //
+ Status =3D InstallTbtPolicy (ImageHandle);
+ DEBUG ((DEBUG_INFO, "Install Tbt Policy done\n"));
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ return Status;
+
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Poli=
cyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Pol=
icyInitDxe.h
new file mode 100644
index 0000000000..5a03dff12e
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitD=
xe.h
@@ -0,0 +1,45 @@
+/** @file
+ Header file for the PolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _POLICY_INIT_DXE_H_
+#define _POLICY_INIT_DXE_H_
+
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+#include "SaPolicyInitDxe.h"
+#include "PchPolicyInitDxe.h"
+#include "SiliconPolicyInitDxe.h"
+#include "GopPolicyInitDxe.h"
+#include "CpuPolicyInitDxe.h"
+
+#include <Library/DxeTbtPolicyLib.h>
+/**
+ Initialize DXE Platform Policy
+
+ @param[in] ImageHandle - Image handle of this driver.
+ @param[in] SystemTable - Global system service table.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driv=
er.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize=
the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+
+EFI_STATUS
+EFIAPI
+PolicyInitDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Poli=
cyInitDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/P=
olicyInitDxe.inf
new file mode 100644
index 0000000000..1d09b990b1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitD=
xe.inf
@@ -0,0 +1,176 @@
+## @file
+# Module Information file for the PolicyInit DXE driver.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x00010017
+ BASE_NAME =3D PolicyInitDxe
+ FILE_GUID =3D 490D0119-4448-440D-8F5C-F58FB53EE057
+ VERSION_STRING =3D 1.0
+ MODULE_TYPE =3D DXE_DRIVER
+ ENTRY_POINT =3D PolicyInitDxeEntryPoint
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ CpuPlatformLib
+ DebugLib
+ DxeServicesTableLib
+ IoLib
+ MemoryAllocationLib
+ DxeSaPolicyLib
+ DxePchPolicyLib
+ PcdLib
+ DxePolicyBoardConfigLib
+ DxePolicyUpdateLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ UefiRuntimeServicesTableLib
+ ConfigBlockLib
+ DevicePathLib
+ DxeTbtPolicyLib
+ PchPcieRpLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ##=
CONSUMES
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ##=
CONSUMES
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ##=
CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable
+ gSiPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable ##=
CONSUMES
+ gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable ##=
CONSUMES
+ gSiPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication ##=
CONSUMES
+ gSiPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication ##=
CONSUMES
+ gSiPkgTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication ##=
CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support
+
+ #
+ # PSS Board Configuration.
+ #
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed
+ gPlatformModuleTokenSpaceGuid.PcdH8S2113Present
+ gPlatformModuleTokenSpaceGuid.PcdNat87393Present
+ gPlatformModuleTokenSpaceGuid.PcdNct677FPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCmlURtd3TableEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate
+
+[Sources]
+ PolicyInitDxe.c
+ SaPolicyInitDxe.c
+ SiliconPolicyInitDxe.c
+ GopPolicyInitDxe.c
+ PchPolicyInitDxe.c
+ CpuPolicyInitDxe.c
+ BoardInitLib.c
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gDxeMePolicyGuid ## PRODUCES
+ gSaPolicyProtocolGuid ## CONSUMES
+ gPchPolicyProtocolGuid ## CONSUMES
+ gDxeSiPolicyProtocolGuid ## PRODUCES
+ gGopPolicyProtocolGuid ## PRODUCES
+ gDxeCpuPolicyProtocolGuid ## PRODUCES
+
+[Guids]
+ gCpuSmmGuid ## CONSUMES
+ gSiMemoryInfoDataGuid
+
+[Depex]
+ gEfiVariableArchProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPo=
licyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/S=
aPolicyInitDxe.c
new file mode 100644
index 0000000000..4cef26d297
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyIni=
tDxe.c
@@ -0,0 +1,60 @@
+/** @file
+ This file is SampleCode for SA DXE Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "SaPolicyInitDxe.h"
+
+
+//
+// Function implementations
+//
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this drive=
r.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali=
ze the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaPolicy;
+
+ //
+ // Call CreateSaDxeConfigBlocks to create & initialize platform policy s=
tructure
+ // and get all Intel default policy settings.
+ //
+ Status =3D CreateSaDxeConfigBlocks(&SaPolicy);
+ DEBUG((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks =3D 0x%x\n ", S=
aPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR(Status);
+
+ UpdateDxeSaPolicyBoardConfig (SaPolicy);
+
+ if (mFirmwareConfiguration !=3D FwConfigDefault) {
+
+ UpdateDxeSaPolicy (SaPolicy);
+ }
+
+ //
+ // Install SaInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So ple=
ase
+ // update and override any setting before calling this function.
+ //
+ Status =3D SaInstallPolicyProtocol (ImageHandle, SaPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPo=
licyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/S=
aPolicyInitDxe.h
new file mode 100644
index 0000000000..c9f042b40a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyIni=
tDxe.h
@@ -0,0 +1,56 @@
+/** @file
+ Header file for the SaPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SA_POLICY_INIT_DXE_H_
+#define _SA_POLICY_INIT_DXE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <FirwmareConfigurations.h>
+#include <Protocol/SaPolicy.h>
+#include <Library/DxeSaPolicyLib.h>
+#include <Library/DxePolicyBoardConfigLib.h>
+#include <Library/DxeSaPolicyUpdateLib.h>
+
+#include <SaAccess.h>
+
+extern UINT8 mFirmwareConfiguration;
+
+/**
+ <b>SA DXE Policy Driver Entry Point</b> \n
+ - <b>Introduction</b> \n
+ System Agent DXE drivers behavior can be controlled by platform policy=
without modifying reference code directly.
+ Platform policy Protocol is initialized with default settings in this =
funciton.
+ This policy Protocol has to be initialized prior to System Agent initi=
alization DXE drivers execution.
+
+ - @pre
+ - Runtime variable service should be ready if policy initialization re=
quired.
+
+ - @result
+ SA_POLICY_PROTOCOL will be installed successfully and ready for System=
Agent reference code use.
+
+ - <b>Porting Recommendations</b> \n
+ Policy should be initialized basing on platform design or user selecti=
on (like BIOS Setup Menu)
+
+ @param[in] ImageHandle - Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize=
the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Sili=
conPolicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInit=
Dxe/SiliconPolicyInitDxe.c
new file mode 100644
index 0000000000..24e165f645
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPoli=
cyInitDxe.c
@@ -0,0 +1,46 @@
+/** @file
+ This file is SampleCode for Intel Silicon DXE Platform Policy initialzat=
ion.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <SiliconPolicyInitDxe.h>
+#include <Library/BaseLib.h>
+
+DXE_SI_POLICY_PROTOCOL mSiPolicyData =3D { 0 };
+
+/**
+ Initilize Intel Cpu DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize=
the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ mSiPolicyData.Revision =3D DXE_SI_POLICY_PROTOCO=
L_REVISION;
+
+ ///
+ /// Install the DXE_SI_POLICY_PROTOCOL interface
+ ///
+ Status =3D gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gDxeSiPolicyProtocolGuid,
+ &mSiPolicyData,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Sili=
conPolicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInit=
Dxe/SiliconPolicyInitDxe.h
new file mode 100644
index 0000000000..1324ad0808
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPoli=
cyInitDxe.h
@@ -0,0 +1,37 @@
+/** @file
+ Header file for the SiliconPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SILICON_POLICY_INIT_DXE_H_
+#define _SILICON_POLICY_INIT_DXE_H_
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Guid/StatusCodeDataTypeId.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+#include <Protocol/SiPolicyProtocol.h>
+
+/**
+ Initilize Intel CPU DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this dr=
iver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali=
ze the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
--=20
2.16.2.windows.1
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From: "Kathappan Esakkithevar" <kathappan.esakkithevar@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
Chasel Chiu <chasel.chiu@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>,
Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>,
Prince Agyeman <prince.agyeman@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 6/7]
CometlakeOpenBoardPkg/CometlakeURvp: Add DSC and build files
Date: Wed, 12 Feb 2020 00:42:40 +0530
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280
Adds the DSC and build files necessary to build the
CometlakeURvp board instance.
Key files
=3D=3D=3D=3D=3D=3D=3D=3D=3D
* build_config.cfg - Board-specific build configuration file.
* OpenBoardPkg.dsc - The CometlakeURvp board description file.
* OpenBoardPkgPcd.dsc - Used for other PCD customization.
* OpenBoardPkg.fdf - The CometlakeURvp board flash file.
* OpenBoardPkgBuildOption.dsc - Sets build options Based
on PCD values.
Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
---
.../CometlakeURvp/OpenBoardPkg.dsc | 454 +++++++++++++
.../CometlakeURvp/OpenBoardPkg.fdf | 702 +++++++++++++++++=
++++
.../CometlakeURvp/OpenBoardPkgBuildOption.dsc | 154 +++++
.../CometlakeURvp/OpenBoardPkgPcd.dsc | 404 ++++++++++++
.../CometlakeURvp/build_config.cfg | 34 +
5 files changed, 1748 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Open=
BoardPkg.dsc
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Open=
BoardPkg.fdf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Open=
BoardPkgBuildOption.dsc
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Open=
BoardPkgPcd.dsc
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/buil=
d_config.cfg
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPk=
g.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
new file mode 100644
index 0000000000..14e82ba34d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
@@ -0,0 +1,454 @@
+## @file
+# The main build description file for the CometlakeURvp board.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg
+ DEFINE PLATFORM_SI_PACKAGE =3D CoffeelakeSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE =3D CoffeelakeSiliconBinPkg
+ DEFINE PLATFORM_FSP_BIN_PACKAGE =3D CometLakeFspBinPkg/CometLake1
+ DEFINE PLATFORM_BOARD_PACKAGE =3D CometlakeOpenBoardPkg
+ DEFINE BOARD =3D CometlakeURvp
+ DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE)/$(BO=
ARD)
+ DEFINE PEI_ARCH =3D IA32
+ DEFINE DXE_ARCH =3D X64
+ DEFINE TOP_MEMORY_ADDRESS =3D 0x0
+
+ #
+ # Default value for OpenBoardPkg.fdf use
+ #
+ DEFINE BIOS_SIZE_OPTION =3D SIZE_70
+
+ PLATFORM_NAME =3D $(PLATFORM_PACKAGE)
+ PLATFORM_GUID =3D 84D0F5BD-0EF3-4CC0-9B09-F2D0F2=
AA5C5E
+ PLATFORM_VERSION =3D 0.1
+ DSC_SPECIFICATION =3D 0x00010005
+ OUTPUT_DIRECTORY =3D Build/$(PROJECT)
+ SUPPORTED_ARCHITECTURES =3D IA32|X64
+ BUILD_TARGETS =3D DEBUG|RELEASE
+ SKUID_IDENTIFIER =3D ALL
+
+ FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf
+ FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0
+
+ #
+ # Include PCD configuration for this board.
+ #
+ !include AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorka=
round.dsc
+ !include OpenBoardPkgPcd.dsc
+ !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
+
+##########################################################################=
######
+#
+# SKU Identification section - list of all SKU IDs supported by this board.
+#
+##########################################################################=
######
+[SkuIds]
+ 0|DEFAULT # 0|DEFAULT is reserved and always required.
+ 0x1|CometlakeURvp
+
+##########################################################################=
######
+#
+# Includes section - other DSC file contents included for this board build.
+#
+##########################################################################=
######
+
+#######################################
+# Library Includes
+#######################################
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
+
+#######################################
+# Component Includes
+#######################################
+# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bugzi=
lla.tianocore.org/show_bug.cgi?id=3D2308
+# is completed
+[Components.IA32]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
+
+# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi=
lla.tianocore.org/show_bug.cgi?id=3D2308
+# is completed
+[Components.X64]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
+
+#######################################
+# Build Option Includes
+#######################################
+!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
+!include OpenBoardPkgBuildOption.dsc
+
+##########################################################################=
######
+#
+# Library Class section - list of all Library Classes needed by this board.
+#
+##########################################################################=
######
+
+[LibraryClasses.common]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs=
pWrapperApiLib.inf
+ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib=
/PeiFspWrapperApiTestLib.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc=
kLib.inf
+ MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPci=
Lib.inf
+ PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDxe=
SmmPchHsioLib.inf
+ PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSm=
mPchPmcLib.inf
+
+ #####################################
+ # Platform Package
+ #####################################
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B=
oardInitLibNull.inf
+ FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra=
pperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp=
erPlatformLib/PeiFspWrapperPlatformLib.inf
+ PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/=
PciHostBridgeLibSimple.inf
+ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl=
e/PciSegmentInfoLibSimple.inf
+ PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
+ PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa=
nagerLib/DxePlatformBootManagerLib.inf
+ ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR=
eportFvLib.inf
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull=
/TestPointCheckLibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba=
seGpioExpanderLib.inf
+ HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLib/Pei=
HdaVerbTableLib.inf
+ I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc=
essLib.inf
+ PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatf=
ormSecLib/SecFspWrapperPlatformSecLib.inf
+ TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib=
.inf
+ # Thunderbolt
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE
+ TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt=
CommonLib/TbtCommonLib.inf
+!endif
+
+ #######################################
+ # Board-specific
+ #######################################
+ PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL=
ib.inf
+
+[LibraryClasses.IA32.SEC]
+ #######################################
+ # Platform Package
+ #######################################
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec=
TestPointCheckLib.inf
+ SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib=
Null/SecBoardInitLibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspPolicyInitLib.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiS=
iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+ TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib=
.inf
+
+[LibraryClasses.common.PEIM]
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic=
onInitLib.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp=
ortLib/PeiMultiBoardInitSupportLib.inf
+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp=
erPlatformLib/PeiFspWrapperPlatformLib.inf
+ MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB=
oardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL=
ib.inf
+!if $(TARGET) =3D=3D DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei=
TestPointCheckLib.inf
+!endif
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrr=
LibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ # Thunderbolt
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE
+ PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe=
iDTbtInitLib/PeiDTbtInitLib.inf
+ PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol=
icyLib/PeiTbtPolicyLib.inf
+!endif
+ PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyInitL=
ib/PeiPolicyInitLib.inf
+ PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyUpd=
ateLib/PeiPolicyUpdateLib.inf
+ SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspPolicyInitLib.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiS=
iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+ TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib=
.inf
+
+ #######################################
+ # Board-specific
+ #######################################
+ PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHook=
lib.inf
+ PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/PeiPo=
licyBoardConfigLib.inf
+
+!if $(TARGET) =3D=3D DEBUG
+ GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseGpi=
oCheckConflictLib.inf
+!else
+ GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/Bas=
eGpioCheckConflictLibNull.inf
+!endif
+
+[LibraryClasses.common.DXE_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport=
Lib/DxeMultiBoardAcpiSupportLib.inf
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp=
ortLib/DxeMultiBoardInitSupportLib.inf
+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp=
erPlatformLib/DxeFspWrapperPlatformLib.inf
+ MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi=
SupportLib/DxeMultiBoardAcpiSupportLib.inf
+ MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB=
oardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL=
ib.inf
+
+!if $(TARGET) =3D=3D DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe=
TestPointCheckLib.inf
+!endif
+
+ #######################################
+ # Board Package
+ #######################################
+ DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolicyUpd=
ateLib/DxePolicyUpdateLib.inf
+ DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol=
icyLib/DxeTbtPolicyLib.inf
+
+ #######################################
+ # Board-specific
+ #######################################
+ DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxePo=
licyBoardConfigLib.inf
+
+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL=
ib/DxeRuntimeResetSystemLib.inf
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLi=
b/SmmSpiFlashCommonLib.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor=
tLib/SmmMultiBoardAcpiSupportLib.inf
+ MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi=
SupportLib/SmmMultiBoardAcpiSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL=
ib.inf
+!if $(TARGET) =3D=3D DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm=
TestPointCheckLib.inf
+!endif
+
+#######################################
+# PEI Components
+#######################################
+# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bugzi=
lla.tianocore.org/show_bug.cgi?id=3D2308
+# is completed
+[Components.IA32]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ UefiCpuPkg/SecCore/SecCore.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+
+ #
+ # In FSP API mode the policy has to be installed before FSP Wrapper upda=
ting UPD.
+ # Add policy as dependency for FSP Wrapper
+ #
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
+ IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp=
lePei.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+ !if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D=
FALSE
+ BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib=
.inf
+ !else
+ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+ !endif
+ NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
+ }
+
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf=
{
+ <LibraryClasses>
+ !if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D=
FALSE
+ BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLi=
b.inf
+ !else
+ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i=
nf
+ !endif
+ }
+
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem=
.inf {
+ <LibraryClasses>
+ SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Silico=
nPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Sili=
conPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ }
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe=
m.inf {
+ <LibraryClasses>
+ SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Silico=
nPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Sili=
conPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ }
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE
+ $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+
+ #######################################
+ # Board Package
+ #######################################
+ # Thunderbolt
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
+!endif
+ $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
+
+#######################################
+# DXE Components
+#######################################
+# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi=
lla.tianocore.org/show_bug.cgi?id=3D2308
+# is completed
+[Components.X64]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
+ MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{
+ <LibraryClasses>
+ NULL|BoardModulePkg/Library/BdsPs2KbcLib/BdsPs2KbcLib.inf
+ }
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ <LibraryClasses>
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma=
ndsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma=
ndsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma=
ndsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com=
mandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1C=
ommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma=
ndsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C=
ommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C=
ommandsLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand=
Lib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePars=
ingLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg=
CommandLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib=
.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ }
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE
+ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
+ <PcdsPatchableInModule>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
+ <LibraryClasses>
+ !if $(TARGET) =3D=3D DEBUG
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialP=
ort.inf
+ !endif
+ }
+!endif
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
+ $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+ $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf {
+ <LibraryClasses>
+ SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli=
cyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPo=
licyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ }
+ $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
+ $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE
+ $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE
+
+ $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+
+ $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+ !if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D=
FALSE
+ BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna=
bleLib.inf
+ !else
+ NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i=
nf
+ !endif
+ }
+
+ $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+
+!endif
+
+ #######################################
+ # Board Package
+ #######################################
+ $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{
+ <LibraryClasses>
+ NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
+ }
+
+ # Thunderbolt
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
+ $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE
+ $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
+!endif
+ BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPk=
g.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
new file mode 100644
index 0000000000..e2d40bcbb6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
@@ -0,0 +1,702 @@
+## @file
+# FDF file of Platform.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
+
+##########################################################################=
######
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+##########################################################################=
######
+[FD.CometlakeURvp]
+#
+# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, c=
annot be
+# assigned with PCD values. Instead, it uses the definitions for its varie=
ty, which
+# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
+#
+BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddr=
ess #The base address of the FLASH Device.
+Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize =
#The size in bytes of the FLASH Device
+ErasePolarity =3D 1
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+NumBlocks =3D $(FLASH_NUM_BLOCKS)
+
+DEFINE SIPKG_DXE_SMM_BIN =3D INF
+DEFINE SIPKG_PEI_BIN =3D INF
+
+# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macr=
o expression is not supported.
+# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to =
get the real CodeCache base address.
+SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenSpa=
ceGuid.PcdFlashFvPreMemoryOffset)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui=
d.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffse=
t)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui=
d.PcdFlashMicrocodeFvSize)
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke=
nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT=
okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP=
kgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashM=
icrocodeFvOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g=
SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok=
enSpaceGuid.PcdFlashMicrocodeFvBase
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok=
enSpaceGuid.PcdFlashMicrocodeFvSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok=
enSpaceGuid.PcdFlashMicrocodeFvOffset
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok=
enSpaceGuid.PcdBiosAreaBaseAddress
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok=
enSpaceGuid.PcdBiosSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgT=
okenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pcd=
FlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgT=
okenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pcd=
FlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgT=
okenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pcd=
FlashFvFspSOffset)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok=
enSpaceGuid.PcdBiosAreaBaseAddress
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok=
enSpaceGuid.PcdBiosSize
+##########################################################################=
######
+#
+# Following are lists of FD Region layout which correspond to the location=
s of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" requir=
ed) followed by
+# the pipe "|" character, followed by the size of the region, also in hex =
with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+# Fv Size can be adjusted
+#
+##########################################################################=
######
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModul=
ePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule=
PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA =3D {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x40000
+ 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
+ #Signature "_FVH" #Attributes
+ 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+ #
+ # Be careful on CheckSum field.
+ #
+ 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
+ #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
+ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ #Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE
+ # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, 0x=
439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+ # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x98,=
0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+ #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable=
Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x1DFB8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xDF, 0x01, 0x00,
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeMod=
ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu=
lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA =3D {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl=
ockSignatureGuid =3D
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0=
x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res=
erved
+ 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModul=
ePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule=
PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgToke=
nSpaceGuid.PcdFlashFvAdvancedSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenS=
paceGuid.PcdFlashFvAdvancedSize
+FV =3D FvAdvanced
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgToke=
nSpaceGuid.PcdFlashFvSecuritySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenS=
paceGuid.PcdFlashFvSecuritySize
+FV =3D FvSecurity
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenS=
paceGuid.PcdFlashFvOsBootSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpa=
ceGuid.PcdFlashFvOsBootSize
+FV =3D FvOsBoot
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgToke=
nSpaceGuid.PcdFlashFvUefiBootSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenS=
paceGuid.PcdFlashFvUefiBootSize
+FV =3D FvUefiBoot
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTo=
kenSpaceGuid.PcdFlashFvPostMemorySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke=
nSpaceGuid.PcdFlashFvPostMemorySize
+FV =3D FvPostMemory
+
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFla=
shMicrocodeFvSize
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlash=
MicrocodeFvSize
+#Microcode
+FV =3D FvMicrocode
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpa=
ceGuid.PcdFlashFvFspSSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpace=
Guid.PcdFlashFvFspSSize
+# FSP_S Section
+FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpa=
ceGuid.PcdFlashFvFspMSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpace=
Guid.PcdFlashFvFspMSize
+# FSP_M Section
+FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpa=
ceGuid.PcdFlashFvFspTSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpace=
Guid.PcdFlashFvFspTSize
+# FSP_T Section
+FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatfo=
rmPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatform=
PkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
+FV =3D FvAdvancedPreMemory
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTok=
enSpaceGuid.PcdFlashFvPreMemorySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgToken=
SpaceGuid.PcdFlashFvPreMemorySize
+FV =3D FvPreMemory
+
+##########################################################################=
######
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed wit=
hin a flash
+# device file. This section also defines order the components and modules=
are positioned
+# within the image. The [FV] section consists of define statements, set s=
tatements and
+# module statements.
+#
+##########################################################################=
######
+[FV.FvMicrocode]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D FALSE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D FALSE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+
+FILE RAW =3D 197DB236-F856-4924-90F8-CDF12FB875F3 {
+ $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.bin
+}
+
+[FV.FvPreMemory]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
+
+INF UefiCpuPkg/SecCore/SecCore.inf
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM=
em.inf
+INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
+
+[FV.FvPostMemoryUncompact]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
+
+# Init Board Config PCD
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i=
nf
+INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPost=
Mem.inf
+
+FILE RAW =3D C9505BC0-AA3D-4056-9995-870C8DE8594E {
+ $(PLATFORM_SI_BIN_PACKAGE)/ChipsetInit/CnlPchLpChipsetInitTable_Dx.bin
+ }
+!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE
+FILE FREEFORM =3DPCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFil=
eGuid) {
+ SECTION RAW =3D $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
+ SECTION UI =3D "Vbt"
+}
+FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
+ SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp
+}
+!endif # PcdPeiDisplayEnable
+
+
+[FV.FvPostMemory]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 9DFE49DB-8EF0-4D9C-B273-0036144DE917
+
+FILE FV_IMAGE =3D 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI=
RED =3D TRUE {
+ SECTION FV_IMAGE =3D FvPostMemoryUncompact
+ }
+}
+
+[FV.FvUefiBootUncompact]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
+INF $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf
+
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
+INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+
+INF ShellPkg/Application/Shell/Shell.inf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+INF $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
+INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
+
+INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
+
+
+[FV.FvUefiBoot]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 0496D33D-EA79-495C-B65D-ABF607184E3B
+
+FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU=
IRED =3D TRUE {
+ SECTION FV_IMAGE =3D FvUefiBootUncompact
+ }
+ }
+
+[FV.FvOsBootUncompact]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE
+INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
+
+INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/Boar=
dAcpiDxe/BoardAcpiDxe.inf
+INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+
+!endif
+
+[FV.FvLateSilicon]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitD=
xe.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmA=
ccess.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSm=
iDispatcher.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmC=
ontrol.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
+
+INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab=
les/SaAcpiTables.inf
+INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab=
les/SaSsdt/SaSsdt.inf
+
+!endif
+
+[FV.FvOsBoot]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 13BF8810-75FD-4B1A-91E6-E16C4201F80A
+
+FILE FV_IMAGE =3D B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU=
IRED =3D TRUE {
+ SECTION FV_IMAGE =3D FvOsBootUncompact
+ }
+ }
+
+FILE FV_IMAGE =3D D4632741-510C-44E3-BE21-C3D6D7881485 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU=
IRED =3D TRUE {
+ SECTION FV_IMAGE =3D FvLateSilicon
+ }
+ }
+
+[FV.FvSecurityPreMemory]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16 #FV alignment and FV attributes setting.
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoS=
amplePei.inf
+
+INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
+
+[FV.FvSecurityPostMemory]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16 #FV alignment and FV attributes setting.
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 4199E560-54AE-45E5-91A4-F7BC3804E14A
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+[FV.FvSecurityLate]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D F753FE9A-EEFD-485B-840B-E032D538102C
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
+INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE
+INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+!endif
+
+[FV.FvSecurity]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
+
+FILE FV_IMAGE =3D 757CC075-1428-423D-A73C-22639706C119 {
+ SECTION FV_IMAGE =3D FvSecurityPreMemory
+ }
+
+FILE FV_IMAGE =3D 80BB8482-44D5-4BEC-82B5-8D87A933830B {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU=
IRED =3D TRUE {
+ SECTION FV_IMAGE =3D FvSecurityPostMemory
+ }
+ }
+
+FILE FV_IMAGE =3D C83522D9-80A1-4D95-8C25-3F1370497406 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU=
IRED =3D TRUE {
+ SECTION FV_IMAGE =3D FvSecurityLate
+ }
+ }
+
+#
+# Pre-memory Advanced Features
+#
+[FV.FvAdvancedPreMemory]
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305
+
+!include AdvancedFeaturePkg/Include/PreMemory.fdf
+
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE
+INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
+!endif
+
+#
+# Post-Memory Advanced Features
+#
+[FV.FvAdvancedUncompact]
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D BE3DF86F-E464-44A3-83F7-0D27E6B88C27
+
+!include AdvancedFeaturePkg/Include/PostMemory.fdf
+
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE
+INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
+INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
+INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+!endif
+
+#
+# Compressed FV with Post-Memory Advanced Features
+#
+[FV.FvAdvanced]
+BlockSize =3D $(FLASH_BLOCK_SIZE)
+FvAlignment =3D 16
+ERASE_POLARITY =3D 1
+MEMORY_MAPPED =3D TRUE
+STICKY_WRITE =3D TRUE
+LOCK_CAP =3D TRUE
+LOCK_STATUS =3D TRUE
+WRITE_DISABLED_CAP =3D TRUE
+WRITE_ENABLED_CAP =3D TRUE
+WRITE_STATUS =3D TRUE
+WRITE_LOCK_CAP =3D TRUE
+WRITE_LOCK_STATUS =3D TRUE
+READ_DISABLED_CAP =3D TRUE
+READ_ENABLED_CAP =3D TRUE
+READ_STATUS =3D TRUE
+READ_LOCK_CAP =3D TRUE
+READ_LOCK_STATUS =3D TRUE
+FvNameGuid =3D B23E7388-9953-45C7-9201-0473DDE5487A
+
+FILE FV_IMAGE =3D 5248467B-B87B-4E74-AC02-398AF4BCB712 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU=
IRED =3D TRUE {
+ SECTION FV_IMAGE =3D FvAdvancedUncompact
+ }
+ }
+
+##########################################################################=
######
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are =
the default
+# rules for the different module type. User can add the customized rules t=
o define the
+# content of the FFS file.
+#
+##########################################################################=
######
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPk=
gBuildOption.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenB=
oardPkgBuildOption.dsc
new file mode 100644
index 0000000000..f77ca32343
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgBuildO=
ption.dsc
@@ -0,0 +1,154 @@
+## @file
+# platform build option configuration file.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[BuildOptions]
+# Define Build Options both for EDK and EDKII drivers.
+
+
+ DEFINE DSC_S3_BUILD_OPTIONS =3D
+
+ DEFINE DSC_CSM_BUILD_OPTIONS =3D
+
+!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE
+ DEFINE DSC_ACPI_BUILD_OPTIONS =3D -DACPI_SUPPORT=3D1
+!else
+ DEFINE DSC_ACPI_BUILD_OPTIONS =3D
+!endif
+
+ DEFINE BIOS_GUARD_BUILD_OPTIONS =3D
+
+ DEFINE OVERCLOCKING_BUILD_OPTION =3D
+
+ DEFINE FSP_BINARY_BUILD_OPTIONS =3D
+
+ DEFINE FSP_WRAPPER_BUILD_OPTIONS =3D -DFSP_WRAPPER_FLAG
+
+ DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =3D
+
+ DEFINE RESTRICTED_OPTION =3D
+
+
+ DEFINE SV_BUILD_OPTIONS =3D
+
+ DEFINE TEST_MENU_BUILD_OPTION =3D
+
+!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE
+ DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL-
+!else
+ DEFINE OPTIMIZE_DISABLE_OPTIONS =3D
+!endif
+
+ DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =3D
+
+
+ DEFINE TPM_BUILD_OPTION =3D
+
+ DEFINE TPM2_BUILD_OPTION =3D
+
+ DEFINE DSC_TBT_BUILD_OPTIONS =3D
+
+ DEFINE DSC_DCTT_BUILD_OPTIONS =3D
+
+ DEFINE EMB_BUILD_OPTIONS =3D
+
+ DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =3D -DMEM_DOWN_FLAG=3D1
+
+ DEFINE DSC_KBCEMUL_BUILD_OPTIONS =3D
+
+ DEFINE BOOT_GUARD_BUILD_OPTIONS =3D
+
+ DEFINE SECURE_BOOT_BUILD_OPTIONS =3D
+
+ DEFINE USBTYPEC_BUILD_OPTION =3D
+
+ DEFINE CAPSULE_BUILD_OPTIONS =3D
+
+ DEFINE PERFORMANCE_BUILD_OPTION =3D
+
+ DEFINE DEBUGUSEUSB_BUILD_OPTION =3D
+
+ DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =3D -DDISABLE_NEW_=
DEPRECATED_INTERFACES=3D1
+
+ DEFINE SINITBIN_BUILD_OPTION =3D
+
+ DEFINE MINTREE_FLAG_BUILD_OPTION =3D -DMINTREE_FLAG=3D1
+
+ DEFINE CPUTYPE_BUILD_OPTION =3D -DCPU_CFL=3D1
+
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTI=
ONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_=
OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT=
IONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGU=
SEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT=
IONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_T=
EMPRAM_INIT_AND_EXIT_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT=
IONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_B=
UILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_=
BUILD_OPTION)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT=
IONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT=
IONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYP=
EC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT=
IONS) $(CPUTYPE_BUILD_OPTION)
+[BuildOptions.Common.EDKII]
+
+#
+# For IA32 Global Build Flag
+#
+ *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P=
I_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI
+ *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For IA32 Specific Build Flag
+#
+GCC: *_*_IA32_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP=
TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI
+MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP=
TIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP=
TIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP=
TIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP=
TIMIZE_DISABLE_OPTIONS)
+
+#
+# For X64 Global Build Flag
+#
+ *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P=
I_SPECIFICATION_VERSION=3D0x00010015
+ *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+
+#
+# For X64 Specific Build Flag
+#
+GCC: *_*_X64_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP=
TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015
+MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP=
TIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP=
TIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support page l=
evel protection
+[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_C=
ORE]
+ MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096
+ GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support Memory=
Attribute table
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096
+ GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support NX pro=
tection
+[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE,=
BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPL=
ICATION]
+ #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096
+ #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPk=
gPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgP=
cd.dsc
new file mode 100644
index 0000000000..1ccdb28f12
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -0,0 +1,404 @@
+## @file
+# PCD configuration build description file for the CometlakeURvp board.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+##########################################################################=
######
+#
+# Pcd Section - list of all PCD Entries used by this board.
+#
+##########################################################################=
######
+
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Key Boot Stage and FSP configuration
+ ######################################
+ #
+ # Please select the Boot Stage here.
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
+
+ #
+ # 0: FSP Wrapper is running in Dispatch mode.
+ # 1: FSP Wrapper is running in API mode.
+ # Note: Dispatch mode is currently NOT supported for this board.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
+
+ #
+ # FALSE: The board is not a FSP wrapper (FSP binary not used)
+ # TRUE: The board is a FSP wrapper (FSP binary is used)
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+ gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+ gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+ gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
+
+ #
+ # When sharing stack with boot loader, FSP only needs a small temp ram f=
or heap
+ #
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x10000
+
+ #
+ # Boot loader stack size has to be large enough for FSP execution
+ #
+ gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ #
+ # PCIe Reserved Memory Space Range
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0xA0000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xDFFFFFFF
+[PcdsFeatureFlag.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst=
|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+!if $(TARGET) =3D=3D RELEASE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!endif
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ######################################
+ # Silicon Configuration
+ ######################################
+ # Build switches
+ gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
+
+ # CPU
+ gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
+
+ # SA
+ gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
+
+ # ME
+ gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
+
+ # Others
+ gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254=
timer is used.
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
+!endif
+
+!if $(TARGET) =3D=3D DEBUG
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
+!endif
+
+ ######################################
+ # Board Configuration
+ ######################################
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE
+
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+!if $(TARGET) =3D=3D RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+!endif
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM=
ORY_ADDRESS)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
+!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+!if $(TARGET) =3D=3D DEBUG
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+!endif
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
+
+ # Specifies timeout value in microseconds for the BSP to detect all APs =
for the first time.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
+
+ #
+ # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBui=
ld
+ # (They will be DynamicEx in FSP Dispatch mode)
+ #
+
+ ## Specifies the size of the microcode Region.
+ # @Prompt Microcode Region size.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
+
+ ## Specifies the AP wait loop state during POST phase.
+ # The value is defined as below.
+ # 1: Place AP in the Hlt-Loop state.
+ # 2: Place AP in the Mwait-Loop state.
+ # 3: Place AP in the Run-Loop state.
+ # @Prompt The AP wait loop state.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+
+ ######################################
+ # Silicon Configuration
+ ######################################
+ gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpace=
Guid.PcdPciExpressRegionLength
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
+
+ #
+ # The PCDs are used to control the Windows SMM Security Mitigations Tabl=
e - Protection Flags
+ #
+ # BIT0: If set, expresses that for all synchronous SMM entries,SMM will =
validate that input and output buffers lie entirely within the expected fix=
ed memory regions.
+ # BIT1: If set, expresses that for all synchronous SMM entries, SMM will=
validate that input and output pointers embedded within the fixed communic=
ation buffer only refer to address ranges \
+ # that lie entirely within the expected fixed memory regions.
+ # BIT2: Firmware setting this bit is an indication that it will not allo=
w reconfiguration of system resources via non-architectural mechanisms.
+ # BIT3-31: Reserved
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+!if $(TARGET) =3D=3D RELEASE
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
+!endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
+!if $(TARGET) =3D=3D RELEASE
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00=
, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0=
x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07=
, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0=
x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07=
, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0=
x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07=
, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0=
x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F=
, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0=
x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F=
, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0=
x00, 0x00}
+!endif
+
+ ######################################
+ # Board Configuration
+ ######################################
+ gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1
+ gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, =
0x1F, 0x00}
+
+[PcdsFixedAtBuild.IA32]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+ gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
+
+[PcdsFixedAtBuild.X64]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+
+ # Default platform supported RFC 4646 languages: (American) English
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
+
+[PcdsPatchableInModule.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+
+ ######################################
+ # Silicon Configuration
+ ######################################
+!if $(TARGET) =3D=3D DEBUG
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
+!endif
+
+[PcdsDynamicDefault]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+
+ #
+ # Set video to native resolution as Windows 8 WHCK requirement.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
+
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
+
+ # Platform will pre-allocate UPD buffer and pass it to FspWrapper
+ # Those dummy address will be patched before FspWrapper executing
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
+
+ ######################################
+ # Board Configuration
+ ######################################
+
+ # Thunderbolt Configuration
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x020100=
11
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
+
+[PcdsDynamicHii.X64.DEFAULT]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|=
gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar=
iableGuid|0x0|1 # Variable: L"Timeout"
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar=
iableGuid|0x0|5 # Variable: L"Timeout"
+!endif
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/build_confi=
g.cfg b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
new file mode 100644
index 0000000000..1e01ae7ea7
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
@@ -0,0 +1,34 @@
+# @ build_config.cfg
+# This is the CometlakeURvp board specific build settings
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN =3D
+EDK_SETUP_OPTION =3D
+openssl_path =3D
+PLATFORM_BOARD_PACKAGE =3D CometlakeOpenBoardPkg
+PROJECT =3D CometlakeOpenBoardPkg/CometlakeURvp
+BOARD =3D CometlakeURvp
+FLASH_MAP_FDF =3D CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMap=
Include.fdf
+PROJECT_DSC =3D CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
+BOARD_PKG_PCD_DSC =3D CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.=
dsc
+PrepRELEASE =3D DEBUG
+SILENT_MODE =3D FALSE
+EXT_CONFIG_CLEAR =3D
+CapsuleBuild =3D FALSE
+EXT_BUILD_FLAGS =3D
+CAPSULE_BUILD =3D 0
+TARGET =3D DEBUG
+TARGET_SHORT =3D D
+PERFORMANCE_BUILD =3D FALSE
+FSP_WRAPPER_BUILD =3D TRUE
+FSP_BIN_PKG =3D CometLakeFspBinPkg/CometLake1
+FSP_PKG_NAME =3D CoffeelakeSiliconPkg
+FSP_BINARY_BUILD =3D FALSE
+FSP_TEST_RELEASE =3D FALSE
+SECURE_BOOT_ENABLE =3D FALSE
+BIOS_INFO_GUID =3D A842B2D2-5C88-44E9-A9E2-4830F26662B7
--=20
2.16.2.windows.1
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From: "Kathappan Esakkithevar" <kathappan.esakkithevar@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
Chasel Chiu <chasel.chiu@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>,
Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>,
Prince Agyeman <prince.agyeman@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 7/7] Update Maintainers.txt
for CometlakeOpenBoardPkg
Date: Wed, 12 Feb 2020 00:42:41 +0530
Message-Id: <20200211191241.53188-8-kathappan.esakkithevar@intel.com>
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280
This change adds owners to the the Maintainers.txt for CometlakeOpenBoardPk=
g.
Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
---
Maintainers.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Maintainers.txt b/Maintainers.txt
index e97ea5b343..96c2f2757c 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -178,6 +178,14 @@ M: Chasel Chiu <chasel.chiu@intel.com>
M: Michael Kubacki <michael.a.kubacki@intel.com>
M: Nate DeSimone <nathaniel.l.desimone@intel.com>
=20
+Platform/Intel/CometlakeOpenBoardPkg
+F: Platform/Intel/CometlakeOpenBoardPkg/
+M: Chasel Chiu <chasel.chiu@intel.com>
+M: Nate DeSimone <nathaniel.l.desimone@intel.com>
+M: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
+R: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
+R: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
+
Platform/Intel/SimicsOpenBoardPkg
F: Platform/Intel/SimicsOpenBoardPkg/
M: Agyeman Prince <prince.agyeman@intel.com>
--=20
2.16.2.windows.1
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