From nobody Fri Mar 29 12:13:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54132+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54132+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15813326758633.8761494095111857; Mon, 10 Feb 2020 03:04:35 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id uTJ9YY1788612xJ8bQTee4WI; Mon, 10 Feb 2020 03:04:34 -0800 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.20492.1581332674325391852 for ; Mon, 10 Feb 2020 03:04:34 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2020 03:04:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,424,1574150400"; d="scan'208";a="227156900" X-Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga008.fm.intel.com with ESMTP; 10 Feb 2020 03:04:33 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty Subject: [edk2-devel] [Patch] IntelSiliconPkg: FIT based shadow microcode PPI support. Date: Mon, 10 Feb 2020 19:04:29 +0800 Message-Id: <20200210110429.33612-1-siyuan.fu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,siyuan.fu@intel.com X-Gm-Message-State: S6n0ZsuIB3Ud90IDkpsKCJtDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581332674; bh=mmQl69WNE9tIAsDsjJIoW2aVgyiwDaD5OTU9t/wzvX8=; h=Cc:Date:From:Reply-To:Subject:To; b=fBq4XYjZghNYKHP9iUvB7uppTnvLBFIqxHccuvDEbxJslStd4ler/TcNhjsD/h3OUci vADoWqSeQy34pm2iWQRKY9nASdWIKitnKk9xHzXv8smqORm9uEOffwpNup+qCjrkSvC/D e/nPw8hmef6B5EzUxiU20t5JDeRdjl0kUIs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This patch adds a platform PEIM for FIT based shadow microcode PPI support. A detailed design doc can be found here: https://edk2.groups.io/g/devel/files/Designs/2020/0214/Support%20 the%202nd%20Microcode%20FV%20Flash%20Region.pdf TEST: Tested on FIT enabled platform. BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=3D2449 Cc: Ray Ni Cc: Rangasai V Chaganty Signed-off-by: Siyuan Fu --- .../Feature/ShadowMicrocode/ShadowMicrocodePei.c | 4 ++++ .../Feature/ShadowMicrocode/ShadowMicrocodePei.inf | 3 +++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 7 +++++++ 3 files changed, 14 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMi= crocodePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/Shadow= MicrocodePei.c index 0ad3eeaa07..f160f59b87 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.c @@ -248,6 +248,10 @@ ShadowMicrocodePatchByFit ( UINTN TotalSize; UINTN TotalLoadSize; =20 + if (!FeaturePcdGet (PcdCpuShadowMicrocodeByFit)) { + return EFI_UNSUPPORTED; + } + FitPointer =3D *(UINT64 *) (UINTN) FIT_POINTER_ADDRESS; if ((FitPointer =3D=3D 0) || (FitPointer =3D=3D 0xFFFFFFFFFFFFFFFF) || diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMi= crocodePei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/Shad= owMicrocodePei.inf index 27d07ac56c..fecb7c3904 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.inf @@ -39,5 +39,8 @@ gEdkiiMicrocodeShadowInfoHobGuid gEdkiiMicrocodeStorageTypeFlashGuid =20 +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit + [Depex] TRUE diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index 2d8e40f0b8..ad093928b7 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -64,6 +64,13 @@ # Include/Protocol/PlatformDeviceSecurityPolicy.h gEdkiiDeviceSecurityPolicyProtocolGuid =3D {0x7ea41a99, 0x5e32, 0x4c97, = {0x88, 0xc4, 0xd6, 0xe7, 0x46, 0x84, 0x9, 0xd4}} =20 +[PcdsFeatureFlag] + ## Indicates if FIT based microcode shadowing will be enabled.

+ # TRUE - FIT base microcode shadowing will be enabled.
+ # FALSE - FIT base microcode shadowing will be disabled.
+ # @Prompt FIT based microcode shadowing. + gIntelSiliconPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit|FALSE|BOOLEAN|= 0x00000006 + [PcdsFixedAtBuild, PcdsPatchableInModule] ## Error code for VTd error.

# EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPE= CIFIC | 0x00000000)) =3D 0x02008000
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