From nobody Sat Apr 20 04:03:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54128+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54128+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1581332348525804.9484628744375; Mon, 10 Feb 2020 02:59:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 07YRYY1788612xyqC1GL5HrP; Mon, 10 Feb 2020 02:59:07 -0800 X-Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web09.20271.1581332344059877189 for ; Mon, 10 Feb 2020 02:59:06 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2020 02:59:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,424,1574150400"; d="scan'208";a="227155584" X-Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga008.fm.intel.com with ESMTP; 10 Feb 2020 02:59:05 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch 1/2] UefiCpuPkg: Remove FIT based microcode shadow logic from MpInitLib. Date: Mon, 10 Feb 2020 18:58:48 +0800 Message-Id: <20200210105849.30472-2-siyuan.fu@intel.com> In-Reply-To: <20200210105849.30472-1-siyuan.fu@intel.com> References: <20200210105849.30472-1-siyuan.fu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,siyuan.fu@intel.com X-Gm-Message-State: nAe1omvU5Xx3qBtU1CEawwNux1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581332347; bh=r7y+z8ucBqXwzlzFD+ZAlYCQVDOEU/X9CovM5JZ+gdQ=; h=Cc:Date:From:Reply-To:Subject:To; b=LaKNehlIqvyMWEy9mAqhol/WH3ducmcE0DWN1u+YWZFGbTnoNOpD7cRXlWWnuoz+OUx oK5dVKmW9guRYARtXXxys4ifBlC1cI4i5LJ0kSs+EqepmQNneoNvq9mX4b9GwzRoqP3cj 5cdHlMTwwCReRCeVqbeloPIxcRe7XuK0TzQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Commit c7c964b and dd01704 add header file for FIT table and update MpInitLib to support FIT based microcode shadow operation. There are comments that FIT is Intel specific specification instead of industry standard, which should not be placed in EDK2 MdePkg and UefiCpuPkg. So this patch adds a platform PPI for the microcode shadow logic, and remove the FIT related code from EDK2. The FIT based microcode shadow support will be implemented as a new platform PEIM in IntelSiliconPkg in edk2-platforms. A detailed design doc can be found here: https://edk2.groups.io/g/devel/files/Designs/2020/0214/Support%20 the%202nd%20Microcode%20FV%20Flash%20Region.pdf TEST: Tested on FIT enabled platform. BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=3D2449 Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Siyuan Fu Acked-by: Laszlo Ersek --- UefiCpuPkg/Include/Ppi/ShadowMicrocode.h | 66 +++++++++++ UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 1 - UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 21 +++- UefiCpuPkg/Library/MpInitLib/Microcode.c | 105 +----------------- UefiCpuPkg/Library/MpInitLib/MpLib.h | 19 +++- UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 4 +- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 70 +++++++++++- UefiCpuPkg/UefiCpuPkg.dec | 11 +- 8 files changed, 179 insertions(+), 118 deletions(-) create mode 100644 UefiCpuPkg/Include/Ppi/ShadowMicrocode.h diff --git a/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h b/UefiCpuPkg/Include/= Ppi/ShadowMicrocode.h new file mode 100644 index 0000000000..17c19d6307 --- /dev/null +++ b/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h @@ -0,0 +1,66 @@ +/** @file + This file declares EDKII Shadow Microcode PPI. + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PPI_SHADOW_MICROCODE_H__ +#define __PPI_SHADOW_MICROCODE_H__ + +#define EDKII_PEI_SHADOW_MICROCODE_PPI_GUID \ + { \ + 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1= , 0xc6 } \ + } + +typedef struct _EDKII_PEI_SHADOW_MICROCODE_PPI EDKII_PEI_SHADOW_MICROCODE= _PPI; + +typedef struct { + UINT32 ProcessorSignature; + UINT8 PlatformId; +} EDKII_PEI_CPU_MICROCODE_ID; + +/** + Shadow microcode update patches to memory. + + The function is used for shadowing microcode update patches to a continu= ous memory. + It shall allocate memory buffer and only shadow the microcode patches fo= r those + processors specified by MicrocodeCpuId array. The checksum verification = may be + skiped in this function so the caller must perform checksum verification= before + using the microcode patches in returned memory buffer. + + @param[in] This The PPI instance pointer. + @param[in] CpuIdCount Number of elements in MicrocodeCpuId ar= ray. + @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_CPU_= MICROCODE_ID + structures. + @param[out] BufferSize Pointer to receive the total size of Bu= ffer. + @param[out] Buffer Pointer to receive address of allocated= memory + with microcode patches data in it. + + @retval EFI_SUCCESS The microcode has been shadowed to memo= ry. + @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of reso= urces. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PEI_SHADOW_MICROCODE) ( + IN EDKII_PEI_SHADOW_MICROCODE_PPI *This, + IN UINTN CpuIdCount, + IN EDKII_PEI_CPU_MICROCODE_ID *MicrocodeCpuId, + OUT UINTN *BufferSize, + OUT VOID **Buffer + ); + +/// +/// This PPI is installed by some platform or chipset-specific PEIM that +/// abstracts handling microcode shadow support. +/// +struct _EDKII_PEI_SHADOW_MICROCODE_PPI { + EDKII_PEI_SHADOW_MICROCODE ShadowMicrocode; +}; + +extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid; + +#endif + diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index bf5d18d521..cd912ab0c5 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -68,6 +68,5 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES - gUefiCpuPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit ## CONS= UMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONS= UMES =20 diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index b17e287bbf..ca52be943e 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -1,7 +1,7 @@ /** @file MP initialize support functions for DXE phase. =20 - Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -816,3 +816,22 @@ MpInitLibEnableDisableAP ( =20 return Status; } + +/** + This funtion will try to invoke platform specific microcode shadow logic= to + relocate microcode update patches into memory. + + @param[in] CpuMpData The pointer to CPU MP Data structure. + + @retval EFI_SUCCESS Shadow microcode success. + @retval EFI_OUT_OF_RESOURCES No enough resource to complete the oper= ation. + @retval EFI_NOT_FOUND Can't find platform specific microcode = shadow + PPI/Protocol. +**/ +EFI_STATUS +PlatformShadowMicrocode ( + IN OUT CPU_MP_DATA *CpuMpData + ) +{ + return EFI_NOT_FOUND; +} diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 247f835b09..0c468cd480 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -619,109 +619,6 @@ OnExit: return; } =20 -/** - Shadow the required microcode patches data into memory according to FIT = microcode entry. - - @param[in, out] CpuMpData The pointer to CPU MP Data structure. - - @return EFI_SUCCESS Microcode patch is shadowed into memory. - @return EFI_UNSUPPORTED FIT based microcode shadowing is not suppo= rted. - @return EFI_OUT_OF_RESOURCES No enough memory resource. - @return EFI_NOT_FOUND There is something wrong in FIT microcode = entry. - -**/ -EFI_STATUS -ShadowMicrocodePatchByFit ( - IN OUT CPU_MP_DATA *CpuMpData - ) -{ - UINT64 FitPointer; - FIRMWARE_INTERFACE_TABLE_ENTRY *FitEntry; - UINT32 EntryNum; - UINT32 Index; - MICROCODE_PATCH_INFO *PatchInfoBuffer; - UINTN MaxPatchNumber; - CPU_MICROCODE_HEADER *MicrocodeEntryPoint; - UINTN PatchCount; - UINTN TotalSize; - UINTN TotalLoadSize; - - if (!FeaturePcdGet (PcdCpuShadowMicrocodeByFit)) { - return EFI_UNSUPPORTED; - } - - FitPointer =3D *(UINT64 *) (UINTN) FIT_POINTER_ADDRESS; - if ((FitPointer =3D=3D 0) || - (FitPointer =3D=3D 0xFFFFFFFFFFFFFFFF) || - (FitPointer =3D=3D 0xEEEEEEEEEEEEEEEE)) { - // - // No FIT table. - // - ASSERT (FALSE); - return EFI_NOT_FOUND; - } - FitEntry =3D (FIRMWARE_INTERFACE_TABLE_ENTRY *) (UINTN) FitPointer; - if ((FitEntry[0].Type !=3D FIT_TYPE_00_HEADER) || - (FitEntry[0].Address !=3D FIT_TYPE_00_SIGNATURE)) { - // - // Invalid FIT table, treat it as no FIT table. - // - ASSERT (FALSE); - return EFI_NOT_FOUND; - } - - EntryNum =3D *(UINT32 *)(&FitEntry[0].Size[0]) & 0xFFFFFF; - - // - // Calculate microcode entry number - // - MaxPatchNumber =3D 0; - for (Index =3D 0; Index < EntryNum; Index++) { - if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) { - MaxPatchNumber++; - } - } - if (MaxPatchNumber =3D=3D 0) { - return EFI_NOT_FOUND; - } - - PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof (MICROCODE_PAT= CH_INFO)); - if (PatchInfoBuffer =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - // - // Fill up microcode patch info buffer according to FIT table. - // - PatchCount =3D 0; - TotalLoadSize =3D 0; - for (Index =3D 0; Index < EntryNum; Index++) { - if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) { - MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) FitEntry[In= dex].Address; - TotalSize =3D (MicrocodeEntryPoint->DataSize =3D=3D 0) ? 2048 : Micr= ocodeEntryPoint->TotalSize; - if (IsMicrocodePatchNeedLoad (CpuMpData, MicrocodeEntryPoint)) { - PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEntry= Point; - PatchInfoBuffer[PatchCount].Size =3D TotalSize; - TotalLoadSize +=3D TotalSize; - PatchCount++; - } - } - } - - if (PatchCount !=3D 0) { - DEBUG (( - DEBUG_INFO, - "%a: 0x%x microcode patches will be loaded into memory, with size 0x= %x.\n", - __FUNCTION__, PatchCount, TotalLoadSize - )); - - ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, To= talLoadSize); - } - - FreePool (PatchInfoBuffer); - return EFI_SUCCESS; -} - /** Shadow the required microcode patches data into memory. =20 @@ -734,7 +631,7 @@ ShadowMicrocodeUpdatePatch ( { EFI_STATUS Status; =20 - Status =3D ShadowMicrocodePatchByFit (CpuMpData); + Status =3D PlatformShadowMicrocode (CpuMpData); if (EFI_ERROR (Status)) { ShadowMicrocodePatchByPcd (CpuMpData); } diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 7c62d75acc..7d505e5621 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -29,9 +29,6 @@ #include #include =20 -#include - - #define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P') =20 #define CPU_INIT_MP_LIB_HOB_GUID \ @@ -634,5 +631,21 @@ GetProcessorNumber ( OUT UINTN *ProcessorNumber ); =20 +/** + This funtion will try to invoke platform specific microcode shadow logic= to + relocate microcode update patches into memory. + + @param[in] CpuMpData The pointer to CPU MP Data structure. + + @retval EFI_SUCCESS Shadow microcode success. + @retval EFI_OUT_OF_RESOURCES No enough resource to complete the oper= ation. + @retval EFI_NOT_FOUND Can't find platform specific microcode = shadow + PPI/Protocol. +**/ +EFI_STATUS +PlatformShadowMicrocode ( + IN OUT CPU_MP_DATA *CpuMpData + ); + #endif =20 diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 555125a7c5..d78d328b42 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -60,7 +60,9 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES - gUefiCpuPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit ## CONS= UMES + +[Ppis] + gEdkiiPeiShadowMicrocodePpiGuid ## SOMETIMES_CONSUMES =20 [Guids] gEdkiiS3SmmInitDoneGuid diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index 06e3f5d0d3..d25cdcc879 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -1,7 +1,7 @@ /** @file MP initialize support functions for PEI phase. =20 - Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -10,6 +10,7 @@ #include #include #include +#include =20 /** S3 SMM Init Done notification function. @@ -640,4 +641,71 @@ MpInitLibEnableDisableAP ( return EnableDisableApWorker (ProcessorNumber, EnableAP, HealthFlag); } =20 +/** + This funtion will try to invoke platform specific microcode shadow logic= to + relocate microcode update patches into memory. + + @param[in] CpuMpData The pointer to CPU MP Data structure. + + @retval EFI_SUCCESS Shadow microcode success. + @retval EFI_OUT_OF_RESOURCES No enough resource to complete the oper= ation. + @retval EFI_NOT_FOUND Can't find platform specific microcode = shadow + PPI/Protocol. +**/ +EFI_STATUS +PlatformShadowMicrocode ( + IN OUT CPU_MP_DATA *CpuMpData + ) +{ + EFI_STATUS Status; + EDKII_PEI_SHADOW_MICROCODE_PPI *ShadowMicrocodePpi; + UINTN CpuCount; + EDKII_PEI_CPU_MICROCODE_ID *MicrocodeCpuId; + UINTN Index; + UINTN BufferSize; + VOID *Buffer; + + Status =3D PeiServicesLocatePpi ( + &gEdkiiPeiShadowMicrocodePpiGuid, + 0, + NULL, + (VOID **) &ShadowMicrocodePpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + CpuCount =3D CpuMpData->CpuCount; + MicrocodeCpuId =3D (EDKII_PEI_CPU_MICROCODE_ID *) AllocateZeroPool (size= of (EDKII_PEI_CPU_MICROCODE_ID) * CpuCount); + if (MicrocodeCpuId =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + MicrocodeCpuId[Index].ProcessorSignature =3D CpuMpData->CpuData[Index]= .ProcessorSignature; + MicrocodeCpuId[Index].PlatformId =3D CpuMpData->CpuData[Index]= .PlatformId; + } + + Status =3D ShadowMicrocodePpi->ShadowMicrocode ( + ShadowMicrocodePpi, + CpuCount, + MicrocodeCpuId, + &BufferSize, + &Buffer + ); + FreePool (MicrocodeCpuId); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + CpuMpData->MicrocodePatchAddress =3D (UINTN) Buffer; + CpuMpData->MicrocodePatchRegionSize =3D BufferSize; + + DEBUG (( + DEBUG_INFO, + "%a: Required microcode patches have been loaded at 0x%lx, with size 0= x%lx.\n", + __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePa= tchRegionSize + )); =20 + return EFI_SUCCESS; +} diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index a6ebdde1cf..e91dc68cbe 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -1,7 +1,7 @@ ## @file UefiCpuPkg.dec # This Package provides UEFI compatible CPU modules and libraries. # -# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -81,6 +81,9 @@ [Ppis] gEdkiiPeiMpServices2PpiGuid =3D { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94,= 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}} =20 + ## Include/Ppi/ShadowMicrocode.h + gEdkiiPeiShadowMicrocodePpiGuid =3D { 0x430f6965, 0x9a69, 0x41c5, { 0x93= , 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }} + [PcdsFeatureFlag] ## Indicates if SMM Profile will be enabled. # If enabled, instruction executions in and data accesses to memory out= side of SMRAM will be logged. @@ -139,12 +142,6 @@ # @Prompt Lock SMM Feature Control MSR. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x= 3213210B =20 - ## Indicates if FIT based microcode shadowing will be enabled.

- # TRUE - FIT base microcode shadowing will be enabled.
- # FALSE - FIT base microcode shadowing will be disabled.
- # @Prompt FIT based microcode shadowing. - gUefiCpuPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit|FALSE|BOOLEAN|0x321= 3210D - [PcdsFixedAtBuild] ## List of exception vectors which need switching stack. # This PCD will only take into effect if PcdCpuStackGuard is enabled. --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54128): https://edk2.groups.io/g/devel/message/54128 Mute This Topic: https://groups.io/mt/71134279/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 04:03:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54129+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54129+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1581332349892399.7971173767054; Mon, 10 Feb 2020 02:59:09 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ImFrYY1788612xKo0cMbiMQb; Mon, 10 Feb 2020 02:59:09 -0800 X-Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web09.20271.1581332344059877189 for ; Mon, 10 Feb 2020 02:59:08 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2020 02:59:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,424,1574150400"; d="scan'208";a="227155591" X-Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga008.fm.intel.com with ESMTP; 10 Feb 2020 02:59:07 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao Subject: [edk2-devel] [Patch 2/2] MdePkg: Remove FIT table industry standard header file. Date: Mon, 10 Feb 2020 18:58:49 +0800 Message-Id: <20200210105849.30472-3-siyuan.fu@intel.com> In-Reply-To: <20200210105849.30472-1-siyuan.fu@intel.com> References: <20200210105849.30472-1-siyuan.fu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,siyuan.fu@intel.com X-Gm-Message-State: 8nGfLNXmRKLIDrZkp6kONJPzx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581332349; bh=Tk7hs+czv8G5VS+ewf7urd0MkkqDaDashKnEs7uN6IQ=; h=Cc:Date:From:Reply-To:Subject:To; b=puGI8Ouc2he17kqTVIWVcCDYU5XzywcclQHCVZg6FJgrkg7J7K4SfGQ2AyrrghhbUen JBuw+REMj9HmyistHzOxdKltUPTnOzOzBIZ63AJCNKnEoku/ZTWKrwXnO3ROiQMVd4YiV n5dWS4h5biHxSBB64LIB2ENekzsSJo+DaC0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Commit c7c964b and dd01704 add header file for FIT table and update MpInitLib to support FIT based microcode shadow operation. There are comments that FIT is Intel specific specification instead of industry standard, which should not be placed in EDK2 MdePkg and UefiCpuPkg. This patch removes the header file added by c7c964b. Cc: Michael D Kinney Cc: Liming Gao Signed-off-by: Siyuan Fu --- .../IndustryStandard/FirmwareInterfaceTable.h | 76 ------------------- 1 file changed, 76 deletions(-) delete mode 100644 MdePkg/Include/IndustryStandard/FirmwareInterfaceTable.h diff --git a/MdePkg/Include/IndustryStandard/FirmwareInterfaceTable.h b/Mde= Pkg/Include/IndustryStandard/FirmwareInterfaceTable.h deleted file mode 100644 index be3e34ae1b..0000000000 --- a/MdePkg/Include/IndustryStandard/FirmwareInterfaceTable.h +++ /dev/null @@ -1,76 +0,0 @@ -/** @file - Industry Standard Definitions of Firmware Interface Table BIOS Specifica= tion 1.0. - - Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __FIRMWARE_INTERFACE_TABLE_H__ -#define __FIRMWARE_INTERFACE_TABLE_H__ - -// -// FIT Entry type definitions -// -#define FIT_TYPE_00_HEADER 0x00 -#define FIT_TYPE_01_MICROCODE 0x01 -#define FIT_TYPE_02_STARTUP_ACM 0x02 -#define FIT_TYPE_07_BIOS_STARTUP_MODULE 0x07 -#define FIT_TYPE_08_TPM_POLICY 0x08 -#define FIT_TYPE_09_BIOS_POLICY 0x09 -#define FIT_TYPE_0A_TXT_POLICY 0x0A -#define FIT_TYPE_0B_KEY_MANIFEST 0x0B -#define FIT_TYPE_0C_BOOT_POLICY_MANIFEST 0x0C -#define FIT_TYPE_10_CSE_SECURE_BOOT 0x10 -#define FIT_TYPE_2D_TXTSX_POLICY 0x2D -#define FIT_TYPE_2F_JMP_DEBUG_POLICY 0x2F -#define FIT_TYPE_7F_SKIP 0x7F - -#define FIT_POINTER_ADDRESS 0xFFFFFFC0 ///< Fixed address = at 4G - 40h - -#define FIT_TYPE_VERSION 0x0100 - -#define FIT_TYPE_00_SIGNATURE SIGNATURE_64 ('_', 'F', 'I', 'T', '_', ' ',= ' ', ' ') - -#pragma pack(1) - -typedef struct { - // - // Address is the base address of the firmware component - // must be aligned on 16 byte boundary - // - UINT64 Address; - // - // Size is the span of the component in multiple of 16 bytes - // - UINT8 Size[3]; - // - // Reserved must be set to 0 - // - UINT8 Reserved; - // - // Component's version number in binary coded decimal (BCD) format. - // For the FIT header entry, the value in this field will indicate the r= evision - // number of the FIT data structure. The upper byte of the revision field - // indicates the major revision and the lower byte indicates the minor r= evision. - // - UINT16 Version; - // - // FIT types 0x00 to 0x7F - // - UINT8 Type : 7; - // - // Checksum Valid indicates whether component has valid checksum. - // - UINT8 C_V : 1; - // - // Component's checksum. The modulo sum of all the bytes in the componen= t and - // the value in this field (Chksum) must add up to zero. This field is o= nly - // valid if the C_V flag is non-zero. - // - UINT8 Chksum; -} FIRMWARE_INTERFACE_TABLE_ENTRY; - -#pragma pack() - -#endif --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54129): https://edk2.groups.io/g/devel/message/54129 Mute This Topic: https://groups.io/mt/71134282/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-