From nobody Tue Nov 26 14:20:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54068+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54068+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1581105980670313.3548455083744; Fri, 7 Feb 2020 12:06:20 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id YGpGYY1788612x5B3drr9HSz; Fri, 07 Feb 2020 12:06:20 -0800 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web09.10529.1581105978095314348 for ; Fri, 07 Feb 2020 12:06:19 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2020 12:06:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,414,1574150400"; d="scan'208";a="225644236" X-Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 07 Feb 2020 12:06:17 -0800 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: New PCI Express feature Relax Ordering Date: Sat, 8 Feb 2020 01:34:40 +0530 Message-Id: <20200207200447.10536-6-ashraf.javeed@intel.com> In-Reply-To: <20200207200447.10536-1-ashraf.javeed@intel.com> References: <20200207200447.10536-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: 7fFmXD9TdXBQzwKEvijj4rRix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581105980; bh=QYsipPdjxW0QsQMDSCto2Bb33DVaJQfubdVPae9bodg=; h=Cc:Date:From:Reply-To:Subject:To; b=NYmDwbpek/Tvefyl7ziFoCeLG1YY26SQbV2XCNe5+tTsMWYCtCP6i3AxavlQrNdlczM fY+qr1gsTHu1KU7B2npWfX6YneBxgFsBujDRbO+MdOW3Uh/CvAUpByzEwLWbmlmXDRhPV kz6bXLrIStNvgfSmXIacfo8dwF7fiVCWkCw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 The code changes are made to enable the configuration of PCI Express feature Relax Ordering (OR), that enables the PCI function to initiate requests if it does not require strong write ordering for its transact- ions; as per the PCI Express Base Specification 4 Revision 1. The code changes are made to configure only those PCI devices which are requested by platform for override, through the new PCI Express Platform protocol interface for device-specific policies. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 4 ++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 70 +++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 18 ++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 5 ++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 61 +++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 157 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 77b44c0..d3d795d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -287,8 +287,12 @@ struct _PCI_IO_DEVICE { // This field is used to support this case. // UINT16 BridgeIoAlignment; + // + // PCI Express features setup flags + // UINT8 SetupMPS; UINT8 SetupMRRS; + PCI_FEATURE_POLICY SetupRO; }; =20 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c index 2810158..3262b76 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c @@ -381,3 +381,73 @@ ProgramMaxReadReqSize ( return Status; } =20 +/** + Overrides the PCI Device Control register Relax Order register field; if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +ProgramRelaxOrder ( + IN PCI_IO_DEVICE *PciDevice, + IN VOID *PciExFeatureConfiguration + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + PcieDev.Uint16 =3D 0; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + ASSERT (Status =3D=3D EFI_SUCCESS); + + if (PciDevice->SetupRO.Override + && PcieDev.Bits.RelaxedOrdering !=3D PciDevice->SetupRO.Act + ) { + PcieDev.Bits.RelaxedOrdering =3D PciDevice->SetupRO.Act; + DEBUG (( DEBUG_INFO, "RO=3D%d,", PciDevice->SetupRO.Act)); + + // + // Raise TPL to high level to disable timer interrupt while the write = operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D Pc= ieDev.Uint16; + } else { + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset); + } + } else { + DEBUG (( DEBUG_INFO, "No RO,", PciDevice->SetupRO.Act)); + } + + return Status; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h index b43fba7..0d17801 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h @@ -97,4 +97,22 @@ ProgramMaxReadReqSize ( IN VOID *PciExFeatureConfiguration ); =20 +/** + Overrides the PCI Device Control register Relax Order register field; if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +ProgramRelaxOrder ( + IN PCI_IO_DEVICE *PciDevice, + IN VOID *PciExFeatureConfiguration + ); + #endif diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index 1caf1f4..267f570 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -42,7 +42,7 @@ EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPl= atformPolicy =3D { // // support for PCI Express feature - Relax Order // - FALSE, + TRUE, // // support for PCI Express feature - No-Snoop // @@ -113,6 +113,9 @@ PCI_EXPRESS_FEATURE_INITIALIZATION_POINT mPciExpressFe= atureInitializationList[] }, { PciExpressFeatureProgramPhase, PciExpressMrrs, ProgramMax= ReadReqSize + }, + { + PciExpressFeatureProgramPhase, PciExpressRelaxOrder, ProgramRel= axOrder } }; =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index f74e566..40eb8a3 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -149,6 +149,45 @@ SetDevicePolicyPciExpressMrrs ( } } =20 +/** + Routine to set the device-specific policy for the PCI feature Relax Orde= ring + + @param RelaxOrder value corresponding to data type EFI_PCI_EXPRESS_R= ELAX_ORDER + @param PciDevice A pointer to PCI_IO_DEVICE +**/ +VOID +SetDevicePolicyPciExpressRo ( + IN EFI_PCI_EXPRESS_RELAX_ORDER RelaxOrder, + OUT PCI_IO_DEVICE *PciDevice + ) +{ + // + // implementation specific rules for the usage of PCI_FEATURE_POLICY mem= bers + // exclusively for the PCI Feature Relax Ordering (RO) + // + // .Override =3D 0 to skip this PCI feature RO for the PCI device + // .Override =3D 1 to program this RO PCI feature + // .Act =3D 1 to enable the RO in the PCI device + // .Act =3D 0 to disable the RO in the PCI device + // + switch (RelaxOrder) { + case EFI_PCI_EXPRESS_RO_AUTO: + PciDevice->SetupRO.Override =3D 0; + break; + case EFI_PCI_EXPRESS_RO_DISABLE: + PciDevice->SetupRO.Override =3D 1; + PciDevice->SetupRO.Act =3D 0; + break; + case EFI_PCI_EXPRESS_RO_ENABLE: + PciDevice->SetupRO.Override =3D 1; + PciDevice->SetupRO.Act =3D 1; + break; + default: + PciDevice->SetupRO.Override =3D 0; + break; + } +} + /** Generic routine to setup the PCI features as per its predetermined defau= lts. **/ @@ -170,6 +209,8 @@ SetupDefaultPciExpressDevicePolicy ( PciDevice->SetupMRRS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; } =20 + PciDevice->SetupRO.Override =3D 0; + } =20 /** @@ -259,6 +300,15 @@ GetPciExpressDevicePolicy ( } else { PciDevice->SetupMRRS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; } + // + // set device specific policy for Relax Ordering + // + if (mPciExpressPlatformPolicy.RelaxOrder) { + SetDevicePolicyPciExpressRo (PciExpressDevicePolicy.DeviceCtlRelaxOr= der, PciDevice); + } else { + PciDevice->SetupRO.Override =3D 0; + } + =20 DEBUG (( DEBUG_INFO, @@ -438,6 +488,17 @@ PciExpressPlatformNotifyDeviceState ( } else { PciExDeviceConfiguration.DeviceCtlMRRS =3D EFI_PCI_EXPRESS_NOT_APPLICA= BLE; } + // + // get the device-specific state for the PCIe Relax Order feature + // + if (mPciExpressPlatformPolicy.RelaxOrder) { + PciExDeviceConfiguration.DeviceCtlRelaxOrder =3D PciDevice->PciExpress= CapabilityStructure.DeviceControl.Bits.RelaxedOrdering + ? EFI_PCI_EXPRESS_RO= _ENABLE + : EFI_PCI_EXPRESS_RO= _DISABLE; + } else { + PciExDeviceConfiguration.DeviceCtlRelaxOrder =3D EFI_PCI_EXPRESS_NOT_A= PPLICABLE; + } + =20 if (mPciExPlatformProtocol !=3D NULL) { return mPciExPlatformProtocol->NotifyDeviceState ( --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54068): https://edk2.groups.io/g/devel/message/54068 Mute This Topic: https://groups.io/mt/71063079/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-