From nobody Tue Nov 26 14:38:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54065+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54065+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1581105968500147.93310493933723; Fri, 7 Feb 2020 12:06:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id RykPYY1788612xjbOJgTU9jA; Fri, 07 Feb 2020 12:06:08 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web09.10525.1581105967427505892 for ; Fri, 07 Feb 2020 12:06:07 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2020 12:06:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,414,1574150400"; d="scan'208";a="225644163" X-Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 07 Feb 2020 12:06:04 -0800 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] MdeModulePkg/PciBusDxe: Setup PCI Express init phase Date: Sat, 8 Feb 2020 01:34:37 +0530 Message-Id: <20200207200447.10536-3-ashraf.javeed@intel.com> In-Reply-To: <20200207200447.10536-1-ashraf.javeed@intel.com> References: <20200207200447.10536-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: pfztSfJrPGqN3no3h05hFqD3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581105968; bh=ujF5FwecCA/sTgNICgHL7RaFuYbZmuX/4oxt7I1wiog=; h=Cc:Date:From:Reply-To:Subject:To; b=LSd8UI0CQe4UxM5AvZWxKSE3xhw1+BZQatE0ozqxsjVZLUJyhSH68ReaKTKD0dvMitJ z1WsubiGWwxv3QCK+yvF/VR5lsiONHyFjDEY8aToo+1ABJmXAUoOKH3kFDw8f54NZg+fj ks5lEqcWWm/zY/qMV+sQc7+PHMXE9fZdIC8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" References:- https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 https://bugzilla.tianocore.org/show_bug.cgi?id=3D2499 https://bugzilla.tianocore.org/show_bug.cgi?id=3D2500 This code change represents the preparation of phase for initializing the PCI Express features at the end of PCI enumeration phase. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 181 +++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------= -------------- MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 23 +++++++++++++++++= ++++++ 2 files changed, 169 insertions(+), 35 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModuleP= kg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index b7832c6..07ee9ba 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -1,7 +1,7 @@ /** @file Supporting functions implementation for PCI devices management. =20 -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
(C) Copyright 2018 Hewlett Packard Enterprise Development LP
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -597,7 +597,7 @@ DeRegisterPciDevice ( } =20 /** - Start to manage the PCI device on the specified root bridge or PCI-PCI B= ridge. + Start the PCI root Ports or PCI-PCI Bridge only. =20 @param Controller The root bridge handle. @param RootBridge A pointer to the PCI_IO_DEVICE. @@ -612,7 +612,82 @@ DeRegisterPciDevice ( =20 **/ EFI_STATUS -StartPciDevicesOnBridge ( +EnablePciBridges ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *RootBridge + ) + +{ + PCI_IO_DEVICE *PciIoDevice; + EFI_STATUS Status; + LIST_ENTRY *CurrentLink; + UINT64 Supports; + + PciIoDevice =3D NULL; + CurrentLink =3D RootBridge->ChildList.ForwardLink; + + while (CurrentLink !=3D NULL && CurrentLink !=3D &RootBridge->ChildList)= { + + PciIoDevice =3D PCI_IO_DEVICE_FROM_LINK (CurrentLink); + + // + // check if the device has been assigned with required resource + // and registered + // + if (!PciIoDevice->Registered && !PciIoDevice->Allocated) { + return EFI_NOT_READY; + } + + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { + Status =3D EnablePciBridges ( + Controller, + PciIoDevice + ); + + PciIoDevice->PciIo.Attributes ( + &(PciIoDevice->PciIo), + EfiPciIoAttributeOperationSupported, + 0, + &Supports + ); + Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; + PciIoDevice->PciIo.Attributes ( + &(PciIoDevice->PciIo), + EfiPciIoAttributeOperationEnable, + Supports, + NULL + ); + + } + + CurrentLink =3D CurrentLink->ForwardLink; + } + + if (PciIoDevice =3D=3D NULL) { + return EFI_NOT_FOUND; + } else { + return EFI_SUCCESS; + } +} + + +/** + Register to manage the PCI device on the specified root bridge or PCI-PC= I Bridge. + + @param Controller The root bridge handle. + @param RootBridge A pointer to the PCI_IO_DEVICE. + @param RemainingDevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL. + @param NumberOfChildren Children number. + @param ChildHandleBuffer A pointer to the child handle buffer. + + @retval EFI_NOT_READY Device is not allocated. + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge. + @retval EFI_NOT_FOUND Can not find the specific device. + @retval EFI_SUCCESS Success to start Pci devices on bridge. + +**/ +EFI_STATUS +RegisterPciDevicesOnBridge ( IN EFI_HANDLE Controller, IN PCI_IO_DEVICE *RootBridge, IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, @@ -626,7 +701,6 @@ StartPciDevicesOnBridge ( EFI_DEVICE_PATH_PROTOCOL *CurrentDevicePath; EFI_STATUS Status; LIST_ENTRY *CurrentLink; - UINT64 Supports; =20 PciIoDevice =3D NULL; CurrentLink =3D RootBridge->ChildList.ForwardLink; @@ -681,7 +755,7 @@ StartPciDevicesOnBridge ( // If it is a PPB // if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { - Status =3D StartPciDevicesOnBridge ( + Status =3D RegisterPciDevicesOnBridge ( Controller, PciIoDevice, CurrentDevicePath, @@ -689,20 +763,6 @@ StartPciDevicesOnBridge ( ChildHandleBuffer ); =20 - PciIoDevice->PciIo.Attributes ( - &(PciIoDevice->PciIo), - EfiPciIoAttributeOperationSupported, - 0, - &Supports - ); - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; - PciIoDevice->PciIo.Attributes ( - &(PciIoDevice->PciIo), - EfiPciIoAttributeOperationEnable, - Supports, - NULL - ); - return Status; } else { =20 @@ -733,28 +793,13 @@ StartPciDevicesOnBridge ( } =20 if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { - Status =3D StartPciDevicesOnBridge ( + Status =3D RegisterPciDevicesOnBridge ( Controller, PciIoDevice, RemainingDevicePath, NumberOfChildren, ChildHandleBuffer ); - - PciIoDevice->PciIo.Attributes ( - &(PciIoDevice->PciIo), - EfiPciIoAttributeOperationSupported, - 0, - &Supports - ); - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; - PciIoDevice->PciIo.Attributes ( - &(PciIoDevice->PciIo), - EfiPciIoAttributeOperationEnable, - Supports, - NULL - ); - } =20 CurrentLink =3D CurrentLink->ForwardLink; @@ -768,6 +813,72 @@ StartPciDevicesOnBridge ( } } =20 +/** + Start to manage the PCI device on the specified root bridge or PCI-PCI B= ridge. + + @param Controller The root bridge handle. + @param RootBridge A pointer to the PCI_IO_DEVICE. + @param RemainingDevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL. + @param NumberOfChildren Children number. + @param ChildHandleBuffer A pointer to the child handle buffer. + + @retval EFI_NOT_READY Device is not allocated. + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge. + @retval EFI_NOT_FOUND Can not find the specific device. + @retval EFI_SUCCESS Success to start Pci devices on bridge. + +**/ +EFI_STATUS +StartPciDevicesOnBridge ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *RootBridge, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, + IN OUT UINT8 *NumberOfChildren, + IN OUT EFI_HANDLE *ChildHandleBuffer + ) + +{ + EFI_STATUS Status; + + // + // first register all the PCI devices + // + Status =3D RegisterPciDevicesOnBridge ( + Controller, + RootBridge, + RemainingDevicePath, + NumberOfChildren, + ChildHandleBuffer + ); + + if (EFI_ERROR (Status)) { + return Status; + } else { + // + // the late configuration of PCI Express features + // the platform is required to indicate its requirement for the initia= lization + // of PCI Express features by publishing its protocol + // + if ( + gFullEnumeration + && IsPciExpressProtocolPresent () + ) { + + Status =3D EnumeratePciExpressFeatures ( + Controller, + RootBridge + ); + } + // + // finally start those PCI bridge port devices only + // + return EnablePciBridges ( + Controller, + RootBridge + ); + } +} + /** Start to manage all the PCI devices it found previously under the entire host bridge. diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h index 2eff8aa..9b7e51f 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -223,4 +223,27 @@ typedef struct { }PCI_EXPRESS_FEATURE_INITIALIZATION_POINT; =20 =20 + +/** + Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge, = to + configure the other PCI features. + + @param RootBridge A pointer to the PCI_IO_DEVICE. + + @retval EFI_SUCCESS The other PCI features configuration durin= g enumeration + of all the nodes of the PCI root bridge in= stance were + programmed in PCI-compliance pattern along= with the + device-specific policy, as applicable. + @retval EFI_UNSUPPORTED One of the override operation maong the no= des of + the PCI hierarchy resulted in a incompatib= le address + range. + @retval EFI_INVALID_PARAMETER The override operation is performed with i= nvalid input + parameters. +**/ +EFI_STATUS +EnumeratePciExpressFeatures ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *RootBridge + ); + #endif --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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