From nobody Tue Nov 26 15:49:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54075+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54075+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1581105997745590.0743447701425; Fri, 7 Feb 2020 12:06:37 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6HKxYY1788612xMayANv0mvW; Fri, 07 Feb 2020 12:06:37 -0800 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web09.10529.1581105978095314348 for ; Fri, 07 Feb 2020 12:06:36 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2020 12:06:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,414,1574150400"; d="scan'208";a="225644353" X-Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 07 Feb 2020 12:06:33 -0800 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/12] PciBusDxe: New PCI Express feature Common CLock Config Date: Sat, 8 Feb 2020 01:34:47 +0530 Message-Id: <20200207200447.10536-13-ashraf.javeed@intel.com> In-Reply-To: <20200207200447.10536-1-ashraf.javeed@intel.com> References: <20200207200447.10536-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: QZqfl4GSvfFFuNPNW3uXleH1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581105997; bh=hDhiCpH4ppaC2EZfUj5egwJs78FhH1NtgOGwY7G7imE=; h=Cc:Date:From:Reply-To:Subject:To; b=iN4J1eFSzJfOe8uAfJRFS7AAcaxTtLKNySyNLnErQe2ukqoX19VfRcuyRUOTfkBjHuZ He7XFCPkPp8L1lL+ObSZuqx9kPvJmWEOTF5NVwpaFBXpSckhfv55IQRbl3H7p1JbDJPPM 0LEPBmNoqmR8bgfpCsw998kCn80zJfJhpUg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2500 This code change enforces the Link Control register CCC field as per the following conditions:- (1) When the Clock Configuration device policy for all the devices are set to EFI_PCI_EXPRESS_CLK_CFG_AUTO:- - Based on the Link Status register's Slot Clock Configuration field, all the devices CCC value shall be aligned (2) When the Clock Configuration device policy for one or more devices are either set to EFI_PCI_EXPRESS_CLK_CFG_ASYNCH or EFI_PCI_EXPRESS_ CLK_CFG_COMMON - enforces the same clock configuration for all the devices from root bridge Note that the recommendation to the platform is to always provide the device policy as EFI_PCI_EXPRESS_CLK_CFG_AUTO. In case for any device its Link Control register CCC field is required to be changed based on its present HW-state, than Link Retraining is preformed on the downstream ports as per the PCI Express Base specification. This programming of CCC, gets the device-specific platform policy using the new PCI Express Platform Protocol interface (ECR version 0.8), defined in the below feature request:- https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 267 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 51 ++++++++++++++++= +++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 20 ++++++++++++++++= ++-- MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 9 +++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 28 ++++++++++++++++= ++++++++++++ 6 files changed, 374 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index b5caffe..34f482d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -299,6 +299,7 @@ struct _PCI_IO_DEVICE { BOOLEAN SetupLtr; UINT8 SetupExtTag; UINT8 SetupAspm; + EFI_PCI_EXPRESS_COMMON_CLOCK_CFG SetupCcc; }; =20 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c index 5e350e7..1e2f4a4 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c @@ -1909,3 +1909,270 @@ ProgramAspm ( return EFI_SUCCESS; } =20 +/** + The main routine to setup the PCI Express feature Common Clock configura= tion + as per the device-specific platform policy, as well as in complaince wit= h the + PCI Express Base specification Revision 5. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE + + @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful. +**/ +EFI_STATUS +SetupCommonClkCfg ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble + ) +{ + PCI_REG_PCIE_LINK_STATUS LinkSts; + + LinkSts.Uint16 =3D PciDevice->PciExpressCapabilityStructure.LinkStatus.U= int16; + + // + // Common Clock Configuration is only applicable to root bridge and its = child + // devices. Not applicable to empty bridge devices or RCiEP devices + // + if (PciExpressConfigurationTable) { + if (PciDevice->SetupCcc =3D=3D EFI_PCI_EXPRESS_CLK_CFG_AUTO) { + // + // as per the PCI Express Base Specification, the link status regist= er + // slot clock configuration of the opposing side of link devices ind= icate + // the clock configuration properly; hence rely on this data to conf= igure + // the link's clock configuration + // + if (LinkSts.Bits.SlotClockConfiguration) { + PciExpressConfigurationTable->CommonClockConfiguration =3D TRUE; + } else { + PciExpressConfigurationTable->CommonClockConfiguration =3D FALSE; + } + } else if (PciDevice->SetupCcc =3D=3D EFI_PCI_EXPRESS_CLK_CFG_ASYNCH) { + // + // platform override to any device shall change for other device on = the + // link, the clock configuration has to be maintained common across = all + // the devices + // + PciExpressConfigurationTable->CommonClockConfiguration =3D FALSE; + } else { + PciExpressConfigurationTable->CommonClockConfiguration =3D TRUE; + } + } + return EFI_SUCCESS; +} + +/** + Program the PCIe Link Control register Coomon Clock Configuration field;= if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +ProgramCcc ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration + ) +{ + PCI_REG_PCIE_LINK_CONTROL LinkCtl; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + // + // Common Clock Configuration is only applicable to root bridge and its = child + // devices. Not applicable to empty bridge devices or RCiEP devices + // + if (!PciExFeatureConfiguration) { + return EFI_SUCCESS; + } + + // + // read the link Control register for the ASPM Control + // + LinkCtl.Uint16 =3D 0; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &LinkCtl.Uint16 + ); + ASSERT (Status =3D=3D EFI_SUCCESS); + + // + // in case Common Clock Configuration is required to be programmed in the + // downstream ports from the root bridge devices in the heirarchy + // + if (PciExFeatureConfiguration->CommonClockConfiguration =3D=3D TRUE) { + if (LinkCtl.Bits.CommonClockConfiguration =3D=3D 0) { + LinkCtl.Bits.CommonClockConfiguration =3D 1; + // + // current clock mode does not match hence retrain of the link at br= idge device + // is required + // + PciExFeatureConfiguration->LinkReTrain =3D TRUE; + } + } else { + // + // in case the opposing devices of the PCI link have different referen= ce clock + // set the link control register CCC field accordingly + // + if (LinkCtl.Bits.CommonClockConfiguration) { + LinkCtl.Bits.CommonClockConfiguration =3D 0; + // + // current clock mode does not match hence retrain of the link at br= idge device + // is required + // + PciExFeatureConfiguration->LinkReTrain =3D TRUE; + } + } + // + // use the retrain flag as a sigm to also update the CCC of the link reg= ister + // + if (PciExFeatureConfiguration->LinkReTrain =3D=3D TRUE) { + DEBUG (( + DEBUG_INFO, + "CCC: %d,", + LinkCtl.Bits.CommonClockConfiguration + )); + // + // Raise TPL to high level to disable timer interrupt while the write = operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &LinkCtl.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR (Status)) { + PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 =3D Link= Ctl.Uint16; + } else { + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset); + return Status; + } + } else { + PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 =3D LinkCt= l.Uint16; + DEBUG (( + DEBUG_INFO, + "No CCC (%d),", + LinkCtl.Bits.CommonClockConfiguration + )); + } + return EFI_SUCCESS; +} + +/** + Second phase of programming for Common Clock COnfiguration, conditoonall= y done + only on the downstream ports (bridge devices only). + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +EnforceCcc ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration + ) +{ + PCI_REG_PCIE_LINK_CONTROL LinkCtl; + PCI_REG_PCIE_LINK_STATUS LinkSts; + PCI_REG_PCIE_CAPABILITY PciExCap; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + // + // Common Clock Configuration is only applicable to root bridge and its = child + // devices. Not applicable to empty bridge devices or RCiEP devices + // + if (!PciExFeatureConfiguration) { + return EFI_SUCCESS; + } + PciExCap.Uint16 =3D PciDevice->PciExpressCapabilityStructure.Capability.= Uint16; + LinkCtl.Uint16 =3D PciDevice->PciExpressCapabilityStructure.LinkControl.= Uint16; + + // + // retrain the bridge device (downstream ports including the root port) + // + if (PciExFeatureConfiguration->LinkReTrain =3D=3D TRUE) { + if (IS_PCI_BRIDGE (&PciDevice->Pci)) { + // + // retrain of the PCI link happens for CCC change only on the downst= ream + // ports + // + if ( + PciExCap.Bits.DevicePortType =3D=3D PCIE_DEVICE_PORT_TYPE_ROOT_PORT + || PciExCap.Bits.DevicePortType =3D=3D PCIE_DEVICE_PORT_TYPE_DOWNS= TREAM_PORT + ) { + LinkCtl.Bits.RetrainLink =3D 1; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl); + // + // Raise TPL to high level to disable timer interrupt while the wr= ite operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &LinkCtl.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR (Status)) { + // + // poll the link status register for the link retrain to be comp= lete + // + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkStatu= s); + do { + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &LinkSts.Uint16 + ); + ASSERT (Status =3D=3D EFI_SUCCESS); + } while (LinkSts.Bits.LinkTraining); + } else { + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumb= er, PciDevice->FunctionNumber, Offset); + return Status; + } + } + // + // ignore the upstream bridge devices + // + } + // + // not applicable to endpoint devices + // + } + return EFI_SUCCESS; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h index 351c61e..33df337 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h @@ -345,4 +345,55 @@ ProgramAspm ( IN VOID *PciExFeatureConfiguration ); =20 +/** + The main routine to setup the PCI Express feature Common Clock configura= tion + as per the device-specific platform policy, as well as in complaince wit= h the + PCI Express Base specification Revision 5. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE + + @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful. +**/ +EFI_STATUS +SetupCommonClkCfg ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble + ); + +/** + Program the PCIe Link Control register Coomon Clock Configuration field;= if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +ProgramCcc ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration + ); + +/** + Second phase of programming for Common Clock COnfiguration, conditoonall= y done + only on the downstream ports (bridge devices only). + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +EnforceCcc ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration + ); #endif diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index 24781c6..4d3641c 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -54,7 +54,7 @@ EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPl= atformPolicy =3D { // // support for PCI Express feature - Common Clock Configuration // - FALSE, + TRUE, // // support for PCI Express feature - Extended Sync // @@ -95,7 +95,15 @@ BOOLEAN mPciExpressGetPlatformPolicyComplete =3D FALSE; // PCI Express feature initialization phase handle routines // PCI_EXPRESS_FEATURE_INITIALIZATION_POINT mPciExpressFeatureInitialization= List[] =3D { - + { + PciExpressFeatureSetupPhase, PciExpressCcc, SetupCommo= nClkCfg + }, + { + PciExpressFeatureEntendedSetupPhase, PciExpressCcc, ProgramCcc + }, + { + PciExpressFeatureProgramPhase, PciExpressCcc, EnforceCcc + }, { PciExpressFeatureSetupPhase, PciExpressAspm, SetupAspm }, @@ -709,6 +717,14 @@ CreatePciRootBridgeDeviceNode ( // start by assuming less than 1us of L1 Exit Latency // PciConfigTable->L1ExitLatency =3D PCIE_LINK_CAPABILITY_L= 1_EXIT_LATENCY_1US; + // + // default link retrain is not required + // + PciConfigTable->LinkReTrain =3D FALSE; + // + // start by assuming no common clock configuration mode for the device= 's link + // + PciConfigTable->CommonClockConfiguration =3D FALSE; } =20 RootBridgeNode->PciExFeaturesConfigurationTable =3D PciConfigTable; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h index 5e0f43b..481bd90 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -112,6 +112,15 @@ struct _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE { // bridge device to its downstream bridge and its endpoint device // UINT8 L1ExitLatency; + // + // flag to indicate the link training is required in the devices of down= stream + // ports + // + BOOLEAN LinkReTrain; + // + // link status slot clock configuration + // + BOOLEAN CommonClockConfiguration; }; =20 // diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index f301557..bf380ab 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -383,6 +383,14 @@ SetupDefaultPciExpressDevicePolicy ( PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; } =20 + // + // default device policy for the device's link clock configuration + // + if (mPciExpressPlatformPolicy.Ccc) { + PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_CLK_CFG_AUTO; + } else { + PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; + } =20 } =20 @@ -536,6 +544,15 @@ GetPciExpressDevicePolicy ( PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; } =20 + // + // set the device policy for the PCI Express feature Common Clock Conf= iguration + // + if (mPciExpressPlatformPolicy.Ccc) { + PciDevice->SetupCcc =3D PciExpressDevicePolicy.LinkCtlCommonClkCfg; + } else { + PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; + } + DEBUG (( DEBUG_INFO, "[device policy: platform]" @@ -850,6 +867,17 @@ PciExpressPlatformNotifyDeviceState ( PciExDeviceConfiguration.LinkCtlASPMState =3D EFI_PCI_EXPRESS_NOT_APPL= ICABLE; } =20 + // + // get the device-specific Common CLock Configuration value + // + if (mPciExpressPlatformPolicy.Ccc) { + PciExDeviceConfiguration.LinkCtlCommonClkCfg =3D + PciDevice->PciExpressCapabilityStructure.LinkControl.Bits.CommonCl= ockConfiguration ? + EFI_PCI_EXPRESS_CLK_CFG_COMMON : EFI_PCI_EXPRESS_CLK_CFG_ASYNC= H; + } else { + PciExDeviceConfiguration.LinkCtlCommonClkCfg =3D EFI_PCI_EXPRESS_NOT_A= PPLICABLE; + } + if (mPciExPlatformProtocol !=3D NULL) { return mPciExPlatformProtocol->NotifyDeviceState ( mPciExPlatformProtocol, --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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