From nobody Tue Nov 26 14:22:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54073+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54073+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1581105993948609.8946315997629; Fri, 7 Feb 2020 12:06:33 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2ITvYY1788612xl668pqYSPu; Fri, 07 Feb 2020 12:06:33 -0800 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web09.10529.1581105978095314348 for ; Fri, 07 Feb 2020 12:06:33 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2020 12:06:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,414,1574150400"; d="scan'208";a="225644334" X-Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 07 Feb 2020 12:06:28 -0800 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI Express feature Extended Tag Date: Sat, 8 Feb 2020 01:34:45 +0530 Message-Id: <20200207200447.10536-11-ashraf.javeed@intel.com> In-Reply-To: <20200207200447.10536-1-ashraf.javeed@intel.com> References: <20200207200447.10536-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: RKhAEgPEJ7p9X2CAXmwGj7i1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581105993; bh=5FO4Ws1OYlHtLtroVpe113S4OdCem6oSfGzCgEPQKgA=; h=Cc:Date:From:Reply-To:Subject:To; b=ctqbN/kJje4jRAuIUXtG5LtN3TUdMFFVjn6WXlWwecBkgCmAb3zt3GnHS6JPaOfmEne bF7TGXr2z4BF/2fBeyb1Aiu9/4d3hBeY1e91IbbDD9am+GXMwHdxbeDxgA2fkESOSiPxS AH5AZ+0Kj7Uy3uLJJ36jdKMDRWXnSm2nH9w= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2499 This code change enables the PCI Express feature Extended Tag, in compliance with the PCI Express Base Specification 5, and uses the device policy under the following conditions: (1) As per the PCI Express Base Specification, all the devices under the root bridge has to be set to a common applicable value (2) The 5b or 8b Extended Tag capability is defined in the Device Capabi- lity register, and the 10b requester as well as completer is defined in the Device Capability 2 register (3) The Extended Tag device policy would be overruled for any device if it does not match with its device capabilities register (4) In case of multiple device policies, due to multiple devices under the root bridge, the lowest applicable value will be programmed for all the devices (5) There is no Extended Tag disable state; hence the default would be 5b or 8b depending upon device HW-state. The 10b requester is disabled by default; hence any device policy request of 10b shall lead to 10b Requester enable state from root bridge to all end devices; if all the devices support 10b Requester as well as the completer capability. In this scenario, the default state of 5b/8b Extended Tag state in Device Control register is ignored as 10b capable devices should be able to handle lower size Extended Tag packet IDs autonomously. This programming of Extended Tag, gets the device-specific platform policy using the new PCI Express Platform Protocol interface (ECR version 0.8), defined in the below feature request:- https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 278 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 50 ++++++++++++++++= ++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 15 ++++++++++++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 4 ++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 36 ++++++++++++++++= ++++++++++++++++++++ 6 files changed, 383 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 7e43a26..6a6f648 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -297,6 +297,7 @@ struct _PCI_IO_DEVICE { PCI_FEATURE_POLICY SetupCTO; EFI_PCI_EXPRESS_ATOMIC_OP SetupAtomicOp; BOOLEAN SetupLtr; + UINT8 SetupExtTag; }; =20 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c index 63a243b..eaef3d3 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c @@ -1240,3 +1240,281 @@ ProgramLtr ( return Status; } =20 +/** + The main routine to setup the PCI Express feature Extended Tag as per the + device-specific platform policy, as well as in complaince with the PCI E= xpress + Base specification Revision 5. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE + + @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful. +**/ +EFI_STATUS +SetupExtTag ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble + ) +{ + PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2; + PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCap; + EFI_PCI_EXPRESS_EXTENDED_TAG PciExpressExtendedTag; + + DeviceCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceCapa= bility.Uint32; + DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceCap= ability2.Uint32; + // + // The PCI Express feature Extended Tag has to be maintained common from= a + // root bridge device to all its child devices. + // The Device Capability 2 register is used to determine the 10b Extende= d Tag + // capability of a device. The device capability register is used to det= ermine + // 5b/8b Extended Tag capability of a device + // + if (DeviceCap2.Bits.TenBitTagCompleterSupported & DeviceCap2.Bits.TenBit= TagRequesterSupported) { + // + // device supports the 10b Extended Tag capability + // + PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT; + } else { + if (DeviceCap.Bits.ExtendedTagField) { + PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT; + } else { + PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT; + } + } + if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_AUTO) { + PciDevice->SetupExtTag =3D PciExpressExtendedTag; + } + // + // in case of PCI Bridge and its child devices + // + if (PciExpressConfigurationTable) { + // + // align the Extended Tag value as per the device supported value + // + PciExpressConfigurationTable->ExtendedTag =3D MIN ( + PciExpressExtendedTag, + PciExpressConfigurationT= able->ExtendedTag + ); + // + // check for any invalid platform policy request for the device; if tr= ue than + // align with the device capability value. Else align as per platform = request + // + if (PciDevice->SetupExtTag > PciExpressConfigurationTable->ExtendedTag= ) { + // + // setup the device Extended Tag to common value supported by all th= e devices + // + PciDevice->SetupExtTag =3D PciExpressConfigurationTable->ExtendedTag; + } + // + // if the platform policy is to downgrade the device's Extended Tag va= lue than + // all the other devices in the PCI tree including the root bridge wil= l be align + // with this device override value + // + if (PciDevice->SetupExtTag < PciExpressConfigurationTable->ExtendedTag= ) { + PciExpressConfigurationTable->ExtendedTag =3D PciDevice->SetupExtTag; + } + } else { + // + // in case of RCiEP devices or the bridge device without any child, ov= errule + // the Extended Tag device policy if it does not match with its capabi= lity + // + PciDevice->SetupExtTag =3D MIN ( + PciDevice->SetupExtTag, + PciExpressExtendedTag + ); + } + + DEBUG (( + DEBUG_INFO, + "ExtTag: %d [cap:%d],", + PciDevice->SetupExtTag, + PciExpressExtendedTag + )); + return EFI_SUCCESS; +} + +/** + Additional routine to setup the PCI Express feature Extended Tag in comp= laince + with the PCI Express Base specification Revision, a common value for all= the + devices in the PCI hierarchy. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE + + @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful. +**/ +EFI_STATUS +AlignExtTag ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble + ) +{ + if (PciExpressConfigurationTable) { + // + // align the Extended Tag value to a common value among all the devices + // + PciDevice->SetupExtTag =3D MIN ( + PciDevice->SetupExtTag, + PciExpressConfigurationTable->ExtendedTag + ); + } + + DEBUG (( + DEBUG_INFO, + "ExtTag: %d,", + PciDevice->SetupExtTag + )); + return EFI_SUCCESS; +} + +/** + Program the PCI Device Control 2 register for 10b Extended Tag value, or= the + Device Control register for 5b/8b Extended Tag value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +ProgramExtTag ( + IN PCI_IO_DEVICE *PciDevice, + IN VOID *PciExFeatureConfiguration + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL DevCtl; + PCI_REG_PCIE_DEVICE_CONTROL2 DevCtl2; + UINT32 Offset; + UINT32 Offset2; + BOOLEAN OverrideDevCtl; + BOOLEAN OverrideDevCtl2; + EFI_STATUS Status; + EFI_TPL OldTpl; + + // + // read the Device Control register for the Extended Tag Field Enable + // + DevCtl.Uint16 =3D 0; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &DevCtl.Uint16 + ); + ASSERT (Status =3D=3D EFI_SUCCESS); + + OverrideDevCtl =3D FALSE; + // + // read the Device COntrol 2 register for the 10-Bit Tag Requester Enable + // + DevCtl2.Uint16 =3D 0; + Offset2 =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset2, + 1, + &DevCtl2.Uint16 + ); + ASSERT (Status =3D=3D EFI_SUCCESS); + + OverrideDevCtl2 =3D FALSE; + + if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT) { + if (DevCtl.Bits.ExtendedTagField) { + DevCtl.Bits.ExtendedTagField =3D 0; + OverrideDevCtl =3D TRUE; + } + + if (DevCtl2.Bits.TenBitTagRequesterEnable) { + DevCtl2.Bits.TenBitTagRequesterEnable =3D 0; + OverrideDevCtl2 =3D TRUE; + } + } + if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT) { + if (!DevCtl.Bits.ExtendedTagField) { + DevCtl.Bits.ExtendedTagField =3D 1; + OverrideDevCtl =3D TRUE; + } + if (DevCtl2.Bits.TenBitTagRequesterEnable) { + DevCtl2.Bits.TenBitTagRequesterEnable =3D 0; + OverrideDevCtl2 =3D TRUE; + } + } + if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT) { + if (!DevCtl2.Bits.TenBitTagRequesterEnable) { + DevCtl2.Bits.TenBitTagRequesterEnable =3D 1; + OverrideDevCtl2 =3D TRUE; + } + } + + if (OverrideDevCtl) { + + DEBUG (( DEBUG_INFO, "ExtTag=3D%d,", DevCtl.Bits.ExtendedTagField)); + + // + // Raise TPL to high level to disable timer interrupt while the write = operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &DevCtl.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D De= vCtl.Uint16; + } else { + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset); + } + } else { + DEBUG (( DEBUG_INFO, "no ExtTag (%d),", DevCtl.Bits.ExtendedTagField)); + } + + if (OverrideDevCtl2) { + + DEBUG (( DEBUG_INFO, "10bExtTag=3D%d,", DevCtl2.Bits.TenBitTagRequeste= rEnable)); + + // + // Raise TPL to high level to disable timer interrupt while the write = operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset2, + 1, + &DevCtl2.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D D= evCtl2.Uint16; + } else { + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset2); + } + } else { + DEBUG (( DEBUG_INFO, "no 10bExtTag (%d),", DevCtl2.Bits.TenBitTagReque= sterEnable)); + } + + return Status; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h index 374fe49..1cfca54 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h @@ -243,4 +243,54 @@ ProgramLtr ( IN VOID *PciExFeatureConfiguration ); =20 +/** + The main routine to setup the PCI Express feature Extended Tag as per the + device-specific platform policy, as well as in complaince with the PCI E= xpress + Base specification Revision 5. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE + + @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful. +**/ +EFI_STATUS +SetupExtTag ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able + ); + +/** + Additional routine to setup the PCI Express feature Extended Tag in comp= laince + with the PCI Express Base specification Revision, a common value for all= the + devices in the PCI hierarchy. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE + + @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful. +**/ +EFI_STATUS +AlignExtTag ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able + ); + +/** + Program the PCI Device Control 2 register for 10b Extended Tag value, or= the + Device Control register for 5b/8b Extended Tag value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +ProgramExtTag ( + IN PCI_IO_DEVICE *PciDevice, + IN VOID *PciExFeatureConfiguration + ); + #endif diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index bdeb0d2..58d3780 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -38,7 +38,7 @@ EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPl= atformPolicy =3D { // // support for PCI Express feature - Extended Tag // - FALSE, + TRUE, // // support for PCI Express feature - Relax Order // @@ -140,6 +140,15 @@ PCI_EXPRESS_FEATURE_INITIALIZATION_POINT mPciExpressF= eatureInitializationList[] }, { PciExpressFeatureProgramPhase, PciExpressLtr, ProgramLtr + }, + { + PciExpressFeatureSetupPhase, PciExpressExtTag, SetupExtTag + }, + { + PciExpressFeatureEntendedSetupPhase, PciExpressExtTag, AlignExtTag + }, + { + PciExpressFeatureProgramPhase, PciExpressExtTag, ProgramExt= Tag } }; =20 @@ -675,6 +684,10 @@ CreatePciRootBridgeDeviceNode ( // tree // PciConfigTable->AtomicOpRoutingSupported =3D TRUE; + // + // start by assuming the Extended Tag is 10b Requester capable + // + PciConfigTable->ExtendedTag =3D EFI_PCI_EXPRESS_EXTEND= ED_TAG_10BIT; } =20 RootBridgeNode->PciExFeaturesConfigurationTable =3D PciConfigTable; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h index 5dded7c..c7cc7e5 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -94,6 +94,10 @@ struct _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE { // the AtomicOp of the EP device // BOOLEAN AtomicOpRoutingSupported; + // + // to configure a common extended tag size for all the childs of a root = port + // + UINT8 ExtendedTag; }; =20 // diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index 83b3aa7..98d9875 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -368,6 +368,12 @@ SetupDefaultPciExpressDevicePolicy ( =20 PciDevice->SetupLtr =3D FALSE; =20 + if (mPciExpressPlatformPolicy.ExtTag) { + PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_AUTO; + } else { + PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; + } + } =20 /** @@ -502,6 +508,15 @@ GetPciExpressDevicePolicy ( PciDevice->SetupLtr =3D FALSE; } =20 + // + // set the device-specifci policy for the PCI Express feature Extended= Tag + // + if (mPciExpressPlatformPolicy.ExtTag) { + PciDevice->SetupExtTag =3D PciExpressDevicePolicy.DeviceCtlExtTag; + } else { + PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; + } + =20 DEBUG (( DEBUG_INFO, @@ -668,6 +683,19 @@ GetPciExpressCto ( return EFI_PCI_EXPRESS_NOT_APPLICABLE; } =20 +EFI_PCI_EXPRESS_EXTENDED_TAG +GetPciExpressExtTag ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + if (PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bits.TenBitT= agRequesterEnable) { + return EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT; + } else if (PciDevice->PciExpressCapabilityStructure.DeviceControl.Bits.E= xtendedTagField) { + return EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT; + } else { + return EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT; + } +} =20 /** Notifies the platform about the current PCI Express state of the device. @@ -768,6 +796,14 @@ PciExpressPlatformNotifyDeviceState ( PciExDeviceConfiguration.DeviceCtl2LTR =3D EFI_PCI_EXPRESS_NOT_APPLICA= BLE; } =20 + // + // get the device-specific state for the PCie Extended Tag in the functi= on + // + if (mPciExpressPlatformPolicy.ExtTag) { + PciExDeviceConfiguration.DeviceCtlExtTag =3D GetPciExpressExtTag (PciD= evice); + } else { + PciExDeviceConfiguration.DeviceCtlExtTag =3D EFI_PCI_EXPRESS_NOT_APPLI= CABLE; + } =20 if (mPciExPlatformProtocol !=3D NULL) { return mPciExPlatformProtocol->NotifyDeviceState ( --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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