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Fri, 7 Feb 2020 07:24:21 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , Varun Sethi Cc: devel@edk2.groups.io, Pankaj Bansal Subject: [edk2-devel] [PATCH 17/19] Silicon/NXP: Add Chassis3V2 Date: Fri, 7 Feb 2020 18:13:26 +0530 Message-Id: <20200207124328.8723-18-pankaj.bansal@nxp.com> In-Reply-To: <20200207124328.8723-1-pankaj.bansal@nxp.com> References: <20200207124328.8723-1-pankaj.bansal@nxp.com> X-ClientProxiedBy: PN1PR01CA0103.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::19) To VI1PR0401MB2496.eurprd04.prod.outlook.com (2603:10a6:800:56::10) MIME-Version: 1.0 X-Received: from uefi-workstation.ap.freescale.net (92.120.1.69) by PN1PR01CA0103.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2707.21 via Frontend Transport; Fri, 7 Feb 2020 07:24:19 +0000 X-Originating-IP: [92.120.1.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d5bbc3b6-a0b0-4649-acb3-08d7ab9ebff9 X-MS-TrafficTypeDiagnostic: VI1PR0401MB2575:|VI1PR0401MB2575: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pankaj.bansal@nxp.com X-Gm-Message-State: kRXz6v5oS5nDHNhDycLwlAlIx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581060264; bh=f2VGaFC6qw0VtLX9yOiI3O0h7IO0TEcDFQztl/r9DK4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=SERQx7nyc7ilNk+t7cNlGe3aYxtpi/cV7ve4P75Sa8Mmw6KVhnM2eF5Ha+6eyq0mcKZ GbeOpYKG6EBeHEskebmXIEpru+UyD4R7vzVug54k1MbZEYKJ5Mjj0zl8zX4scNU199zyE cj7ZOKSo271EvH1mu/5teQidQiCCo8mfvEk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Chassis3V2 Signed-off-by: Pankaj Bansal --- Silicon/NXP/Chassis3V2/Chassis3V2.dec | 23 +++ Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 + Silicon/NXP/Chassis3V2/Include/Chassis.h | 42 ++++ .../Library/ChassisLib/ChassisLib.c | 186 ++++++++++++++++++ .../Library/ChassisLib/ChassisLib.inf | 41 ++++ 5 files changed, 302 insertions(+) create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec b/Silicon/NXP/Chassis3V2= /Chassis3V2.dec new file mode 100644 index 0000000000..106b118188 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec @@ -0,0 +1,23 @@ +#/** @file +# NXP Layerscape processor package. +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + DEC_SPECIFICATION =3D 1.27 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package + diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc b/Silicon/NXP/Chassi= s3V2/Chassis3V2.dsc.inc new file mode 100644 index 0000000000..dabe2ae230 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc @@ -0,0 +1,10 @@ +# @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[LibraryClasses.common] + ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h b/Silicon/NXP/Chassis= 3V2/Include/Chassis.h new file mode 100644 index 0000000000..2771f26fe3 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h @@ -0,0 +1,42 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __CHASSIS_H__ +#define __CHASSIS_H__ + +#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000 + +#define TP_CLUSTER_ITYPE_IDX 0x3f +#define TP_CLUSTER_EOC BIT31 +#define TP_ITYPE_AVAILABLE BIT0 +#define TP_ITYPE_TYPE(x) (((x) & 0x06) >> 1) +#define TP_ITYPE_ARM 0x0 +#define TP_ITYPE_VERSION(x) (((x) & 0xe0) >> 5) + +#define TP_ITYPE_VERSION_A53 0x2 +#define TP_ITYPE_VERSION_A72 0x4 + +/** + The Device Configuration Unit provides general purpose configuration and= status for the + device. These registers only support 32-bit accesses. +**/ +#pragma pack(1) +typedef struct { + UINT8 Reserved0[0x100 - 0x0]; + UINT32 RcwSr[32]; // Reset Control Word Status Register + UINT8 Reserved180[0x200 - 0x180]; + UINT32 ScratchRw[16]; /// Scratch Read / Write Register + UINT8 Reserved240[0x740-0x240]; + UINT32 TpItyp[65]; /// Topology Initiator Type Register + struct { + UINT32 Lower; + UINT32 Upper; + }TpCluster[8]; +} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG; +#pragma pack() + +#endif diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c b/Silic= on/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c new file mode 100644 index 0000000000..99567bb76f --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c @@ -0,0 +1,186 @@ +/** @file + Chassis specific functions common to all SOCs based on a specific Chessis + + Copyright 2020 NXP + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +UINT32 +EFIAPI +DcfgRead32 ( + IN UINTN Address + ) +{ + if (FeaturePcdGet (PcdDcfgBigEndian)) { + return SwapMmioRead32 (Address); + } else { + return MmioRead32 (Address); + } +} + +UINT32 +EFIAPI +DcfgWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + if (FeaturePcdGet (PcdDcfgBigEndian)) { + return SwapMmioWrite32 (Address, Value); + } else { + return MmioWrite32 (Address, Value); + } +} + +/** + Get the type of core in cluster + + The core can be of type ARM or PowerPC or Hardware Accelerator. + If the core is enabled and of type ARM EFI_SUCCESS is returned and a cod= e for type of ARM core is returned + + @param[in] TpItypeIdx Index of Core to be searched in TpItyp in Devi= ce Config Registers. + @param[out] CoreType If the core is ARM core then the type of core = i.e. A53/A72 etc. + These cores are identified based on their code= s like TP_ITYPE_VERSION_A72 + + @return EFI_NOT_FOUND No enabled ARM core found + @return EFI_SUCCESS An enabled ARM core found +**/ +STATIC +EFI_STATUS +SocGetCoreType ( + IN UINT8 TpItypeIdx, + OUT UINT8 *CoreType + ) +{ + NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg; + UINT32 TpItype; + + Dcfg =3D (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASS= IS3V2_DCFG_ADDRESS; + TpItype =3D MmioRead32 ((UINTN)&Dcfg->TpItyp[TpItypeIdx]); + if (TpItype & TP_ITYPE_AVAILABLE) { + if (TP_ITYPE_TYPE (TpItype) =3D=3D TP_ITYPE_ARM) { + *CoreType =3D TP_ITYPE_VERSION (TpItype); + } else { + return EFI_NOT_FOUND; + } + } else { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + Return the number of cores present in SOC + + This function returns the number of cores present in SOC. + and also their position (cluster number and core number) in the form of = ARM_CORE_INFO array + and NxpCoreTable array. + NxpCoreTable array can be used to find out the type of core. it's values= are of type + TP_ITYPE_VERSION_*. + The number of cores present in SOC can vary depending on which flavour o= f SOC is being used. + This function doesn't allocte any memory and must be provided memory for= array of ARM_CORE_INFO + and NxpCoreTable for maximum number of cores the SOC can have. + + @param[out] NxpCoreTable array of UINT8 for maximum number of co= res the SOC can have. + @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum numb= er of cores the SOC can have. + @param[in] ArmCoreTableSize Size of ArmCoreTable + + @return Actual number of cores present in SOC. After calling thi= s function only the returned + value number of entries in ArmCoreTable are valid entrie= s. +**/ +UINTN +__attribute__((weak)) +SocGetMpCoreInfo ( + OUT UINT8 *NxpCoreTable, + OUT ARM_CORE_INFO *ArmCoreTable, + IN UINTN CoreTableSize + ) +{ + NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg; + UINT32 TpClusterLower; + UINT8 TpClusterParser; + UINT8 ClusterIndex; + UINT8 CoreIndex; + UINTN CoreCount; + UINT8 CoreType; + EFI_STATUS Status; + + Dcfg =3D (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASS= IS3V2_DCFG_ADDRESS; + ClusterIndex =3D 0; + CoreCount =3D 0; + while (TRUE) { + TpClusterLower =3D MmioRead32 ((UINTN)&Dcfg->TpCluster[ClusterIndex].L= ower); + for (CoreIndex =3D 0; CoreIndex < (sizeof (TpClusterLower) / sizeof (T= pClusterParser)); CoreIndex++) { + TpClusterParser =3D (TpClusterLower >> (8 * CoreIndex)); + Status =3D SocGetCoreType (TpClusterParser & TP_CLUSTER_ITYPE_IDX, &= CoreType); + if (Status !=3D EFI_NOT_FOUND) { + ArmCoreTable[CoreCount].ClusterId =3D ClusterIndex; + ArmCoreTable[CoreCount].CoreId =3D CoreIndex; + ArmCoreTable[CoreCount].MailboxSetAddress =3D 0; + ArmCoreTable[CoreCount].MailboxGetAddress =3D 0; + ArmCoreTable[CoreCount].MailboxClearAddress =3D 0; + ArmCoreTable[CoreCount].MailboxClearValue =3D ~0; + + NxpCoreTable[CoreCount] =3D CoreType; + CoreCount++; + if (CoreCount =3D=3D CoreTableSize) { + break; + } + } + } + if (TpClusterLower & TP_CLUSTER_EOC) { + break; + } + if (CoreCount =3D=3D CoreTableSize) { + break; + } + ClusterIndex++; + } + + return CoreCount; +} + +/** + Function to initialize Chassis Specific functions + **/ +VOID +ChassisInit ( + VOID + ) +{ + UINT64 BaudRate; + UINT32 ReceiveFifoDepth; + EFI_PARITY_TYPE Parity; + UINT8 DataBits; + EFI_STOP_BITS_TYPE StopBits; + UINT32 Timeout; + + BaudRate =3D FixedPcdGet64 (PcdUartDefaultBaudRate); + ReceiveFifoDepth =3D FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); + Timeout =3D 0; + Parity =3D (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); + DataBits =3D FixedPcdGet8 (PcdUartDefaultDataBits); + StopBits =3D (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits); + + // + // Early init serial Port to get board information. + // + SerialPortSetAttributes ( + &BaudRate, + &ReceiveFifoDepth, + &Timeout, + &Parity, + &DataBits, + &StopBits + ); +} diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf b/Sil= icon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf new file mode 100644 index 0000000000..302296bf65 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Chassis3V2Lib + FILE_GUID =3D fae0d077-5fc2-494f-b8e1-c51a3023ee3e + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ChassisLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis3V2/Chassis3V2.dec + +[LibraryClasses] + IoLib + IoAccessLib + PcdLib + SerialPortLib + +[Sources.common] + ChassisLib.c + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth + --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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