From nobody Sat May 4 06:43:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+53740+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+53740+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1580851847485496.999531270514; Tue, 4 Feb 2020 13:30:47 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Wpp9YY1788612xERfp9IcXWm; Tue, 04 Feb 2020 13:30:47 -0800 X-Received: from atlmailgw2.ami.com (atlmailgw2.ami.com [63.147.10.42]) by mx.groups.io with SMTP id smtpd.web09.360.1580851845942104199 for ; Tue, 04 Feb 2020 13:30:46 -0800 X-AuditID: ac10606f-819ff70000000872-7c-5e39e2870a6b X-Received: from atlms1.us.megatrends.com (atlms1.us.megatrends.com [172.16.96.144]) (using TLS with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (Client did not present a certificate) by atlmailgw2.ami.com (Symantec Messaging Gateway) with SMTP id EE.27.02162.782E93E5; Tue, 4 Feb 2020 16:30:47 -0500 (EST) X-Received: from Felix7.us.megatrends.com (172.16.99.93) by atlms1.us.megatrends.com (172.16.96.144) with Microsoft SMTP Server id 14.3.468.0; Tue, 4 Feb 2020 16:30:12 -0500 From: "Felix Polyudov" To: CC: , , Subject: [edk2-devel] [PATCH] MdePkg: Add PCI Express 5.0 Header File Date: Tue, 4 Feb 2020 16:30:12 -0500 Message-ID: <20200204213012.67268-1-felixp@ami.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsWyRiBhgm77I8s4gx/zNSzaJ8xms1hxbwO7 RUfHPyYHZo/t3y8weize85IpgCmqgdEmMS8vvySxJFUhJbU42VYpoCizLDG5UkkhM8VWyVBJ oSAnMTk1NzWvxFYpsaAgNS9FyY5LAQPYAJVl5imk5iXnp2TmpdsqeQb761pYmFrqGirZhWSk KmTmpeUX5SaWZObnKSTn55UAVaemAEUVEro5M15sesBc8NW4YvqEoywNjMfUuhg5OCQETCRu NVR3MXJxCAnsYpI4OvshO4SznlGia8Fcpi5GTg42AVWJLRNXsYDYIgJSElMOzASLMwuEStw4 uYQdxBYWsJB42jeNFcRmEVCRaL28gxHE5hUwlli75SsbiC0hoCkxfdZrZoi4oMTJmU9YIOZI SBx88QIsLiQgLXH24W/GCYy8s5CUzUJStoCRaRWjUGJJTm5iZk56uZFeYm6mXnJ+7iZGSKzk 72D8+NH8ECMTB+MhRgkOZiUR3vP6lnFCvCmJlVWpRfnxRaU5qcWHGJ2ADp3ILMUNCihgyMcb GxhIicI4hiZmJuZG5oaWJubGxkrivKvWfIsREkgHxmB2ampBahHMECYOTqkGxqTPEqfq4xg9 0+4wP/0+JcU/VYKfaf5G3yNWzoKqr7fNepn2u2SLteu0pxqvGfdcbNpcY3bkTOgrkffK1qfW Mkh9nhBTzLNFdrff7jMnlbObxLo928INfs2a98lZzUlGuXnD/QUs058nfruc+M01wb7hBXty TMzaZ1fMIkKV9xtvnxe6i4X1oxJLcUaioRZzUXEiAJfgarqqAgAA Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,felixp@ami.com X-Gm-Message-State: NU3PJT7GAxs4T2M7wHW2MHS7x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1580851847; bh=HKjD2i/KQ1nC4ta3BFVIRhSX6v9ELECSqe+OMXDH2lg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=YRAoAdJUyiiKgfsaHU3Eew4Auic5CiS5naEjhsSx9LajTFKcQrExEXKhM7JswO7A6Bv c3SoIq0jqACKpp7jJ+LbZoSpqS46usWo/9vet1UK/syjWEmF1ndgnjTX7cikm6u8+3jdH NV5tNhA3fy1S6Li7gWvseOhFw2ySjQRQTC0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The header includes Physical Layer PCI Express Extended Capability definitions based on section 7.7.6 of PCI Express Base Specification 5.0. Signed-off-by: Felix Polyudov Reviewed-by: Liming Gao --- MdePkg/Include/IndustryStandard/PciExpress50.h | 136 +++++++++++++++++++++= ++++ 1 file changed, 136 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/PciExpress50.h diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Includ= e/IndustryStandard/PciExpress50.h new file mode 100644 index 0000000..26eae0b --- /dev/null +++ b/MdePkg/Include/IndustryStandard/PciExpress50.h @@ -0,0 +1,136 @@ +/** @file +Support for the PCI Express 5.0 standard. + +This header file may not define all structures. Please extend as required. + +Copyright (c) 2020, American Megatrends International LLC. All rights rese= rved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIEXPRESS50_H_ +#define _PCIEXPRESS50_H_ + +#include + +#pragma pack(1) + +/// The Physical Layer PCI Express Extended Capability definitions. +/// +/// Based on section 7.7.6 of PCI Express Base Specification 5.0. +///@{ +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1 + +// Register offsets from Physical Layer PCI-E Ext Cap Header +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET = 0x04 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET = 0x08 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET = 0x0C +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET = 0x10 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET = 0x14 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET= 0x18 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET= 0x1C +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFS= ET 0x20 + +typedef union { + struct { + UINT32 EqualizationByPassToHighestRateSupport : 1; //= bit 0 + UINT32 NoEqualizationNeededSupport : 1; //= bit 1 + UINT32 Reserved1 : 6; //= Reserved bit 2:7 + UINT32 ModifiedTSUsageMode0Support : 1; //= bit 8 + UINT32 ModifiedTSUsageMode1Support : 1; //= bit 9 + UINT32 ModifiedTSUsageMode2Support : 1; //= bit 10 + UINT32 ModifiedTSReservedUsageModes : 5; //= bit 11:15 + UINT32 Reserved2 : 16; /= / Reserved bit 16:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES; + +typedef union { + struct { + UINT32 EqualizationByPassToHighestRateDisable : 1; //= bit 0 + UINT32 NoEqualizationNeededDisable : 1; //= bit 1 + UINT32 Reserved1 : 6; //= Reserved bit 2:7 + UINT32 ModifiedTSUsageModeSelected : 3; //= bit 8:10 + UINT32 Reserved2 : 21; /= / Reserved bit 11:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL; + +typedef union { + struct { + UINT32 EqualizationComplete : 1; // bit 0 + UINT32 EqualizationPhase1Success : 1; // bit 1 + UINT32 EqualizationPhase2Success : 1; // bit 2 + UINT32 EqualizationPhase3Success : 1; // bit 3 + UINT32 LinkEqualizationRequest : 1; // bit 4 + UINT32 ModifiedTSRcvd : 1; // bit 5 + UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7 + UINT32 TransmitterPrecodingOn : 1; // bit 8 + UINT32 TransmitterPrecodeRequest : 1; // bit 9 + UINT32 NoEqualizationNeededRcvd : 1; // bit 10 + UINT32 Reserved : 21; // Reserved bit 11:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS; + +typedef union { + struct { + UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2 + UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15 + UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1; + +typedef union { + struct { + UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23 + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 + UINT32 Reserved : 6; // Reserved bit 26:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2; + +typedef union { + struct { + UINT32 TransModifiedTSUsageMode : 3; // bit 0:2 + UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15 + UINT32 TransModifiedTSVendorId : 16; // bit 16:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1; + +typedef union { + struct { + UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23 + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 + UINT32 Reserved : 6; // Reserved bit 26:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2; + +typedef union { + struct { + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 + } Bits; + UINT8 Uint8; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablitie= s; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifi= edTs1Data; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifi= edTs2Data; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModif= iedTs1Data; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModif= iedTs2Data; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEquali= zationControl[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0; +///@} + +#pragma pack() + +#endif --=20 2.10.0.windows.1 Please consider the environment before printing this email. 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