From nobody Mon Feb 9 23:42:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52982+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52982+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1578395209; cv=none; d=zohomail.com; s=zohoarc; b=JfS3+mpsmBX+nZzLKEg3Ti6e2y7Nt7lk6u9+UQrFjqJqmjv5T2AYrCHxGxDnVYLtFMd4UTJ9iKuf2QrHxGCIkhL3WW2/zVcQhULrOiOdtRQ/iV9cgAZbkP0r4MHGt7DzzO83uqkjtctzD8wCuy9P+gTcGhDTC1pjQyljNoYiJAY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578395209; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=FJqqDrAn7Q0Ph10ILb8vbtlnAvuXdiuk4poBvEyXWxc=; b=NvTw1iooYlIWeHhUT3VS9zw37Yb3bOY00az4QYcCLe/4locHeMuSWJgvt2euCC+aRD3YegEeeAOLxUgfSdUFdxeE/HkRPkNdlPEgQsfLgcSYROdeZSXFCPrwslEAFrRB4dMkTGEOfbTn+bu8q1fpg4Ts7LsZ4+rAdiw9vhQlxGY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52982+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1578395209756400.3235641801101; Tue, 7 Jan 2020 03:06:49 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id zPyGYY1788612xoeW85BjU2B; Tue, 07 Jan 2020 03:06:49 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4171.1578395207142852474 for ; Tue, 07 Jan 2020 03:06:47 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Jan 2020 03:06:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,405,1571727600"; d="scan'208";a="422445531" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by fmsmga006.fm.intel.com with ESMTP; 07 Jan 2020 03:06:44 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCH 1/3] MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection Date: Tue, 7 Jan 2020 12:06:19 +0100 Message-Id: <20200107110621.232-2-mateusz.albecki@intel.com> In-Reply-To: <20200107110621.232-1-mateusz.albecki@intel.com> References: <20200107110621.232-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: VWOM5UgsBIir6D6dusgCQ6I6x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1578395209; bh=QS0aHGUrvdkalHZR/BC3GKDUnVqu5/Fv4uQZVcIkkGY=; h=Cc:Date:From:Reply-To:Subject:To; b=jCFF2D7mXYEubAVevXNxicldPI8XCC15zzQjTcO6ixRAHkG37KMj112mspA8sWW2yix 3ZrPbpkzM/FrHuNwGaFEVYOAkhwDxKv4KuKtPd7w1fz8gbWOnm6csQN/t5BhFV7dMqzLi DLVH+ZF1XQ/49G2VMfur46GhYdUl4Koxruw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1140 Error detection function will now check if the command failure has been caused by one of the errors that can appear randomly on link(CRC error + end bit error). If such an error has been a cause of failure function will return EFI_CRC_ERROR instead of EFI_DEVICE_ERROR to indicate to the higher level that command has a chance of succeeding if resent. In addition this patch also fixes 2 small bugs. First one is DAT lane being reset on current limit error. Second one is data timeout error not being cleared after transfer has been completed. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 234 +++++++++++++++----= ---- 1 file changed, 158 insertions(+), 76 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index e7f2fac69b..8b5e54f321 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -7,7 +7,7 @@ It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. =20 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -2137,6 +2137,154 @@ SdMmcExecTrb ( return Status; } =20 +/** + Performs SW reset based on passed error status mask. + + @param[in] Private Pointer to driver private data. + @param[in] Slot Index of the slot to reset. + @param[in] ErrIntStatus Error interrupt status mask. + + @retval EFI_SUCCESS Software reset performed successfully. + @retval Other Software reset failed. +**/ +EFI_STATUS +SdMmcSoftwareReset ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN UINT16 ErrIntStatus + ) +{ + UINT8 SwReset; + EFI_STATUS Status; + + SwReset =3D 0; + if ((ErrIntStatus & 0x0F) !=3D 0) { + SwReset |=3D BIT1; + } + if ((ErrIntStatus & 0x70) !=3D 0) { + SwReset |=3D BIT2; + } + + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_SW_RST, + FALSE, + sizeof (SwReset), + &SwReset + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D SdMmcHcWaitMmioSet ( + Private->PciIo, + Slot, + SD_MMC_HC_SW_RST, + sizeof (SwReset), + 0xFF, + 0, + SD_MMC_HC_GENERIC_TIMEOUT + ); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + +/** + Checks the error status in error status register + and issues appropriate software reset as described in + SD specification section 3.10. + + @param[in] Private Pointer to driver private data. + @param[in] Trb Pointer to currently executing TRB. + + @retval EFI_CRC_ERROR CRC error happened during CMD execution. + @retval EFI_SUCCESS No error reported. + @retval Others Some other error happened. + +**/ +EFI_STATUS +SdMmcCheckAndRecoverErrors ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot + ) +{ + UINT16 IntStatus; + UINT16 ErrIntStatus; + UINT16 ErrIntStatusOr; + EFI_STATUS Status; + EFI_STATUS ErrorStatus; + + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + TRUE, + sizeof (IntStatus), + &IntStatus + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((IntStatus & BIT15) =3D=3D 0) { + return EFI_SUCCESS; + } + + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_ERR_INT_STS, + TRUE, + sizeof (ErrIntStatus), + &ErrIntStatus + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // We treat both CMD and DAT CRC errors and + // end bits errors as EFI_CRC_ERROR. This will + // let higher layer know that the error possibly + // happened due to random bus condition and the + // command can be retried. + // + if (ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) { + ErrorStatus =3D EFI_CRC_ERROR; + } else if ((ErrIntStatus & BIT4) && (IntStatus & BIT1)){ + // + // If the data timeout error is reported + // but data transfer is signaled as completed we + // have to ignore data timeout. + // + ErrorStatus =3D EFI_SUCCESS; + ErrIntStatusOr =3D BIT4; + Status =3D SdMmcHcOrMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_ERR_INT_STS, + sizeof (ErrIntStatus), + &ErrIntStatusOr + ); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + ErrorStatus =3D EFI_DEVICE_ERROR; + } + + Status =3D SdMmcSoftwareReset (Private, Slot, ErrIntStatus); + if (EFI_ERROR (Status)) { + return Status; + } + + return ErrorStatus; +} + /** Check the TRB execution result. =20 @@ -2160,10 +2308,8 @@ SdMmcCheckTrbResult ( UINT32 Response[4]; UINT64 SdmaAddr; UINT8 Index; - UINT8 SwReset; UINT32 PioLength; =20 - SwReset =3D 0; Packet =3D Trb->Packet; // // Check Trb execution result by reading Normal Interrupt Status registe= r. @@ -2179,87 +2325,23 @@ SdMmcCheckTrbResult ( if (EFI_ERROR (Status)) { goto Done; } + // - // Check Transfer Complete bit is set or not. + // Check if there are any errors reported by host controller + // and if neccessary recover the controller before next command is execu= ted. // - if ((IntStatus & BIT1) =3D=3D BIT1) { - if ((IntStatus & BIT15) =3D=3D BIT15) { - // - // Read Error Interrupt Status register to check if the error is - // Data Timeout Error. - // If yes, treat it as success as Transfer Complete has higher - // priority than Data Timeout Error. - // - Status =3D SdMmcHcRwMmio ( - Private->PciIo, - Trb->Slot, - SD_MMC_HC_ERR_INT_STS, - TRUE, - sizeof (IntStatus), - &IntStatus - ); - if (!EFI_ERROR (Status)) { - if ((IntStatus & BIT4) =3D=3D BIT4) { - Status =3D EFI_SUCCESS; - } else { - Status =3D EFI_DEVICE_ERROR; - } - } - } - + Status =3D SdMmcCheckAndRecoverErrors (Private, Trb->Slot); + if (EFI_ERROR (Status)) { goto Done; } + // - // Check if there is a error happened during cmd execution. - // If yes, then do error recovery procedure to follow SD Host Controller - // Simplified Spec 3.0 section 3.10.1. + // Check Transfer Complete bit is set or not. // - if ((IntStatus & BIT15) =3D=3D BIT15) { - Status =3D SdMmcHcRwMmio ( - Private->PciIo, - Trb->Slot, - SD_MMC_HC_ERR_INT_STS, - TRUE, - sizeof (IntStatus), - &IntStatus - ); - if (EFI_ERROR (Status)) { - goto Done; - } - if ((IntStatus & 0x0F) !=3D 0) { - SwReset |=3D BIT1; - } - if ((IntStatus & 0xF0) !=3D 0) { - SwReset |=3D BIT2; - } - - Status =3D SdMmcHcRwMmio ( - Private->PciIo, - Trb->Slot, - SD_MMC_HC_SW_RST, - FALSE, - sizeof (SwReset), - &SwReset - ); - if (EFI_ERROR (Status)) { - goto Done; - } - Status =3D SdMmcHcWaitMmioSet ( - Private->PciIo, - Trb->Slot, - SD_MMC_HC_SW_RST, - sizeof (SwReset), - 0xFF, - 0, - SD_MMC_HC_GENERIC_TIMEOUT - ); - if (EFI_ERROR (Status)) { - goto Done; - } - - Status =3D EFI_DEVICE_ERROR; + if ((IntStatus & BIT1) =3D=3D BIT1) { goto Done; } + // // Check if DMA interrupt is signalled for the SDMA transfer. // --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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