From nobody Sun Feb 8 21:28:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52617+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52617+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577753365; cv=none; d=zohomail.com; s=zohoarc; b=iOJvkm6wGlNp6rpHKGJD/MthNpCr58J5fpMfr/vcUykNh0TR8fwLEmZAFjQp6Lz/TQUDvUzIPGvd3W1EcDR8UfEsV3oiEvkjnre0mNc+5UIIEIvAcqmD5KlLpdU3yn/vhLkeY+nDEtlHMI5+gDS7dZnDgJ19jY8dJQ6SZ1O9QmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577753365; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=Xh04MlhwDGXJYHTjPmfpwhuF7NO3zPBOxFrFc959uEg=; b=mwa7dmALA4UKASDgNbeDjzVv/JgsBuoycmp7TNqve8k0M+s8i05FWYEbNwPmtUR1JttMoRcqXvSTEOfm05wzwK6h106fsKix9AIns0FA5/uoXxr7/ziwh8ujaaf03OK6COp1fUZ8AMGrcQOTEF1Fei3fNoiY9QE+IqnBDSvByCI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52617+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577753365530241.1081801751343; Mon, 30 Dec 2019 16:49:25 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 00UuYY1788612xKn2RSpVkBB; Mon, 30 Dec 2019 16:49:25 -0800 X-Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web09.2417.1577753357960224652 for ; Mon, 30 Dec 2019 16:49:24 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Dec 2019 16:49:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,377,1571727600"; d="scan'208";a="221273782" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by orsmga003.jf.intel.com with ESMTP; 30 Dec 2019 16:49:22 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v5 4/6] UefiCpuPkg/MpInitLib: Produce EDKII microcode patch HOB Date: Tue, 31 Dec 2019 08:49:12 +0800 Message-Id: <20191231004914.8520-5-hao.a.wu@intel.com> In-Reply-To: <20191231004914.8520-1-hao.a.wu@intel.com> References: <20191231004914.8520-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: hJxvpQTTlaTPK442VWaaCc8Sx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577753365; bh=vAs+f5SeEJanHgFTTcYEquQuTcAYZOUXgKDLTrIbyFE=; h=Cc:Date:From:Reply-To:Subject:To; b=d5kFK3ISBrPiWeAkaw9BfmnGATk1DvrH/hGPvong7IS6UhqauThvt8gvJei92VUnGgm dsFO3NkXQAtyIkpFxoDUMngIX1BQFUYFPhMR5U5mFrJBDCdRw2o8j16vpb+fHaVzPJXS4 USFxfN/B4cmMHiuAnEJbGntCYQhWAncUDu4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2430 This commit will update the MpInitLib to: A. Collect the base address and size information after microcode patches being loaded into memory; B. Collect the detected microcode patch for each processor within system; C. Based on the collected information, produce the EDKII microcode patch HOB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu Reviewed-by: Eric Dong --- UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/MpLib.h | 24 +++++++-- UefiCpuPkg/Library/MpInitLib/Microcode.c | 20 +++++-- UefiCpuPkg/Library/MpInitLib/MpLib.c | 8 ++- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 55 ++++++++++++++++++++ 5 files changed, 100 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 1538185ef9..326703cc9a 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -63,3 +63,4 @@ [Pcd] =20 [Guids] gEdkiiS3SmmInitDoneGuid + gEdkiiMicrocodePatchHobGuid diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 56b0df664a..885656900c 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -138,6 +138,7 @@ typedef struct { EFI_EVENT WaitEvent; UINT32 ProcessorSignature; UINT8 PlatformId; + UINT64 MicrocodeEntryAddr; } CPU_AP_DATA; =20 // @@ -580,13 +581,15 @@ CheckAndUpdateApsStatus ( /** Detect whether specified processor can find matching microcode patch and= load it. =20 - @param[in] CpuMpData The pointer to CPU MP Data structure. - @param[in] IsBspCallIn Indicate whether the caller is BSP or not. + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] ProcessorNumber The handle number of the processor. The ran= ge is + from 0 to the total number of logical proce= ssors + minus 1. **/ VOID MicrocodeDetect ( IN CPU_MP_DATA *CpuMpData, - IN BOOLEAN IsBspCallIn + IN UINTN ProcessorNumber ); =20 /** @@ -619,5 +622,20 @@ EnableDebugAgent ( VOID ); =20 +/** + Find the current Processor number by APIC ID. + + @param[in] CpuMpData Pointer to PEI CPU MP Data + @param[out] ProcessorNumber Return the pocessor number found + + @retval EFI_SUCCESS ProcessorNumber is found and returned. + @retval EFI_NOT_FOUND ProcessorNumber is not found. +**/ +EFI_STATUS +GetProcessorNumber ( + IN CPU_MP_DATA *CpuMpData, + OUT UINTN *ProcessorNumber + ); + #endif =20 diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 330fd99623..4162b4a8dc 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -65,13 +65,15 @@ GetCurrentMicrocodeSignature ( It does not guarantee that the data has not been modified. CPU has its own mechanism to verify Microcode Binary part. =20 - @param[in] CpuMpData The pointer to CPU MP Data structure. - @param[in] IsBspCallIn Indicate whether the caller is BSP or not. + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] ProcessorNumber The handle number of the processor. The ran= ge is + from 0 to the total number of logical proce= ssors + minus 1. **/ VOID MicrocodeDetect ( IN CPU_MP_DATA *CpuMpData, - IN BOOLEAN IsBspCallIn + IN UINTN ProcessorNumber ) { UINT32 ExtendedTableLength; @@ -93,6 +95,7 @@ MicrocodeDetect ( MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; UINT32 ProcessorFlags; UINT32 ThreadId; + BOOLEAN IsBspCallIn; =20 // // set ProcessorFlags to suppress incorrect compiler/analyzer warnings @@ -107,6 +110,7 @@ MicrocodeDetect ( } =20 CurrentRevision =3D GetCurrentMicrocodeSignature (); + IsBspCallIn =3D (ProcessorNumber =3D=3D (UINTN)CpuMpData->BspNumber)= ? TRUE : FALSE; if (CurrentRevision !=3D 0 && !IsBspCallIn) { // // Skip loading microcode if it has been loaded successfully @@ -295,6 +299,16 @@ MicrocodeDetect ( } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd)); =20 Done: + if (LatestRevision !=3D 0) { + // + // Save the detected microcode patch entry address (including the + // microcode patch header) for each processor. + // It will be used when building the microcode patch cache HOB. + // + CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr =3D + (UINTN) MicrocodeData - sizeof (CPU_MICROCODE_HEADER); + } + if (LatestRevision > CurrentRevision) { // // BIOS only authenticate updates that contain a numerically larger re= vision diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index c72bf3c9ee..e611a8ca40 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -399,12 +399,16 @@ ApInitializeSync ( ) { CPU_MP_DATA *CpuMpData; + UINTN ProcessorNumber; + EFI_STATUS Status; =20 CpuMpData =3D (CPU_MP_DATA *) Buffer; + Status =3D GetProcessorNumber (CpuMpData, &ProcessorNumber); + ASSERT_EFI_ERROR (Status); // // Load microcode on AP // - MicrocodeDetect (CpuMpData, FALSE); + MicrocodeDetect (CpuMpData, ProcessorNumber); // // Sync BSP's MTRR table to AP // @@ -1761,7 +1765,7 @@ MpInitLibInitialize ( // // Detect and apply Microcode on BSP // - MicrocodeDetect (CpuMpData, TRUE); + MicrocodeDetect (CpuMpData, CpuMpData->BspNumber); // // Store BSP's MTRR setting // diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index 3999603c3e..06e3f5d0d3 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -9,6 +9,7 @@ #include "MpLib.h" #include #include +#include =20 /** S3 SMM Init Done notification function. @@ -291,6 +292,59 @@ CheckAndUpdateApsStatus ( } =20 /** + Build the microcode patch HOB that contains the base address and size of= the + microcode patch stored in the memory. + + @param[in] CpuMpData Pointer to the CPU_MP_DATA structure. + +**/ +VOID +BuildMicrocodeCacheHob ( + IN CPU_MP_DATA *CpuMpData + ) +{ + EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; + UINTN HobDataLength; + UINT32 Index; + + HobDataLength =3D sizeof (EDKII_MICROCODE_PATCH_HOB) + + sizeof (UINT64) * CpuMpData->CpuCount; + + MicrocodeHob =3D AllocatePool (HobDataLength); + if (MicrocodeHob =3D=3D NULL) { + ASSERT (FALSE); + return; + } + + // + // Store the information of the memory region that holds the microcode p= atches. + // + MicrocodeHob->MicrocodePatchAddress =3D CpuMpData->MicrocodePatchAddr= ess; + MicrocodeHob->MicrocodePatchRegionSize =3D CpuMpData->MicrocodePatchRegi= onSize; + + // + // Store the detected microcode patch for each processor as well. + // + MicrocodeHob->ProcessorCount =3D CpuMpData->CpuCount; + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + if (CpuMpData->CpuData[Index].MicrocodeEntryAddr !=3D 0) { + MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D + CpuMpData->CpuData[Index].MicrocodeEntryAddr - CpuMpData->Microcod= ePatchAddress; + } else { + MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D MAX_UINT64; + } + } + + BuildGuidDataHob ( + &gEdkiiMicrocodePatchHobGuid, + MicrocodeHob, + HobDataLength + ); + + return; +} + +/** Initialize global data for MP support. =20 @param[in] CpuMpData The pointer to CPU MP Data structure. @@ -302,6 +356,7 @@ InitMpGlobalData ( { EFI_STATUS Status; =20 + BuildMicrocodeCacheHob (CpuMpData); SaveCpuMpData (CpuMpData); =20 /// --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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