From nobody Fri May 3 20:52:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52582+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52582+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577431956; cv=none; d=zohomail.com; s=zohoarc; b=MZKrxxcARA1dvR7cMR0BefYktsQYe9d+XULPwXSNEugQj9kBf+ddqoXbYUMMQZctjUqZfMFabpREp2M4Jevu7ghiUxi5hLIVTupQva8PcIHaAM1JEVYEJgcXoyxHLUjSQwezJXxgPkDD6+rNlnl0Lpwd9ZY4Xovx8X2XgV27Mwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577431956; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=5igPKLSjUvz67ntt8R510NPGtcVE4ACM1tRMFZDbkM0=; b=T8cRL53D1PVEko1VddnI1rcki929ayfSRPoiYh0hp1OOYJ2rY9d+7M3BRiIIJOqMfnKDl5vhoRlxplIPffLmyPPtmCRAI6QGWVrmmKwtg/Y9zPYMdfB3WMXXdlkR9vQQ2aR/mNxUP2aSytkT5kdbHTToiVqpJpL6ujAj73uO5VQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52582+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577431956083359.4288595230429; Thu, 26 Dec 2019 23:32:36 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id KZd3YY1788612xQqmAmaLQdE; Thu, 26 Dec 2019 23:32:35 -0800 X-Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web12.29151.1577431953513368188 for ; Thu, 26 Dec 2019 23:32:34 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Dec 2019 23:32:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,362,1571727600"; d="scan'208";a="220445488" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by orsmga003.jf.intel.com with ESMTP; 26 Dec 2019 23:32:33 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v4 1/6] UefiCpuPkg/MpInitLib: Collect processors' CPUID & Platform ID info Date: Fri, 27 Dec 2019 15:32:24 +0800 Message-Id: <20191227073229.9416-2-hao.a.wu@intel.com> In-Reply-To: <20191227073229.9416-1-hao.a.wu@intel.com> References: <20191227073229.9416-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: CHHZxo9sQZW8czIxHyNRYKBRx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577431955; bh=Pt4T8iuv10rT4VRgMvOfMVo3EfwQMOtYvT0BC7I/Ki4=; h=Cc:Date:From:Reply-To:Subject:To; b=D3GQQ+oCtSqiUQbXDnkB0A4S0TOPc/Eyk2/xbuCh/zffgvnLqaFKq3I1ncs+ta6pkGs NqlLaGAv+ILvXKj8TL2f4/g6UU67JRN0j9B5e0NIuSb2LoWPdxYxLmZ85lgyPzSxiAC6T KPk748bQEySHMNhnlNrlBL88oPbTotkWljo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2429 This commit will collect the CPUID and Platform ID information for each processor within system. They will be stored in the CPU_AP_DATA structure. These information will be used in the next commit to decide whether a microcode patch will be loaded into memory. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu Reviewed-by: Ray Ni Reviewed-by: Eric Dong --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 2 ++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 14 +++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 8fa07b12c5..4440dc2701 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -122,6 +122,8 @@ typedef struct { UINT64 CurrentTime; UINT64 TotalTime; EFI_EVENT WaitEvent; + UINT32 ProcessorSignature; + UINT8 PlatformId; } CPU_AP_DATA; =20 // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index d32adf0780..d5077e080e 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -548,7 +548,8 @@ InitializeApData ( IN UINT64 ApTopOfStack ) { - CPU_INFO_IN_HOB *CpuInfoInHob; + CPU_INFO_IN_HOB *CpuInfoInHob; + MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; =20 CpuInfoInHob =3D (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob[ProcessorNumber].InitialApicId =3D GetInitialApicId (); @@ -559,6 +560,17 @@ InitializeApData ( CpuMpData->CpuData[ProcessorNumber].Waiting =3D FALSE; CpuMpData->CpuData[ProcessorNumber].CpuHealthy =3D (BistData =3D=3D 0) ?= TRUE : FALSE; =20 + PlatformIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + CpuMpData->CpuData[ProcessorNumber].PlatformId =3D (UINT8) PlatformIdMsr= .Bits.PlatformId; + + AsmCpuid ( + CPUID_VERSION_INFO, + &CpuMpData->CpuData[ProcessorNumber].ProcessorSignature, + NULL, + NULL, + NULL + ); + InitializeSpinLock(&CpuMpData->CpuData[ProcessorNumber].ApLock); SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle); } --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#52582): https://edk2.groups.io/g/devel/message/52582 Mute This Topic: https://groups.io/mt/69283204/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 20:52:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52583+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52583+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577431958; cv=none; d=zohomail.com; s=zohoarc; b=KumJMqA3XHsXtTdMmXgerN7foWEo8L9e3xywOnb6xLjZcRNjAXsSiAFj8zXA/KOlCXclGmOhX9y/sCcC/D0IIUgE78A2k5IjzN6JmLmmGSiMOyJXr90chK93gGrb2y0jPGEAC5PiS4x6tm09KjEE6posCIp4XEw1UzeF2ahy2QE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577431958; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=Mj2HBWLzv+PH+ELf/zjJvUmy+dtFB6aBHN8HcaP9gnY=; b=iJE2K51Opmcmg7Gj098Wxn0NkczOCuXKa+sUExVC8/LgDKZKc4RaQKzGoTn2dWGyiDUrNw13vSVos7fYnvvgXTILnyx5ZVQH+uu1xmd0N4+im96VzHdJ0EMTrJfTND0g2g3YHm2cHs1Xo9GEkBDB0OK8NsUSxO8hM0WL8Btdjp8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52583+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577431958484591.0812990887805; Thu, 26 Dec 2019 23:32:38 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZEryYY1788612xIPhCznymn0; Thu, 26 Dec 2019 23:32:37 -0800 X-Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web12.29151.1577431953513368188 for ; Thu, 26 Dec 2019 23:32:36 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Dec 2019 23:32:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,362,1571727600"; d="scan'208";a="220445496" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by orsmga003.jf.intel.com with ESMTP; 26 Dec 2019 23:32:34 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v4 2/6] UefiCpuPkg/MpInitLib: Reduce the size when loading microcode patches Date: Fri, 27 Dec 2019 15:32:25 +0800 Message-Id: <20191227073229.9416-3-hao.a.wu@intel.com> In-Reply-To: <20191227073229.9416-1-hao.a.wu@intel.com> References: <20191227073229.9416-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: ZI1GvXg8Lzth0C0OGDlIEhmLx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577431957; bh=wZZleaNzmJF+nPk9H7DIPpwHw1eTWmZ1WuLYnONaSJ8=; h=Cc:Date:From:Reply-To:Subject:To; b=C7qMROWtPi1MvlUK5gG360Sznw6tJ+VWGSB/6qgZSWSDlYbtGQelGIr/05sklF0cmWh k1388yJ3sL8HPRkDrZggovhIv3VYT4E5Qh0G9Wn9ebXCwLH/HbAdU93Wv+7wu3peQVnEC 3k6ndSZOEP36VodW7AeMjofL9VCnoslcwjM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2429 This commit will attempt to reduce the copy size when loading the microcode patches data from flash into memory. Such optimization is done by a pre-process of the microcode patch headers (on flash). A microcode patch will be loaded into memory only when the below 3 criteria are met: A. With a microcode patch header (which means the data is not padding data between microcode patches); B. The 'ProcessorSignature' & 'ProcessorFlags' fields in the header match at least one processor within system; C. If the Extended Signature Table exists in a microcode patch, the 'ProcessorSignature' & 'ProcessorFlag' fields in the table entries match at least one processor within system. Criterion B and C will require all the processors to be woken up once to collect their CPUID and Platform ID information. Hence, this commit will move the copy, detect and apply of microcode patch on BSP and APs after all the processors have been woken up. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 24 ++ UefiCpuPkg/Library/MpInitLib/Microcode.c | 288 ++++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 90 ++---- 3 files changed, 340 insertions(+), 62 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 4440dc2701..56b0df664a 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -44,6 +44,20 @@ #define CPU_SWITCH_STATE_LOADED 2 =20 // +// Default maximum number of entries to store the microcode patches inform= ation +// +#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8 + +// +// Data structure for microcode patch information +// +typedef struct { + UINTN Address; + UINTN Size; + UINTN AlignedSize; +} MICROCODE_PATCH_INFO; + +// // CPU exchange information for switch BSP // typedef struct { @@ -576,6 +590,16 @@ MicrocodeDetect ( ); =20 /** + Load the required microcode patches data into memory. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. +**/ +VOID +LoadMicrocodePatch ( + IN OUT CPU_MP_DATA *CpuMpData + ); + +/** Detect whether Mwait-monitor feature is supported. =20 @retval TRUE Mwait-monitor feature is supported. diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 199b1f23ce..62a104742a 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -331,3 +331,291 @@ Done: MicroData [0x%08x], Revision [0x%08x]\n", Eax.Uint32, ProcessorFlag= s, (UINTN) MicrocodeData, LatestRevision)); } } + +/** + Determine if a microcode patch will be loaded into memory. + + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] ProcessorSignature The processor signature field value + supported by a microcode patch. + @param[in] ProcessorFlags The prcessor flags field value support= ed by + a microcode patch. + + @retval TRUE The specified microcode patch will be loaded. + @retval FALSE The specified microcode patch will not be loaded. +**/ +BOOLEAN +IsMicrocodePatchNeedLoad ( + IN CPU_MP_DATA *CpuMpData, + IN UINT32 ProcessorSignature, + IN UINT32 ProcessorFlags + ) +{ + UINTN Index; + CPU_AP_DATA *CpuData; + + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + CpuData =3D &CpuMpData->CpuData[Index]; + if ((ProcessorSignature =3D=3D CpuData->ProcessorSignature) && + (ProcessorFlags & (1 << CpuData->PlatformId)) !=3D 0) { + return TRUE; + } + } + + return FALSE; +} + +/** + Actual worker function that loads the required microcode patches into me= mory. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. + @param[in] Patches The pointer to an array of information= on + the microcode patches that will be loa= ded + into memory. + @param[in] PatchCount The number of microcode patches that w= ill + be loaded into memory. + @param[in] TotalLoadSize The total size of all the microcode pa= tches + to be loaded. +**/ +VOID +LoadMicrocodePatchWorker ( + IN OUT CPU_MP_DATA *CpuMpData, + IN MICROCODE_PATCH_INFO *Patches, + IN UINTN PatchCount, + IN UINTN TotalLoadSize + ) +{ + UINTN Index; + VOID *MicrocodePatchInRam; + UINT8 *Walker; + + ASSERT ((Patches !=3D NULL) && (PatchCount !=3D 0)); + + MicrocodePatchInRam =3D AllocatePages (EFI_SIZE_TO_PAGES (TotalLoadSize)= ); + if (MicrocodePatchInRam =3D=3D NULL) { + return; + } + + // + // Load all the required microcode patches into memory + // + for (Walker =3D MicrocodePatchInRam, Index =3D 0; Index < PatchCount; In= dex++) { + CopyMem ( + Walker, + (VOID *) Patches[Index].Address, + Patches[Index].Size + ); + + // + // Zero-fill the padding area + // Please note that AlignedSize will be no less than Size + // + ZeroMem ( + Walker + Patches[Index].Size, + Patches[Index].AlignedSize - Patches[Index].Size + ); + + Walker +=3D Patches[Index].AlignedSize; + } + + // + // Update the microcode patch related fields in CpuMpData + // + CpuMpData->MicrocodePatchAddress =3D (UINTN) MicrocodePatchInRam; + CpuMpData->MicrocodePatchRegionSize =3D TotalLoadSize; + + DEBUG (( + DEBUG_INFO, + "%a: Required microcode patches have been loaded at 0x%lx, with size 0= x%lx.\n", + __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePa= tchRegionSize + )); + + return; +} + +/** + Load the required microcode patches data into memory. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. +**/ +VOID +LoadMicrocodePatch ( + IN OUT CPU_MP_DATA *CpuMpData + ) +{ + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN MicrocodeEnd; + UINTN DataSize; + UINTN TotalSize; + CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; + UINT32 ExtendedTableCount; + CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; + MICROCODE_PATCH_INFO *PatchInfoBuffer; + UINTN MaxPatchNumber; + UINTN PatchCount; + UINTN TotalLoadSize; + UINTN Index; + BOOLEAN NeedLoad; + + // + // Initialize the microcode patch related fields in CpuMpData as the val= ues + // specified by the PCD pair. If the microcode patches are loaded into m= emory, + // these fields will be updated. + // + CpuMpData->MicrocodePatchAddress =3D PcdGet64 (PcdCpuMicrocodePatchAd= dress); + CpuMpData->MicrocodePatchRegionSize =3D PcdGet64 (PcdCpuMicrocodePatchRe= gionSize); + + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->M= icrocodePatchAddress; + MicrocodeEnd =3D (UINTN) MicrocodeEntryPoint + + (UINTN) CpuMpData->MicrocodePatchRegionSize; + if ((MicrocodeEntryPoint =3D=3D NULL) || ((UINTN) MicrocodeEntryPoint = =3D=3D MicrocodeEnd)) { + // + // There is no microcode patches + // + return; + } + + PatchCount =3D 0; + MaxPatchNumber =3D DEFAULT_MAX_MICROCODE_PATCH_NUM; + TotalLoadSize =3D 0; + PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof (MICROCODE_PAT= CH_INFO)); + if (PatchInfoBuffer =3D=3D NULL) { + return; + } + + // + // Process the header of each microcode patch within the region. + // The purpose is to decide which microcode patch(es) will be loaded int= o memory. + // + do { + if (MicrocodeEntryPoint->HeaderVersion !=3D 0x1) { + // + // Padding data between the microcode patches, skip 1KB to check nex= t entry. + // + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode= EntryPoint) + SIZE_1KB); + continue; + } + + DataSize =3D MicrocodeEntryPoint->DataSize; + TotalSize =3D (DataSize =3D=3D 0) ? 2048 : MicrocodeEntryPoint->TotalS= ize; + if ( (UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize) || + ((UINTN)MicrocodeEntryPoint + TotalSize) > MicrocodeEnd || + (DataSize & 0x3) !=3D 0 || + (TotalSize & (SIZE_1KB - 1)) !=3D 0 || + TotalSize < DataSize + ) { + // + // Not a valid microcode header, skip 1KB to check next entry. + // + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode= EntryPoint) + SIZE_1KB); + continue; + } + + // + // Check the 'ProcessorSignature' and 'ProcessorFlags' of the microcode + // patch header with the CPUID and PlatformID of the processors within + // system to decide if it will be copied into memory + // + NeedLoad =3D IsMicrocodePatchNeedLoad ( + CpuMpData, + MicrocodeEntryPoint->ProcessorSignature.Uint32, + MicrocodeEntryPoint->ProcessorFlags + ); + + // + // If the Extended Signature Table exists, check if the processor is i= n the + // support list + // + if ((!NeedLoad) && (DataSize !=3D 0) && + (TotalSize - DataSize > sizeof (CPU_MICROCODE_HEADER) + + sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADE= R))) { + ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UI= NT8 *) (MicrocodeEntryPoint) + + DataSize + sizeof (CPU_MICROCODE_HEADER)); + ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignatureCount; + ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTa= bleHeader + 1); + + for (Index =3D 0; Index < ExtendedTableCount; Index ++) { + // + // Avoid access content beyond MicrocodeEnd + // + if ((UINTN) ExtendedTable > MicrocodeEnd - sizeof (CPU_MICROCODE_E= XTENDED_TABLE)) { + break; + } + + // + // Check the 'ProcessorSignature' and 'ProcessorFlag' of the Exten= ded + // Signature Table entry with the CPUID and PlatformID of the proc= essors + // within system to decide if it will be copied into memory + // + NeedLoad =3D IsMicrocodePatchNeedLoad ( + CpuMpData, + ExtendedTable->ProcessorSignature.Uint32, + ExtendedTable->ProcessorFlag + ); + if (NeedLoad) { + break; + } + ExtendedTable ++; + } + } + + if (NeedLoad) { + PatchCount++; + if (PatchCount >=3D MaxPatchNumber) { + // + // Current 'PatchInfoBuffer' cannot hold the information, double t= he size + // and allocate a new buffer. + // + if (MaxPatchNumber > MAX_UINTN / 2 / sizeof (MICROCODE_PATCH_INFO)= ) { + // + // Overflow check for MaxPatchNumber + // + goto OnExit; + } + + PatchInfoBuffer =3D ReallocatePool ( + MaxPatchNumber * sizeof (MICROCODE_PATCH_INFO), + 2 * MaxPatchNumber * sizeof (MICROCODE_PATCH_I= NFO), + PatchInfoBuffer + ); + if (PatchInfoBuffer =3D=3D NULL) { + goto OnExit; + } + MaxPatchNumber =3D MaxPatchNumber * 2; + } + + // + // Store the information of this microcode patch + // + if (TotalSize > ALIGN_VALUE (TotalSize, SIZE_1KB) || + ALIGN_VALUE (TotalSize, SIZE_1KB) > MAX_UINTN - TotalLoadSize) { + goto OnExit; + } + PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) MicrocodeEnt= ryPoint; + PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; + PatchInfoBuffer[PatchCount - 1].AlignedSize =3D ALIGN_VALUE (TotalSi= ze, SIZE_1KB); + TotalLoadSize +=3D PatchInfoBuffer[PatchCount - 1].AlignedSize; + } + + // + // Process the next microcode patch + // + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEn= tryPoint) + TotalSize); + } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd)); + + if (PatchCount !=3D 0) { + DEBUG (( + DEBUG_INFO, + "%a: 0x%x microcode patches will be loaded into memory, with size 0x= %x.\n", + __FUNCTION__, PatchCount, TotalLoadSize + )); + + LoadMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, Tota= lLoadSize); + } + +OnExit: + if (PatchInfoBuffer !=3D NULL) { + FreePool (PatchInfoBuffer); + } + return; +} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index d5077e080e..c72bf3c9ee 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -628,10 +628,6 @@ ApWakeupFunction ( ApTopOfStack =3D CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpD= ata->CpuApStackSize; BistData =3D *(UINT32 *) ((UINTN) ApTopOfStack - sizeof (UINTN)); // - // Do some AP initialize sync - // - ApInitializeSync (CpuMpData); - // // CpuMpData->CpuData[0].VolatileRegisters is initialized based on B= SP environment, // to initialize AP in InitConfig path. // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegisters= points to a different IDT shared by all APs. @@ -1615,7 +1611,6 @@ MpInitLibInitialize ( UINTN ApResetVectorSize; UINTN BackupBufferAddr; UINTN ApIdtBase; - VOID *MicrocodePatchInRam; =20 OldCpuMpData =3D GetCpuMpDataFromGuidedHob (); if (OldCpuMpData =3D=3D NULL) { @@ -1683,39 +1678,7 @@ MpInitLibInitialize ( CpuMpData->SwitchBspFlag =3D FALSE; CpuMpData->CpuData =3D (CPU_AP_DATA *) (CpuMpData + 1); CpuMpData->CpuInfoInHob =3D (UINT64) (UINTN) (CpuMpData->CpuData + M= axLogicalProcessorNumber); - if (OldCpuMpData =3D=3D NULL) { - CpuMpData->MicrocodePatchRegionSize =3D PcdGet64 (PcdCpuMicrocodePatch= RegionSize); - // - // If platform has more than one CPU, relocate microcode to memory to = reduce - // loading microcode time. - // - MicrocodePatchInRam =3D NULL; - if (MaxLogicalProcessorNumber > 1) { - MicrocodePatchInRam =3D AllocatePages ( - EFI_SIZE_TO_PAGES ( - (UINTN)CpuMpData->MicrocodePatchRegionSize - ) - ); - } - if (MicrocodePatchInRam =3D=3D NULL) { - // - // there is only one processor, or no microcode patch is available, = or - // memory allocation failed - // - CpuMpData->MicrocodePatchAddress =3D PcdGet64 (PcdCpuMicrocodePatchA= ddress); - } else { - // - // there are multiple processors, and a microcode patch is available= , and - // memory allocation succeeded - // - CopyMem ( - MicrocodePatchInRam, - (VOID *)(UINTN)PcdGet64 (PcdCpuMicrocodePatchAddress), - (UINTN)CpuMpData->MicrocodePatchRegionSize - ); - CpuMpData->MicrocodePatchAddress =3D (UINTN)MicrocodePatchInRam; - } - }else { + if (OldCpuMpData !=3D NULL) { CpuMpData->MicrocodePatchRegionSize =3D OldCpuMpData->MicrocodePatchRe= gionSize; CpuMpData->MicrocodePatchAddress =3D OldCpuMpData->MicrocodePatchAd= dress; } @@ -1762,14 +1725,6 @@ MpInitLibInitialize ( (UINT32 *)(MonitorBuffer + MonitorFilterSize * Index); } // - // Load Microcode on BSP - // - MicrocodeDetect (CpuMpData, TRUE); - // - // Store BSP's MTRR setting - // - MtrrGetAllMtrrs (&CpuMpData->MtrrTable); - // // Enable the local APIC for Virtual Wire Mode. // ProgramVirtualWireMode (); @@ -1781,6 +1736,11 @@ MpInitLibInitialize ( // CollectProcessorCount (CpuMpData); } + + // + // Load required microcode patches data into memory + // + LoadMicrocodePatch (CpuMpData); } else { // // APs have been wakeup before, just get the CPU Information @@ -1788,7 +1748,6 @@ MpInitLibInitialize ( // CpuMpData->CpuCount =3D OldCpuMpData->CpuCount; CpuMpData->BspNumber =3D OldCpuMpData->BspNumber; - CpuMpData->InitFlag =3D ApInitReconfig; CpuMpData->CpuInfoInHob =3D OldCpuMpData->CpuInfoInHob; CpuInfoInHob =3D (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { @@ -1797,21 +1756,28 @@ MpInitLibInitialize ( CpuMpData->CpuData[Index].ApFunction =3D 0; CopyMem (&CpuMpData->CpuData[Index].VolatileRegisters, &VolatileRegi= sters, sizeof (CPU_VOLATILE_REGISTERS)); } - if (MaxLogicalProcessorNumber > 1) { - // - // Wakeup APs to do some AP initialize sync - // - WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE); - // - // Wait for all APs finished initialization - // - while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) { - CpuPause (); - } - CpuMpData->InitFlag =3D ApInitDone; - for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { - SetApState (&CpuMpData->CpuData[Index], CpuStateIdle); - } + } + + // + // Detect and apply Microcode on BSP + // + MicrocodeDetect (CpuMpData, TRUE); + // + // Store BSP's MTRR setting + // + MtrrGetAllMtrrs (&CpuMpData->MtrrTable); + + // + // Wakeup APs to do some AP initialize sync (Microcode & MTRR) + // + if (CpuMpData->CpuCount > 1) { + WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE); + while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) { + CpuPause (); + } + + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + SetApState (&CpuMpData->CpuData[Index], CpuStateIdle); } } =20 --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#52583): https://edk2.groups.io/g/devel/message/52583 Mute This Topic: https://groups.io/mt/69283205/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 20:52:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52584+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52584+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577431960; cv=none; d=zohomail.com; s=zohoarc; b=WQkCSAQP2ywluHS+SmfHljVTgqZZYdSPLlGAWa+UpFqWLIK4X6M6JY62xnXsqRNpoK2o+JmLD3gbZeaNcV4TRCjpAEk48rL3U8XoyazvsQhsuzLhWFwjw0d3+x5HO7qh825x4KDghI3u/HG9fa23okQACodpWofmQ5BhILtlrKE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577431960; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=sGRg2shwbCJMYnfd4dHyOFcfTFrHK6rdVzRovvRXs3c=; b=ln8me5ratJetsSKzWmV3cqCZm4u1imYIBX1UesoTRrntTN0iLXyxRvyP1PKaTfjzJbVNHCA3lBjDk1DSv7/Dnz4vtklbE8VApz6r1kKJZzfPtYxxmk56viCGY0AwvQXBXT38wwSG/TU4o6xCu8+Ct56vkFKKONLJK6DU+71FlA8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52584+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577431960950175.11815797445706; Thu, 26 Dec 2019 23:32:40 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id itwxYY1788612xcuogV5Zb5p; Thu, 26 Dec 2019 23:32:39 -0800 X-Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web12.29151.1577431953513368188 for ; Thu, 26 Dec 2019 23:32:38 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Dec 2019 23:32:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,362,1571727600"; d="scan'208";a="220445503" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by orsmga003.jf.intel.com with ESMTP; 26 Dec 2019 23:32:36 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v4 3/6] UefiCpuPkg: Add definitions for EDKII microcode patch HOB Date: Fri, 27 Dec 2019 15:32:26 +0800 Message-Id: <20191227073229.9416-4-hao.a.wu@intel.com> In-Reply-To: <20191227073229.9416-1-hao.a.wu@intel.com> References: <20191227073229.9416-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: QCXCu1Tkk5EoQGwsdEyQroVPx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577431959; bh=solhm36uzMoSeZq5dCHDVGYLhF5xn+20uwGNZfXiHWs=; h=Cc:Date:From:Reply-To:Subject:To; b=vr/18eu8d2DZKeb3Zs0zrcK/WNesvwZs5omosRYt7QmPTg+QSFxU74lZKRNnAYIh/qA USAW/ADO7p4B39Oc/qWNHsX8Hm+iBW8ilUKeCf4dJGKKHZu5abIFMDss2M9SuZ0vbP7L8 52Fr61jR7rx8bSMPQdt5JSlVkWbyQsrkYGo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2430 This commit will add the definitions for EDKII microcode patch HOB. The intention of adding this HOB is to provide a scheme to store the below information: A. The base address and size of the microcode patches that are being loaded (from flash) into memory; B. The information of detected microcode patch for each processor within the system. The producer of the HOB will be the UefiCpuPkg/MpInitLib (where the load, detect and apply of the microcode happen). The consumer of the HOB can be modules that want to detect/apply the microcode patch by themselves again later during the boot flow. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu Reviewed-by: Ray Ni Reviewed-by: Eric Dong --- UefiCpuPkg/UefiCpuPkg.dec | 3 ++ UefiCpuPkg/Include/Guid/MicrocodePatchHob.h | 44 ++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 797f948631..45b267ac61 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -63,6 +63,9 @@ [Guids] ## Include/Guid/CpuFeaturesInitDone.h gEdkiiCpuFeaturesInitDoneGuid =3D { 0xc77c3a41, 0x61ab, 0x4143, { 0x98,= 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} =20 + ## Include/Guid/MicrocodePatchHob.h + gEdkiiMicrocodePatchHobGuid =3D { 0xd178f11d, 0x8716, 0x418e, { 0xa1,= 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94,= 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} diff --git a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h b/UefiCpuPkg/Inclu= de/Guid/MicrocodePatchHob.h new file mode 100644 index 0000000000..2d307fbffb --- /dev/null +++ b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h @@ -0,0 +1,44 @@ +/** @file + The microcode patch HOB is used to store the information of: + A. Base address and size of the loaded microcode patches data; + B. Detected microcode patch for each processor within system. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MICROCODE_PATCH_HOB_H_ +#define _MICROCODE_PATCH_HOB_H_ + +extern EFI_GUID gEdkiiMicrocodePatchHobGuid; + +// +// The EDKII microcode patch HOB will be produced by MpInitLib and it can = be +// consumed by modules that want to detect/apply microcode patches. +// +typedef struct { + // + // The base address of the microcode patches data after being loaded into + // memory. + // + UINT64 MicrocodePatchAddress; + // + // The total size of the loaded microcode patches. + // + UINT64 MicrocodePatchRegionSize; + // + // The number of processors within the system. + // + UINT32 ProcessorCount; + // + // An array with 'ProcessorCount' elements that stores the offset (with + // regard to 'MicrocodePatchAddress') of the detected microcode patch + // (including the CPU_MICROCODE_HEADER data structure) for each processo= r. + // If no microcode patch is detected for certain processor, the relating + // element will be set to MAX_UINT64. + // + UINT64 ProcessorSpecificPatchOffset[0]; +} EDKII_MICROCODE_PATCH_HOB; + +#endif --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#52584): https://edk2.groups.io/g/devel/message/52584 Mute This Topic: https://groups.io/mt/69283206/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 20:52:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52585+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52585+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577431961; cv=none; d=zohomail.com; s=zohoarc; b=TzL/xWOIcRIPz9wKBUtG3UqAA1ge6RhZbdbDOFeSAZlhmmmxwtYSc211rtwTJp50BL6hzaSB6C4nwOVYlb4u2ymjqRNf/Jy+XtOfXf8PKwkSKVu/CMVwutNNA27dqXvXEgQyLN9Z4aDjTDs5X1WEuKmUgcSwflFEhcJnJbfP+NM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577431961; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=lzr9Y8uE9ML+nq6Zia0nsouJpO7b1G9c0uWA6vA7Mno=; b=PypgQ3SjlVSJ1zF37G++SzyRygCZTnITitSPxdXWuTddrZBHkXhtDobRESlqZj2gV/nuaPTxbqMeuGyWC6wWv032gYoTk8WyTn8yhdVW+EKlO3XeTpSA67ucWCyMxbyxeOg3ZcY+qENzF2RmBxWyKBFFHzSjmtDwgVGIB5D2aEo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52585+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577431961675343.28017170833584; Thu, 26 Dec 2019 23:32:41 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id JFmNYY1788612xdjvx5hEcFL; Thu, 26 Dec 2019 23:32:41 -0800 X-Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web12.29151.1577431953513368188 for ; Thu, 26 Dec 2019 23:32:40 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Dec 2019 23:32:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,362,1571727600"; d="scan'208";a="220445509" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by orsmga003.jf.intel.com with ESMTP; 26 Dec 2019 23:32:38 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v4 4/6] UefiCpuPkg/MpInitLib: Produce EDKII microcode patch HOB Date: Fri, 27 Dec 2019 15:32:27 +0800 Message-Id: <20191227073229.9416-5-hao.a.wu@intel.com> In-Reply-To: <20191227073229.9416-1-hao.a.wu@intel.com> References: <20191227073229.9416-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: 7spDPIIlJN5VJWu1JwciSV48x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577431961; bh=jBpnpcvIhCf0Knky4bc28B422XYfFLPQ7Wk/bc4JZdU=; h=Cc:Date:From:Reply-To:Subject:To; b=pofUN+c5l09RrPvHMj2Kukp6OP6JilvpSF+xbvqgHJ9R2ojtXj2Kp9oEG3EMRcc1m2x avQWT2G4G4bbADTDAhShRyob1KS9C3w6k7a9rM6yv7vEDBQ41P77I9OmpvvPVdusvQOwc pVgIPM6x9ektsKXDhcpY4gbeRjl7TAeTN1Q= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2430 This commit will update the MpInitLib to: A. Collect the base address and size information after microcode patches being loaded into memory; B. Collect the detected microcode patch for each processor within system; C. Based on the collected information, produce the EDKII microcode patch HOB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu --- UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/MpLib.h | 24 +++++++-- UefiCpuPkg/Library/MpInitLib/Microcode.c | 20 +++++-- UefiCpuPkg/Library/MpInitLib/MpLib.c | 8 ++- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 55 ++++++++++++++++++++ 5 files changed, 100 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 1538185ef9..326703cc9a 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -63,3 +63,4 @@ [Pcd] =20 [Guids] gEdkiiS3SmmInitDoneGuid + gEdkiiMicrocodePatchHobGuid diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 56b0df664a..885656900c 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -138,6 +138,7 @@ typedef struct { EFI_EVENT WaitEvent; UINT32 ProcessorSignature; UINT8 PlatformId; + UINT64 MicrocodeEntryAddr; } CPU_AP_DATA; =20 // @@ -580,13 +581,15 @@ CheckAndUpdateApsStatus ( /** Detect whether specified processor can find matching microcode patch and= load it. =20 - @param[in] CpuMpData The pointer to CPU MP Data structure. - @param[in] IsBspCallIn Indicate whether the caller is BSP or not. + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] ProcessorNumber The handle number of the processor. The ran= ge is + from 0 to the total number of logical proce= ssors + minus 1. **/ VOID MicrocodeDetect ( IN CPU_MP_DATA *CpuMpData, - IN BOOLEAN IsBspCallIn + IN UINTN ProcessorNumber ); =20 /** @@ -619,5 +622,20 @@ EnableDebugAgent ( VOID ); =20 +/** + Find the current Processor number by APIC ID. + + @param[in] CpuMpData Pointer to PEI CPU MP Data + @param[out] ProcessorNumber Return the pocessor number found + + @retval EFI_SUCCESS ProcessorNumber is found and returned. + @retval EFI_NOT_FOUND ProcessorNumber is not found. +**/ +EFI_STATUS +GetProcessorNumber ( + IN CPU_MP_DATA *CpuMpData, + OUT UINTN *ProcessorNumber + ); + #endif =20 diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 62a104742a..74a34c48fa 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -65,13 +65,15 @@ GetCurrentMicrocodeSignature ( It does not guarantee that the data has not been modified. CPU has its own mechanism to verify Microcode Binary part. =20 - @param[in] CpuMpData The pointer to CPU MP Data structure. - @param[in] IsBspCallIn Indicate whether the caller is BSP or not. + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] ProcessorNumber The handle number of the processor. The ran= ge is + from 0 to the total number of logical proce= ssors + minus 1. **/ VOID MicrocodeDetect ( IN CPU_MP_DATA *CpuMpData, - IN BOOLEAN IsBspCallIn + IN UINTN ProcessorNumber ) { UINT32 ExtendedTableLength; @@ -93,6 +95,7 @@ MicrocodeDetect ( MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; UINT32 ProcessorFlags; UINT32 ThreadId; + BOOLEAN IsBspCallIn; =20 // // set ProcessorFlags to suppress incorrect compiler/analyzer warnings @@ -107,6 +110,7 @@ MicrocodeDetect ( } =20 CurrentRevision =3D GetCurrentMicrocodeSignature (); + IsBspCallIn =3D (ProcessorNumber =3D=3D (UINTN)CpuMpData->BspNumber)= ? TRUE : FALSE; if (CurrentRevision !=3D 0 && !IsBspCallIn) { // // Skip loading microcode if it has been loaded successfully @@ -319,6 +323,16 @@ Done: } } =20 + if (LatestRevision !=3D 0) { + // + // Save the detected microcode patch entry address (including the + // microcode patch header) for each processor. + // It will be used when building the microcode patch cache HOB. + // + CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr =3D + (UINTN) MicrocodeData - sizeof (CPU_MICROCODE_HEADER); + } + if (IsBspCallIn && (LatestRevision !=3D 0)) { // // Save BSP processor info and microcode info for later AP use. diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index c72bf3c9ee..e611a8ca40 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -399,12 +399,16 @@ ApInitializeSync ( ) { CPU_MP_DATA *CpuMpData; + UINTN ProcessorNumber; + EFI_STATUS Status; =20 CpuMpData =3D (CPU_MP_DATA *) Buffer; + Status =3D GetProcessorNumber (CpuMpData, &ProcessorNumber); + ASSERT_EFI_ERROR (Status); // // Load microcode on AP // - MicrocodeDetect (CpuMpData, FALSE); + MicrocodeDetect (CpuMpData, ProcessorNumber); // // Sync BSP's MTRR table to AP // @@ -1761,7 +1765,7 @@ MpInitLibInitialize ( // // Detect and apply Microcode on BSP // - MicrocodeDetect (CpuMpData, TRUE); + MicrocodeDetect (CpuMpData, CpuMpData->BspNumber); // // Store BSP's MTRR setting // diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index 3999603c3e..06e3f5d0d3 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -9,6 +9,7 @@ #include "MpLib.h" #include #include +#include =20 /** S3 SMM Init Done notification function. @@ -291,6 +292,59 @@ CheckAndUpdateApsStatus ( } =20 /** + Build the microcode patch HOB that contains the base address and size of= the + microcode patch stored in the memory. + + @param[in] CpuMpData Pointer to the CPU_MP_DATA structure. + +**/ +VOID +BuildMicrocodeCacheHob ( + IN CPU_MP_DATA *CpuMpData + ) +{ + EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; + UINTN HobDataLength; + UINT32 Index; + + HobDataLength =3D sizeof (EDKII_MICROCODE_PATCH_HOB) + + sizeof (UINT64) * CpuMpData->CpuCount; + + MicrocodeHob =3D AllocatePool (HobDataLength); + if (MicrocodeHob =3D=3D NULL) { + ASSERT (FALSE); + return; + } + + // + // Store the information of the memory region that holds the microcode p= atches. + // + MicrocodeHob->MicrocodePatchAddress =3D CpuMpData->MicrocodePatchAddr= ess; + MicrocodeHob->MicrocodePatchRegionSize =3D CpuMpData->MicrocodePatchRegi= onSize; + + // + // Store the detected microcode patch for each processor as well. + // + MicrocodeHob->ProcessorCount =3D CpuMpData->CpuCount; + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + if (CpuMpData->CpuData[Index].MicrocodeEntryAddr !=3D 0) { + MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D + CpuMpData->CpuData[Index].MicrocodeEntryAddr - CpuMpData->Microcod= ePatchAddress; + } else { + MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D MAX_UINT64; + } + } + + BuildGuidDataHob ( + &gEdkiiMicrocodePatchHobGuid, + MicrocodeHob, + HobDataLength + ); + + return; +} + +/** Initialize global data for MP support. =20 @param[in] CpuMpData The pointer to CPU MP Data structure. @@ -302,6 +356,7 @@ InitMpGlobalData ( { EFI_STATUS Status; =20 + BuildMicrocodeCacheHob (CpuMpData); SaveCpuMpData (CpuMpData); =20 /// --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#52585): https://edk2.groups.io/g/devel/message/52585 Mute This Topic: https://groups.io/mt/69283207/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 20:52:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52586+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52586+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577431963; cv=none; d=zohomail.com; s=zohoarc; b=Ie/uxTjzHXN7817YmdqpDuHJjaWniAi9qkU2K303G/tRctn78PBDSHF9pPZSn5vhRq2Rwo8ieD/wLblgPZ6BDsd2q4pa59CdSV+zgVP8twmNMzejw2Jka2k+XokeP+3XwoS22HHAspRVOaX6ubAlsYOvpxmYuy0C2qq1yunI4kw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577431963; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=3KVcDNOS/a4BeJjxhIj0D6fLIUXLlHRyxYkM1TSEcik=; b=jJKTIxNa3T9JbqXdOcnL4ooGT/vMJft/qj1IHw0EDYSeC5XzuhFOsEkKtQkhFm+PsEq1QsoUeKU3xsOaj0+Izn5ggNNWVD+ql08mspCWyt+jgXgOMspAkWjJ/d2sCi29SEjZy/tCPs6UXksSRiNWcTc0uNCRWT7dDJMkLicGSMo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52586+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577431963116554.6036280969245; Thu, 26 Dec 2019 23:32:43 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id AF5cYY1788612xcZkySwM1Mr; Thu, 26 Dec 2019 23:32:42 -0800 X-Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web12.29151.1577431953513368188 for ; Thu, 26 Dec 2019 23:32:42 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Dec 2019 23:32:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,362,1571727600"; d="scan'208";a="220445514" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by orsmga003.jf.intel.com with ESMTP; 26 Dec 2019 23:32:40 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v4 5/6] UefiCpuPkg/MpInitLib: Relocate microcode patch fields in CPU_MP_DATA Date: Fri, 27 Dec 2019 15:32:28 +0800 Message-Id: <20191227073229.9416-6-hao.a.wu@intel.com> In-Reply-To: <20191227073229.9416-1-hao.a.wu@intel.com> References: <20191227073229.9416-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: f7H7p55jRXjucYvig4JzssNQx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577431962; bh=8WaTS892BlKP5h2j0x8a6qlYO8N1Irwi7FJstl1kgio=; h=Cc:Date:From:Reply-To:Subject:To; b=bHl1P0Lr2OqTOLffGL71LTct0fqZxw6CSqQbY0Q6HzZ/S4G+owSGL1wzz7MgW3g5JnJ GXuZMD8cZAl823thRMBIlzCoJUc5ada3tJbFnoTFOyGp8UnOQyQRANNQDSCDUa/X1J1h4 nB+CSPDuu7fjC/N0VGc40C656F9tYTLhg3Q= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The below 2 microcode patch related fields in structure CPU_MP_DATA: UINT64 MicrocodePatchAddress; UINT64 MicrocodePatchRegionSize; They will be passed from PEI phase and be reused DXE phase. Previously, these 2 fields were placed after some fields with type 'UINTN', this will lead to different field offset in different architecture for them. This commit will move them before the fields with different size in different architecture to ensure they can be properly used in DXE phase. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu Reviewed-by: Ray Ni Reviewed-by: Eric Dong --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 885656900c..5f50e79744 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -217,6 +217,8 @@ struct _CPU_MP_DATA { UINT64 CpuInfoInHob; UINT32 CpuCount; UINT32 BspNumber; + UINT64 MicrocodePatchAddress; + UINT64 MicrocodePatchRegionSize; // // The above fields data will be passed from PEI to DXE // Please make sure the fields offset same in the different @@ -260,8 +262,6 @@ struct _CPU_MP_DATA { UINT8 Vector; BOOLEAN PeriodicMode; BOOLEAN TimerInterruptState; - UINT64 MicrocodePatchAddress; - UINT64 MicrocodePatchRegionSize; =20 UINT32 ProcessorSignature; UINT32 ProcessorFlags; --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#52586): https://edk2.groups.io/g/devel/message/52586 Mute This Topic: https://groups.io/mt/69283208/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 20:52:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52587+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52587+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577431966; cv=none; d=zohomail.com; s=zohoarc; b=Vq0A42Q/Rn5V+nLUQpv4oxLXqi6i6bFSegQ184+2PmXy5/ojY6n0vhQxOlxE3xT5QuqG2YOKttIZnXDmJz1mKiEDGZO8U0lJxqZAguOaP69GoBQ0PovLT0Pa7iEdsA9t/pJI6hw9/G5/oVHPv7mkKlPRygeUQk09sIamQ2GBylY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577431966; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=3rQ5MKzBHcL1yueHEqFeCZ2RNciYdCaY46N9AREg5KY=; b=HP6CULwArmAvCyBLZ3tM6TVxlVsMyOw/gWSI74YQ0uAdr5GqFX/xd7LPlDEOoDKONeLJppRQ0hKtfhNKefZ8eB1IBkZ76UI6otoLtZQfdOmFEbK3O6RVaBFJPm3pEKLc8iqC/5GOgkxFbN8LYrWnH1ySdz0MB2Km4CVF9C2py90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52587+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577431966922210.0803115948528; Thu, 26 Dec 2019 23:32:46 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id gyvTYY1788612xa59yzZ4IKI; Thu, 26 Dec 2019 23:32:44 -0800 X-Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web12.29151.1577431953513368188 for ; Thu, 26 Dec 2019 23:32:43 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Dec 2019 23:32:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,362,1571727600"; d="scan'208";a="220445520" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by orsmga003.jf.intel.com with ESMTP; 26 Dec 2019 23:32:41 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v4 6/6] UefiCpuPkg/MpInitLib: Remove redundant microcode fields in CPU_MP_DATA Date: Fri, 27 Dec 2019 15:32:29 +0800 Message-Id: <20191227073229.9416-7-hao.a.wu@intel.com> In-Reply-To: <20191227073229.9416-1-hao.a.wu@intel.com> References: <20191227073229.9416-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: SYKtZFB6wgO5SAgwQaiSpQotx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577431964; bh=UgGDeCRpu+1+JvIMeFDgrEebIBelJKv7ORZHQd6rQAI=; h=Cc:Date:From:Reply-To:Subject:To; b=iyICJd7gTXVnLQoRswP4GCLtN0CCfTXM3SZzRb5832NR5WYG+CyZZFPS5DAy8CvhuhG I/3bAycKIcu3vTYUDHCeHR07MrcoFgla3jpZHNoGNwdizEPkSMuaIU4MqU28TH1LfuO9W YAKNrpieEwYgc/lElcUXUL+Zx4R+gRAfScw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previous commits have introduced below fields in structure CPU_AP_DATA: UINT32 ProcessorSignature; UINT8 PlatformId; UINT64 MicrocodeEntryAddr; which store the information of: A. CPUID B. Platform ID C. Detected microcode patch entry address (including the microcode patch header) for each processor within system. Therefore, the below fields in structure CPU_MP_DATA: UINT32 ProcessorSignature; UINT32 ProcessorFlags; UINT64 MicrocodeDataAddress; UINT32 MicrocodeRevision; which store the BSP's information of: A. CPUID B. Platform ID C. The address and revision of detected microcode patch are redundant and can be removed. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu Reviewed-by: Eric Dong --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 5 -- UefiCpuPkg/Library/MpInitLib/Microcode.c | 51 ++++++-------------- 2 files changed, 14 insertions(+), 42 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 5f50e79744..6609c958ce 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -263,11 +263,6 @@ struct _CPU_MP_DATA { BOOLEAN PeriodicMode; BOOLEAN TimerInterruptState; =20 - UINT32 ProcessorSignature; - UINT32 ProcessorFlags; - UINT64 MicrocodeDataAddress; - UINT32 MicrocodeRevision; - // // Whether need to use Init-Sipi-Sipi to wake up the APs. // Two cases need to set this value to TRUE. One is in HLT diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 74a34c48fa..4ec54b6220 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -85,6 +85,7 @@ MicrocodeDetect ( UINTN Index; UINT8 PlatformId; CPUID_VERSION_INFO_EAX Eax; + CPU_AP_DATA *CpuData; UINT32 CurrentRevision; UINT32 LatestRevision; UINTN TotalSize; @@ -92,16 +93,9 @@ MicrocodeDetect ( UINT32 InCompleteCheckSum32; BOOLEAN CorrectMicrocode; VOID *MicrocodeData; - MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; - UINT32 ProcessorFlags; UINT32 ThreadId; BOOLEAN IsBspCallIn; =20 - // - // set ProcessorFlags to suppress incorrect compiler/analyzer warnings - // - ProcessorFlags =3D 0; - if (CpuMpData->MicrocodePatchRegionSize =3D=3D 0) { // // There is no microcode patches @@ -127,28 +121,25 @@ MicrocodeDetect ( } =20 ExtendedTableLength =3D 0; - // - // Here data of CPUID leafs have not been collected into context buffer,= so - // GetProcessorCpuid() cannot be used here to retrieve CPUID data. - // - AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); - - // - // The index of platform information resides in bits 50:52 of MSR IA32_P= LATFORM_ID - // - PlatformIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); - PlatformId =3D (UINT8) PlatformIdMsr.Bits.PlatformId; + Eax.Uint32 =3D CpuMpData->CpuData[ProcessorNumber].ProcessorSignature; + PlatformId =3D CpuMpData->CpuData[ProcessorNumber].PlatformId; =20 // // Check whether AP has same processor with BSP. // If yes, direct use microcode info saved by BSP. // if (!IsBspCallIn) { - if ((CpuMpData->ProcessorSignature =3D=3D Eax.Uint32) && - (CpuMpData->ProcessorFlags & (1 << PlatformId)) !=3D 0) { - MicrocodeData =3D (VOID *)(UINTN) CpuMpData->MicrocodeDataAddress; - LatestRevision =3D CpuMpData->MicrocodeRevision; - goto Done; + // + // Get the CPU data for BSP + // + CpuData =3D &(CpuMpData->CpuData[CpuMpData->BspNumber]); + if ((CpuData->ProcessorSignature =3D=3D Eax.Uint32) && + (CpuData->PlatformId =3D=3D PlatformId) && + (CpuData->MicrocodeEntryAddr !=3D 0)) { + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *)(UINTN) CpuData->Mic= rocodeEntryAddr; + MicrocodeData =3D (VOID *) (MicrocodeEntryPoint + 1); + LatestRevision =3D MicrocodeEntryPoint->UpdateRevision; + goto Done; } } =20 @@ -216,7 +207,6 @@ MicrocodeDetect ( CheckSum32 +=3D MicrocodeEntryPoint->Checksum; if (CheckSum32 =3D=3D 0) { CorrectMicrocode =3D TRUE; - ProcessorFlags =3D MicrocodeEntryPoint->ProcessorFlags; } } else if ((MicrocodeEntryPoint->DataSize !=3D 0) && (MicrocodeEntryPoint->UpdateRevision > LatestRevision)) { @@ -260,7 +250,6 @@ MicrocodeDetect ( // Find one // CorrectMicrocode =3D TRUE; - ProcessorFlags =3D ExtendedTable->ProcessorFlag; break; } } @@ -332,18 +321,6 @@ Done: CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr =3D (UINTN) MicrocodeData - sizeof (CPU_MICROCODE_HEADER); } - - if (IsBspCallIn && (LatestRevision !=3D 0)) { - // - // Save BSP processor info and microcode info for later AP use. - // - CpuMpData->ProcessorSignature =3D Eax.Uint32; - CpuMpData->ProcessorFlags =3D ProcessorFlags; - CpuMpData->MicrocodeDataAddress =3D (UINTN) MicrocodeData; - CpuMpData->MicrocodeRevision =3D LatestRevision; - DEBUG ((DEBUG_INFO, "BSP Microcode:: signature [0x%08x], ProcessorFlag= s [0x%08x], \ - MicroData [0x%08x], Revision [0x%08x]\n", Eax.Uint32, ProcessorFlag= s, (UINTN) MicrocodeData, LatestRevision)); - } } =20 /** --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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