From nobody Sun May 5 20:49:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52510+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52510+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577151423; cv=none; d=zohomail.com; s=zohoarc; b=l7aQ5qtnKqwt7c8CizqJDxl1osCXkLVhJgYErCXRhejUfHmbLnRSfJcd8aP3wDgM5zGJCwE7qKNvBMyjY7fNedW9Hr/PAqWDC38VVWvuo8Nsc6KJCrt5J5d6EF9jXlyJT3VetAi9EqhJfGkXP69UKoc+EqUl2GJ09gOi/7mRPuE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577151423; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=lpKlTiGo0MJzu5U6R7ARMQo7ltsQDMUsfAAz10LvX38=; b=kMLPjFSB4b+iX0jOr/XVdBeCDn+YTcRD4/hHF5zscAMI6PkFZDGeEnG7oYpY4PRsyTD7r3vzKs7nApquFqgDqm8Z19LNJUqeIOv8r0lD56wBZDIpy2oeZnVBUhD8TZRUbQ/OwnF4sjsuvktKyG0XnizYhWMs1ui+iLvorXUGqqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52510+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 157715142394591.62428338654081; Mon, 23 Dec 2019 17:37:03 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id fpVHYY1788612xBHWnZu3aTr; Mon, 23 Dec 2019 17:37:03 -0800 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web09.334.1577151420986085921 for ; Mon, 23 Dec 2019 17:37:02 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Dec 2019 17:37:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,349,1571727600"; d="scan'208";a="249667557" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by fmsmga002.fm.intel.com with ESMTP; 23 Dec 2019 17:37:00 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v1 1/4] UefiCpuPkg/MpInitLib: Collect processors' CPUID & Platform ID info Date: Tue, 24 Dec 2019 09:36:53 +0800 Message-Id: <20191224013656.13404-2-hao.a.wu@intel.com> In-Reply-To: <20191224013656.13404-1-hao.a.wu@intel.com> References: <20191224013656.13404-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: cfDoqJR9lnHM6bpLvM96Z9jAx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577151423; bh=AUeTrPGKnN/6vopEFDFOzccJA6GEKfq1uu53ijPiPKo=; h=Cc:Date:From:Reply-To:Subject:To; b=gGbjq83ZOjK93G0lZxpOR27fnyLRn594wn3ABGLBw0i6ckXaoIeL0nIgSIwQywHn34r 0K36qqhpLevwBfdiuMX0azXXQDQIJOWTrCf3KDgCIoAiAlT0ZYkOcljtJNbiPH7cFld6Z x0NQbRWw1oMXL5xdCIWiMI+nqjNESvwuxhg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2429 This commit will collect the CPUID and Platform ID information for each processor within system. They will be stored in the CPU_AP_DATA structure. These information will be used in the next commit to decide whether a microcode patch will be loaded into memory. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu Reviewed-by: Ray Ni --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 2 ++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 14 +++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 8fa07b12c5..4440dc2701 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -122,6 +122,8 @@ typedef struct { UINT64 CurrentTime; UINT64 TotalTime; EFI_EVENT WaitEvent; + UINT32 ProcessorSignature; + UINT8 PlatformId; } CPU_AP_DATA; =20 // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index d32adf0780..d5077e080e 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -548,7 +548,8 @@ InitializeApData ( IN UINT64 ApTopOfStack ) { - CPU_INFO_IN_HOB *CpuInfoInHob; + CPU_INFO_IN_HOB *CpuInfoInHob; + MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; =20 CpuInfoInHob =3D (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob[ProcessorNumber].InitialApicId =3D GetInitialApicId (); @@ -559,6 +560,17 @@ InitializeApData ( CpuMpData->CpuData[ProcessorNumber].Waiting =3D FALSE; CpuMpData->CpuData[ProcessorNumber].CpuHealthy =3D (BistData =3D=3D 0) ?= TRUE : FALSE; =20 + PlatformIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + CpuMpData->CpuData[ProcessorNumber].PlatformId =3D (UINT8) PlatformIdMsr= .Bits.PlatformId; + + AsmCpuid ( + CPUID_VERSION_INFO, + &CpuMpData->CpuData[ProcessorNumber].ProcessorSignature, + NULL, + NULL, + NULL + ); + InitializeSpinLock(&CpuMpData->CpuData[ProcessorNumber].ApLock); SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle); } --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#52510): https://edk2.groups.io/g/devel/message/52510 Mute This Topic: https://groups.io/mt/69242652/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 20:49:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52511+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52511+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577151425; cv=none; d=zohomail.com; s=zohoarc; b=BSEzfqz2dW7l/uI66ZYhVgkxrMUAfyylR3xoEEs22q92CLsD9vb9jBMHJDFDVGMZeVHuzpzin7AIRL3Am5QqRNUFkXw/zMXY6T5GQMONvnLTI0jVAtVJGZyJ0cuuBTXU+ShIwkFENYaO+jzyDUdJqLWDLIrMrl9kdRqDhMEkRIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577151425; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=kAde0nmbIMRAVbay7CfzPlqoE0ts0dIKeoYVmxGWoWw=; b=D8iP4Z15zg6TJCddVegb0s4GoINBotNOMBx/3hIiXTKqIAV5AS7sCUOkKwnoqnYEU3ZmD2DUsORvAxETlWgUG+o09aHA5RAI+RFAGfMVIGA8GUruqd76XuybrQx5ohsPTwXwj9Tsn1qvwkEM26ntTIqJ/YTSbZsXgcZPLPYJbbc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52511+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577151425755229.31661322963782; Mon, 23 Dec 2019 17:37:05 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1rCjYY1788612xO0UybQLXnu; Mon, 23 Dec 2019 17:37:05 -0800 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web09.334.1577151420986085921 for ; Mon, 23 Dec 2019 17:37:04 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Dec 2019 17:37:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,349,1571727600"; d="scan'208";a="249667572" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by fmsmga002.fm.intel.com with ESMTP; 23 Dec 2019 17:37:02 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v1 2/4] UefiCpuPkg/MpInitLib: Reduce the size when loading microcode patches Date: Tue, 24 Dec 2019 09:36:54 +0800 Message-Id: <20191224013656.13404-3-hao.a.wu@intel.com> In-Reply-To: <20191224013656.13404-1-hao.a.wu@intel.com> References: <20191224013656.13404-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: m2cfDzPKpagXOyZdtBJFJIYpx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577151425; bh=Ie+vxjRbLQCKf0IjZCsGPPM8UOXcLfRoh2n28GuLi+g=; h=Cc:Date:From:Reply-To:Subject:To; b=jUwDJ9cZc7VOHGoJa+l2KEFRYiiUZwKObY87bq6FYh7RLu8JUtrhFatfwQV6CuAOQOP joHnmS4V20OG5K8BSCxyO8NIiT9XWxgkl0owM+4u8HbMNvCvqlR1rnctwyuoaAQFLDKWX AygjtK2OPyCLNq4rTxD9ode91heiwDUZENY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2429 This commit will attempt to reduce the copy size when loading the microcode patches data from flash into memory. Such optimization is done by a pre-process of the microcode patch headers (on flash). A microcode patch will be loaded into memory only when the below 2 criteria are met: A. With a microcode patch header (which means the data is not padding data between microcode patches); B. The 'ProcessorSignature' & 'ProcessorFlags' fields in the header match at least one processor within system. Criterion B will require all the processors to be woken up once to collect their CPUID and Platform ID information. Hence, this commit will move the copy, detect and apply of microcode patch on BSP and APs after all the processors have been woken up. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 24 ++ UefiCpuPkg/Library/MpInitLib/Microcode.c | 235 ++++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 82 ++----- 3 files changed, 283 insertions(+), 58 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 4440dc2701..56b0df664a 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -44,6 +44,20 @@ #define CPU_SWITCH_STATE_LOADED 2 =20 // +// Default maximum number of entries to store the microcode patches inform= ation +// +#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8 + +// +// Data structure for microcode patch information +// +typedef struct { + UINTN Address; + UINTN Size; + UINTN AlignedSize; +} MICROCODE_PATCH_INFO; + +// // CPU exchange information for switch BSP // typedef struct { @@ -576,6 +590,16 @@ MicrocodeDetect ( ); =20 /** + Load the required microcode patches data into memory. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. +**/ +VOID +LoadMicrocodePatch ( + IN OUT CPU_MP_DATA *CpuMpData + ); + +/** Detect whether Mwait-monitor feature is supported. =20 @retval TRUE Mwait-monitor feature is supported. diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 199b1f23ce..68088b26a5 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -331,3 +331,238 @@ Done: MicroData [0x%08x], Revision [0x%08x]\n", Eax.Uint32, ProcessorFlag= s, (UINTN) MicrocodeData, LatestRevision)); } } + +/** + Actual worker function that loads the required microcode patches into me= mory. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. + @param[in] PatchInfoBuffer The pointer to an array of informati= on on + the microcode patches that will be l= oaded + into memory. + @param[in] PatchNumber The number of microcode patches that= will + be loaded into memory. + @param[in] TotalLoadSize The total size of all the microcode + patches to be loaded. +**/ +VOID +LoadMicrocodePatchWorker ( + IN OUT CPU_MP_DATA *CpuMpData, + IN MICROCODE_PATCH_INFO *PatchInfoBuffer, + IN UINTN PatchNumber, + IN UINTN TotalLoadSize + ) +{ + UINTN Index; + VOID *MicrocodePatchInRam; + UINT8 *Walker; + + ASSERT ((PatchInfoBuffer !=3D NULL) && (PatchNumber !=3D 0)); + + MicrocodePatchInRam =3D AllocatePages (EFI_SIZE_TO_PAGES (TotalLoadSize)= ); + if (MicrocodePatchInRam =3D=3D NULL) { + return; + } + + // + // Load all the required microcode patches into memory + // + for (Walker =3D MicrocodePatchInRam, Index =3D 0; Index < PatchNumber; I= ndex++) { + CopyMem ( + Walker, + (VOID *) PatchInfoBuffer[Index].Address, + PatchInfoBuffer[Index].Size + ); + + if (PatchInfoBuffer[Index].AlignedSize > PatchInfoBuffer[Index].Size) { + // + // Zero-fill the padding area + // + ZeroMem ( + Walker + PatchInfoBuffer[Index].Size, + PatchInfoBuffer[Index].AlignedSize - PatchInfoBuffer[Index].Size + ); + } + + Walker +=3D PatchInfoBuffer[Index].AlignedSize; + } + + // + // Update the microcode patch related fields in CpuMpData + // + CpuMpData->MicrocodePatchAddress =3D (UINTN) MicrocodePatchInRam; + CpuMpData->MicrocodePatchRegionSize =3D TotalLoadSize; + + DEBUG (( + DEBUG_INFO, + "%a: Required microcode patches have been loaded at 0x%lx, with size 0= x%lx.\n", + __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePa= tchRegionSize + )); + + return; +} + +/** + Load the required microcode patches data into memory. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. +**/ +VOID +LoadMicrocodePatch ( + IN OUT CPU_MP_DATA *CpuMpData + ) +{ + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN MicrocodeEnd; + UINTN DataSize; + UINTN TotalSize; + MICROCODE_PATCH_INFO *PatchInfoBuffer; + UINTN MaxPatchNumber; + UINTN PatchNumber; + UINTN TotalLoadSize; + UINT32 ProcessorSignature; + UINT32 ProcessorFlags; + UINTN Index; + CPU_AP_DATA *CpuData; + BOOLEAN NeedLoad; + + // + // Initialize the microcode patch related fields in CpuMpData as the val= ues + // specified by the PCD pair. If the microcode patches are loaded into m= emory, + // these fields will be updated. + // + CpuMpData->MicrocodePatchAddress =3D PcdGet64 (PcdCpuMicrocodePatchAd= dress); + CpuMpData->MicrocodePatchRegionSize =3D PcdGet64 (PcdCpuMicrocodePatchRe= gionSize); + + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->M= icrocodePatchAddress; + MicrocodeEnd =3D (UINTN) MicrocodeEntryPoint + + (UINTN) CpuMpData->MicrocodePatchRegionSize; + if ((MicrocodeEntryPoint =3D=3D NULL) || ((UINTN) MicrocodeEntryPoint = =3D=3D MicrocodeEnd)) { + // + // There is no microcode patches + // + return; + } + + PatchNumber =3D 0; + MaxPatchNumber =3D DEFAULT_MAX_MICROCODE_PATCH_NUM; + TotalLoadSize =3D 0; + PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof (MICROCODE_PAT= CH_INFO)); + if (PatchInfoBuffer =3D=3D NULL) { + return; + } + + // + // Process the header of each microcode patch within the region. + // The purpose is to decide which microcode patch(es) will be loaded int= o memory. + // + do { + if (MicrocodeEntryPoint->HeaderVersion !=3D 0x1) { + // + // Padding data between the microcode patches, skip 1KB to check nex= t entry. + // + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode= EntryPoint) + SIZE_1KB); + continue; + } + + DataSize =3D MicrocodeEntryPoint->DataSize; + if (DataSize =3D=3D 0) { + TotalSize =3D sizeof (CPU_MICROCODE_HEADER) + 2000; + } else { + TotalSize =3D sizeof (CPU_MICROCODE_HEADER) + DataSize; + } + + if ( (UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize) || + ((UINTN)MicrocodeEntryPoint + TotalSize) > MicrocodeEnd || + (TotalSize & 0x3) !=3D 0 + ) { + // + // Not a valid microcode header, skip 1KB to check next entry. + // + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode= EntryPoint) + SIZE_1KB); + continue; + } + + TotalSize =3D (DataSize =3D=3D 0) ? 2048 : MicrocodeEntryPoint->TotalS= ize; + + // + // Check the 'ProcessorSignature' & 'ProcessorFlags' of this microcode= patch + // with the processors' CPUID & PlatformID to decide if it will be cop= ied + // into memory + // + ProcessorSignature =3D MicrocodeEntryPoint->ProcessorSignature.Uint32; + ProcessorFlags =3D MicrocodeEntryPoint->ProcessorFlags; + NeedLoad =3D FALSE; + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + CpuData =3D &CpuMpData->CpuData[Index]; + if ((ProcessorSignature =3D=3D CpuData->ProcessorSignature) && + (ProcessorFlags & (1 << CpuData->PlatformId)) !=3D 0) { + NeedLoad =3D TRUE; + break; + } + } + + if (NeedLoad) { + PatchNumber++; + if (PatchNumber >=3D MaxPatchNumber) { + // + // Current 'PatchInfoBuffer' cannot hold the information, double t= he size + // and allocate a new buffer. + // + if (MaxPatchNumber > MAX_UINTN / 2 / sizeof (MICROCODE_PATCH_INFO)= ) { + // + // Overflow check for MaxPatchNumber + // + goto OnExit; + } + + PatchInfoBuffer =3D ReallocatePool ( + MaxPatchNumber * sizeof (MICROCODE_PATCH_INFO), + 2 * MaxPatchNumber * sizeof (MICROCODE_PATCH_I= NFO), + PatchInfoBuffer + ); + if (PatchInfoBuffer =3D=3D NULL) { + goto OnExit; + } + MaxPatchNumber =3D MaxPatchNumber * 2; + } + + // + // Store the information of this microcode patch + // + if (TotalSize > MAX_UINTN - TotalLoadSize || + ALIGN_VALUE (TotalSize, SIZE_1KB) > MAX_UINTN - TotalLoadSize) { + goto OnExit; + } + PatchInfoBuffer[PatchNumber - 1].Address =3D (UINTN) MicrocodeEn= tryPoint; + PatchInfoBuffer[PatchNumber - 1].Size =3D TotalSize; + PatchInfoBuffer[PatchNumber - 1].AlignedSize =3D ALIGN_VALUE (TotalS= ize, SIZE_1KB); + TotalLoadSize +=3D PatchInfoBuffer[PatchNumber - 1].AlignedSize; + } + + // + // Process the next microcode patch + // + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEn= tryPoint) + TotalSize); + } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd)); + + if (PatchNumber =3D=3D 0) { + // + // No patch needs to be loaded + // + goto OnExit; + } + + DEBUG (( + DEBUG_INFO, + "%a: 0x%x microcode patches will be loaded into memory, with size 0x%x= .\n", + __FUNCTION__, PatchNumber, TotalLoadSize + )); + + LoadMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchNumber, Total= LoadSize); + +OnExit: + if (PatchInfoBuffer !=3D NULL) { + FreePool (PatchInfoBuffer); + } + return; +} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index d5077e080e..199468156b 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -628,10 +628,6 @@ ApWakeupFunction ( ApTopOfStack =3D CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpD= ata->CpuApStackSize; BistData =3D *(UINT32 *) ((UINTN) ApTopOfStack - sizeof (UINTN)); // - // Do some AP initialize sync - // - ApInitializeSync (CpuMpData); - // // CpuMpData->CpuData[0].VolatileRegisters is initialized based on B= SP environment, // to initialize AP in InitConfig path. // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegisters= points to a different IDT shared by all APs. @@ -1615,7 +1611,6 @@ MpInitLibInitialize ( UINTN ApResetVectorSize; UINTN BackupBufferAddr; UINTN ApIdtBase; - VOID *MicrocodePatchInRam; =20 OldCpuMpData =3D GetCpuMpDataFromGuidedHob (); if (OldCpuMpData =3D=3D NULL) { @@ -1683,39 +1678,7 @@ MpInitLibInitialize ( CpuMpData->SwitchBspFlag =3D FALSE; CpuMpData->CpuData =3D (CPU_AP_DATA *) (CpuMpData + 1); CpuMpData->CpuInfoInHob =3D (UINT64) (UINTN) (CpuMpData->CpuData + M= axLogicalProcessorNumber); - if (OldCpuMpData =3D=3D NULL) { - CpuMpData->MicrocodePatchRegionSize =3D PcdGet64 (PcdCpuMicrocodePatch= RegionSize); - // - // If platform has more than one CPU, relocate microcode to memory to = reduce - // loading microcode time. - // - MicrocodePatchInRam =3D NULL; - if (MaxLogicalProcessorNumber > 1) { - MicrocodePatchInRam =3D AllocatePages ( - EFI_SIZE_TO_PAGES ( - (UINTN)CpuMpData->MicrocodePatchRegionSize - ) - ); - } - if (MicrocodePatchInRam =3D=3D NULL) { - // - // there is only one processor, or no microcode patch is available, = or - // memory allocation failed - // - CpuMpData->MicrocodePatchAddress =3D PcdGet64 (PcdCpuMicrocodePatchA= ddress); - } else { - // - // there are multiple processors, and a microcode patch is available= , and - // memory allocation succeeded - // - CopyMem ( - MicrocodePatchInRam, - (VOID *)(UINTN)PcdGet64 (PcdCpuMicrocodePatchAddress), - (UINTN)CpuMpData->MicrocodePatchRegionSize - ); - CpuMpData->MicrocodePatchAddress =3D (UINTN)MicrocodePatchInRam; - } - }else { + if (OldCpuMpData !=3D NULL) { CpuMpData->MicrocodePatchRegionSize =3D OldCpuMpData->MicrocodePatchRe= gionSize; CpuMpData->MicrocodePatchAddress =3D OldCpuMpData->MicrocodePatchAd= dress; } @@ -1762,10 +1725,6 @@ MpInitLibInitialize ( (UINT32 *)(MonitorBuffer + MonitorFilterSize * Index); } // - // Load Microcode on BSP - // - MicrocodeDetect (CpuMpData, TRUE); - // // Store BSP's MTRR setting // MtrrGetAllMtrrs (&CpuMpData->MtrrTable); @@ -1781,6 +1740,11 @@ MpInitLibInitialize ( // CollectProcessorCount (CpuMpData); } + + // + // Load required microcode patches data into memory + // + LoadMicrocodePatch (CpuMpData); } else { // // APs have been wakeup before, just get the CPU Information @@ -1788,7 +1752,6 @@ MpInitLibInitialize ( // CpuMpData->CpuCount =3D OldCpuMpData->CpuCount; CpuMpData->BspNumber =3D OldCpuMpData->BspNumber; - CpuMpData->InitFlag =3D ApInitReconfig; CpuMpData->CpuInfoInHob =3D OldCpuMpData->CpuInfoInHob; CpuInfoInHob =3D (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { @@ -1797,21 +1760,24 @@ MpInitLibInitialize ( CpuMpData->CpuData[Index].ApFunction =3D 0; CopyMem (&CpuMpData->CpuData[Index].VolatileRegisters, &VolatileRegi= sters, sizeof (CPU_VOLATILE_REGISTERS)); } - if (MaxLogicalProcessorNumber > 1) { - // - // Wakeup APs to do some AP initialize sync - // - WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE); - // - // Wait for all APs finished initialization - // - while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) { - CpuPause (); - } - CpuMpData->InitFlag =3D ApInitDone; - for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { - SetApState (&CpuMpData->CpuData[Index], CpuStateIdle); - } + } + + // + // Detect and apply Microcode on BSP + // + MicrocodeDetect (CpuMpData, TRUE); + + // + // Wakeup APs to do some AP initialize sync (Microcode & MTRR) + // + if (CpuMpData->CpuCount > 1) { + WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE); + while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) { + CpuPause (); + } + + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + SetApState (&CpuMpData->CpuData[Index], CpuStateIdle); } } =20 --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#52511): https://edk2.groups.io/g/devel/message/52511 Mute This Topic: https://groups.io/mt/69242654/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 20:49:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52512+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52512+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577151427; cv=none; d=zohomail.com; s=zohoarc; b=PPwllm9TbfvSsof6HVgipWq7ATVhVCLA+evarixP6NM5+HZemxxz0LHT0FW9MGpR9xQjlH+U8XczHfhsIP4xYwrp7ZWAaziDkbJ6IXVEjOy+iqNOaa3+UyTXaeRs5zKBmxzwZDJeEXV9cxPtUIFiYImqCqQm5vPWeWyAArE6W+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577151427; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=ckNSfolpXJbaqZNDv3GcfYUGDRI2+NKAjt/ZO81uGAo=; b=EsmlSsKfexv87ZQHa1oCsxNjsUxMgT9BXOGHdz5CLixeG1fio67zbLEiii98unlUGM+8ZD9AYi01Xwn1qZUR/9+2WfQKld1g7bRjcYd5Q/sU5Q2aXI6G4r4DuF98PvS2HeNkMwBxPvgYHXNJrh4UXVGjhMuKrFqr1VqbE5Rmkxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52512+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 157715142700433.763456121045124; Mon, 23 Dec 2019 17:37:07 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id HZCoYY1788612xvP2OJleVda; Mon, 23 Dec 2019 17:37:06 -0800 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web09.334.1577151420986085921 for ; Mon, 23 Dec 2019 17:37:06 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Dec 2019 17:37:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,349,1571727600"; d="scan'208";a="249667589" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by fmsmga002.fm.intel.com with ESMTP; 23 Dec 2019 17:37:04 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v1 3/4] UefiCpuPkg: Add definitions for EDKII microcode patch HOB Date: Tue, 24 Dec 2019 09:36:55 +0800 Message-Id: <20191224013656.13404-4-hao.a.wu@intel.com> In-Reply-To: <20191224013656.13404-1-hao.a.wu@intel.com> References: <20191224013656.13404-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: kdQVtcUMQGcv0LcTOobuUuPsx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577151426; bh=7ho3JUiXYkkJz9QeXRVSu3ySAVQ6PeUpxRoxjiQ0hsQ=; h=Cc:Date:From:Reply-To:Subject:To; b=T/FdWdLefT63HX7SxO05IBkmUvzmkl13wEEUcj5kaW6yvvNOqy8BqgnHBGCQjRM+yZF QV3wgryhvvk7euFa6qpl4tsMg8vNYIQmd/UtPu3kg3BTBZMYCUMN4U5woyuM3Jlt79I/H qPlov8V6ni/ZlgFopQh9axph33LBy/OQz+k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2430 This commit will add the definitions for EDKII microcode patch HOB. The intention of adding this HOB is to provide a scheme to store the below information: A. The base address and size of the microcode patches that are being loaded (from flash) into memory; B. The information of applied microcode patch for each processor within the system. The producer of the HOB will be the UefiCpuPkg/MpInitLib (where the load, detect and apply of the microcode happen). The consumer of the HOB can be modules that want to detect/apply the microcode patch by themselves again later during the boot flow. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu --- UefiCpuPkg/UefiCpuPkg.dec | 3 ++ UefiCpuPkg/Include/Guid/MicrocodePatchHob.h | 50 ++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 797f948631..45b267ac61 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -63,6 +63,9 @@ [Guids] ## Include/Guid/CpuFeaturesInitDone.h gEdkiiCpuFeaturesInitDoneGuid =3D { 0xc77c3a41, 0x61ab, 0x4143, { 0x98,= 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} =20 + ## Include/Guid/MicrocodePatchHob.h + gEdkiiMicrocodePatchHobGuid =3D { 0xd178f11d, 0x8716, 0x418e, { 0xa1,= 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94,= 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} diff --git a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h b/UefiCpuPkg/Inclu= de/Guid/MicrocodePatchHob.h new file mode 100644 index 0000000000..3667fc3786 --- /dev/null +++ b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h @@ -0,0 +1,50 @@ +/** @file + The microcode patch HOB is used to store the information of: + A. Base address and size of the loaded microcode patches data; + B. Applied microcode patch for each processor within system. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _MICROCODE_PATCH_HOB_H_ +#define _MICROCODE_PATCH_HOB_H_ + +extern EFI_GUID gEdkiiMicrocodePatchHobGuid; + +// +// The EDKII microcode patch HOB will be produced by MpInitLib and it can = be +// consumed by modules that want to detect/apply microcode patches. +// +typedef struct { + // + // The base address of the microcode patches data after being loaded into + // memory. + // + UINT64 MicrocodePatchAddress; + // + // The total size of the loaded microcode patches. + // + UINT64 MicrocodePatchRegionSize; + // + // The number of processors within the system. + // + UINT32 ProcessorNumber; + // + // An array with 'ProcessorNumber' elements that stores the offset (with + // regard to 'MicrocodePatchAddress') of the applied microcode patch for= each + // processor. + // If no microcode patch is applied for certain processor, the relating + // element will be set to MAX_UINT64. + // + UINT64 DetectedPatchOffset[0]; +} EDKII_MICROCODE_PATCH_HOB; + +#endif --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#52512): https://edk2.groups.io/g/devel/message/52512 Mute This Topic: https://groups.io/mt/69242655/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 20:49:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52513+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52513+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1577151428; cv=none; d=zohomail.com; s=zohoarc; b=UZ84YgMhes16bJBvlrUILHcvJ5YdmhLU5X8sG2hzFFIOj1V6qFlTR1fAIPEOT0V7FNJGLszRuwPkR7/JhyjxbWfCHR1/0VCnqvFD8V7JpgLka9phjjMGuzmSJLHbPy+KANeuPv2hf95Mbswxp8i7biy+5MvpjJDxRGZ1UIWzmhg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1577151428; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=2gTF+TfoqK3Sd0o7caTjYvQie7j7P4hH8tezjQSVc0U=; b=nQIH/eclu673lfIlR+cp12lpTFxf+UyKk/tbHJn7e86GgO5QZlPOd1gRxG8qx8moIH1VFOFZI+78eWEqFFmHu4bicxkyV5uh0ABMZ2DUQIhTwncrUB+Bsw0Rry3kl4wPcZ503TtYEF1POMVDnNwT/rNOYXZ7W3wu98uLK7xMxfk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52513+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1577151428693324.8879704221795; Mon, 23 Dec 2019 17:37:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id XYkvYY1788612xiuK95mk8f8; Mon, 23 Dec 2019 17:37:08 -0800 X-Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web09.334.1577151420986085921 for ; Mon, 23 Dec 2019 17:37:07 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Dec 2019 17:37:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,349,1571727600"; d="scan'208";a="249667612" X-Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.8]) by fmsmga002.fm.intel.com with ESMTP; 23 Dec 2019 17:37:05 -0800 From: "Wu, Hao A" To: devel@edk2.groups.io Cc: Hao A Wu , Eric Dong , Ray Ni , Laszlo Ersek , Star Zeng , Siyuan Fu , Michael D Kinney Subject: [edk2-devel] [PATCH v1 4/4] UefiCpuPkg/MpInitLib: Produce EDKII microcode patch HOB Date: Tue, 24 Dec 2019 09:36:56 +0800 Message-Id: <20191224013656.13404-5-hao.a.wu@intel.com> In-Reply-To: <20191224013656.13404-1-hao.a.wu@intel.com> References: <20191224013656.13404-1-hao.a.wu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com X-Gm-Message-State: jrJIhl0LkP5snoEfYAlkCDDjx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1577151428; bh=jrAxTrwYRLe1k0/YfCRPWRY2m/VLPZX431FNyVwq3nY=; h=Cc:Date:From:Reply-To:Subject:To; b=ReoUFbRN/bVFaId7tIOFOPqZIvsD10J2xczI5XwEi+/pQ6Frt6IJeXk2QnKQ+rOBPEO /pCvI9Fvz/ysLdOOGWkd7O1KGr/9vGBR/VXlXSyJhqnNnOse3l/1ZTkSquVAMnbrCsCkp zUaug5FVRXu1iB5I0kxyMkRpCtq12CGUw44= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2430 This commit will update the MpInitLib to: A. Collect the base address and size information after microcode patches being loaded into memory; B. Collect the applied microcode patch for each processor within system; C. Based on the collected information, produce the EDKII microcode patch HOB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Cc: Siyuan Fu Cc: Michael D Kinney Signed-off-by: Hao A Wu --- UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/MpLib.h | 24 +++++++-- UefiCpuPkg/Library/MpInitLib/Microcode.c | 16 ++++-- UefiCpuPkg/Library/MpInitLib/MpLib.c | 8 ++- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 55 ++++++++++++++++++++ 5 files changed, 96 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 1538185ef9..326703cc9a 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -63,3 +63,4 @@ [Pcd] =20 [Guids] gEdkiiS3SmmInitDoneGuid + gEdkiiMicrocodePatchHobGuid diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 56b0df664a..fb251d7aef 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -138,6 +138,7 @@ typedef struct { EFI_EVENT WaitEvent; UINT32 ProcessorSignature; UINT8 PlatformId; + UINT64 MicrocodeData; } CPU_AP_DATA; =20 // @@ -580,13 +581,15 @@ CheckAndUpdateApsStatus ( /** Detect whether specified processor can find matching microcode patch and= load it. =20 - @param[in] CpuMpData The pointer to CPU MP Data structure. - @param[in] IsBspCallIn Indicate whether the caller is BSP or not. + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] ProcessorNumber The handle number of the processor. The ran= ge is + from 0 to the total number of logical proce= ssors + minus 1. **/ VOID MicrocodeDetect ( IN CPU_MP_DATA *CpuMpData, - IN BOOLEAN IsBspCallIn + IN UINTN ProcessorNumber ); =20 /** @@ -619,5 +622,20 @@ EnableDebugAgent ( VOID ); =20 +/** + Find the current Processor number by APIC ID. + + @param[in] CpuMpData Pointer to PEI CPU MP Data + @param[out] ProcessorNumber Return the pocessor number found + + @retval EFI_SUCCESS ProcessorNumber is found and returned. + @retval EFI_NOT_FOUND ProcessorNumber is not found. +**/ +EFI_STATUS +GetProcessorNumber ( + IN CPU_MP_DATA *CpuMpData, + OUT UINTN *ProcessorNumber + ); + #endif =20 diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 68088b26a5..bbc40f81bf 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -65,13 +65,15 @@ GetCurrentMicrocodeSignature ( It does not guarantee that the data has not been modified. CPU has its own mechanism to verify Microcode Binary part. =20 - @param[in] CpuMpData The pointer to CPU MP Data structure. - @param[in] IsBspCallIn Indicate whether the caller is BSP or not. + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] ProcessorNumber The handle number of the processor. The ran= ge is + from 0 to the total number of logical proce= ssors + minus 1. **/ VOID MicrocodeDetect ( IN CPU_MP_DATA *CpuMpData, - IN BOOLEAN IsBspCallIn + IN UINTN ProcessorNumber ) { UINT32 ExtendedTableLength; @@ -93,6 +95,7 @@ MicrocodeDetect ( MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; UINT32 ProcessorFlags; UINT32 ThreadId; + BOOLEAN IsBspCallIn; =20 // // set ProcessorFlags to suppress incorrect compiler/analyzer warnings @@ -107,6 +110,7 @@ MicrocodeDetect ( } =20 CurrentRevision =3D GetCurrentMicrocodeSignature (); + IsBspCallIn =3D (ProcessorNumber =3D=3D (UINTN)CpuMpData->BspNumber)= ? TRUE : FALSE; if (CurrentRevision !=3D 0 && !IsBspCallIn) { // // Skip loading microcode if it has been loaded successfully @@ -316,6 +320,12 @@ Done: DEBUG ((EFI_D_ERROR, "Updated microcode signature [0x%08x] does not = match \ loaded microcode signature [0x%08x]\n", CurrentRevision, L= atestRevision)); ReleaseSpinLock(&CpuMpData->MpLock); + } else { + // + // Save the detected microcode patch address for each processor. + // It will be used when building the microcode patch cache HOB. + // + CpuMpData->CpuData[ProcessorNumber].MicrocodeData =3D (UINTN) Microc= odeData; } } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 199468156b..8f4b2b1973 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -399,12 +399,16 @@ ApInitializeSync ( ) { CPU_MP_DATA *CpuMpData; + UINTN ProcessorNumber; + EFI_STATUS Status; =20 CpuMpData =3D (CPU_MP_DATA *) Buffer; + Status =3D GetProcessorNumber (CpuMpData, &ProcessorNumber); + ASSERT_EFI_ERROR (Status); // // Load microcode on AP // - MicrocodeDetect (CpuMpData, FALSE); + MicrocodeDetect (CpuMpData, ProcessorNumber); // // Sync BSP's MTRR table to AP // @@ -1765,7 +1769,7 @@ MpInitLibInitialize ( // // Detect and apply Microcode on BSP // - MicrocodeDetect (CpuMpData, TRUE); + MicrocodeDetect (CpuMpData, CpuMpData->BspNumber); =20 // // Wakeup APs to do some AP initialize sync (Microcode & MTRR) diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index 3999603c3e..977818fda4 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -9,6 +9,7 @@ #include "MpLib.h" #include #include +#include =20 /** S3 SMM Init Done notification function. @@ -291,6 +292,59 @@ CheckAndUpdateApsStatus ( } =20 /** + Build the microcode patch HOB that contains the base address and size of= the + microcode patch stored in the memory. + + @param[in] CpuMpData Pointer to the CPU_MP_DATA structure. + +**/ +VOID +BuildMicrocodeCacheHob ( + IN CPU_MP_DATA *CpuMpData + ) +{ + EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; + UINTN HobDataLength; + UINT32 Index; + + HobDataLength =3D sizeof (EDKII_MICROCODE_PATCH_HOB) + + sizeof (UINT64) * CpuMpData->CpuCount; + + MicrocodeHob =3D AllocatePool (HobDataLength); + if (MicrocodeHob =3D=3D NULL) { + ASSERT (FALSE); + return; + } + + // + // Store the information of the memory region that holds the microcode p= atches. + // + MicrocodeHob->MicrocodePatchAddress =3D CpuMpData->MicrocodePatchAddr= ess; + MicrocodeHob->MicrocodePatchRegionSize =3D CpuMpData->MicrocodePatchRegi= onSize; + + // + // Store the detected microcode patch for each processor as well. + // + MicrocodeHob->ProcessorNumber =3D CpuMpData->CpuCount; + for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { + if (CpuMpData->CpuData[Index].MicrocodeData !=3D 0) { + MicrocodeHob->DetectedPatchOffset[Index] =3D CpuMpData->CpuData[Inde= x].MicrocodeData - + CpuMpData->MicrocodePatch= Address; + } else { + MicrocodeHob->DetectedPatchOffset[Index] =3D MAX_UINT64; + } + } + + BuildGuidDataHob ( + &gEdkiiMicrocodePatchHobGuid, + MicrocodeHob, + HobDataLength + ); + + return; +} + +/** Initialize global data for MP support. =20 @param[in] CpuMpData The pointer to CPU MP Data structure. @@ -303,6 +357,7 @@ InitMpGlobalData ( EFI_STATUS Status; =20 SaveCpuMpData (CpuMpData); + BuildMicrocodeCacheHob (CpuMpData); =20 /// /// Install Notify --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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