From nobody Fri May 3 22:27:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52463+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52463+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1576862128; cv=none; d=zohomail.com; s=zohoarc; b=ULX89WRv1iK2SXeqWVrU+iyAfvNv3DU8VFX82HKfMs2+/jnLLdAdCMalVKfx7LOaXRibq5KLdBvGufRDsErKvIi5u5euVOwUmIJPxQ6nz0iEkySBhPjk739RoA6UrjyxoBotUV6l1BrrIwmpHezif8JIZms0TnrC2tvk0GXXNwE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576862128; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=1TzwoY1sWolg86hNMriJ598eKZ34zq/ygmzLUfbDv/k=; b=jGrup+I2W1SR2oRm/HW2Uhm1sRwdO5/PdE5dy22wqrc5ps40hotlJhx1xWse5GZTuRinvpCWaiCqJaTWE4reFK0hnVVoiO+C02zWrWUgVNRiHMFC3VSyO15EmTFrWQtkeMAEbqc4lFIArrElMIJPkI0/kkSUizJeczdRQAHHJaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52463+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1576862128393351.15762173149926; Fri, 20 Dec 2019 09:15:28 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id INrzYY1788612xhFbYzL52WX; Fri, 20 Dec 2019 09:15:27 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.11622.1576862085947015476 for ; Fri, 20 Dec 2019 09:14:46 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2019 09:14:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,336,1571727600"; d="scan'208";a="218533633" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by orsmga006.jf.intel.com with ESMTP; 20 Dec 2019 09:14:42 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCH 1/2] SdMmcPciHcDxe: Send EdkiiSdMmcSwitchClockFreq after SD clock start Date: Fri, 20 Dec 2019 18:13:11 +0100 Message-Id: <20191220171312.3120-2-mateusz.albecki@intel.com> In-Reply-To: <20191220171312.3120-1-mateusz.albecki@intel.com> References: <20191220171312.3120-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: 7hw5DkGkmbBOH1MVy8z4pLI5x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1576862127; bh=VqieA5W8mHRUXKcYUZGBO5xZQHknKQEIURaSywkSGI4=; h=Cc:Date:From:Reply-To:Subject:To; b=gy1uNUkXjSS3xwiAMk7Q/csSVg7uo7iaNZHQ1TYc3HRWKeuC2/E7kvFUOAy+3rOzkFL 9205RhQF4M1Le0R//v3K4Uan5COEoGhsFbpeKShcg93uDJLqT15w0ojz+6GeegVHMKrLd 4zGKHf7u36AI+L5ds0byOlMqvvBDCLinxGw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For eMMC modules we used to notify the platform about frequency change only after sending CMD13 which meant that platform might not get a chance to apply required post frequency change fixes to get the clock stable. To fix this notification has been moved to SdMmcHcClockSupply function just after we start the SD clock. During first time setup the notification won't be sent to avoid changing old behavior. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu Tested-by: Hao A Wu Tested-by: Marcin Wojtas --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 20 +--- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 28 ++---- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 24 +++++ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 107 +++++++++--------= ---- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 44 --------- 5 files changed, 81 insertions(+), 142 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg= /Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c index 082904ccc5..776c0e796c 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c @@ -727,7 +727,7 @@ EmmcSwitchBusTiming ( // // Convert the clock freq unit from MHz to KHz. // - Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->B= aseClkFreq[Slot], Private->ControllerVersion[Slot]); + Status =3D SdMmcHcClockSupply (Private, Slot, BusTiming, FALSE, ClockFre= q * 1000); if (EFI_ERROR (Status)) { return Status; } @@ -745,24 +745,6 @@ EmmcSwitchBusTiming ( return EFI_DEVICE_ERROR; } =20 - if (mOverride !=3D NULL && mOverride->NotifyPhase !=3D NULL) { - Status =3D mOverride->NotifyPhase ( - Private->ControllerHandle, - Slot, - EdkiiSdMmcSwitchClockFreqPost, - &BusTiming - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a: SD/MMC switch clock freq post notifier callback failed - %r\n= ", - __FUNCTION__, - Status - )); - return Status; - } - } - return Status; } =20 diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/B= us/Pci/SdMmcPciHcDxe/SdDevice.c index 336baade9e..d63dc54e8c 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c @@ -1145,29 +1145,11 @@ SdCardSetBusMode ( return Status; } =20 - Status =3D SdMmcHcClockSupply (PciIo, Slot, BusMode.ClockFreq * 1000, Pr= ivate->BaseClkFreq[Slot], Private->ControllerVersion[Slot]); + Status =3D SdMmcHcClockSupply (Private, Slot, BusMode.BusTiming, FALSE, = BusMode.ClockFreq * 1000); if (EFI_ERROR (Status)) { return Status; } =20 - if (mOverride !=3D NULL && mOverride->NotifyPhase !=3D NULL) { - Status =3D mOverride->NotifyPhase ( - Private->ControllerHandle, - Slot, - EdkiiSdMmcSwitchClockFreqPost, - &BusMode.BusTiming - ); - if (EFI_ERROR (Status)) { - DEBUG (( - DEBUG_ERROR, - "%a: SD/MMC switch clock freq post notifier callback failed - %r\n= ", - __FUNCTION__, - Status - )); - return Status; - } - } - if ((BusMode.BusTiming =3D=3D SdMmcUhsSdr104) || ((BusMode.BusTiming =3D= =3D SdMmcUhsSdr50) && (Capability->TuningSDR50 !=3D 0))) { Status =3D SdCardTuningClock (PciIo, PassThru, Slot); if (EFI_ERROR (Status)) { @@ -1345,7 +1327,13 @@ SdCardIdentification ( goto Error; } =20 - SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Priva= te->ControllerVersion[Slot]); + // + // Restart the clock with first time parameters. + // NOTE: it is not required to actually restart the clock + // and go through internal clock setup again. Some time + // could be saved if we simply started the SD clock. + // + SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400); =20 gBS->Stall (1000); =20 diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h index c29e48767e..0304960132 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h @@ -796,6 +796,30 @@ SdCardIdentification ( IN UINT8 Slot ); =20 +/** + SD/MMC card clock supply. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for detail= s. + + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA insta= nce. + @param[in] Slot The slot number of the SD card to send the co= mmand to. + @param[in] BusTiming BusTiming at which the frequency change is do= ne. + @param[in] FirstTimeSetup Flag to indicate whether the clock is being s= etup for the first time. + @param[in] ClockFreq The max clock frequency to be set. The unit i= s KHz. + + @retval EFI_SUCCESS The clock is supplied successfully. + @retval Others The clock isn't supplied successfully. + +**/ +EFI_STATUS +SdMmcHcClockSupply ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN SD_MMC_BUS_MODE BusTiming, + IN BOOLEAN FirstTimeSetup, + IN UINT64 ClockFreq + ); + /** Software reset the specified SD/MMC host controller. =20 diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index b9d04e0f17..f667264c5e 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -763,11 +763,11 @@ SdMmcHcStopClock ( =20 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for detail= s. =20 - @param[in] PciIo The PCI IO protocol instance. - @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] ClockFreq The max clock frequency to be set. The unit is= KHz. - @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. - @param[in] ControllerVer The version of host controller. + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA insta= nce. + @param[in] Slot The slot number of the SD card to send the co= mmand to. + @param[in] BusTiming BusTiming at which the frequency change is do= ne. + @param[in] FirstTimeSetup Flag to indicate whether the clock is being s= etup for the first time. + @param[in] ClockFreq The max clock frequency to be set. The unit i= s KHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -775,11 +775,11 @@ SdMmcHcStopClock ( **/ EFI_STATUS SdMmcHcClockSupply ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN UINT8 Slot, - IN UINT64 ClockFreq, - IN UINT32 BaseClkFreq, - IN UINT16 ControllerVer + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN SD_MMC_BUS_MODE BusTiming, + IN BOOLEAN FirstTimeSetup, + IN UINT64 ClockFreq ) { EFI_STATUS Status; @@ -787,13 +787,15 @@ SdMmcHcClockSupply ( UINT32 Divisor; UINT32 Remainder; UINT16 ClockCtrl; + UINT32 BaseClkFreq; + UINT16 ControllerVer; + EFI_PCI_IO_PROTOCOL *PciIo; =20 - // - // Calculate a divisor for SD clock frequency - // - ASSERT (BaseClkFreq !=3D 0); + PciIo =3D Private->PciIo; + BaseClkFreq =3D Private->BaseClkFreq[Slot]; + ControllerVer =3D Private->ControllerVersion[Slot]; =20 - if (ClockFreq =3D=3D 0) { + if (BaseClkFreq =3D=3D 0 || ClockFreq =3D=3D 0) { return EFI_INVALID_PARAMETER; } =20 @@ -883,6 +885,29 @@ SdMmcHcClockSupply ( ClockCtrl =3D BIT2; Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (Clo= ckCtrl), &ClockCtrl); =20 + // + // We don't notify the platform on first time setup to avoid changing + // legacy behavior. During first time setup we also don't know what type + // of the card slot it is and which enum value of BusTiming applies. + // + if (!FirstTimeSetup && mOverride !=3D NULL && mOverride->NotifyPhase != =3D NULL) { + Status =3D mOverride->NotifyPhase ( + Private->ControllerHandle, + Slot, + EdkiiSdMmcSwitchClockFreqPost, + &BusTiming + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n= ", + __FUNCTION__, + Status + )); + return Status; + } + } + return Status; } =20 @@ -1038,49 +1063,6 @@ SdMmcHcInitV4Enhancements ( return EFI_SUCCESS; } =20 -/** - Supply SD/MMC card with lowest clock frequency at initialization. - - @param[in] PciIo The PCI IO protocol instance. - @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. - @param[in] ControllerVer The version of host controller. - - @retval EFI_SUCCESS The clock is supplied successfully. - @retval Others The clock isn't supplied successfully. - -**/ -EFI_STATUS -SdMmcHcInitClockFreq ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN UINT8 Slot, - IN UINT32 BaseClkFreq, - IN UINT16 ControllerVer - ) -{ - EFI_STATUS Status; - UINT32 InitFreq; - - // - // According to SDHCI specification ver. 4.2, BaseClkFreq field value of - // the Capability Register 1 can be zero, which means a need for obtaini= ng - // the clock frequency via another method. Fail in case it is not updated - // by SW at this point. - // - if (BaseClkFreq =3D=3D 0) { - // - // Don't support get Base Clock Frequency information via another meth= od - // - return EFI_UNSUPPORTED; - } - // - // Supply 400KHz clock frequency at initialization phase. - // - InitFreq =3D 400; - Status =3D SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, Contr= ollerVer); - return Status; -} - /** Supply SD/MMC card with maximum voltage at initialization. =20 @@ -1216,7 +1198,14 @@ SdMmcHcInitHost ( return Status; } =20 - Status =3D SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]= , Private->ControllerVersion[Slot]); + // + // Perform first time clock setup with 400 KHz frequency. + // We send the 0 as the BusTiming value because at this time + // we still do not know the slot type and which enum value will apply. + // Since it is a first time setup SdMmcHcClockSupply won't notify + // the platofrm driver anyway so it doesn't matter. + // + Status =3D SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400); if (EFI_ERROR (Status)) { return Status; } diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h index 088c70451c..826e851b04 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h @@ -478,30 +478,6 @@ SdMmcHcStopClock ( IN UINT8 Slot ); =20 -/** - SD/MMC card clock supply. - - Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for detail= s. - - @param[in] PciIo The PCI IO protocol instance. - @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] ClockFreq The max clock frequency to be set. The unit is= KHz. - @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. - @param[in] ControllerVer The version of host controller. - - @retval EFI_SUCCESS The clock is supplied successfully. - @retval Others The clock isn't supplied successfully. - -**/ -EFI_STATUS -SdMmcHcClockSupply ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN UINT8 Slot, - IN UINT64 ClockFreq, - IN UINT32 BaseClkFreq, - IN UINT16 ControllerVer - ); - /** SD/MMC bus power control. =20 @@ -542,26 +518,6 @@ SdMmcHcSetBusWidth ( IN UINT16 BusWidth ); =20 -/** - Supply SD/MMC card with lowest clock frequency at initialization. - - @param[in] PciIo The PCI IO protocol instance. - @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. - @param[in] ControllerVer The version of host controller. - - @retval EFI_SUCCESS The clock is supplied successfully. - @retval Others The clock isn't supplied successfully. - -**/ -EFI_STATUS -SdMmcHcInitClockFreq ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN UINT8 Slot, - IN UINT32 BaseClkFreq, - IN UINT16 ControllerVer - ); - /** Supply SD/MMC card with maximum voltage at initialization. =20 --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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View/Reply Online (#52463): https://edk2.groups.io/g/devel/message/52463 Mute This Topic: https://groups.io/mt/68852796/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 22:27:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+52464+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52464+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1576862136; cv=none; d=zohomail.com; s=zohoarc; b=mJ3kODNKqDOnZGMjgV9+hk0cSaOXUASuzJRfS7H+IwuTWtI8GgxNvnDmNJjxTVgGE4A/grd5MWEce+B5ydzi2WCd56wARBd0DaflowwqDAK65VOnZI51lfDJTmugxE5IItj9ndtm0ZcXIAg0fwOwLVUICpdg+2Vsh1NIzYeXnNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576862136; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=F5TPkqNGg4qCMPxlEX2JSQmbp9VtJxFOq/niKGKXqEY=; b=K11QISbpxrvZKu5/XPJNeypJN+Srp/bmJ5ZmB2cbX+GunUDW59D4R+2VzAF4T9/U6yxjcREAdPKzw5h/FsZaMw6IsPG9FDk8cTP+DwVKl1TVjIumZnI1El6RgwgcXOJKMpD5L4hkLu3syp4/XO+LyIk29I6ZASG7UIgguwISRwM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+52464+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1576862136345972.811540325311; Fri, 20 Dec 2019 09:15:36 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id HJIgYY1788612xQj9FmtBrtg; Fri, 20 Dec 2019 09:15:35 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.11524.1576862092625300866 for ; Fri, 20 Dec 2019 09:14:52 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2019 09:14:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,336,1571727600"; d="scan'208";a="218533656" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.28.45]) by orsmga006.jf.intel.com with ESMTP; 20 Dec 2019 09:14:49 -0800 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu , Marcin Wojtas , Zhichao Gao , Liming Gao Subject: [edk2-devel] [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Add function to start SD clock Date: Fri, 20 Dec 2019 18:13:12 +0100 Message-Id: <20191220171312.3120-3-mateusz.albecki@intel.com> In-Reply-To: <20191220171312.3120-1-mateusz.albecki@intel.com> References: <20191220171312.3120-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com X-Gm-Message-State: HqSZBUbIQ27UCxJJsxw2u6KTx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1576862135; bh=KLnjEAyp/Wz3O4d/zSuKsMBu1vhKzOaGhlxWTfZhCsM=; h=Cc:Date:From:Reply-To:Subject:To; b=KTGNTvMSqo6dOKTtimmSXOP3HJwcsGjK7v9+9vGWx15ev4BcAhlmZ/h8pkEf+4UqSb4 G5RTRKklnR/sZQ4p/JqdYOknwBWABfTma5xKw2q+yXflPIWz7oh9WPJGDkNFFGJUPk2Bl aTrs45PmONjS6Eq6GwXWkkIdDOskQwdzxW0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In SD card voltage switch flow we used to redo the entire internal clock setup after voltage switch. Since internal clock has already been setup this is wasting time on polling the internal clock stable. This commit changes it to only start the SD clock. Cc: Hao A Wu Cc: Marcin Wojtas Cc: Zhichao Gao Cc: Liming Gao Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu Tested-by: Hao A Wu Tested-by: Marcin Wojtas --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 11 +++----- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 33 ++++++++++++++++++++= ---- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 15 +++++++++++ 3 files changed, 47 insertions(+), 12 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/B= us/Pci/SdMmcPciHcDxe/SdDevice.c index d63dc54e8c..b630daab76 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c @@ -1327,13 +1327,10 @@ SdCardIdentification ( goto Error; } =20 - // - // Restart the clock with first time parameters. - // NOTE: it is not required to actually restart the clock - // and go through internal clock setup again. Some time - // could be saved if we simply started the SD clock. - // - SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400); + Status =3D SdMmcHcStartSdClock (PciIo, Slot); + if (EFI_ERROR (Status)) { + goto Error; + } =20 gBS->Stall (1000); =20 diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index f667264c5e..e7f2fac69b 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -758,6 +758,30 @@ SdMmcHcStopClock ( return Status; } =20 +/** + Start the SD clock. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number. + + @retval EFI_SUCCESS Succeeded to start the SD clock. + @rtval Others Failed to start the SD clock. +**/ +EFI_STATUS +SdMmcHcStartSdClock ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot + ) +{ + UINT16 ClockCtrl; + + // + // Set SD Clock Enable in the Clock Control register to 1 + // + ClockCtrl =3D BIT2; + return SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCt= rl), &ClockCtrl); +} + /** SD/MMC card clock supply. =20 @@ -879,11 +903,10 @@ SdMmcHcClockSupply ( return Status; } =20 - // - // Set SD Clock Enable in the Clock Control register to 1 - // - ClockCtrl =3D BIT2; - Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (Clo= ckCtrl), &ClockCtrl); + Status =3D SdMmcHcStartSdClock (PciIo, Slot); + if (EFI_ERROR (Status)) { + return Status; + } =20 // // We don't notify the platform on first time setup to avoid changing diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h index 826e851b04..4753bb6864 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h @@ -478,6 +478,21 @@ SdMmcHcStopClock ( IN UINT8 Slot ); =20 +/** + Start the SD clock. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number. + + @retval EFI_SUCCESS Succeeded to start the SD clock. + @rtval Others Failed to start the SD clock. +**/ +EFI_STATUS +SdMmcHcStartSdClock ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot + ); + /** SD/MMC bus power control. =20 --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydz= ial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-31= 6 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata= i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wi= adomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiek= olwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by others is strictly prohibited. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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